Skip to content

X
x393
Commit 8dd16a59 authored by Andrey Filippov's avatar Andrey Filippov
Browse files
Options

Preparing for the HiSPi sensor testing

parent 71f603b7
Expand all Show whitespace changes
Inline Side-by-side
Showing with 1363 additions and 540 deletions
.project
View file @ 8dd16a59
...@@ -62,47 +62,47 @@ ...@@ -62,47 +62,47 @@
<link> <link>
<name>vivado_logs/VivadoBitstream.log</name> <name>vivado_logs/VivadoBitstream.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151105184905573.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151107161322372.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOpt.log</name> <name>vivado_logs/VivadoOpt.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151105184905573.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151107161051349.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPhys.log</name> <name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151105184905573.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151107161322372.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPower.log</name> <name>vivado_logs/VivadoOptPower.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151105184905573.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151107161051349.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoPlace.log</name> <name>vivado_logs/VivadoPlace.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151105184905573.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151107161322372.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoRoute.log</name> <name>vivado_logs/VivadoRoute.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151105184905573.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151107161322372.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoSynthesis.log</name> <name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151105184905573.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151107160339590.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name> <name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151105184905573.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151107161322372.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name> <name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20150725144907208.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20151105233458943.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimingReportImplemented.log</name> <name>vivado_logs/VivadoTimingReportImplemented.log</name>
......
.settings/com.elphel.vdt.VivadoSynthesis.prefs
View file @ 8dd16a59
...@@ -2,7 +2,7 @@ VivadoSynthesis_101_MaxMsg=10000 ...@@ -2,7 +2,7 @@ VivadoSynthesis_101_MaxMsg=10000
VivadoSynthesis_102_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@-> VivadoSynthesis_102_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@->
VivadoSynthesis_115_flatten_hierarchy=none VivadoSynthesis_115_flatten_hierarchy=none
VivadoSynthesis_121_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@-> VivadoSynthesis_121_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@->
VivadoSynthesis_122_ConstraintsFiles=x393.xdc<-@\#\#@->x393_nox2_timing.xdc<-@\#\#@-> VivadoSynthesis_122_ConstraintsFiles=x393_hispi.xdc<-@\#\#@->x393_hispi_timing.xdc<-@\#\#@->
VivadoSynthesis_122_SkipSnapshotSynth=true VivadoSynthesis_122_SkipSnapshotSynth=true
VivadoSynthesis_123_ResetProject=true VivadoSynthesis_123_ResetProject=true
VivadoSynthesis_123_SkipSnapshotSynth=true VivadoSynthesis_123_SkipSnapshotSynth=true
......
ddrc_test01.xdc
View file @ 8dd16a59
...@@ -203,10 +203,6 @@ set_property PACKAGE_PIN L5 [get_ports {SDDML}] ...@@ -203,10 +203,6 @@ set_property PACKAGE_PIN L5 [get_ports {SDDML}]
set_property IOSTANDARD SSTL15 [get_ports {SDDMU}] set_property IOSTANDARD SSTL15 [get_ports {SDDMU}]
set_property PACKAGE_PIN J5 [get_ports {SDDMU}] set_property PACKAGE_PIN J5 [get_ports {SDDMU}]
# output DUMMY_TO_KEEP, // to keep PS7 signals from "optimization"
set_property IOSTANDARD SSTL15 [get_ports {DUMMY_TO_KEEP}]
set_property PACKAGE_PIN E3 [get_ports {DUMMY_TO_KEEP}]
#not yet used, just for debugging #not yet used, just for debugging
# input MEMCLK, // to keep PS7 signals from "optimization" # input MEMCLK, // to keep PS7 signals from "optimization"
set_property IOSTANDARD SSTL15 [get_ports {MEMCLK}] set_property IOSTANDARD SSTL15 [get_ports {MEMCLK}]
......
fpga_version.vh
View file @ 8dd16a59
parameter FPGA_VERSION = 32'h0393006a; // modified clock generation, trying with HiSPi - 72.77% utilization
parameter FPGA_VERSION = 32'h03930066; // trying just one histogram to watch utilization - with 4 was: Slice 15913 (80.98%), now Slice = 14318 (72.87%) // parameter FPGA_VERSION = 32'h03930069; // modified clock generation, rebuilding for parallel sensors - all met, 71.8% utilization
// parameter FPGA_VERSION = 32'h03930068; // trying BUFR/FUFIO on all sensors ipclk/ipclk2x
// parameter FPGA_VERSION = 32'h03930067; // removing DUMMY_TO_KEEP, moving IOSTANDARD to HDL code
// parameter FPGA_VERSION = 32'h03930066; // trying just one histogram to watch utilization - with 4 was: Slice 15913 (80.98%), now Slice = 14318 (72.87%)
// parameter FPGA_VERSION = 32'h03930065; // (same rev) all met, using "old" (non-inverted) phase - OK (full phase range) // parameter FPGA_VERSION = 32'h03930065; // (same rev) all met, using "old" (non-inverted) phase - OK (full phase range)
// parameter FPGA_VERSION = 32'h03930065; // switch phy_top.v (all met) - OK with inverted phase control (reduced phase range) // parameter FPGA_VERSION = 32'h03930065; // switch phy_top.v (all met) - OK with inverted phase control (reduced phase range)
// parameter FPGA_VERSION = 32'h03930064; // switch mcomtr_sequencer.v (xclk not met) - wrong! // parameter FPGA_VERSION = 32'h03930064; // switch mcomtr_sequencer.v (xclk not met) - wrong!
......
includes/x393_parameters.vh
View file @ 8dd16a59
This diff is collapsed.
memctrl/mcntrl393.v
View file @ 8dd16a59
...@@ -142,15 +142,11 @@ module mcntrl393 #( ...@@ -142,15 +142,11 @@ module mcntrl393 #(
parameter HIGH_PERFORMANCE_MODE = "FALSE", parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter CLKIN_PERIOD = 20, // 10, //ns >1.25, 600<Fvco<1200 // Hardware 150MHz , change to | 6.667 parameter CLKIN_PERIOD = 20, // 10, //ns >1.25, 600<Fvco<1200 // Hardware 150MHz , change to | 6.667
parameter CLKFBOUT_MULT = 16, // 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE | 16 parameter CLKFBOUT_MULT = 16, // 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE | 16
parameter CLKFBOUT_MULT_REF = 16, // 18, // 9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE | 6
parameter CLKFBOUT_DIV_REF = 4, // 200Mhz 3, // To get 300MHz for the reference clock
`else `else
parameter real REFCLK_FREQUENCY = 300.0, parameter real REFCLK_FREQUENCY = 300.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE", parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter CLKIN_PERIOD = 10, //ns >1.25, 600<Fvco<1200 parameter CLKIN_PERIOD = 10, //ns >1.25, 600<Fvco<1200
parameter CLKFBOUT_MULT = 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE parameter CLKFBOUT_MULT = 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_MULT_REF = 9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_DIV_REF = 3, // To get 300MHz for the reference clock
`endif `endif
parameter DIVCLK_DIVIDE= 1, parameter DIVCLK_DIVIDE= 1,
parameter CLKFBOUT_USE_FINE_PS= 1, // 0 - old, 1 - new parameter CLKFBOUT_USE_FINE_PS= 1, // 0 - old, 1 - new
...@@ -251,7 +247,7 @@ module mcntrl393 #( ...@@ -251,7 +247,7 @@ module mcntrl393 #(
output mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port output mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port
input mrst, // @posedge mclk synchronous reset - should not interrupt mclk generation input mrst, // @posedge mclk synchronous reset - should not interrupt mclk generation
output locked, // to generate sync reset output locked, // to generate sync reset
output ref_clk, // global clock for idelay_ctrl calibration input ref_clk, // global clock for idelay_ctrl calibration
output idelay_ctrl_reset, output idelay_ctrl_reset,
// programming interface // programming interface
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3 input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
...@@ -402,9 +398,6 @@ module mcntrl393 #( ...@@ -402,9 +398,6 @@ module mcntrl393 #(
inout DQSU, // UDQS I/O pad inout DQSU, // UDQS I/O pad
inout NDQSU //, inout NDQSU //,
// output DUMMY_TO_KEEP // to keep PS7 signals from "optimization"
// input MEMCLK
// temporary debug data
,output [11:0] tmp_debug // add some signals generated here? ,output [11:0] tmp_debug // add some signals generated here?
); );
localparam COL_WDTH = COLADDR_NUMBER-3; // number of column address bits in bursts localparam COL_WDTH = COLADDR_NUMBER-3; // number of column address bits in bursts
...@@ -1814,8 +1807,6 @@ module mcntrl393 #( ...@@ -1814,8 +1807,6 @@ module mcntrl393 #(
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE), .HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.CLKIN_PERIOD (CLKIN_PERIOD), .CLKIN_PERIOD (CLKIN_PERIOD),
.CLKFBOUT_MULT (CLKFBOUT_MULT), .CLKFBOUT_MULT (CLKFBOUT_MULT),
.CLKFBOUT_MULT_REF (CLKFBOUT_MULT_REF),
.CLKFBOUT_DIV_REF (CLKFBOUT_DIV_REF),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE), .DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKFBOUT_USE_FINE_PS (CLKFBOUT_USE_FINE_PS), .CLKFBOUT_USE_FINE_PS (CLKFBOUT_USE_FINE_PS),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE), .CLKFBOUT_PHASE (CLKFBOUT_PHASE),
...@@ -1835,7 +1826,7 @@ module mcntrl393 #( ...@@ -1835,7 +1826,7 @@ module mcntrl393 #(
.mclk (mclk), // output .mclk (mclk), // output
.mrst (mrst), // input .mrst (mrst), // input
.locked (locked), // output .locked (locked), // output
.ref_clk (ref_clk), // output .ref_clk (ref_clk), // input
.idelay_ctrl_reset (idelay_ctrl_reset), // output .idelay_ctrl_reset (idelay_ctrl_reset), // output
.cmd_ad (cmd_mcontr_ad), // input[7:0] .cmd_ad (cmd_mcontr_ad), // input[7:0]
.cmd_stb (cmd_mcontr_stb), // input .cmd_stb (cmd_mcontr_stb), // input
......
memctrl/memctrl16.v
View file @ 8dd16a59
...@@ -115,15 +115,11 @@ module memctrl16 #( ...@@ -115,15 +115,11 @@ module memctrl16 #(
parameter HIGH_PERFORMANCE_MODE = "FALSE", parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter CLKIN_PERIOD = 20, // 10, //ns >1.25, 600<Fvco<1200 // Hardware 150MHz , change to | 6.667 parameter CLKIN_PERIOD = 20, // 10, //ns >1.25, 600<Fvco<1200 // Hardware 150MHz , change to | 6.667
parameter CLKFBOUT_MULT = 16, // 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE | 16 parameter CLKFBOUT_MULT = 16, // 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE | 16
parameter CLKFBOUT_MULT_REF = 16, // 18, // 9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE | 6
parameter CLKFBOUT_DIV_REF = 4, // 200Mhz 3, // To get 300MHz for the reference clock
`else `else
parameter real REFCLK_FREQUENCY = 300.0, parameter real REFCLK_FREQUENCY = 300.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE", parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter CLKIN_PERIOD = 10, //ns >1.25, 600<Fvco<1200 parameter CLKIN_PERIOD = 10, //ns >1.25, 600<Fvco<1200
parameter CLKFBOUT_MULT = 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE parameter CLKFBOUT_MULT = 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_MULT_REF = 9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_DIV_REF = 3, // To get 300MHz for the reference clock
`endif `endif
parameter DIVCLK_DIVIDE= 1, parameter DIVCLK_DIVIDE= 1,
parameter CLKFBOUT_USE_FINE_PS= 1, // 0 - old, 1 - new parameter CLKFBOUT_USE_FINE_PS= 1, // 0 - old, 1 - new
...@@ -144,7 +140,7 @@ module memctrl16 #( ...@@ -144,7 +140,7 @@ module memctrl16 #(
output mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port output mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port
input mrst, // @posedge mclk synchronous reset - should not interrupt mclk generation input mrst, // @posedge mclk synchronous reset - should not interrupt mclk generation
output locked, // to generate sync reset output locked, // to generate sync reset
output ref_clk, // global clock for idelay_ctrl calibration input ref_clk, // global clock for idelay_ctrl calibration
output idelay_ctrl_reset, output idelay_ctrl_reset,
// programming interface // programming interface
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3 input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
...@@ -541,8 +537,6 @@ module memctrl16 #( ...@@ -541,8 +537,6 @@ module memctrl16 #(
output SDDMU, // UDM I/O pad (actually only output) output SDDMU, // UDM I/O pad (actually only output)
inout DQSU, // UDQS I/O pad inout DQSU, // UDQS I/O pad
inout NDQSU //, inout NDQSU //,
// output DUMMY_TO_KEEP // to keep PS7 signals from "optimization"
// input MEMCLK
// temporary debug data // temporary debug data
,output [11:0] tmp_debug // add some signals generated here? ,output [11:0] tmp_debug // add some signals generated here?
); );
...@@ -903,8 +897,6 @@ end ...@@ -903,8 +897,6 @@ end
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE), .HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.CLKIN_PERIOD (CLKIN_PERIOD), .CLKIN_PERIOD (CLKIN_PERIOD),
.CLKFBOUT_MULT (CLKFBOUT_MULT), .CLKFBOUT_MULT (CLKFBOUT_MULT),
.CLKFBOUT_MULT_REF (CLKFBOUT_MULT_REF),
.CLKFBOUT_DIV_REF (CLKFBOUT_DIV_REF),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE), .DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKFBOUT_USE_FINE_PS (CLKFBOUT_USE_FINE_PS), .CLKFBOUT_USE_FINE_PS (CLKFBOUT_USE_FINE_PS),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE), .CLKFBOUT_PHASE (CLKFBOUT_PHASE),
...@@ -942,7 +934,7 @@ end ...@@ -942,7 +934,7 @@ end
.mclk (mclk), // output .mclk (mclk), // output
.mrst (mrst), // input .mrst (mrst), // input
.locked (locked), // output .locked (locked), // output
.ref_clk (ref_clk), // output .ref_clk (ref_clk), // input
.idelay_ctrl_reset (idelay_ctrl_reset), .idelay_ctrl_reset (idelay_ctrl_reset),
.cmd0_clk (cmd0_clk), // input .cmd0_clk (cmd0_clk), // input
......
memctrl/phy/mcontr_sequencer.v
View file @ 8dd16a59
...@@ -77,8 +77,6 @@ module mcontr_sequencer #( ...@@ -77,8 +77,6 @@ module mcontr_sequencer #(
parameter HIGH_PERFORMANCE_MODE = "FALSE", parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter CLKIN_PERIOD = 10, //ns >1.25, 600<Fvco<1200 parameter CLKIN_PERIOD = 10, //ns >1.25, 600<Fvco<1200
parameter CLKFBOUT_MULT = 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE parameter CLKFBOUT_MULT = 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_MULT_REF = 9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_DIV_REF = 3, // To get 300MHz for the reference clock
parameter DIVCLK_DIVIDE= 1, parameter DIVCLK_DIVIDE= 1,
parameter CLKFBOUT_USE_FINE_PS= 1, // 0 - old, 1 - new parameter CLKFBOUT_USE_FINE_PS= 1, // 0 - old, 1 - new
parameter CLKFBOUT_PHASE = 0.000, parameter CLKFBOUT_PHASE = 0.000,
...@@ -118,7 +116,7 @@ module mcontr_sequencer #( ...@@ -118,7 +116,7 @@ module mcontr_sequencer #(
output mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port output mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port
input mrst, // @posedge mclk, sync reset (should not interrupt mclk!) input mrst, // @posedge mclk, sync reset (should not interrupt mclk!)
output locked, // to generate sync reset output locked, // to generate sync reset
output ref_clk, // global clock for idelay_ctrl calibration input ref_clk, // global clock for idelay_ctrl calibration
output idelay_ctrl_reset, output idelay_ctrl_reset,
// command port 0 (filled by software - 32w->32r) - used for mode set, refresh, write levelling, ... // command port 0 (filled by software - 32w->32r) - used for mode set, refresh, write levelling, ...
input cmd0_clk, input cmd0_clk,
...@@ -549,8 +547,6 @@ module mcontr_sequencer #( ...@@ -549,8 +547,6 @@ module mcontr_sequencer #(
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE), .HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.CLKIN_PERIOD (CLKIN_PERIOD), .CLKIN_PERIOD (CLKIN_PERIOD),
.CLKFBOUT_MULT (CLKFBOUT_MULT), .CLKFBOUT_MULT (CLKFBOUT_MULT),
.CLKFBOUT_MULT_REF (CLKFBOUT_MULT_REF),
.CLKFBOUT_DIV_REF (CLKFBOUT_DIV_REF),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE), .DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKFBOUT_USE_FINE_PS (CLKFBOUT_USE_FINE_PS), .CLKFBOUT_USE_FINE_PS (CLKFBOUT_USE_FINE_PS),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE), .CLKFBOUT_PHASE (CLKFBOUT_PHASE),
...@@ -586,7 +582,7 @@ module mcontr_sequencer #( ...@@ -586,7 +582,7 @@ module mcontr_sequencer #(
.rst_in (rst_in), // input .rst_in (rst_in), // input
.mclk (mclk), // output .mclk (mclk), // output
.mrst (mrst), // input .mrst (mrst), // input
.ref_clk (ref_clk), // output .ref_clk (ref_clk), // input
.idelay_ctrl_reset (idelay_ctrl_reset), // output .idelay_ctrl_reset (idelay_ctrl_reset), // output
.dly_data (dly_data[7:0]), // input[7:0] .dly_data (dly_data[7:0]), // input[7:0]
.dly_addr (dly_addr[6:0]), // input[6:0] .dly_addr (dly_addr[6:0]), // input[6:0]
......
memctrl/phy/phy_cmd.v
View file @ 8dd16a59
...@@ -33,8 +33,6 @@ module phy_cmd#( ...@@ -33,8 +33,6 @@ module phy_cmd#(
parameter HIGH_PERFORMANCE_MODE = "FALSE", parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter CLKIN_PERIOD = 10, //ns >1.25, 600<Fvco<1200 parameter CLKIN_PERIOD = 10, //ns >1.25, 600<Fvco<1200
parameter CLKFBOUT_MULT = 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE parameter CLKFBOUT_MULT = 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_MULT_REF = 9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_DIV_REF = 3, // To get 300MHz for the reference clock
parameter DIVCLK_DIVIDE= 1, parameter DIVCLK_DIVIDE= 1,
parameter CLKFBOUT_USE_FINE_PS= 1, // 0 - old, 1 - new parameter CLKFBOUT_USE_FINE_PS= 1, // 0 - old, 1 - new
parameter CLKFBOUT_PHASE = 0.000, parameter CLKFBOUT_PHASE = 0.000,
...@@ -73,7 +71,7 @@ module phy_cmd#( ...@@ -73,7 +71,7 @@ module phy_cmd#(
input rst_in, input rst_in,
output mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port output mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port
input mrst, // @posedge mclk synchronous reset - should not interrupt mclk generation input mrst, // @posedge mclk synchronous reset - should not interrupt mclk generation
output ref_clk, // global clock for idelay_ctrl calibration input ref_clk, // global clock for idelay_ctrl calibration
output idelay_ctrl_reset, output idelay_ctrl_reset,
// inteface to control I/O delays and mmcm // inteface to control I/O delays and mmcm
input [7:0] dly_data, // delay value (3 LSB - fine delay) input [7:0] dly_data, // delay value (3 LSB - fine delay)
...@@ -377,8 +375,6 @@ module phy_cmd#( ...@@ -377,8 +375,6 @@ module phy_cmd#(
.BANDWIDTH ("OPTIMIZED"), .BANDWIDTH ("OPTIMIZED"),
.CLKIN_PERIOD (CLKIN_PERIOD), .CLKIN_PERIOD (CLKIN_PERIOD),
.CLKFBOUT_MULT (CLKFBOUT_MULT), .CLKFBOUT_MULT (CLKFBOUT_MULT),
.CLKFBOUT_MULT_REF(CLKFBOUT_MULT_REF),
.CLKFBOUT_DIV_REF (CLKFBOUT_DIV_REF),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE), .DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKFBOUT_USE_FINE_PS (CLKFBOUT_USE_FINE_PS), .CLKFBOUT_USE_FINE_PS (CLKFBOUT_USE_FINE_PS),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE), .CLKFBOUT_PHASE (CLKFBOUT_PHASE),
...@@ -413,7 +409,7 @@ module phy_cmd#( ...@@ -413,7 +409,7 @@ module phy_cmd#(
.clk_div (clk_div), // output .clk_div (clk_div), // output
.mclk (mclk), // output .mclk (mclk), // output
.mrst (mrst), // input .mrst (mrst), // input
.ref_clk (ref_clk), // output .ref_clk (ref_clk), // input
.idelay_ctrl_reset (idelay_ctrl_reset), // output .idelay_ctrl_reset (idelay_ctrl_reset), // output
.rst_in (rst_in), // input .rst_in (rst_in), // input
......
memctrl/phy/phy_top.v
View file @ 8dd16a59
...@@ -40,8 +40,6 @@ module phy_top #( ...@@ -40,8 +40,6 @@ module phy_top #(
// Assuming 100MHz input clock, 800MHz Fvco, 400MHz clk, 200MHz clk_div, 200MHz mclk // Assuming 100MHz input clock, 800MHz Fvco, 400MHz clk, 200MHz clk_div, 200MHz mclk
parameter CLKIN_PERIOD = 10, //ns >1.25, 600<Fvco<1200 parameter CLKIN_PERIOD = 10, //ns >1.25, 600<Fvco<1200
parameter CLKFBOUT_MULT = 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE parameter CLKFBOUT_MULT = 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_MULT_REF = 9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_DIV_REF = 3, // To get 300MHz for the reference clock
parameter DIVCLK_DIVIDE= 1, parameter DIVCLK_DIVIDE= 1,
parameter CLKFBOUT_USE_FINE_PS =1, // if 1 move CLKFBOUT_PHASE and SDCLK_PHASE, if 0 - other outputs (moved phases should be 0/same) parameter CLKFBOUT_USE_FINE_PS =1, // if 1 move CLKFBOUT_PHASE and SDCLK_PHASE, if 0 - other outputs (moved phases should be 0/same)
parameter CLKFBOUT_PHASE = 0.000, parameter CLKFBOUT_PHASE = 0.000,
...@@ -78,7 +76,7 @@ module phy_top #( ...@@ -78,7 +76,7 @@ module phy_top #(
output clk_div, // free-running half clk frequency, front aligned to clk (shared for R/W), BUFR output output clk_div, // free-running half clk frequency, front aligned to clk (shared for R/W), BUFR output
output mclk, // same as clk_div, through separate BUFG and static phase adjust output mclk, // same as clk_div, through separate BUFG and static phase adjust
input mrst, // @posedge mclk synchronous reset - should not interrupt mclk generation input mrst, // @posedge mclk synchronous reset - should not interrupt mclk generation
output ref_clk, // global clock for idelay_ctrl calibration input ref_clk, // global clock for idelay_ctrl calibration
output idelay_ctrl_reset, output idelay_ctrl_reset,
input rst_in, // reset delays/serdes - global reset? input rst_in, // reset delays/serdes - global reset?
input ddr_rst, // active high - generate NRST to memory input ddr_rst, // active high - generate NRST to memory
...@@ -120,14 +118,9 @@ module phy_top #( ...@@ -120,14 +118,9 @@ module phy_top #(
output ps_rdy, output ps_rdy,
output [PHASE_WIDTH-1:0] ps_out output [PHASE_WIDTH-1:0] ps_out
); );
assign locked_pll = 1; // not used anymore, reference clock generation moved to other module
reg rst= 1'b1; reg rst= 1'b1;
// always @(negedge clk_div or posedge rst_in) begin // Why is it @ negedge clk_div?
// if (rst_in) rst <= 1'b1;
// else rst <= 1'b0;
// end
// always @(negedge clk_div) begin // Why is it @ negedge clk_div?
always @(posedge clk_div) begin // Why is it @ negedge clk_div? always @(posedge clk_div) begin // Why is it @ negedge clk_div?
if (mrst) rst <= 1'b1; if (mrst) rst <= 1'b1;
else rst <= 1'b0; else rst <= 1'b0;
...@@ -137,27 +130,15 @@ module phy_top #( ...@@ -137,27 +130,15 @@ module phy_top #(
wire ld_data_h = (dly_addr[6:5] == 2'h1) && ld_delay ; wire ld_data_h = (dly_addr[6:5] == 2'h1) && ld_delay ;
wire ld_cmda = (dly_addr[6:5] == 2'h2) && ld_delay ; wire ld_cmda = (dly_addr[6:5] == 2'h2) && ld_delay ;
wire ld_mmcm= (dly_addr[6:0] == 7'h60) && ld_delay ; wire ld_mmcm= (dly_addr[6:0] == 7'h60) && ld_delay ;
wire clkfb_ref, clk_ref_pre; // wire clkfb_ref, clk_ref_pre;
// wire ref_clk; // 200MHz/300Mhz to calibrate I/O delays
// wire locked_mmcm,locked_pll, dly_ready, dci_ready;
// assign locked=locked_mmcm && locked_pll && dly_ready && dci_ready; // both PLL ready, I/O delay calibrated
wire clkin_stopped_mmcm; wire clkin_stopped_mmcm;
wire clkfb_stopped_mmcm; wire clkfb_stopped_mmcm;
reg dbg1=0; reg dbg1=0;
reg dbg2=0; reg dbg2=0;
/*
always @ (posedge rst_in or posedge mclk) begin
if (rst_in) dbg1 <= 0;
else dbg1 <= ~dbg1;
end
always @ (posedge rst_in or posedge clk_div) begin
if (rst_in) dbg2 <= 0;
else dbg2 <= ~dbg2;
end
*/
always @ (posedge mclk) begin always @ (posedge mclk) begin
if (mrst) dbg1 <= 0; if (mrst) dbg1 <= 0;
else dbg1 <= ~dbg1; else dbg1 <= ~dbg1;
...@@ -316,10 +297,7 @@ BUFR clk_bufr_i (.O(clk), .CE(), .CLR(), .I(clk_pre)); ...@@ -316,10 +297,7 @@ BUFR clk_bufr_i (.O(clk), .CE(), .CLR(), .I(clk_pre));
//BUFIO clk_buf_i (.O(clk), .I(clk_pre)); //BUFIO clk_buf_i (.O(clk), .I(clk_pre));
BUFR clk_div_bufr_i (.O(clk_div), .CE(), .CLR(), .I(clk_div_pre)); BUFR clk_div_bufr_i (.O(clk_div), .CE(), .CLR(), .I(clk_div_pre));
BUFIO iclk_bufio_i (.O(sdclk), .I(sdclk_pre) ); BUFIO iclk_bufio_i (.O(sdclk), .I(sdclk_pre) );
//BUFIO clk_ref_i (.O(ref_clk), .I(clk_ref_pre)); ///BUFG clk_ref_i (.O(ref_clk), .I(clk_ref_pre));
//assign ref_clk=clk_ref_pre;
//BUFH clk_ref_i (.O(ref_clk), .I(clk_ref_pre));
BUFG clk_ref_i (.O(ref_clk), .I(clk_ref_pre));
BUFG mclk_i (.O(mclk),.I(mclk_pre) ); BUFG mclk_i (.O(mclk),.I(mclk_pre) );
mmcm_phase_cntr #( mmcm_phase_cntr #(
.PHASE_WIDTH (PHASE_WIDTH), .PHASE_WIDTH (PHASE_WIDTH),
...@@ -390,30 +368,6 @@ BUFG mclk_i (.O(mclk),.I(mclk_pre) ); ...@@ -390,30 +368,6 @@ BUFG mclk_i (.O(mclk),.I(mclk_pre) );
.clkfb_stopped (clkfb_stopped_mmcm) // output .clkfb_stopped (clkfb_stopped_mmcm) // output
// output // output
); );
// Generate reference clock for the I/O delays
pll_base #(
.CLKIN_PERIOD(CLKIN_PERIOD),
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT(CLKFBOUT_MULT_REF),
.CLKOUT0_DIVIDE(CLKFBOUT_DIV_REF),
.REF_JITTER1(0.010),
.STARTUP_WAIT("FALSE")
) pll_base_i (
.clkin(clk_in), // input
.clkfbin(clkfb_ref), // input
// .rst(rst), // input
.rst(rst_in), // input
.pwrdwn(1'b0), // input
.clkout0(clk_ref_pre), // output
.clkout1(), // output
.clkout2(), // output
.clkout3(), // output
.clkout4(), // output
.clkout5(), // output
.clkfbout(clkfb_ref), // output
.locked(locked_pll) // output
);
// Does it need to be re-calibrated periodically - yes when temperature changes, same as dci_reset // Does it need to be re-calibrated periodically - yes when temperature changes, same as dci_reset
assign idelay_ctrl_reset = rst || dly_rst; assign idelay_ctrl_reset = rst || dly_rst;
idelay_ctrl# ( idelay_ctrl# (
......
sensor/sens_10398.v
View file @ 8dd16a59
...@@ -76,18 +76,21 @@ module sens_10398 #( ...@@ -76,18 +76,21 @@ module sens_10398 #(
parameter HISPI_MSB_FIRST = 0, parameter HISPI_MSB_FIRST = 0,
parameter HISPI_NUMLANES = 4, parameter HISPI_NUMLANES = 4,
parameter HISPI_DELAY_CLK = "FALSE",
parameter HISPI_MMCM = "TRUE",
parameter HISPI_CAPACITANCE = "DONT_CARE", parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "TRUE", parameter HISPI_DIFF_TERM = "TRUE",
parameter HISPI_DQS_BIAS = "TRUE", parameter HISPI_DQS_BIAS = "TRUE",
parameter HISPI_IBUF_DELAY_VALUE = "0", parameter HISPI_IBUF_DELAY_VALUE = "0",
parameter HISPI_IBUF_LOW_PWR = "TRUE", parameter HISPI_IBUF_LOW_PWR = "TRUE",
parameter HISPI_IFD_DELAY_VALUE = "AUTO", parameter HISPI_IFD_DELAY_VALUE = "AUTO",
parameter HISPI_IOSTANDARD = "DEFAULT", parameter HISPI_IOSTANDARD = "DIFF_SSTL18_I", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
// Other (non-HiSPi) sensor I/Os // Other (non-HiSPi) sensor I/Os
parameter integer PXD_DRIVE = 12, parameter integer PXD_DRIVE = 12,
parameter PXD_IBUF_LOW_PWR = "TRUE", parameter PXD_IBUF_LOW_PWR = "TRUE",
parameter PXD_IOSTANDARD = "DEFAULT", // 1.8V single-ended parameter PXD_IOSTANDARD = "LVCMOS18", // 1.8V single-ended
parameter PXD_SLEW = "SLOW", parameter PXD_SLEW = "SLOW",
parameter PXD_CAPACITANCE = "DONT_CARE", parameter PXD_CAPACITANCE = "DONT_CARE",
parameter PXD_CLK_DIV = 10, // 220MHz -> 22MHz parameter PXD_CLK_DIV = 10, // 220MHz -> 22MHz
...@@ -324,6 +327,8 @@ module sens_10398 #( ...@@ -324,6 +327,8 @@ module sens_10398 #(
.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD), .SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD),
.HISPI_MSB_FIRST (HISPI_MSB_FIRST), .HISPI_MSB_FIRST (HISPI_MSB_FIRST),
.HISPI_NUMLANES (HISPI_NUMLANES), .HISPI_NUMLANES (HISPI_NUMLANES),
.HISPI_DELAY_CLK (HISPI_DELAY_CLK),
.HISPI_MMCM (HISPI_MMCM),
.HISPI_CAPACITANCE (HISPI_CAPACITANCE), .HISPI_CAPACITANCE (HISPI_CAPACITANCE),
.HISPI_DIFF_TERM (HISPI_DIFF_TERM), .HISPI_DIFF_TERM (HISPI_DIFF_TERM),
.HISPI_DQS_BIAS (HISPI_DQS_BIAS), .HISPI_DQS_BIAS (HISPI_DQS_BIAS),
...@@ -356,16 +361,43 @@ module sens_10398 #( ...@@ -356,16 +361,43 @@ module sens_10398 #(
.clkin_pxd_stopped_mmcm (clkin_pxd_stopped_mmcm), // output .clkin_pxd_stopped_mmcm (clkin_pxd_stopped_mmcm), // output
.clkfb_pxd_stopped_mmcm (clkfb_pxd_stopped_mmcm) // output .clkfb_pxd_stopped_mmcm (clkfb_pxd_stopped_mmcm) // output
); );
/*
obufds #( obufds #(
.CAPACITANCE("DONT_CARE"), .CAPACITANCE("DONT_CARE"),
.IOSTANDARD("DEFAULT"), .IOSTANDARD(PXD_IOSTANDARD), // not diff, just opposite phase signals
.SLEW("SLOW") .SLEW("SLOW")
) obufds_i ( ) obufds_i (
.o (sens_ext_clk_p), // output .o (sens_ext_clk_p), // output
.ob (sens_ext_clk_n), // output .ob (sens_ext_clk_n), // output
.i (pxd_clk_cntr[PXD_CLK_DIV_BITS-1]) // input .i (pxd_clk_cntr[PXD_CLK_DIV_BITS-1]) // input
); );
*/
// reg [1:0] ext_clk_r;
// always @(posedge pclk) begin
// ext_clk_r <= {pxd_clk_cntr[PXD_CLK_DIV_BITS-1], !pxd_clk_cntr[PXD_CLK_DIV_BITS-1]};
// end
obuf #(
.CAPACITANCE (PXD_CAPACITANCE),
.DRIVE (PXD_DRIVE),
.IOSTANDARD (PXD_IOSTANDARD),
.SLEW (PXD_SLEW)
) ext_clk_p_i (
.O (sens_ext_clk_p), // output
.I (pxd_clk_cntr[PXD_CLK_DIV_BITS-1]) //ext_clk_r[0]) // input
);
obuf #(
.CAPACITANCE (PXD_CAPACITANCE),
.DRIVE (PXD_DRIVE),
.IOSTANDARD (PXD_IOSTANDARD),
.SLEW (PXD_SLEW)
) ext_clk_n_i (
.O (sens_ext_clk_n), // output
.I (iarst) // ~pxd_clk_cntr[PXD_CLK_DIV_BITS-1]) // ext_clk_r[1]) // input
);
// Probe programmable/ control PROGRAM pin // Probe programmable/ control PROGRAM pin
reg [1:0] xpgmen_d; reg [1:0] xpgmen_d;
reg force_senspgm=0; reg force_senspgm=0;
......
sensor/sens_hispi12l4.v
View file @ 8dd16a59
...@@ -46,13 +46,15 @@ module sens_hispi12l4#( ...@@ -46,13 +46,15 @@ module sens_hispi12l4#(
parameter HISPI_MSB_FIRST = 0, parameter HISPI_MSB_FIRST = 0,
parameter HISPI_NUMLANES = 4, parameter HISPI_NUMLANES = 4,
parameter HISPI_DELAY_CLK = "FALSE",
parameter HISPI_MMCM = "TRUE",
parameter HISPI_CAPACITANCE = "DONT_CARE", parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "TRUE", parameter HISPI_DIFF_TERM = "TRUE",
parameter HISPI_DQS_BIAS = "TRUE", parameter HISPI_DQS_BIAS = "TRUE",
parameter HISPI_IBUF_DELAY_VALUE = "0", parameter HISPI_IBUF_DELAY_VALUE = "0",
parameter HISPI_IBUF_LOW_PWR = "TRUE", parameter HISPI_IBUF_LOW_PWR = "TRUE",
parameter HISPI_IFD_DELAY_VALUE = "AUTO", parameter HISPI_IFD_DELAY_VALUE = "AUTO",
parameter HISPI_IOSTANDARD = "DEFAULT", parameter HISPI_IOSTANDARD = "DIFF_SSTL18_I", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA),
parameter HISPI_KEEP_IRST = 5 // number of cycles to keep irst on after release of prst (small number - use 1 hot) parameter HISPI_KEEP_IRST = 5 // number of cycles to keep irst on after release of prst (small number - use 1 hot)
)( )(
input pclk, // global clock input, pixel rate (220MHz for MT9F002) input pclk, // global clock input, pixel rate (220MHz for MT9F002)
...@@ -112,6 +114,14 @@ module sens_hispi12l4#( ...@@ -112,6 +114,14 @@ module sens_hispi12l4#(
.SENS_SS_EN (SENS_SS_EN), .SENS_SS_EN (SENS_SS_EN),
.SENS_SS_MODE (SENS_SS_MODE), .SENS_SS_MODE (SENS_SS_MODE),
.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD), .SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD),
.IODELAY_GRP (IODELAY_GRP),
.IDELAY_VALUE (IDELAY_VALUE),
.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.HISPI_DELAY_CLK (HISPI_DELAY_CLK),
.HISPI_MMCM (HISPI_MMCM),
.HISPI_CAPACITANCE (HISPI_CAPACITANCE), .HISPI_CAPACITANCE (HISPI_CAPACITANCE),
.HISPI_DIFF_TERM (HISPI_DIFF_TERM), .HISPI_DIFF_TERM (HISPI_DIFF_TERM),
.HISPI_DQS_BIAS (HISPI_DQS_BIAS), .HISPI_DQS_BIAS (HISPI_DQS_BIAS),
...@@ -124,6 +134,7 @@ module sens_hispi12l4#( ...@@ -124,6 +134,7 @@ module sens_hispi12l4#(
.mrst (mrst), // input .mrst (mrst), // input
.phase (dly_data[7:0]), // input[7:0] .phase (dly_data[7:0]), // input[7:0]
.set_phase (set_clk_phase), // input .set_phase (set_clk_phase), // input
.load (ld_idelay), // input
.rst_mmcm (rst_mmcm), // input .rst_mmcm (rst_mmcm), // input
.clp_p (sns_clkp), // input .clp_p (sns_clkp), // input
.clk_n (sns_clkn), // input .clk_n (sns_clkn), // input
......
sensor/sens_hispi_clock.v
View file @ 8dd16a59
...@@ -23,9 +23,7 @@ ...@@ -23,9 +23,7 @@
module sens_hispi_clock#( module sens_hispi_clock#(
parameter SENS_PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors) parameter SENS_PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
// parameter SENS_PCLK_PERIOD = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW" parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"
parameter CLKIN_PERIOD_SENSOR = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps parameter CLKIN_PERIOD_SENSOR = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 3, // 330 MHz --> 990 MHz parameter CLKFBOUT_MULT_SENSOR = 3, // 330 MHz --> 990 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000) parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
...@@ -40,22 +38,28 @@ module sens_hispi_clock#( ...@@ -40,22 +38,28 @@ module sens_hispi_clock#(
parameter SENS_SS_EN = "FALSE", // Enables Spread Spectrum mode parameter SENS_SS_EN = "FALSE", // Enables Spread Spectrum mode
parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW" parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
parameter SENS_SS_MOD_PERIOD = 10000, // integer 4000-40000 - SS modulation period in ns parameter SENS_SS_MOD_PERIOD = 10000, // integer 4000-40000 - SS modulation period in ns
// Used with delay
parameter IODELAY_GRP = "IODELAY_SENSOR", // may need different for different channels?
parameter integer IDELAY_VALUE = 0,
parameter real REFCLK_FREQUENCY = 200.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter HISPI_DELAY_CLK = "FALSE",
parameter HISPI_MMCM = "TRUE",
parameter HISPI_CAPACITANCE = "DONT_CARE", parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "TRUE", parameter HISPI_DIFF_TERM = "TRUE",
parameter HISPI_DQS_BIAS = "TRUE", parameter HISPI_DQS_BIAS = "TRUE",
parameter HISPI_IBUF_DELAY_VALUE = "0", parameter HISPI_IBUF_DELAY_VALUE = "0",
parameter HISPI_IBUF_LOW_PWR = "TRUE", parameter HISPI_IBUF_LOW_PWR = "TRUE",
parameter HISPI_IFD_DELAY_VALUE = "AUTO", parameter HISPI_IFD_DELAY_VALUE = "AUTO",
parameter HISPI_IOSTANDARD = "DEFAULT" parameter HISPI_IOSTANDARD = "DIFF_SSTL18_I" //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
)( )(
input mclk, input mclk,
input mrst, input mrst,
input [7:0] phase, input [7:0] phase,
input set_phase, input set_phase,
input load, // only used when delay, not phase
input rst_mmcm, input rst_mmcm,
input clp_p, input clp_p,
input clk_n, input clk_n,
...@@ -72,6 +76,15 @@ module sens_hispi_clock#( ...@@ -72,6 +76,15 @@ module sens_hispi_clock#(
wire clk_fb; wire clk_fb;
wire prst = mrst; wire prst = mrst;
wire clk_in; wire clk_in;
wire clk_int;
wire set_phase_w = (HISPI_DELAY_CLK == "TRUE") ? 1'b0: set_phase;
wire [7:0] phase_w = (HISPI_DELAY_CLK == "TRUE") ? 8'b0: phase;
wire ps_rdy_w;
wire [7:0] ps_out_w;
assign ps_rdy = (HISPI_DELAY_CLK == "TRUE") ? 1'b1 : ps_rdy_w;
assign ps_out = (HISPI_DELAY_CLK == "TRUE") ? 8'b0 : ps_out_w;
ibufds_ibufgds #( ibufds_ibufgds #(
.CAPACITANCE (HISPI_CAPACITANCE), .CAPACITANCE (HISPI_CAPACITANCE),
.DIFF_TERM (HISPI_DIFF_TERM), .DIFF_TERM (HISPI_DIFF_TERM),
...@@ -81,15 +94,36 @@ module sens_hispi_clock#( ...@@ -81,15 +94,36 @@ module sens_hispi_clock#(
.IFD_DELAY_VALUE (HISPI_IFD_DELAY_VALUE), .IFD_DELAY_VALUE (HISPI_IFD_DELAY_VALUE),
.IOSTANDARD (HISPI_IOSTANDARD) .IOSTANDARD (HISPI_IOSTANDARD)
) ibufds_ibufgds0_i ( ) ibufds_ibufgds0_i (
.O (clk_in), // output .O (clk_int), // output
.I (clp_p), // input .I (clp_p), // input
.IB (clk_n) // input .IB (clk_n) // input
); );
generate
if (HISPI_DELAY_CLK == "TRUE") begin
idelay_nofine # (
.IODELAY_GRP (IODELAY_GRP),
.DELAY_VALUE (IDELAY_VALUE),
.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE)
) clk_dly_i(
.clk (mclk),
.rst (mrst),
.set (set_phase),
.ld (load),
.delay (phase[4:0]),
.data_in (clk_int),
.data_out (clk_in)
);
end else begin
assign clk_in = clk_int;
end
endgenerate
// generate phase-shifterd pixel clock (and 2x version) from either the internal clock (that is output to the sensor) or from the clock // generate phase-shifterd pixel clock (and 2x version) from either the internal clock (that is output to the sensor) or from the clock
// received from the sensor (may need to reset MMCM after resetting sensor) // received from the sensor (may need to reset MMCM after resetting sensor)
generate
if (HISPI_MMCM == "TRUE") begin
mmcm_phase_cntr #( mmcm_phase_cntr #(
.PHASE_WIDTH (SENS_PHASE_WIDTH), .PHASE_WIDTH (SENS_PHASE_WIDTH),
.CLKIN_PERIOD (CLKIN_PERIOD_SENSOR), .CLKIN_PERIOD (CLKIN_PERIOD_SENSOR),
...@@ -111,19 +145,20 @@ module sens_hispi_clock#( ...@@ -111,19 +145,20 @@ module sens_hispi_clock#(
.SS_MODE (SENS_SS_MODE), .SS_MODE (SENS_SS_MODE),
.SS_MOD_PERIOD (SENS_SS_MOD_PERIOD), .SS_MOD_PERIOD (SENS_SS_MOD_PERIOD),
.STARTUP_WAIT ("FALSE") .STARTUP_WAIT ("FALSE")
) mmcm_or_pll_i (
) mmcm_phase_cntr_i (
.clkin1 (clk_in), // input .clkin1 (clk_in), // input
.clkin2 (1'b0), // input .clkin2 (1'b0), // input
.sel_clk2 (1'b0), // input .sel_clk2 (1'b0), // input
.clkfbin (clk_fb), // input .clkfbin (clk_fb), // input
.rst (rst_mmcm), // input .rst (rst_mmcm), // input
.pwrdwn (1'b0), // input .pwrdwn (1'b0), // input
.psclk (mclk), // input .psclk (mclk), // input
.ps_we (set_phase), // input .ps_we (set_phase_w), // input
.ps_din (phase), // input[7:0] .ps_din (phase_w), // input[7:0]
.ps_ready (ps_rdy), // output .ps_ready (ps_rdy_w), // output
.ps_dout (ps_out), // output[7:0] reg .ps_dout (ps_out_w), // output[7:0] reg
.clkout0 (ipclk_pre), // output .clkout0 (ipclk_pre), // output
.clkout1 (ipclk2x_pre), // output .clkout1 (ipclk2x_pre), // output
.clkout2(), // output .clkout2(), // output
...@@ -142,8 +177,44 @@ module sens_hispi_clock#( ...@@ -142,8 +177,44 @@ module sens_hispi_clock#(
.clkfb_stopped (clkfb_pxd_stopped_mmcm) // output .clkfb_stopped (clkfb_pxd_stopped_mmcm) // output
// output // output
); );
end else begin
pll_base #(
.CLKIN_PERIOD (CLKIN_PERIOD_SENSOR),
.BANDWIDTH (SENS_BANDWIDTH),
.CLKFBOUT_MULT (CLKFBOUT_MULT_SENSOR), // 4
.DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE_SENSOR),
.CLKOUT0_PHASE (IPCLK_PHASE),
.CLKOUT1_PHASE (IPCLK2X_PHASE),
.CLKOUT0_DIVIDE (CLKFBOUT_MULT_SENSOR * 2), // 6 // 8.000),
.CLKOUT1_DIVIDE (CLKFBOUT_MULT_SENSOR ), // 3 // 4),
.REF_JITTER1 (SENS_REF_JITTER1),
.STARTUP_WAIT ("FALSE")
) mmcm_or_pll_i (
.clkin (clk_in), // input
.clkfbin (clk_fb), // input
.rst (rst_mmcm), // input
.pwrdwn (1'b0), // input
.clkout0 (ipclk_pre), // output
.clkout1 (ipclk2x_pre), // output
.clkout2(), // output
.clkout3(), // output
.clkout4(), // output
.clkout5(), // output
.clkfbout (clk_fb), // output
.locked (locked_pxd_mmcm)
// output
);
assign clkin_pxd_stopped_mmcm = 0;
assign clkfb_pxd_stopped_mmcm = 0;
assign ps_rdy_w = 1;
assign ps_out_w = 0; // alternatively - register delay written
end
endgenerate
generate generate
if (BUF_IPCLK == "BUFG") BUFG clk1x_i (.O(ipclk), .I(ipclk_pre)); if (BUF_IPCLK == "BUFR2") BUFR #(.BUFR_DIVIDE(2)) clk1x_i (.O(ipclk), .I(ipclk2x_pre), .CE(1'b1), .CLR(rst_mmcm));
else if (BUF_IPCLK == "BUFG") BUFG clk1x_i (.O(ipclk), .I(ipclk_pre));
else if (BUF_IPCLK == "BUFH") BUFH clk1x_i (.O(ipclk), .I(ipclk_pre)); else if (BUF_IPCLK == "BUFH") BUFH clk1x_i (.O(ipclk), .I(ipclk_pre));
else if (BUF_IPCLK == "BUFR") BUFR clk1x_i (.O(ipclk), .I(ipclk_pre), .CE(1'b1), .CLR(prst)); else if (BUF_IPCLK == "BUFR") BUFR clk1x_i (.O(ipclk), .I(ipclk_pre), .CE(1'b1), .CLR(prst));
else if (BUF_IPCLK == "BUFMR") BUFMR clk1x_i (.O(ipclk), .I(ipclk_pre)); else if (BUF_IPCLK == "BUFMR") BUFMR clk1x_i (.O(ipclk), .I(ipclk_pre));
......
sensor/sens_hispi_din.v
View file @ 8dd16a59
...@@ -33,7 +33,7 @@ module sens_hispi_din #( ...@@ -33,7 +33,7 @@ module sens_hispi_din #(
parameter HISPI_IBUF_DELAY_VALUE = "0", parameter HISPI_IBUF_DELAY_VALUE = "0",
parameter HISPI_IBUF_LOW_PWR = "TRUE", parameter HISPI_IBUF_LOW_PWR = "TRUE",
parameter HISPI_IFD_DELAY_VALUE = "AUTO", parameter HISPI_IFD_DELAY_VALUE = "AUTO",
parameter HISPI_IOSTANDARD = "DEFAULT" parameter HISPI_IOSTANDARD = "DIFF_SSTL18_I" //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
)( )(
input mclk, input mclk,
input mrst, input mrst,
......
sensor/sensor_channel.v
View file @ 8dd16a59
...@@ -181,7 +181,6 @@ module sensor_channel#( ...@@ -181,7 +181,6 @@ module sensor_channel#(
//sensor_i2c_io other parameters //sensor_i2c_io other parameters
parameter integer SENSI2C_DRIVE= 12, parameter integer SENSI2C_DRIVE= 12,
parameter SENSI2C_IBUF_LOW_PWR= "TRUE", parameter SENSI2C_IBUF_LOW_PWR= "TRUE",
parameter SENSI2C_IOSTANDARD = "DEFAULT",
parameter SENSI2C_SLEW = "SLOW", parameter SENSI2C_SLEW = "SLOW",
`ifndef HISPI `ifndef HISPI
...@@ -197,7 +196,6 @@ module sensor_channel#( ...@@ -197,7 +196,6 @@ module sensor_channel#(
parameter integer IDELAY_VALUE = 0, parameter integer IDELAY_VALUE = 0,
parameter integer PXD_DRIVE = 12, parameter integer PXD_DRIVE = 12,
parameter PXD_IBUF_LOW_PWR = "TRUE", parameter PXD_IBUF_LOW_PWR = "TRUE",
parameter PXD_IOSTANDARD = "DEFAULT",
parameter PXD_SLEW = "SLOW", parameter PXD_SLEW = "SLOW",
parameter real SENS_REFCLK_FREQUENCY = 300.0, parameter real SENS_REFCLK_FREQUENCY = 300.0,
parameter SENS_HIGH_PERFORMANCE_MODE = "FALSE", parameter SENS_HIGH_PERFORMANCE_MODE = "FALSE",
...@@ -219,12 +217,16 @@ module sensor_channel#( ...@@ -219,12 +217,16 @@ module sensor_channel#(
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000) parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000, parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000, parameter IPCLK2X_PHASE = 0.000,
parameter PXD_IOSTANDARD = "LVCMOS18",
parameter SENSI2C_IOSTANDARD = "LVCMOS18",
`else `else
parameter CLKIN_PERIOD_SENSOR = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps parameter CLKIN_PERIOD_SENSOR = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 8, // 100 MHz --> 800 MHz parameter CLKFBOUT_MULT_SENSOR = 8, // 100 MHz --> 800 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000) parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000, parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000, parameter IPCLK2X_PHASE = 0.000,
parameter PXD_IOSTANDARD = "LVCMOS25",
parameter SENSI2C_IOSTANDARD = "LVCMOS25",
`endif `endif
parameter BUF_IPCLK = "BUFR", parameter BUF_IPCLK = "BUFR",
...@@ -240,13 +242,15 @@ module sensor_channel#( ...@@ -240,13 +242,15 @@ module sensor_channel#(
`ifdef HISPI `ifdef HISPI
,parameter HISPI_MSB_FIRST = 0, ,parameter HISPI_MSB_FIRST = 0,
parameter HISPI_NUMLANES = 4, parameter HISPI_NUMLANES = 4,
parameter HISPI_DELAY_CLK = "FALSE",
parameter HISPI_MMCM = "TRUE",
parameter HISPI_CAPACITANCE = "DONT_CARE", parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "TRUE", parameter HISPI_DIFF_TERM = "TRUE",
parameter HISPI_DQS_BIAS = "TRUE", parameter HISPI_DQS_BIAS = "TRUE",
parameter HISPI_IBUF_DELAY_VALUE = "0", parameter HISPI_IBUF_DELAY_VALUE = "0",
parameter HISPI_IBUF_LOW_PWR = "TRUE", parameter HISPI_IBUF_LOW_PWR = "TRUE",
parameter HISPI_IFD_DELAY_VALUE = "AUTO", parameter HISPI_IFD_DELAY_VALUE = "AUTO",
parameter HISPI_IOSTANDARD = "DEFAULT" parameter HISPI_IOSTANDARD = "DIFF_SSTL18_I" //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
`endif `endif
`ifdef DEBUG_RING `ifdef DEBUG_RING
...@@ -266,12 +270,16 @@ module sensor_channel#( ...@@ -266,12 +270,16 @@ module sensor_channel#(
input prst, // @posedge pclk, sync reset input prst, // @posedge pclk, sync reset
// I/O pads, pin names match circuit diagram // I/O pads, pin names match circuit diagram
inout [7:0] sns_dp,
inout [7:0] sns_dn,
`ifdef HISPI `ifdef HISPI
input [3:0] sns_dp,
input [3:0] sns_dn,
inout [7:4] sns_dp74,
inout [7:4] sns_dn74,
input sns_clkp, input sns_clkp,
input sns_clkn, input sns_clkn,
`else `else
inout [7:0] sns_dp,
inout [7:0] sns_dn,
inout sns_clkp, inout sns_clkp,
inout sns_clkn, inout sns_clkn,
`endif `endif
...@@ -732,6 +740,8 @@ module sensor_channel#( ...@@ -732,6 +740,8 @@ module sensor_channel#(
.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD), .SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD),
.HISPI_MSB_FIRST (HISPI_MSB_FIRST), .HISPI_MSB_FIRST (HISPI_MSB_FIRST),
.HISPI_NUMLANES (HISPI_NUMLANES), .HISPI_NUMLANES (HISPI_NUMLANES),
.HISPI_DELAY_CLK (HISPI_DELAY_CLK),
.HISPI_MMCM (HISPI_MMCM),
.HISPI_CAPACITANCE (HISPI_CAPACITANCE), .HISPI_CAPACITANCE (HISPI_CAPACITANCE),
.HISPI_DIFF_TERM (HISPI_DIFF_TERM), .HISPI_DIFF_TERM (HISPI_DIFF_TERM),
.HISPI_DQS_BIAS (HISPI_DQS_BIAS), .HISPI_DQS_BIAS (HISPI_DQS_BIAS),
...@@ -763,16 +773,16 @@ module sensor_channel#( ...@@ -763,16 +773,16 @@ module sensor_channel#(
.sns_dn (sns_dn[3:0]), // input[3:0] .sns_dn (sns_dn[3:0]), // input[3:0]
.sns_clkp (sns_clkp), // input .sns_clkp (sns_clkp), // input
.sns_clkn (sns_clkn), // input .sns_clkn (sns_clkn), // input
.sens_ext_clk_p (sns_dp[6]), // output .sens_ext_clk_p (sns_dp74[6]), // output
.sens_ext_clk_n (sns_dn[6]), // output .sens_ext_clk_n (sns_dn74[6]), // output
.sns_pgm (sns_pg), // inout .sns_pgm (sns_pg), // inout
.sns_ctl_tck (sns_ctl), // output .sns_ctl_tck (sns_ctl), // output
.sns_mrst (sns_dp[7]), // output .sns_mrst (sns_dp74[7]), // output
.sns_arst_tms (sns_dn[7]), // output .sns_arst_tms (sns_dn74[7]), // output
.sns_gp0_tdi (sns_dp[5]), // output .sns_gp0_tdi (sns_dp74[5]), // output
.sns_gp1 (sns_dn[5]), // output .sns_gp1 (sns_dn74[5]), // output
.sns_flash_tdo (sns_dp[4]), // input .sns_flash_tdo (sns_dp74[4]), // input
.sns_shutter_done (sns_dn[4]), // input .sns_shutter_done (sns_dn74[4]), // input
.pxd (pxd), // output[11:0] .pxd (pxd), // output[11:0]
.hact (hact), // output .hact (hact), // output
.sof (sof), // output .sof (sof), // output
...@@ -806,7 +816,6 @@ module sensor_channel#( ...@@ -806,7 +816,6 @@ module sensor_channel#(
.IODELAY_GRP (IODELAY_GRP), .IODELAY_GRP (IODELAY_GRP),
.IDELAY_VALUE (IDELAY_VALUE), .IDELAY_VALUE (IDELAY_VALUE),
.PXD_DRIVE (PXD_DRIVE), .PXD_DRIVE (PXD_DRIVE),
.PXD_IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.PXD_IOSTANDARD (PXD_IOSTANDARD), .PXD_IOSTANDARD (PXD_IOSTANDARD),
.PXD_SLEW (PXD_SLEW), .PXD_SLEW (PXD_SLEW),
.SENS_REFCLK_FREQUENCY (SENS_REFCLK_FREQUENCY), .SENS_REFCLK_FREQUENCY (SENS_REFCLK_FREQUENCY),
...@@ -819,6 +828,7 @@ module sensor_channel#( ...@@ -819,6 +828,7 @@ module sensor_channel#(
.CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR), .CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR),
.IPCLK_PHASE (IPCLK_PHASE), .IPCLK_PHASE (IPCLK_PHASE),
.IPCLK2X_PHASE (IPCLK2X_PHASE), .IPCLK2X_PHASE (IPCLK2X_PHASE),
.PXD_IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.BUF_IPCLK (BUF_IPCLK), .BUF_IPCLK (BUF_IPCLK),
.BUF_IPCLK2X (BUF_IPCLK2X), .BUF_IPCLK2X (BUF_IPCLK2X),
.SENS_DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE), .SENS_DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE),
......
sensor/sensor_i2c_io.v
View file @ 8dd16a59
...@@ -56,7 +56,11 @@ module sensor_i2c_io#( ...@@ -56,7 +56,11 @@ module sensor_i2c_io#(
// I/O parameters // I/O parameters
parameter integer SENSI2C_DRIVE = 12, parameter integer SENSI2C_DRIVE = 12,
parameter SENSI2C_IBUF_LOW_PWR = "TRUE", parameter SENSI2C_IBUF_LOW_PWR = "TRUE",
parameter SENSI2C_IOSTANDARD = "DEFAULT", `ifdef HISPI
parameter SENSI2C_IOSTANDARD = "LVCMOS18",
`else
parameter SENSI2C_IOSTANDARD = "LVCMOS25",
`endif
parameter SENSI2C_SLEW = "SLOW" parameter SENSI2C_SLEW = "SLOW"
)( )(
input mrst, // @mclk input mrst, // @mclk
......
sensor/sensors393.v
View file @ 8dd16a59
...@@ -181,7 +181,6 @@ module sensors393 #( ...@@ -181,7 +181,6 @@ module sensors393 #(
//sensor_i2c_io other parameters //sensor_i2c_io other parameters
parameter integer SENSI2C_DRIVE= 12, parameter integer SENSI2C_DRIVE= 12,
parameter SENSI2C_IBUF_LOW_PWR= "TRUE", parameter SENSI2C_IBUF_LOW_PWR= "TRUE",
parameter SENSI2C_IOSTANDARD = "DEFAULT",
parameter SENSI2C_SLEW = "SLOW", parameter SENSI2C_SLEW = "SLOW",
`ifndef HISPI `ifndef HISPI
...@@ -215,7 +214,6 @@ module sensors393 #( ...@@ -215,7 +214,6 @@ module sensors393 #(
parameter integer IDELAY_VALUE = 0, parameter integer IDELAY_VALUE = 0,
parameter integer PXD_DRIVE = 12, parameter integer PXD_DRIVE = 12,
parameter PXD_IBUF_LOW_PWR = "TRUE", parameter PXD_IBUF_LOW_PWR = "TRUE",
parameter PXD_IOSTANDARD = "DEFAULT",
parameter PXD_SLEW = "SLOW", parameter PXD_SLEW = "SLOW",
parameter real SENS_REFCLK_FREQUENCY = 300.0, parameter real SENS_REFCLK_FREQUENCY = 300.0,
parameter SENS_HIGH_PERFORMANCE_MODE = "FALSE", parameter SENS_HIGH_PERFORMANCE_MODE = "FALSE",
...@@ -235,12 +233,16 @@ module sensors393 #( ...@@ -235,12 +233,16 @@ module sensors393 #(
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000) parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000, parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000, parameter IPCLK2X_PHASE = 0.000,
parameter PXD_IOSTANDARD = "LVCMOS18",
parameter SENSI2C_IOSTANDARD = "LVCMOS18",
`else `else
parameter CLKIN_PERIOD_SENSOR = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps parameter CLKIN_PERIOD_SENSOR = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 8, // 100 MHz --> 800 MHz parameter CLKFBOUT_MULT_SENSOR = 8, // 100 MHz --> 800 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000) parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000, parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000, parameter IPCLK2X_PHASE = 0.000,
parameter PXD_IOSTANDARD = "LVCMOS25",
parameter SENSI2C_IOSTANDARD = "LVCMOS25",
`endif `endif
// parameter BUF_IPCLK = "BUFR", // parameter BUF_IPCLK = "BUFR",
// parameter BUF_IPCLK2X = "BUFR", // parameter BUF_IPCLK2X = "BUFR",
...@@ -266,13 +268,21 @@ module sensors393 #( ...@@ -266,13 +268,21 @@ module sensors393 #(
`ifdef HISPI `ifdef HISPI
,parameter HISPI_MSB_FIRST = 0, ,parameter HISPI_MSB_FIRST = 0,
parameter HISPI_NUMLANES = 4, parameter HISPI_NUMLANES = 4,
parameter HISPI_DELAY_CLK0= "FALSE",
parameter HISPI_DELAY_CLK1= "FALSE",
parameter HISPI_DELAY_CLK2= "FALSE",
parameter HISPI_DELAY_CLK3= "FALSE",
parameter HISPI_MMCM0 = "TRUE",
parameter HISPI_MMCM1 = "TRUE",
parameter HISPI_MMCM2 = "TRUE",
parameter HISPI_MMCM3 = "TRUE",
parameter HISPI_CAPACITANCE = "DONT_CARE", parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "TRUE", parameter HISPI_DIFF_TERM = "TRUE",
parameter HISPI_DQS_BIAS = "TRUE", parameter HISPI_DQS_BIAS = "TRUE",
parameter HISPI_IBUF_DELAY_VALUE = "0", parameter HISPI_IBUF_DELAY_VALUE = "0",
parameter HISPI_IBUF_LOW_PWR = "TRUE", parameter HISPI_IBUF_LOW_PWR = "TRUE",
parameter HISPI_IFD_DELAY_VALUE = "AUTO", parameter HISPI_IFD_DELAY_VALUE = "AUTO",
parameter HISPI_IOSTANDARD = "DEFAULT" parameter HISPI_IOSTANDARD = "DIFF_SSTL18_I" //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
`endif `endif
`ifdef DEBUG_RING `ifdef DEBUG_RING
...@@ -301,12 +311,16 @@ module sensors393 #( ...@@ -301,12 +311,16 @@ module sensors393 #(
input status_start, // Acknowledge of the first status packet byte (address) input status_start, // Acknowledge of the first status packet byte (address)
// I/O pads, pin names match circuit diagram (each sensor) // I/O pads, pin names match circuit diagram (each sensor)
inout [31:0] sns_dp,
inout [31:0] sns_dn,
`ifdef HISPI `ifdef HISPI
inout [3:0] sns_clkp, // SuppressThisWarning all - input-only in HiSPi mode input [15:0] sns_dp,
inout [3:0] sns_clkn, // SuppressThisWarning all - input-only in HiSPi mode input [15:0] sns_dn,
inout [15:0] sns_dp74,
inout [15:0] sns_dn74,
input [3:0] sns_clkp, // SuppressThisWarning all - input-only in HiSPi mode
input [3:0] sns_clkn, // SuppressThisWarning all - input-only in HiSPi mode
`else `else
inout [31:0] sns_dp,
inout [31:0] sns_dn,
inout [3:0] sns_clkp, inout [3:0] sns_clkp,
inout [3:0] sns_clkn, inout [3:0] sns_clkn,
`endif `endif
...@@ -580,6 +594,10 @@ module sensors393 #( ...@@ -580,6 +594,10 @@ module sensors393 #(
`ifdef HISPI `ifdef HISPI
,.HISPI_MSB_FIRST (HISPI_MSB_FIRST), ,.HISPI_MSB_FIRST (HISPI_MSB_FIRST),
.HISPI_NUMLANES (HISPI_NUMLANES), .HISPI_NUMLANES (HISPI_NUMLANES),
.HISPI_DELAY_CLK ((i & 2) ? ((i & 1) ? HISPI_DELAY_CLK3 : HISPI_DELAY_CLK2) : ((i & 1) ?HISPI_DELAY_CLK1 : HISPI_DELAY_CLK0 )),
.HISPI_MMCM ((i & 2) ? ((i & 1) ? HISPI_MMCM3 : HISPI_MMCM2) : ((i & 1) ?HISPI_MMCM1 : HISPI_MMCM0 )),
.HISPI_CAPACITANCE (HISPI_CAPACITANCE), .HISPI_CAPACITANCE (HISPI_CAPACITANCE),
.HISPI_DIFF_TERM (HISPI_DIFF_TERM), .HISPI_DIFF_TERM (HISPI_DIFF_TERM),
.HISPI_DQS_BIAS (HISPI_DQS_BIAS), .HISPI_DQS_BIAS (HISPI_DQS_BIAS),
...@@ -599,11 +617,19 @@ module sensors393 #( ...@@ -599,11 +617,19 @@ module sensors393 #(
`endif `endif
.mrst (mrst), // input .mrst (mrst), // input
.prst (prst), // input .prst (prst), // input
`ifdef HISPI
.sns_dp (sns_dp[i * 4 +: 4]), // input[3:0]
.sns_dn (sns_dn[i * 4 +: 4]), // input[3:0]
.sns_dp74 (sns_dp74[i * 4 +: 4]), // input[3:0]
.sns_dn74 (sns_dn74[i * 4 +: 4]), // input[3:0]
.sns_clkp (sns_clkp[i]), // input
.sns_clkn (sns_clkn[i]), // input
`else
.sns_dp (sns_dp[i * 8 +: 8]), // inout[7:0] .sns_dp (sns_dp[i * 8 +: 8]), // inout[7:0]
.sns_dn (sns_dn[i * 8 +: 8]), // inout[7:0] .sns_dn (sns_dn[i * 8 +: 8]), // inout[7:0]
.sns_clkp (sns_clkp[i]), // inout .sns_clkp (sns_clkp[i]), // inout
.sns_clkn (sns_clkn[i]), // inout .sns_clkn (sns_clkn[i]), // inout
`endif
.sns_scl (sns_scl[i]), // inout .sns_scl (sns_scl[i]), // inout
.sns_sda (sns_sda[i]), // inout .sns_sda (sns_sda[i]), // inout
.sns_ctl (sns_ctl[i]), // inout .sns_ctl (sns_ctl[i]), // inout
......
system_defines.vh
View file @ 8dd16a59
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
`define PRELOAD_BRAMS `define PRELOAD_BRAMS
`define DISPLAY_COMPRESSED_DATA `define DISPLAY_COMPRESSED_DATA
// if HISPI is not defined, parallel sensor interface is used for all channels // if HISPI is not defined, parallel sensor interface is used for all channels
// `define HISPI `define HISPI
// `define USE_OLD_XDCT393 // `define USE_OLD_XDCT393
// `define USE_PCLK2X // `define USE_PCLK2X
// `define USE_XCLK2X // `define USE_XCLK2X
......
unisims_extra/IBUFG.v 0 → 100644
View file @ 8dd16a59
/*******************************************************************************
* Module: IBUFG
* Date:2015-11-06
* Author: andrey
* Description: Module name "known" to synthesis, but missing in unisims
*
* Copyright (c) 2015 Elphel, Inc .
* IBUFG.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* IBUFG.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module IBUFG #(
parameter CAPACITANCE = "DONT_CARE",
// parameter IBUF_DELAY_VALUE = "0",
parameter IBUF_LOW_PWR = "TRUE",
// parameter IFD_DELAY_VALUE = "AUTO",
parameter IOSTANDARD = "DEFAULT"
)(
output O,
input I
);
ibuf_ibufg #(
.CAPACITANCE (CAPACITANCE),
// .IBUF_DELAY_VALUE (IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (IBUF_LOW_PWR),
// .IFD_DELAY_VALUE (IFD_DELAY_VALUE),
.IOSTANDARD (IOSTANDARD)
) IBUF_i (
.O (O), // output
.I (I) // input
);
endmodule
unisims_extra/IBUFGDS.v 0 → 100644
View file @ 8dd16a59
/*******************************************************************************
* Module: IBUFGDS
* Date:2015-11-06
* Author: andrey
* Description: Module name "known" to synthesis, but missing in unisims
*
* Copyright (c) 2015 Elphel, Inc .
* IBUFGDS.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* IBUFGDS.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module IBUFGDS # (
parameter CAPACITANCE = "DONT_CARE",
parameter DIFF_TERM = "FALSE",
// parameter DQS_BIAS = "FALSE",
// parameter IBUF_DELAY_VALUE = "0",
parameter IBUF_LOW_PWR = "TRUE",
// parameter IFD_DELAY_VALUE = "AUTO",
parameter IOSTANDARD = "DEFAULT"
)(
output O,
input I,
input IB
);
ibufds_ibufgds #(
.CAPACITANCE (CAPACITANCE),
.DIFF_TERM (DIFF_TERM),
// .DQS_BIAS (HISPI_DQS_BIAS),
// .IBUF_DELAY_VALUE (HISPI_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (IBUF_LOW_PWR),
// .IFD_DELAY_VALUE (HISPI_IFD_DELAY_VALUE),
.IOSTANDARD (IOSTANDARD)
) ibufds_ibufgds_i (
.O (O), // output
.I (I), // input
.IB (IB) // input
);
endmodule
util_modules/clocks393.v
View file @ 8dd16a59
...@@ -63,25 +63,17 @@ module clocks393#( ...@@ -63,25 +63,17 @@ module clocks393#(
parameter BUF_CLK1X_SYNC = "BUFG", parameter BUF_CLK1X_SYNC = "BUFG",
parameter MEMCLK_CAPACITANCE = "DONT_CARE", parameter MEMCLK_CAPACITANCE = "DONT_CARE",
parameter MEMCLK_IBUF_DELAY_VALUE = "0",
parameter MEMCLK_IBUF_LOW_PWR = "TRUE", parameter MEMCLK_IBUF_LOW_PWR = "TRUE",
parameter MEMCLK_IFD_DELAY_VALUE = "AUTO",
parameter MEMCLK_IOSTANDARD = "DEFAULT", parameter MEMCLK_IOSTANDARD = "DEFAULT",
parameter FFCLK0_CAPACITANCE = "DONT_CARE", parameter FFCLK0_CAPACITANCE = "DONT_CARE",
parameter FFCLK0_DIFF_TERM = "FALSE", parameter FFCLK0_DIFF_TERM = "FALSE",
parameter FFCLK0_DQS_BIAS = "FALSE",
parameter FFCLK0_IBUF_DELAY_VALUE = "0",
parameter FFCLK0_IBUF_LOW_PWR = "TRUE", parameter FFCLK0_IBUF_LOW_PWR = "TRUE",
parameter FFCLK0_IFD_DELAY_VALUE = "AUTO",
parameter FFCLK0_IOSTANDARD = "DEFAULT", parameter FFCLK0_IOSTANDARD = "DEFAULT",
parameter FFCLK1_CAPACITANCE = "DONT_CARE", parameter FFCLK1_CAPACITANCE = "DONT_CARE",
parameter FFCLK1_DIFF_TERM = "FALSE", parameter FFCLK1_DIFF_TERM = "FALSE",
parameter FFCLK1_DQS_BIAS = "FALSE",
parameter FFCLK1_IBUF_DELAY_VALUE = "0",
parameter FFCLK1_IBUF_LOW_PWR = "TRUE", parameter FFCLK1_IBUF_LOW_PWR = "TRUE",
parameter FFCLK1_IFD_DELAY_VALUE = "AUTO",
parameter FFCLK1_IOSTANDARD = "DEFAULT" parameter FFCLK1_IOSTANDARD = "DEFAULT"
)( )(
...@@ -275,9 +267,7 @@ module clocks393#( ...@@ -275,9 +267,7 @@ module clocks393#(
ibuf_ibufg #( ibuf_ibufg #(
.CAPACITANCE (MEMCLK_CAPACITANCE), .CAPACITANCE (MEMCLK_CAPACITANCE),
.IBUF_DELAY_VALUE (MEMCLK_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (MEMCLK_IBUF_LOW_PWR), .IBUF_LOW_PWR (MEMCLK_IBUF_LOW_PWR),
.IFD_DELAY_VALUE (MEMCLK_IFD_DELAY_VALUE),
.IOSTANDARD (MEMCLK_IOSTANDARD) .IOSTANDARD (MEMCLK_IOSTANDARD)
) ibuf_ibufg_i ( ) ibuf_ibufg_i (
.O (memclk), // output .O (memclk), // output
...@@ -287,10 +277,7 @@ module clocks393#( ...@@ -287,10 +277,7 @@ module clocks393#(
ibufds_ibufgds #( ibufds_ibufgds #(
.CAPACITANCE (FFCLK0_CAPACITANCE), .CAPACITANCE (FFCLK0_CAPACITANCE),
.DIFF_TERM (FFCLK0_DIFF_TERM), .DIFF_TERM (FFCLK0_DIFF_TERM),
.DQS_BIAS (FFCLK0_DQS_BIAS),
.IBUF_DELAY_VALUE (FFCLK0_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (FFCLK0_IBUF_LOW_PWR), .IBUF_LOW_PWR (FFCLK0_IBUF_LOW_PWR),
.IFD_DELAY_VALUE (FFCLK0_IFD_DELAY_VALUE),
.IOSTANDARD (FFCLK0_IOSTANDARD) .IOSTANDARD (FFCLK0_IOSTANDARD)
) ibufds_ibufgds0_i ( ) ibufds_ibufgds0_i (
.O (ffclk0), // output .O (ffclk0), // output
...@@ -301,10 +288,7 @@ module clocks393#( ...@@ -301,10 +288,7 @@ module clocks393#(
ibufds_ibufgds #( ibufds_ibufgds #(
.CAPACITANCE (FFCLK1_CAPACITANCE), .CAPACITANCE (FFCLK1_CAPACITANCE),
.DIFF_TERM (FFCLK1_DIFF_TERM), .DIFF_TERM (FFCLK1_DIFF_TERM),
.DQS_BIAS (FFCLK1_DQS_BIAS),
.IBUF_DELAY_VALUE (FFCLK1_IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (FFCLK1_IBUF_LOW_PWR), .IBUF_LOW_PWR (FFCLK1_IBUF_LOW_PWR),
.IFD_DELAY_VALUE (FFCLK1_IFD_DELAY_VALUE),
.IOSTANDARD (FFCLK1_IOSTANDARD) .IOSTANDARD (FFCLK1_IOSTANDARD)
) ibufds_ibufgds10_i ( ) ibufds_ibufgds10_i (
.O (ffclk1), // output .O (ffclk1), // output
......
util_modules/clocks393m.v 0 → 100644
View file @ 8dd16a59
This diff is collapsed.
wrap/ibuf_ibufg.v
View file @ 8dd16a59
...@@ -23,6 +23,12 @@ ...@@ -23,6 +23,12 @@
The IBUF and IBUFG primitives are the same. IBUFGs are used when an input buffer is The IBUF and IBUFG primitives are the same. IBUFGs are used when an input buffer is
used as a clock input. In the Xilinx software tools, an IBUFG is automatically placed at used as a clock input. In the Xilinx software tools, an IBUFG is automatically placed at
clock input sites. clock input sites.
Actually, it still complains:
WARNING: [DRC 23-20] Rule violation (CKLD-2) Clock Net has direct IO Driver - Clock net clocks393_i/ibuf_ibufg_i/memclk_0 is directly
driven by an IO rather than a Clock Buffer. Driverx393.s: clocks393_i/ibuf_ibufg_i/IBUF_i/O[VivadoPlace:0000]
*/ */
module ibuf_ibufg #( module ibuf_ibufg #(
parameter CAPACITANCE = "DONT_CARE", parameter CAPACITANCE = "DONT_CARE",
......
wrap/ibufds_ibufgds.v
View file @ 8dd16a59
...@@ -23,6 +23,10 @@ ...@@ -23,6 +23,10 @@
/*Quote from Xilinx "7 Series FPGA SelectIO Primitives": /*Quote from Xilinx "7 Series FPGA SelectIO Primitives":
The IBUFDS and IBUFGDS primitives are the same, IBUFGDS is used when an differential The IBUFDS and IBUFGDS primitives are the same, IBUFGDS is used when an differential
input buffer is used as a clock input. input buffer is used as a clock input.
Actually, it still complains:
WARNING: [DRC 23-20] Rule violation (CKLD-2) Clock Net has direct IO Driver - Clock net clocks393_i/ibuf_ibufg_i/memclk_0 is directly driven by an IO rather than a Clock Buffer. Driverx393.s: clocks393_i/ibuf_ibufg_i/IBUF_i/O[VivadoPlace:0000]
*/ */
module ibufds_ibufgds #( module ibufds_ibufgds #(
parameter CAPACITANCE = "DONT_CARE", parameter CAPACITANCE = "DONT_CARE",
......
wrap/ibufg.v 0 → 100644
View file @ 8dd16a59
/*******************************************************************************
* Module: ibufg
* Date:2015-07-17
* Author: Andrey Filippov
* Description: Wrapper for IBUFG primitive
*
* Copyright (c) 2015 Elphel, Inc .
* ibufg.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* ibufg.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
/*Quote from Xilinx "7 Series FPGA SelectIO Primitives":
The IBUF and IBUFG primitives are the same. IBUFGs are used when an input buffer is
used as a clock input. In the Xilinx software tools, an IBUFG is automatically placed at
clock input sites.
Actually, it still complains:
WARNING: [DRC 23-20] Rule violation (CKLD-2) Clock Net has direct IO Driver - Clock net clocks393_i/ibufg_i/memclk_0 is directly
driven by an IO rather than a Clock Buffer. Driverx393.s: clocks393_i/ibufg_i/IBUF_i/O[VivadoPlace:0000]
*/
module ibufg #(
parameter CAPACITANCE = "DONT_CARE",
// parameter IBUF_DELAY_VALUE = "0",
parameter IBUF_LOW_PWR = "TRUE",
// parameter IFD_DELAY_VALUE = "AUTO",
parameter IOSTANDARD = "DEFAULT"
)(
output O,
input I
);
IBUFG #(
.CAPACITANCE (CAPACITANCE),
// .IBUF_DELAY_VALUE (IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (IBUF_LOW_PWR),
// .IFD_DELAY_VALUE (IFD_DELAY_VALUE),
.IOSTANDARD (IOSTANDARD)
) IBUFG_i (
.O (O), // output
.I (I) // input
);
endmodule
wrap/ibufgds.v 0 → 100644
View file @ 8dd16a59
/*******************************************************************************
* Module: ibufgds
* Date:2015-07-17
* Author: Andrey Filippov
* Description: Wrapper for IBUFDS primitive
*
* Copyright (c) 2015 Elphel, Inc .
* ibufgds.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* ibufgds.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
/*Quote from Xilinx "7 Series FPGA SelectIO Primitives":
The IBUFDS and IBUFGDS primitives are the same, IBUFGDS is used when an differential
input buffer is used as a clock input.
Actually, it still complains:
WARNING: [DRC 23-20] Rule violation (CKLD-2) Clock Net has direct IO Driver - Clock net clocks393_i/ibufds_ibufgds0_i/ffclk0 is directly driven by an IO rather than a Clock Buffer. Driverx393.s: clocks393_i/ibufds_ibufgds0_i/IBUFDS_i/O[VivadoPlace:0000]
*/
module ibufgds #(
parameter CAPACITANCE = "DONT_CARE",
parameter DIFF_TERM = "FALSE",
// parameter DQS_BIAS = "FALSE",
// parameter IBUF_DELAY_VALUE = "0",
parameter IBUF_LOW_PWR = "TRUE",
// parameter IFD_DELAY_VALUE = "AUTO",
parameter IOSTANDARD = "DEFAULT"
)(
output O,
input I,
input IB
);
IBUFGDS #(
.CAPACITANCE (CAPACITANCE),
.DIFF_TERM (DIFF_TERM),
// .DQS_BIAS (DQS_BIAS),
// .IBUF_DELAY_VALUE (IBUF_DELAY_VALUE),
.IBUF_LOW_PWR (IBUF_LOW_PWR),
// .IFD_DELAY_VALUE (IFD_DELAY_VALUE),
.IOSTANDARD (IOSTANDARD)
) IBUFGDS_i (
.O (O), // output
.I (I), // input
.IB (IB) // input
);
endmodule
wrap/select_clk_buf.v 0 → 100644
View file @ 8dd16a59
/*******************************************************************************
* Module: select_clk_buf
* Date:2015-11-07
* Author: andrey
* Description: Select one of the clock buffers primitives by parameter
*
* Copyright (c) 2015 Elphel, Inc .
* select_clk_buf.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* select_clk_buf.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module select_clk_buf #(
parameter BUFFER_TYPE = "BUFR" // to use clr
)(
output o,
input i,
input clr // for BUFR_only
);
generate
if (BUFFER_TYPE == "BUFG") BUFG clk1x_i (.O(o), .I(i));
else if (BUFFER_TYPE == "BUFH") BUFH clk1x_i (.O(o), .I(i));
else if (BUFFER_TYPE == "BUFR") BUFR clk1x_i (.O(o), .I(i), .CE(1'b1), .CLR(clr));
else if (BUFFER_TYPE == "BUFMR") BUFMR clk1x_i (.O(o), .I(i));
else if (BUFFER_TYPE == "BUFIO") BUFIO clk1x_i (.O(o), .I(i));
else assign o = i;
endgenerate
endmodule
x393.v
View file @ 8dd16a59
This diff is collapsed.
x393.xdc
View file @ 8dd16a59
This diff is collapsed.
x393_hispi.xdc 0 → 100644
View file @ 8dd16a59
This diff is collapsed.
x393_hispi_timing.xdc 0 → 100644
View file @ 8dd16a59
#################################################################################
# Filename: x393_timing.xdc
# Date:2014-02-25
# Author: Andrey Filippov
# Description: DDR3 controller test with axi constraints
#
# Copyright (c) 2015 Elphel, Inc.
# x393_timing.xdc is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# x393_timing.xdc is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/> .
#################################################################################
create_clock -name axi_aclk -period 20 [get_nets -hierarchical *axi_aclk]
create_generated_clock -name ddr3_sdclk [get_nets -hierarchical sdclk_pre ]
create_generated_clock -name ddr3_clk [get_nets -hierarchical clk_pre ]
create_generated_clock -name ddr3_clk_div [get_nets -hierarchical clk_div_pre ]
create_generated_clock -name ddr3_mclk [get_nets -hierarchical mclk_pre]
#create_generated_clock -name ddr3_clk_ref [get_nets -hierarchical clk_ref_pre ]
create_generated_clock -name ddr3_clk_ref [get_nets clocks393_i/dly_ref_clk_pre ]
#create_generated_clock -name axihp_clk [get_nets clocks393_i/dual_clock_axihp_i/clk1x_pre ]
create_generated_clock -name axihp_clk [get_nets clocks393_i/hclk_pre ]
#create_generated_clock -name xclk [get_nets clocks393_i/dual_clock_xclk_i/clk1x_pre ]
create_generated_clock -name xclk [get_nets clocks393_i/xclk_pre ]
#clock for inter - camera synchronization and event logger
#create_generated_clock -name sclk [get_nets clocks393_i/dual_clock_sync_clk_i/clk1x_pre ]
create_generated_clock -name sclk [get_nets clocks393_i/sync_clk_pre ]
create_clock -name ffclk0 -period 41.667 [get_ports {ffclk0p}]
#Generated clocks are assumed to be tied to clkin1 (not 2), so until external ffclk0 is constrained, derivative clocks are not generated
create_generated_clock -name pclk [get_nets clocks393_i/dual_clock_pclk_i/clk1x_pre ]
#create_generated_clock -name pclk2x [get_nets clocks393_i/dual_clock_pclk_i/clk2x_pre ]
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/ibufds_ibufgds0_i/clkin1_pre]
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block\[0\].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/ibufds_ibufgds0_i/clkin1_pre]
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block\[1\].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/ibufds_ibufgds0_i/clkin1_pre]
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block\[2\].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/ibufds_ibufgds0_i/clkin1_pre]
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block\[3\].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/ibufds_ibufgds0_i/clkin1_pre]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block\[0\].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/clk_in]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block\[1\].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/clk_in]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block\[2\].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/clk_in]
set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block\[3\].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/clk_in]
#set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets sensors393_i/sensor_channel_block[3].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/ibufds_ibufgds0_i/clkin1]
#set_property CLOCK_DEDICATED_ROUTE BACKBONE [get_nets sensors393_i/sensor_channel_block\[3\].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/ibufds_ibufgds0_i/clkin0]
#set_property CLOCK_DEDICATED_ROUTE FALSE [get_nets sensors393_i/sensor_channel_block\[3\].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/mmcm_phase_cntr_i/clkout1]
#Sensor-synchronous clocks
#create_generated_clock -name iclk0 [get_nets sensors393_i/sensor_channel_block\[0\].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/ipclk_pre ]
#create_generated_clock -name iclk2x0 [get_nets sensors393_i/sensor_channel_block\[0\].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/ipclk2x_pre ]
#create_generated_clock -name iclk1 [get_nets sensors393_i/sensor_channel_block\[1\].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/ipclk_pre ]
#create_generated_clock -name iclk2x1 [get_nets sensors393_i/sensor_channel_block\[1\].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/ipclk2x_pre ]
#create_generated_clock -name iclk2 [get_nets sensors393_i/sensor_channel_block\[2\].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/ipclk_pre ]
#create_generated_clock -name iclk2x2 [get_nets sensors393_i/sensor_channel_block\[2\].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/ipclk2x_pre ]
#create_generated_clock -name iclk3 [get_nets sensors393_i/sensor_channel_block\[3\].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/ipclk_pre ]
#create_generated_clock -name iclk2x3 [get_nets sensors393_i/sensor_channel_block\[3\].sensor_channel_i/sens_10398_i/sens_hispi12l4_i/sens_hispi_clock_i/ipclk2x_pre ]
# do not check timing between axi_aclk and other clocks. Code should provide correct asynchronous crossing of the clock boundary.
set_clock_groups -name ps_async_clock -asynchronous -group {axi_aclk}
# do not check timing between clk_axihp_pre and other clocks. Code should provide correct asynchronous crossing of the clock boundary.
set_clock_groups -name ps_async_clock_axihp -asynchronous -group {axihp_clk}
#set_clock_groups -name compressor_clocks_xclk_xclk2x -asynchronous -group {xclk xclk2x}
#set_clock_groups -name sensor_clocks_pclk_pclk2x -asynchronous -group {pclk pclk2x}
set_clock_groups -name compressor_clocks_xclk_xclk2x -asynchronous -group {xclk }
set_clock_groups -name sensor_clocks_pclk_pclk2x -asynchronous -group {pclk}
set_clock_groups -name sync_logger_clocks_sclk -asynchronous -group {sclk }
#set_clock_groups -name sensor0_clocks_iclk_pclk2x -asynchronous -group {iclk0 iclk2x0}
#set_clock_groups -name sensor1_clocks_iclk_pclk2x -asynchronous -group {iclk1 iclk2x1}
#set_clock_groups -name sensor2_clocks_iclk_pclk2x -asynchronous -group {iclk2 iclk2x2}
#set_clock_groups -name sensor3_clocks_iclk_pclk2x -asynchronous -group {iclk3 iclk2x3}
set_clock_groups -name external_clock_ffclk0 -asynchronous -group {ffclk0}
\ No newline at end of file
x393_nox2_timing.xdc
View file @ 8dd16a59
...@@ -73,14 +73,19 @@ create_generated_clock -name ddr3_sdclk [get_nets -hierarchical sdclk_pre ] ...@@ -73,14 +73,19 @@ create_generated_clock -name ddr3_sdclk [get_nets -hierarchical sdclk_pre ]
create_generated_clock -name ddr3_clk [get_nets -hierarchical clk_pre ] create_generated_clock -name ddr3_clk [get_nets -hierarchical clk_pre ]
create_generated_clock -name ddr3_clk_div [get_nets -hierarchical clk_div_pre ] create_generated_clock -name ddr3_clk_div [get_nets -hierarchical clk_div_pre ]
create_generated_clock -name ddr3_mclk [get_nets -hierarchical mclk_pre] create_generated_clock -name ddr3_mclk [get_nets -hierarchical mclk_pre]
create_generated_clock -name ddr3_clk_ref [get_nets -hierarchical clk_ref_pre ] #create_generated_clock -name ddr3_clk_ref [get_nets -hierarchical clk_ref_pre ]
create_generated_clock -name axihp_clk [get_nets clocks393_i/dual_clock_axihp_i/clk1x_pre ] create_generated_clock -name ddr3_clk_ref [get_nets clocks393_i/dly_ref_clk_pre ]
#create_generated_clock -name axihp_clk [get_nets clocks393_i/dual_clock_axihp_i/clk1x_pre ]
create_generated_clock -name axihp_clk [get_nets clocks393_i/hclk_pre ]
create_generated_clock -name xclk [get_nets clocks393_i/dual_clock_xclk_i/clk1x_pre ] #create_generated_clock -name xclk [get_nets clocks393_i/dual_clock_xclk_i/clk1x_pre ]
create_generated_clock -name xclk [get_nets clocks393_i/xclk_pre ]
#create_generated_clock -name xclk2x [get_nets clocks393_i/dual_clock_xclk_i/clk2x_pre ] #create_generated_clock -name xclk2x [get_nets clocks393_i/dual_clock_xclk_i/clk2x_pre ]
#create_generated_clock -name xclk2x [get_nets clocks393_i/xclk2x_pre ]
#clock for inter - camera synchronization and event logger #clock for inter - camera synchronization and event logger
create_generated_clock -name sclk [get_nets clocks393_i/dual_clock_sync_clk_i/clk1x_pre ] #create_generated_clock -name sclk [get_nets clocks393_i/dual_clock_sync_clk_i/clk1x_pre ]
create_generated_clock -name sclk [get_nets clocks393_i/sync_clk_pre ]
create_clock -name ffclk0 -period 41.667 [get_ports {ffclk0p}] create_clock -name ffclk0 -period 41.667 [get_ports {ffclk0p}]
#Generated clocks are assumed to be tied to clkin1 (not 2), so until external ffclk0 is constrained, derivative clocks are not generated #Generated clocks are assumed to be tied to clkin1 (not 2), so until external ffclk0 is constrained, derivative clocks are not generated
......
x393_testbench01.tf
View file @ 8dd16a59
...@@ -159,7 +159,6 @@ assign #10 gpio_pins[9] = gpio_pins[8]; ...@@ -159,7 +159,6 @@ assign #10 gpio_pins[9] = gpio_pins[8];
wire SDDMU; // inout wire SDDMU; // inout
wire DQSU; // inout wire DQSU; // inout
wire NDQSU; // inout wire NDQSU; // inout
wire DUMMY_TO_KEEP; // output to keep PS7 signals from "optimization" // SuppressThisWarning all - not used
wire memclk; wire memclk;
wire ffclk0p; // input wire ffclk0p; // input
...@@ -828,8 +827,6 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP; ...@@ -828,8 +827,6 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP;
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE), .HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.CLKIN_PERIOD (CLKIN_PERIOD), .CLKIN_PERIOD (CLKIN_PERIOD),
.CLKFBOUT_MULT (CLKFBOUT_MULT), .CLKFBOUT_MULT (CLKFBOUT_MULT),
.CLKFBOUT_MULT_REF (CLKFBOUT_MULT_REF),
.CLKFBOUT_DIV_REF (CLKFBOUT_DIV_REF),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE), .DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE), .CLKFBOUT_PHASE (CLKFBOUT_PHASE),
.SDCLK_PHASE (SDCLK_PHASE), .SDCLK_PHASE (SDCLK_PHASE),
...@@ -974,8 +971,7 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP; ...@@ -974,8 +971,7 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP;
.ffclk0p (ffclk0p), // input .ffclk0p (ffclk0p), // input
.ffclk0n (ffclk0n), // input .ffclk0n (ffclk0n), // input
.ffclk1p (ffclk1p), // input .ffclk1p (ffclk1p), // input
.ffclk1n (ffclk1n), // input .ffclk1n (ffclk1n) // input
.DUMMY_TO_KEEP(DUMMY_TO_KEEP) // to keep PS7 signals from "optimization"
); );
// just to simplify extra delays in tri-state memory bus - provide output enable // just to simplify extra delays in tri-state memory bus - provide output enable
wire WRAP_MCLK=x393_i.mclk; wire WRAP_MCLK=x393_i.mclk;
......
x393_testbench02.tf
View file @ 8dd16a59
...@@ -317,7 +317,6 @@ assign #10 gpio_pins[9] = gpio_pins[8]; ...@@ -317,7 +317,6 @@ assign #10 gpio_pins[9] = gpio_pins[8];
wire SDDMU; // inout wire SDDMU; // inout
wire DQSU; // inout wire DQSU; // inout
wire NDQSU; // inout wire NDQSU; // inout
wire DUMMY_TO_KEEP; // output to keep PS7 signals from "optimization" // SuppressThisWarning all - not used
wire memclk; wire memclk;
wire ffclk0p; // input wire ffclk0p; // input
...@@ -1292,8 +1291,6 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP; ...@@ -1292,8 +1291,6 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP;
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE), .HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.CLKIN_PERIOD (CLKIN_PERIOD), .CLKIN_PERIOD (CLKIN_PERIOD),
.CLKFBOUT_MULT (CLKFBOUT_MULT), .CLKFBOUT_MULT (CLKFBOUT_MULT),
.CLKFBOUT_MULT_REF (CLKFBOUT_MULT_REF),
.CLKFBOUT_DIV_REF (CLKFBOUT_DIV_REF),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE), .DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE), .CLKFBOUT_PHASE (CLKFBOUT_PHASE),
.CLKFBOUT_USE_FINE_PS (CLKFBOUT_USE_FINE_PS), .CLKFBOUT_USE_FINE_PS (CLKFBOUT_USE_FINE_PS),
...@@ -1439,8 +1436,7 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP; ...@@ -1439,8 +1436,7 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP;
.ffclk0p (ffclk0p), // input .ffclk0p (ffclk0p), // input
.ffclk0n (ffclk0n), // input .ffclk0n (ffclk0n), // input
.ffclk1p (ffclk1p), // input .ffclk1p (ffclk1p), // input
.ffclk1n (ffclk1n), // input .ffclk1n (ffclk1n) // input
.DUMMY_TO_KEEP(DUMMY_TO_KEEP) // to keep PS7 signals from "optimization"
); );
// just to simplify extra delays in tri-state memory bus - provide output enable // just to simplify extra delays in tri-state memory bus - provide output enable
wire WRAP_MCLK=x393_i.mclk; wire WRAP_MCLK=x393_i.mclk;
......
x393_testbench03.tf
View file @ 8dd16a59
...@@ -439,7 +439,6 @@ assign #10 gpio_pins[9] = gpio_pins[8]; ...@@ -439,7 +439,6 @@ assign #10 gpio_pins[9] = gpio_pins[8];
wire SDDMU; // inout wire SDDMU; // inout
wire DQSU; // inout wire DQSU; // inout
wire NDQSU; // inout wire NDQSU; // inout
wire DUMMY_TO_KEEP; // output to keep PS7 signals from "optimization" // SuppressThisWarning all - not used
wire memclk; wire memclk;
wire ffclk0p; // input wire ffclk0p; // input
...@@ -1420,8 +1419,6 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP; ...@@ -1420,8 +1419,6 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP;
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE), .HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.CLKIN_PERIOD (CLKIN_PERIOD), .CLKIN_PERIOD (CLKIN_PERIOD),
.CLKFBOUT_MULT (CLKFBOUT_MULT), .CLKFBOUT_MULT (CLKFBOUT_MULT),
.CLKFBOUT_MULT_REF (CLKFBOUT_MULT_REF),
.CLKFBOUT_DIV_REF (CLKFBOUT_DIV_REF),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE), .DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKFBOUT_USE_FINE_PS (CLKFBOUT_USE_FINE_PS), .CLKFBOUT_USE_FINE_PS (CLKFBOUT_USE_FINE_PS),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE), .CLKFBOUT_PHASE (CLKFBOUT_PHASE),
...@@ -1567,8 +1564,7 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP; ...@@ -1567,8 +1564,7 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP;
.ffclk0p (ffclk0p), // input .ffclk0p (ffclk0p), // input
.ffclk0n (ffclk0n), // input .ffclk0n (ffclk0n), // input
.ffclk1p (ffclk1p), // input .ffclk1p (ffclk1p), // input
.ffclk1n (ffclk1n), // input .ffclk1n (ffclk1n) // input
.DUMMY_TO_KEEP(DUMMY_TO_KEEP) // to keep PS7 signals from "optimization"
); );
// just to simplify extra delays in tri-state memory bus - provide output enable // just to simplify extra delays in tri-state memory bus - provide output enable
wire WRAP_MCLK=x393_i.mclk; wire WRAP_MCLK=x393_i.mclk;
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment