Commit 8dd16a59 authored by Andrey Filippov's avatar Andrey Filippov

Preparing for the HiSPi sensor testing

parent 71f603b7
...@@ -62,47 +62,47 @@ ...@@ -62,47 +62,47 @@
<link> <link>
<name>vivado_logs/VivadoBitstream.log</name> <name>vivado_logs/VivadoBitstream.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151105184905573.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151107161322372.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOpt.log</name> <name>vivado_logs/VivadoOpt.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151105184905573.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151107161051349.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPhys.log</name> <name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151105184905573.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151107161322372.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPower.log</name> <name>vivado_logs/VivadoOptPower.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151105184905573.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151107161051349.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoPlace.log</name> <name>vivado_logs/VivadoPlace.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151105184905573.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151107161322372.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoRoute.log</name> <name>vivado_logs/VivadoRoute.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151105184905573.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151107161322372.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoSynthesis.log</name> <name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151105184905573.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151107160339590.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name> <name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151105184905573.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151107161322372.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name> <name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20150725144907208.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20151105233458943.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimingReportImplemented.log</name> <name>vivado_logs/VivadoTimingReportImplemented.log</name>
......
...@@ -2,7 +2,7 @@ VivadoSynthesis_101_MaxMsg=10000 ...@@ -2,7 +2,7 @@ VivadoSynthesis_101_MaxMsg=10000
VivadoSynthesis_102_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@-> VivadoSynthesis_102_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@->
VivadoSynthesis_115_flatten_hierarchy=none VivadoSynthesis_115_flatten_hierarchy=none
VivadoSynthesis_121_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@-> VivadoSynthesis_121_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@->
VivadoSynthesis_122_ConstraintsFiles=x393.xdc<-@\#\#@->x393_nox2_timing.xdc<-@\#\#@-> VivadoSynthesis_122_ConstraintsFiles=x393_hispi.xdc<-@\#\#@->x393_hispi_timing.xdc<-@\#\#@->
VivadoSynthesis_122_SkipSnapshotSynth=true VivadoSynthesis_122_SkipSnapshotSynth=true
VivadoSynthesis_123_ResetProject=true VivadoSynthesis_123_ResetProject=true
VivadoSynthesis_123_SkipSnapshotSynth=true VivadoSynthesis_123_SkipSnapshotSynth=true
......
...@@ -203,10 +203,6 @@ set_property PACKAGE_PIN L5 [get_ports {SDDML}] ...@@ -203,10 +203,6 @@ set_property PACKAGE_PIN L5 [get_ports {SDDML}]
set_property IOSTANDARD SSTL15 [get_ports {SDDMU}] set_property IOSTANDARD SSTL15 [get_ports {SDDMU}]
set_property PACKAGE_PIN J5 [get_ports {SDDMU}] set_property PACKAGE_PIN J5 [get_ports {SDDMU}]
# output DUMMY_TO_KEEP, // to keep PS7 signals from "optimization"
set_property IOSTANDARD SSTL15 [get_ports {DUMMY_TO_KEEP}]
set_property PACKAGE_PIN E3 [get_ports {DUMMY_TO_KEEP}]
#not yet used, just for debugging #not yet used, just for debugging
# input MEMCLK, // to keep PS7 signals from "optimization" # input MEMCLK, // to keep PS7 signals from "optimization"
set_property IOSTANDARD SSTL15 [get_ports {MEMCLK}] set_property IOSTANDARD SSTL15 [get_ports {MEMCLK}]
......
parameter FPGA_VERSION = 32'h0393006a; // modified clock generation, trying with HiSPi - 72.77% utilization
parameter FPGA_VERSION = 32'h03930066; // trying just one histogram to watch utilization - with 4 was: Slice 15913 (80.98%), now Slice = 14318 (72.87%) // parameter FPGA_VERSION = 32'h03930069; // modified clock generation, rebuilding for parallel sensors - all met, 71.8% utilization
// parameter FPGA_VERSION = 32'h03930068; // trying BUFR/FUFIO on all sensors ipclk/ipclk2x
// parameter FPGA_VERSION = 32'h03930067; // removing DUMMY_TO_KEEP, moving IOSTANDARD to HDL code
// parameter FPGA_VERSION = 32'h03930066; // trying just one histogram to watch utilization - with 4 was: Slice 15913 (80.98%), now Slice = 14318 (72.87%)
// parameter FPGA_VERSION = 32'h03930065; // (same rev) all met, using "old" (non-inverted) phase - OK (full phase range) // parameter FPGA_VERSION = 32'h03930065; // (same rev) all met, using "old" (non-inverted) phase - OK (full phase range)
// parameter FPGA_VERSION = 32'h03930065; // switch phy_top.v (all met) - OK with inverted phase control (reduced phase range) // parameter FPGA_VERSION = 32'h03930065; // switch phy_top.v (all met) - OK with inverted phase control (reduced phase range)
// parameter FPGA_VERSION = 32'h03930064; // switch mcomtr_sequencer.v (xclk not met) - wrong! // parameter FPGA_VERSION = 32'h03930064; // switch mcomtr_sequencer.v (xclk not met) - wrong!
......
This diff is collapsed.
...@@ -142,15 +142,11 @@ module mcntrl393 #( ...@@ -142,15 +142,11 @@ module mcntrl393 #(
parameter HIGH_PERFORMANCE_MODE = "FALSE", parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter CLKIN_PERIOD = 20, // 10, //ns >1.25, 600<Fvco<1200 // Hardware 150MHz , change to | 6.667 parameter CLKIN_PERIOD = 20, // 10, //ns >1.25, 600<Fvco<1200 // Hardware 150MHz , change to | 6.667
parameter CLKFBOUT_MULT = 16, // 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE | 16 parameter CLKFBOUT_MULT = 16, // 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE | 16
parameter CLKFBOUT_MULT_REF = 16, // 18, // 9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE | 6
parameter CLKFBOUT_DIV_REF = 4, // 200Mhz 3, // To get 300MHz for the reference clock
`else `else
parameter real REFCLK_FREQUENCY = 300.0, parameter real REFCLK_FREQUENCY = 300.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE", parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter CLKIN_PERIOD = 10, //ns >1.25, 600<Fvco<1200 parameter CLKIN_PERIOD = 10, //ns >1.25, 600<Fvco<1200
parameter CLKFBOUT_MULT = 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE parameter CLKFBOUT_MULT = 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_MULT_REF = 9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_DIV_REF = 3, // To get 300MHz for the reference clock
`endif `endif
parameter DIVCLK_DIVIDE= 1, parameter DIVCLK_DIVIDE= 1,
parameter CLKFBOUT_USE_FINE_PS= 1, // 0 - old, 1 - new parameter CLKFBOUT_USE_FINE_PS= 1, // 0 - old, 1 - new
...@@ -251,7 +247,7 @@ module mcntrl393 #( ...@@ -251,7 +247,7 @@ module mcntrl393 #(
output mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port output mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port
input mrst, // @posedge mclk synchronous reset - should not interrupt mclk generation input mrst, // @posedge mclk synchronous reset - should not interrupt mclk generation
output locked, // to generate sync reset output locked, // to generate sync reset
output ref_clk, // global clock for idelay_ctrl calibration input ref_clk, // global clock for idelay_ctrl calibration
output idelay_ctrl_reset, output idelay_ctrl_reset,
// programming interface // programming interface
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3 input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
...@@ -402,9 +398,6 @@ module mcntrl393 #( ...@@ -402,9 +398,6 @@ module mcntrl393 #(
inout DQSU, // UDQS I/O pad inout DQSU, // UDQS I/O pad
inout NDQSU //, inout NDQSU //,
// output DUMMY_TO_KEEP // to keep PS7 signals from "optimization"
// input MEMCLK
// temporary debug data
,output [11:0] tmp_debug // add some signals generated here? ,output [11:0] tmp_debug // add some signals generated here?
); );
localparam COL_WDTH = COLADDR_NUMBER-3; // number of column address bits in bursts localparam COL_WDTH = COLADDR_NUMBER-3; // number of column address bits in bursts
...@@ -1814,8 +1807,6 @@ module mcntrl393 #( ...@@ -1814,8 +1807,6 @@ module mcntrl393 #(
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE), .HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.CLKIN_PERIOD (CLKIN_PERIOD), .CLKIN_PERIOD (CLKIN_PERIOD),
.CLKFBOUT_MULT (CLKFBOUT_MULT), .CLKFBOUT_MULT (CLKFBOUT_MULT),
.CLKFBOUT_MULT_REF (CLKFBOUT_MULT_REF),
.CLKFBOUT_DIV_REF (CLKFBOUT_DIV_REF),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE), .DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKFBOUT_USE_FINE_PS (CLKFBOUT_USE_FINE_PS), .CLKFBOUT_USE_FINE_PS (CLKFBOUT_USE_FINE_PS),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE), .CLKFBOUT_PHASE (CLKFBOUT_PHASE),
...@@ -1835,7 +1826,7 @@ module mcntrl393 #( ...@@ -1835,7 +1826,7 @@ module mcntrl393 #(
.mclk (mclk), // output .mclk (mclk), // output
.mrst (mrst), // input .mrst (mrst), // input
.locked (locked), // output .locked (locked), // output
.ref_clk (ref_clk), // output .ref_clk (ref_clk), // input
.idelay_ctrl_reset (idelay_ctrl_reset), // output .idelay_ctrl_reset (idelay_ctrl_reset), // output
.cmd_ad (cmd_mcontr_ad), // input[7:0] .cmd_ad (cmd_mcontr_ad), // input[7:0]
.cmd_stb (cmd_mcontr_stb), // input .cmd_stb (cmd_mcontr_stb), // input
......
...@@ -115,15 +115,11 @@ module memctrl16 #( ...@@ -115,15 +115,11 @@ module memctrl16 #(
parameter HIGH_PERFORMANCE_MODE = "FALSE", parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter CLKIN_PERIOD = 20, // 10, //ns >1.25, 600<Fvco<1200 // Hardware 150MHz , change to | 6.667 parameter CLKIN_PERIOD = 20, // 10, //ns >1.25, 600<Fvco<1200 // Hardware 150MHz , change to | 6.667
parameter CLKFBOUT_MULT = 16, // 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE | 16 parameter CLKFBOUT_MULT = 16, // 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE | 16
parameter CLKFBOUT_MULT_REF = 16, // 18, // 9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE | 6
parameter CLKFBOUT_DIV_REF = 4, // 200Mhz 3, // To get 300MHz for the reference clock
`else `else
parameter real REFCLK_FREQUENCY = 300.0, parameter real REFCLK_FREQUENCY = 300.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE", parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter CLKIN_PERIOD = 10, //ns >1.25, 600<Fvco<1200 parameter CLKIN_PERIOD = 10, //ns >1.25, 600<Fvco<1200
parameter CLKFBOUT_MULT = 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE parameter CLKFBOUT_MULT = 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_MULT_REF = 9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_DIV_REF = 3, // To get 300MHz for the reference clock
`endif `endif
parameter DIVCLK_DIVIDE= 1, parameter DIVCLK_DIVIDE= 1,
parameter CLKFBOUT_USE_FINE_PS= 1, // 0 - old, 1 - new parameter CLKFBOUT_USE_FINE_PS= 1, // 0 - old, 1 - new
...@@ -144,7 +140,7 @@ module memctrl16 #( ...@@ -144,7 +140,7 @@ module memctrl16 #(
output mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port output mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port
input mrst, // @posedge mclk synchronous reset - should not interrupt mclk generation input mrst, // @posedge mclk synchronous reset - should not interrupt mclk generation
output locked, // to generate sync reset output locked, // to generate sync reset
output ref_clk, // global clock for idelay_ctrl calibration input ref_clk, // global clock for idelay_ctrl calibration
output idelay_ctrl_reset, output idelay_ctrl_reset,
// programming interface // programming interface
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3 input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
...@@ -541,8 +537,6 @@ module memctrl16 #( ...@@ -541,8 +537,6 @@ module memctrl16 #(
output SDDMU, // UDM I/O pad (actually only output) output SDDMU, // UDM I/O pad (actually only output)
inout DQSU, // UDQS I/O pad inout DQSU, // UDQS I/O pad
inout NDQSU //, inout NDQSU //,
// output DUMMY_TO_KEEP // to keep PS7 signals from "optimization"
// input MEMCLK
// temporary debug data // temporary debug data
,output [11:0] tmp_debug // add some signals generated here? ,output [11:0] tmp_debug // add some signals generated here?
); );
...@@ -903,8 +897,6 @@ end ...@@ -903,8 +897,6 @@ end
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE), .HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.CLKIN_PERIOD (CLKIN_PERIOD), .CLKIN_PERIOD (CLKIN_PERIOD),
.CLKFBOUT_MULT (CLKFBOUT_MULT), .CLKFBOUT_MULT (CLKFBOUT_MULT),
.CLKFBOUT_MULT_REF (CLKFBOUT_MULT_REF),
.CLKFBOUT_DIV_REF (CLKFBOUT_DIV_REF),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE), .DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKFBOUT_USE_FINE_PS (CLKFBOUT_USE_FINE_PS), .CLKFBOUT_USE_FINE_PS (CLKFBOUT_USE_FINE_PS),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE), .CLKFBOUT_PHASE (CLKFBOUT_PHASE),
...@@ -942,7 +934,7 @@ end ...@@ -942,7 +934,7 @@ end
.mclk (mclk), // output .mclk (mclk), // output
.mrst (mrst), // input .mrst (mrst), // input
.locked (locked), // output .locked (locked), // output
.ref_clk (ref_clk), // output .ref_clk (ref_clk), // input
.idelay_ctrl_reset (idelay_ctrl_reset), .idelay_ctrl_reset (idelay_ctrl_reset),
.cmd0_clk (cmd0_clk), // input .cmd0_clk (cmd0_clk), // input
......
...@@ -77,8 +77,6 @@ module mcontr_sequencer #( ...@@ -77,8 +77,6 @@ module mcontr_sequencer #(
parameter HIGH_PERFORMANCE_MODE = "FALSE", parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter CLKIN_PERIOD = 10, //ns >1.25, 600<Fvco<1200 parameter CLKIN_PERIOD = 10, //ns >1.25, 600<Fvco<1200
parameter CLKFBOUT_MULT = 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE parameter CLKFBOUT_MULT = 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_MULT_REF = 9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_DIV_REF = 3, // To get 300MHz for the reference clock
parameter DIVCLK_DIVIDE= 1, parameter DIVCLK_DIVIDE= 1,
parameter CLKFBOUT_USE_FINE_PS= 1, // 0 - old, 1 - new parameter CLKFBOUT_USE_FINE_PS= 1, // 0 - old, 1 - new
parameter CLKFBOUT_PHASE = 0.000, parameter CLKFBOUT_PHASE = 0.000,
...@@ -118,7 +116,7 @@ module mcontr_sequencer #( ...@@ -118,7 +116,7 @@ module mcontr_sequencer #(
output mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port output mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port
input mrst, // @posedge mclk, sync reset (should not interrupt mclk!) input mrst, // @posedge mclk, sync reset (should not interrupt mclk!)
output locked, // to generate sync reset output locked, // to generate sync reset
output ref_clk, // global clock for idelay_ctrl calibration input ref_clk, // global clock for idelay_ctrl calibration
output idelay_ctrl_reset, output idelay_ctrl_reset,
// command port 0 (filled by software - 32w->32r) - used for mode set, refresh, write levelling, ... // command port 0 (filled by software - 32w->32r) - used for mode set, refresh, write levelling, ...
input cmd0_clk, input cmd0_clk,
...@@ -549,8 +547,6 @@ module mcontr_sequencer #( ...@@ -549,8 +547,6 @@ module mcontr_sequencer #(
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE), .HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.CLKIN_PERIOD (CLKIN_PERIOD), .CLKIN_PERIOD (CLKIN_PERIOD),
.CLKFBOUT_MULT (CLKFBOUT_MULT), .CLKFBOUT_MULT (CLKFBOUT_MULT),
.CLKFBOUT_MULT_REF (CLKFBOUT_MULT_REF),
.CLKFBOUT_DIV_REF (CLKFBOUT_DIV_REF),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE), .DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKFBOUT_USE_FINE_PS (CLKFBOUT_USE_FINE_PS), .CLKFBOUT_USE_FINE_PS (CLKFBOUT_USE_FINE_PS),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE), .CLKFBOUT_PHASE (CLKFBOUT_PHASE),
...@@ -586,7 +582,7 @@ module mcontr_sequencer #( ...@@ -586,7 +582,7 @@ module mcontr_sequencer #(
.rst_in (rst_in), // input .rst_in (rst_in), // input
.mclk (mclk), // output .mclk (mclk), // output
.mrst (mrst), // input .mrst (mrst), // input
.ref_clk (ref_clk), // output .ref_clk (ref_clk), // input
.idelay_ctrl_reset (idelay_ctrl_reset), // output .idelay_ctrl_reset (idelay_ctrl_reset), // output
.dly_data (dly_data[7:0]), // input[7:0] .dly_data (dly_data[7:0]), // input[7:0]
.dly_addr (dly_addr[6:0]), // input[6:0] .dly_addr (dly_addr[6:0]), // input[6:0]
......
...@@ -33,8 +33,6 @@ module phy_cmd#( ...@@ -33,8 +33,6 @@ module phy_cmd#(
parameter HIGH_PERFORMANCE_MODE = "FALSE", parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter CLKIN_PERIOD = 10, //ns >1.25, 600<Fvco<1200 parameter CLKIN_PERIOD = 10, //ns >1.25, 600<Fvco<1200
parameter CLKFBOUT_MULT = 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE parameter CLKFBOUT_MULT = 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_MULT_REF = 9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_DIV_REF = 3, // To get 300MHz for the reference clock
parameter DIVCLK_DIVIDE= 1, parameter DIVCLK_DIVIDE= 1,
parameter CLKFBOUT_USE_FINE_PS= 1, // 0 - old, 1 - new parameter CLKFBOUT_USE_FINE_PS= 1, // 0 - old, 1 - new
parameter CLKFBOUT_PHASE = 0.000, parameter CLKFBOUT_PHASE = 0.000,
...@@ -73,7 +71,7 @@ module phy_cmd#( ...@@ -73,7 +71,7 @@ module phy_cmd#(
input rst_in, input rst_in,
output mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port output mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port
input mrst, // @posedge mclk synchronous reset - should not interrupt mclk generation input mrst, // @posedge mclk synchronous reset - should not interrupt mclk generation
output ref_clk, // global clock for idelay_ctrl calibration input ref_clk, // global clock for idelay_ctrl calibration
output idelay_ctrl_reset, output idelay_ctrl_reset,
// inteface to control I/O delays and mmcm // inteface to control I/O delays and mmcm
input [7:0] dly_data, // delay value (3 LSB - fine delay) input [7:0] dly_data, // delay value (3 LSB - fine delay)
...@@ -377,8 +375,6 @@ module phy_cmd#( ...@@ -377,8 +375,6 @@ module phy_cmd#(
.BANDWIDTH ("OPTIMIZED"), .BANDWIDTH ("OPTIMIZED"),
.CLKIN_PERIOD (CLKIN_PERIOD), .CLKIN_PERIOD (CLKIN_PERIOD),
.CLKFBOUT_MULT (CLKFBOUT_MULT), .CLKFBOUT_MULT (CLKFBOUT_MULT),
.CLKFBOUT_MULT_REF(CLKFBOUT_MULT_REF),
.CLKFBOUT_DIV_REF (CLKFBOUT_DIV_REF),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE), .DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKFBOUT_USE_FINE_PS (CLKFBOUT_USE_FINE_PS), .CLKFBOUT_USE_FINE_PS (CLKFBOUT_USE_FINE_PS),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE), .CLKFBOUT_PHASE (CLKFBOUT_PHASE),
...@@ -413,7 +409,7 @@ module phy_cmd#( ...@@ -413,7 +409,7 @@ module phy_cmd#(
.clk_div (clk_div), // output .clk_div (clk_div), // output
.mclk (mclk), // output .mclk (mclk), // output
.mrst (mrst), // input .mrst (mrst), // input
.ref_clk (ref_clk), // output .ref_clk (ref_clk), // input
.idelay_ctrl_reset (idelay_ctrl_reset), // output .idelay_ctrl_reset (idelay_ctrl_reset), // output
.rst_in (rst_in), // input .rst_in (rst_in), // input
......
...@@ -40,8 +40,6 @@ module phy_top #( ...@@ -40,8 +40,6 @@ module phy_top #(
// Assuming 100MHz input clock, 800MHz Fvco, 400MHz clk, 200MHz clk_div, 200MHz mclk // Assuming 100MHz input clock, 800MHz Fvco, 400MHz clk, 200MHz clk_div, 200MHz mclk
parameter CLKIN_PERIOD = 10, //ns >1.25, 600<Fvco<1200 parameter CLKIN_PERIOD = 10, //ns >1.25, 600<Fvco<1200
parameter CLKFBOUT_MULT = 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE parameter CLKFBOUT_MULT = 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_MULT_REF = 9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_DIV_REF = 3, // To get 300MHz for the reference clock
parameter DIVCLK_DIVIDE= 1, parameter DIVCLK_DIVIDE= 1,
parameter CLKFBOUT_USE_FINE_PS =1, // if 1 move CLKFBOUT_PHASE and SDCLK_PHASE, if 0 - other outputs (moved phases should be 0/same) parameter CLKFBOUT_USE_FINE_PS =1, // if 1 move CLKFBOUT_PHASE and SDCLK_PHASE, if 0 - other outputs (moved phases should be 0/same)
parameter CLKFBOUT_PHASE = 0.000, parameter CLKFBOUT_PHASE = 0.000,
...@@ -78,7 +76,7 @@ module phy_top #( ...@@ -78,7 +76,7 @@ module phy_top #(
output clk_div, // free-running half clk frequency, front aligned to clk (shared for R/W), BUFR output output clk_div, // free-running half clk frequency, front aligned to clk (shared for R/W), BUFR output
output mclk, // same as clk_div, through separate BUFG and static phase adjust output mclk, // same as clk_div, through separate BUFG and static phase adjust
input mrst, // @posedge mclk synchronous reset - should not interrupt mclk generation input mrst, // @posedge mclk synchronous reset - should not interrupt mclk generation
output ref_clk, // global clock for idelay_ctrl calibration input ref_clk, // global clock for idelay_ctrl calibration
output idelay_ctrl_reset, output idelay_ctrl_reset,
input rst_in, // reset delays/serdes - global reset? input rst_in, // reset delays/serdes - global reset?
input ddr_rst, // active high - generate NRST to memory input ddr_rst, // active high - generate NRST to memory
...@@ -120,14 +118,9 @@ module phy_top #( ...@@ -120,14 +118,9 @@ module phy_top #(
output ps_rdy, output ps_rdy,
output [PHASE_WIDTH-1:0] ps_out output [PHASE_WIDTH-1:0] ps_out
); );
assign locked_pll = 1; // not used anymore, reference clock generation moved to other module
reg rst= 1'b1; reg rst= 1'b1;
// always @(negedge clk_div or posedge rst_in) begin // Why is it @ negedge clk_div?
// if (rst_in) rst <= 1'b1;
// else rst <= 1'b0;
// end
// always @(negedge clk_div) begin // Why is it @ negedge clk_div?
always @(posedge clk_div) begin // Why is it @ negedge clk_div? always @(posedge clk_div) begin // Why is it @ negedge clk_div?
if (mrst) rst <= 1'b1; if (mrst) rst <= 1'b1;
else rst <= 1'b0; else rst <= 1'b0;
...@@ -137,27 +130,15 @@ module phy_top #( ...@@ -137,27 +130,15 @@ module phy_top #(
wire ld_data_h = (dly_addr[6:5] == 2'h1) && ld_delay ; wire ld_data_h = (dly_addr[6:5] == 2'h1) && ld_delay ;
wire ld_cmda = (dly_addr[6:5] == 2'h2) && ld_delay ; wire ld_cmda = (dly_addr[6:5] == 2'h2) && ld_delay ;
wire ld_mmcm= (dly_addr[6:0] == 7'h60) && ld_delay ; wire ld_mmcm= (dly_addr[6:0] == 7'h60) && ld_delay ;
wire clkfb_ref, clk_ref_pre; // wire clkfb_ref, clk_ref_pre;
// wire ref_clk; // 200MHz/300Mhz to calibrate I/O delays
// wire locked_mmcm,locked_pll, dly_ready, dci_ready;
// assign locked=locked_mmcm && locked_pll && dly_ready && dci_ready; // both PLL ready, I/O delay calibrated
wire clkin_stopped_mmcm; wire clkin_stopped_mmcm;
wire clkfb_stopped_mmcm; wire clkfb_stopped_mmcm;
reg dbg1=0; reg dbg1=0;
reg dbg2=0; reg dbg2=0;
/*
always @ (posedge rst_in or posedge mclk) begin
if (rst_in) dbg1 <= 0;
else dbg1 <= ~dbg1;
end
always @ (posedge rst_in or posedge clk_div) begin
if (rst_in) dbg2 <= 0;
else dbg2 <= ~dbg2;
end
*/
always @ (posedge mclk) begin always @ (posedge mclk) begin
if (mrst) dbg1 <= 0; if (mrst) dbg1 <= 0;
else dbg1 <= ~dbg1; else dbg1 <= ~dbg1;
...@@ -316,10 +297,7 @@ BUFR clk_bufr_i (.O(clk), .CE(), .CLR(), .I(clk_pre)); ...@@ -316,10 +297,7 @@ BUFR clk_bufr_i (.O(clk), .CE(), .CLR(), .I(clk_pre));
//BUFIO clk_buf_i (.O(clk), .I(clk_pre)); //BUFIO clk_buf_i (.O(clk), .I(clk_pre));
BUFR clk_div_bufr_i (.O(clk_div), .CE(), .CLR(), .I(clk_div_pre)); BUFR clk_div_bufr_i (.O(clk_div), .CE(), .CLR(), .I(clk_div_pre));
BUFIO iclk_bufio_i (.O(sdclk), .I(sdclk_pre) ); BUFIO iclk_bufio_i (.O(sdclk), .I(sdclk_pre) );
//BUFIO clk_ref_i (.O(ref_clk), .I(clk_ref_pre)); ///BUFG clk_ref_i (.O(ref_clk), .I(clk_ref_pre));
//assign ref_clk=clk_ref_pre;
//BUFH clk_ref_i (.O(ref_clk), .I(clk_ref_pre));
BUFG clk_ref_i (.O(ref_clk), .I(clk_ref_pre));
BUFG mclk_i (.O(mclk),.I(mclk_pre) ); BUFG mclk_i (.O(mclk),.I(mclk_pre) );
mmcm_phase_cntr #( mmcm_phase_cntr #(
.PHASE_WIDTH (PHASE_WIDTH), .PHASE_WIDTH (PHASE_WIDTH),
...@@ -390,30 +368,6 @@ BUFG mclk_i (.O(mclk),.I(mclk_pre) ); ...@@ -390,30 +368,6 @@ BUFG mclk_i (.O(mclk),.I(mclk_pre) );
.clkfb_stopped (clkfb_stopped_mmcm) // output .clkfb_stopped (clkfb_stopped_mmcm) // output
// output // output
); );
// Generate reference clock for the I/O delays
pll_base #(
.CLKIN_PERIOD(CLKIN_PERIOD),
.BANDWIDTH("OPTIMIZED"),
.CLKFBOUT_MULT(CLKFBOUT_MULT_REF),
.CLKOUT0_DIVIDE(CLKFBOUT_DIV_REF),
.REF_JITTER1(0.010),
.STARTUP_WAIT("FALSE")
) pll_base_i (
.clkin(clk_in), // input
.clkfbin(clkfb_ref), // input
// .rst(rst), // input
.rst(rst_in), // input
.pwrdwn(1'b0), // input
.clkout0(clk_ref_pre), // output
.clkout1(), // output
.clkout2(), // output
.clkout3(), // output
.clkout4(), // output
.clkout5(), // output
.clkfbout(clkfb_ref), // output
.locked(locked_pll) // output
);
// Does it need to be re-calibrated periodically - yes when temperature changes, same as dci_reset // Does it need to be re-calibrated periodically - yes when temperature changes, same as dci_reset
assign idelay_ctrl_reset = rst || dly_rst; assign idelay_ctrl_reset = rst || dly_rst;
idelay_ctrl# ( idelay_ctrl# (
......
...@@ -76,18 +76,21 @@ module sens_10398 #( ...@@ -76,18 +76,21 @@ module sens_10398 #(
parameter HISPI_MSB_FIRST = 0, parameter HISPI_MSB_FIRST = 0,
parameter HISPI_NUMLANES = 4, parameter HISPI_NUMLANES = 4,
parameter HISPI_DELAY_CLK = "FALSE",
parameter HISPI_MMCM = "TRUE",
parameter HISPI_CAPACITANCE = "DONT_CARE", parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "TRUE", parameter HISPI_DIFF_TERM = "TRUE",
parameter HISPI_DQS_BIAS = "TRUE", parameter HISPI_DQS_BIAS = "TRUE",
parameter HISPI_IBUF_DELAY_VALUE = "0", parameter HISPI_IBUF_DELAY_VALUE = "0",
parameter HISPI_IBUF_LOW_PWR = "TRUE", parameter HISPI_IBUF_LOW_PWR = "TRUE",
parameter HISPI_IFD_DELAY_VALUE = "AUTO", parameter HISPI_IFD_DELAY_VALUE = "AUTO",
parameter HISPI_IOSTANDARD = "DEFAULT", parameter HISPI_IOSTANDARD = "DIFF_SSTL18_I", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
// Other (non-HiSPi) sensor I/Os // Other (non-HiSPi) sensor I/Os
parameter integer PXD_DRIVE = 12, parameter integer PXD_DRIVE = 12,
parameter PXD_IBUF_LOW_PWR = "TRUE", parameter PXD_IBUF_LOW_PWR = "TRUE",
parameter PXD_IOSTANDARD = "DEFAULT", // 1.8V single-ended parameter PXD_IOSTANDARD = "LVCMOS18", // 1.8V single-ended
parameter PXD_SLEW = "SLOW", parameter PXD_SLEW = "SLOW",
parameter PXD_CAPACITANCE = "DONT_CARE", parameter PXD_CAPACITANCE = "DONT_CARE",
parameter PXD_CLK_DIV = 10, // 220MHz -> 22MHz parameter PXD_CLK_DIV = 10, // 220MHz -> 22MHz
...@@ -324,6 +327,8 @@ module sens_10398 #( ...@@ -324,6 +327,8 @@ module sens_10398 #(
.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD), .SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD),
.HISPI_MSB_FIRST (HISPI_MSB_FIRST), .HISPI_MSB_FIRST (HISPI_MSB_FIRST),
.HISPI_NUMLANES (HISPI_NUMLANES), .HISPI_NUMLANES (HISPI_NUMLANES),
.HISPI_DELAY_CLK (HISPI_DELAY_CLK),
.HISPI_MMCM (HISPI_MMCM),
.HISPI_CAPACITANCE (HISPI_CAPACITANCE), .HISPI_CAPACITANCE (HISPI_CAPACITANCE),
.HISPI_DIFF_TERM (HISPI_DIFF_TERM), .HISPI_DIFF_TERM (HISPI_DIFF_TERM),
.HISPI_DQS_BIAS (HISPI_DQS_BIAS), .HISPI_DQS_BIAS (HISPI_DQS_BIAS),
...@@ -356,16 +361,43 @@ module sens_10398 #( ...@@ -356,16 +361,43 @@ module sens_10398 #(
.clkin_pxd_stopped_mmcm (clkin_pxd_stopped_mmcm), // output .clkin_pxd_stopped_mmcm (clkin_pxd_stopped_mmcm), // output
.clkfb_pxd_stopped_mmcm (clkfb_pxd_stopped_mmcm) // output .clkfb_pxd_stopped_mmcm (clkfb_pxd_stopped_mmcm) // output
); );
/*
obufds #( obufds #(
.CAPACITANCE("DONT_CARE"), .CAPACITANCE("DONT_CARE"),
.IOSTANDARD("DEFAULT"), .IOSTANDARD(PXD_IOSTANDARD), // not diff, just opposite phase signals
.SLEW("SLOW") .SLEW("SLOW")
) obufds_i ( ) obufds_i (
.o (sens_ext_clk_p), // output .o (sens_ext_clk_p), // output
.ob (sens_ext_clk_n), // output .ob (sens_ext_clk_n), // output
.i (pxd_clk_cntr[PXD_CLK_DIV_BITS-1]) // input .i (pxd_clk_cntr[PXD_CLK_DIV_BITS-1]) // input
); );
*/
// reg [1:0] ext_clk_r;
// always @(posedge pclk) begin
// ext_clk_r <= {pxd_clk_cntr[PXD_CLK_DIV_BITS-1], !pxd_clk_cntr[PXD_CLK_DIV_BITS-1]};
// end
obuf #(
.CAPACITANCE (PXD_CAPACITANCE),
.DRIVE (PXD_DRIVE),
.IOSTANDARD (PXD_IOSTANDARD),
.SLEW (PXD_SLEW)
) ext_clk_p_i (
.O (sens_ext_clk_p), // output
.I (pxd_clk_cntr[PXD_CLK_DIV_BITS-1]) //ext_clk_r[0]) // input
);
obuf #(
.CAPACITANCE (PXD_CAPACITANCE),
.DRIVE (PXD_DRIVE),
.IOSTANDARD (PXD_IOSTANDARD),
.SLEW (PXD_SLEW)
) ext_clk_n_i (
.O (sens_ext_clk_n), // output
.I (iarst) // ~pxd_clk_cntr[PXD_CLK_DIV_BITS-1]) // ext_clk_r[1]) // input
);
// Probe programmable/ control PROGRAM pin // Probe programmable/ control PROGRAM pin
reg [1:0] xpgmen_d; reg [1:0] xpgmen_d;
reg force_senspgm=0; reg force_senspgm=0;
......
...@@ -46,13 +46,15 @@ module sens_hispi12l4#( ...@@ -46,13 +46,15 @@ module sens_hispi12l4#(
parameter HISPI_MSB_FIRST = 0, parameter HISPI_MSB_FIRST = 0,
parameter HISPI_NUMLANES = 4, parameter HISPI_NUMLANES = 4,
parameter HISPI_DELAY_CLK = "FALSE",
parameter HISPI_MMCM = "TRUE",
parameter HISPI_CAPACITANCE = "DONT_CARE", parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "TRUE", parameter HISPI_DIFF_TERM = "TRUE",
parameter HISPI_DQS_BIAS = "TRUE", parameter HISPI_DQS_BIAS = "TRUE",
parameter HISPI_IBUF_DELAY_VALUE = "0", parameter HISPI_IBUF_DELAY_VALUE = "0",
parameter HISPI_IBUF_LOW_PWR = "TRUE", parameter HISPI_IBUF_LOW_PWR = "TRUE",
parameter HISPI_IFD_DELAY_VALUE = "AUTO", parameter HISPI_IFD_DELAY_VALUE = "AUTO",
parameter HISPI_IOSTANDARD = "DEFAULT", parameter HISPI_IOSTANDARD = "DIFF_SSTL18_I", //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA),
parameter HISPI_KEEP_IRST = 5 // number of cycles to keep irst on after release of prst (small number - use 1 hot) parameter HISPI_KEEP_IRST = 5 // number of cycles to keep irst on after release of prst (small number - use 1 hot)
)( )(
input pclk, // global clock input, pixel rate (220MHz for MT9F002) input pclk, // global clock input, pixel rate (220MHz for MT9F002)
...@@ -112,6 +114,14 @@ module sens_hispi12l4#( ...@@ -112,6 +114,14 @@ module sens_hispi12l4#(
.SENS_SS_EN (SENS_SS_EN), .SENS_SS_EN (SENS_SS_EN),
.SENS_SS_MODE (SENS_SS_MODE), .SENS_SS_MODE (SENS_SS_MODE),
.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD), .SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD),
.IODELAY_GRP (IODELAY_GRP),
.IDELAY_VALUE (IDELAY_VALUE),
.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.HISPI_DELAY_CLK (HISPI_DELAY_CLK),
.HISPI_MMCM (HISPI_MMCM),
.HISPI_CAPACITANCE (HISPI_CAPACITANCE), .HISPI_CAPACITANCE (HISPI_CAPACITANCE),
.HISPI_DIFF_TERM (HISPI_DIFF_TERM), .HISPI_DIFF_TERM (HISPI_DIFF_TERM),
.HISPI_DQS_BIAS (HISPI_DQS_BIAS), .HISPI_DQS_BIAS (HISPI_DQS_BIAS),
...@@ -124,6 +134,7 @@ module sens_hispi12l4#( ...@@ -124,6 +134,7 @@ module sens_hispi12l4#(
.mrst (mrst), // input .mrst (mrst), // input
.phase (dly_data[7:0]), // input[7:0] .phase (dly_data[7:0]), // input[7:0]
.set_phase (set_clk_phase), // input .set_phase (set_clk_phase), // input
.load (ld_idelay), // input
.rst_mmcm (rst_mmcm), // input .rst_mmcm (rst_mmcm), // input
.clp_p (sns_clkp), // input .clp_p (sns_clkp), // input
.clk_n (sns_clkn), // input .clk_n (sns_clkn), // input
......
This diff is collapsed.
...@@ -33,7 +33,7 @@ module sens_hispi_din #( ...@@ -33,7 +33,7 @@ module sens_hispi_din #(
parameter HISPI_IBUF_DELAY_VALUE = "0", parameter HISPI_IBUF_DELAY_VALUE = "0",
parameter HISPI_IBUF_LOW_PWR = "TRUE", parameter HISPI_IBUF_LOW_PWR = "TRUE",
parameter HISPI_IFD_DELAY_VALUE = "AUTO", parameter HISPI_IFD_DELAY_VALUE = "AUTO",
parameter HISPI_IOSTANDARD = "DEFAULT" parameter HISPI_IOSTANDARD = "DIFF_SSTL18_I" //"DIFF_SSTL18_II" for high current (13.4mA vs 8mA)
)( )(
input mclk, input mclk,
input mrst, input mrst,
......
...@@ -181,7 +181,6 @@ module sensor_channel#( ...@@ -181,7 +181,6 @@ module sensor_channel#(
//sensor_i2c_io other parameters //sensor_i2c_io other parameters
parameter integer SENSI2C_DRIVE= 12, parameter integer SENSI2C_DRIVE= 12,
parameter