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Commit 8bf77f19 authored by Andrey Filippov's avatar Andrey Filippov
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updated project settings to new format, cleaned them up

parent 1cd46f93
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Showing with 134 additions and 228 deletions
.eclipse_project_setup/.project
View file @ 8bf77f19
...@@ -62,42 +62,42 @@ ...@@ -62,42 +62,42 @@
<link> <link>
<name>vivado_logs/VivadoBitstream.log</name> <name>vivado_logs/VivadoBitstream.log</name>
<type>1</type> <type>1</type>
<location>/home/eyesis/git/elphel393/fpga-elphel/x393/vivado_logs/VivadoBitstream-20160624124420633.log</location> <location>/home/eyesis/git/x393-neon/vivado_logs/VivadoBitstream-20160702183003482.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOpt.log</name> <name>vivado_logs/VivadoOpt.log</name>
<type>1</type> <type>1</type>
<location>/home/eyesis/git/elphel393/fpga-elphel/x393/vivado_logs/VivadoOpt-20160624124420633.log</location> <location>/home/eyesis/git/x393-neon/vivado_logs/VivadoOpt-20160702183003482.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPhys.log</name> <name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type> <type>1</type>
<location>/home/eyesis/git/elphel393/fpga-elphel/x393/vivado_logs/VivadoOptPhys-20160624124420633.log</location> <location>/home/eyesis/git/x393-neon/vivado_logs/VivadoOptPhys-20160702183003482.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPower.log</name> <name>vivado_logs/VivadoOptPower.log</name>
<type>1</type> <type>1</type>
<location>/home/eyesis/git/elphel393/fpga-elphel/x393/vivado_logs/VivadoOptPower-20160624124420633.log</location> <location>/home/eyesis/git/x393-neon/vivado_logs/VivadoOptPower-20160702183003482.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoPlace.log</name> <name>vivado_logs/VivadoPlace.log</name>
<type>1</type> <type>1</type>
<location>/home/eyesis/git/elphel393/fpga-elphel/x393/vivado_logs/VivadoPlace-20160624124420633.log</location> <location>/home/eyesis/git/x393-neon/vivado_logs/VivadoPlace-20160702183003482.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoRoute.log</name> <name>vivado_logs/VivadoRoute.log</name>
<type>1</type> <type>1</type>
<location>/home/eyesis/git/elphel393/fpga-elphel/x393/vivado_logs/VivadoRoute-20160624124420633.log</location> <location>/home/eyesis/git/x393-neon/vivado_logs/VivadoRoute-20160702183003482.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoSynthesis.log</name> <name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/eyesis/git/elphel393/fpga-elphel/x393/vivado_logs/VivadoSynthesis-20160624124420633.log</location> <location>/home/eyesis/git/x393-neon/vivado_logs/VivadoSynthesis-20160702181949899.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name> <name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type> <type>1</type>
<location>/home/eyesis/git/elphel393/fpga-elphel/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20160624124420633.log</location> <location>/home/eyesis/git/x393-neon/vivado_logs/VivadoTimimgSummaryReportImplemented-20160702183003482.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name> <name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
......
.eclipse_project_setup/.settings/com.elphel.vdt.FPGA_project.prefs
View file @ 8bf77f19
FPGA_project_0_SimulationTopFile=x393_testbench03.tf FPGA_project_@_DUTTopFile=cocotb/x393_dut.v
FPGA_project_1_SimulationTopModule=x393_testbench03 FPGA_project_@_DUTTopModule=x393_dut
FPGA_project_2_DUTTopFile=cocotb/x393_dut.v FPGA_project_@_ImplementationTopFile=x393.v
FPGA_project_2_ImplementationTopFile=x393.v FPGA_project_@_SimulationTopFile=x393_testbench03.tf
FPGA_project_3_DUTTopModule=x393_dut FPGA_project_@_SimulationTopModule=x393_testbench03
FPGA_project_4_part=xc7z030fbg484-1 FPGA_project_@_part=xc7z030fbg484-1
FPGA_project_5_part=xc7z030fbg484-1 com.elphel.store.context.FPGA_project=FPGA_project_@_SimulationTopFile<-@\#\#@->FPGA_project_@_DUTTopModule<-@\#\#@->FPGA_project_@_ImplementationTopFile<-@\#\#@->FPGA_project_@_DUTTopFile<-@\#\#@->FPGA_project_@_SimulationTopModule<-@\#\#@->FPGA_project_@_part<-@\#\#@->
com.elphel.store.context.FPGA_project=FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_4_part<-@\#\#@->FPGA_project_0_SimulationTopFile<-@\#\#@->FPGA_project_1_SimulationTopModule<-@\#\#@->FPGA_project_5_part<-@\#\#@->FPGA_project_2_DUTTopFile<-@\#\#@->FPGA_project_3_DUTTopModule<-@\#\#@-> com.elphel.store.version.FPGA_project=1.0
eclipse.preferences.version=1 eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.ISExst.prefs
View file @ 8bf77f19
ISExst_170_constraints=ddrc_test01.xcf ISExst_@_OtherProblems=HDLCompiler\:413<-@\#\#@->
ISExst_96_OtherProblems=HDLCompiler\:413<-@\#\#@-> ISExst_@_constraints=ddrc_test01.xcf
com.elphel.store.context.ISExst=ISExst_170_constraints<-@\#\#@->ISExst_96_OtherProblems<-@\#\#@-> com.elphel.store.context.ISExst=ISExst_@_OtherProblems<-@\#\#@->ISExst_@_constraints<-@\#\#@->
eclipse.preferences.version=1 eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.VivadoBitstream.prefs
View file @ 8bf77f19
VivadoBitstream_103_PreBitstreamTCL=set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [current_design]<-@\#\#@-> VivadoBitstream_@_PreBitstreamTCL=set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [current_design]<-@\#\#@->
VivadoBitstream_105_force=true VivadoBitstream_@_force=true
VivadoBitstream_122_PreBitstreamTCL=set_property "BITSTREAM.STARTUP.MATCH_CYCLE" NoWait [current_design]<-@\#\#@-> VivadoBitstream_@_rawfile=x393_hispi
VivadoBitstream_123_PreBitstreamTCL=set_property "BITSTREAM.STARTUP.MATCH_CYCLE" NoWait [current_design]<-@\#\#@-> com.elphel.store.context.VivadoBitstream=VivadoBitstream_@_rawfile<-@\#\#@->VivadoBitstream_@_force<-@\#\#@->VivadoBitstream_@_PreBitstreamTCL<-@\#\#@->
VivadoBitstream_124_force=true
VivadoBitstream_124_rawfile=x393_hispi
com.elphel.store.context.VivadoBitstream=VivadoBitstream_105_force<-@\#\#@->VivadoBitstream_103_PreBitstreamTCL<-@\#\#@->VivadoBitstream_124_force<-@\#\#@->VivadoBitstream_122_PreBitstreamTCL<-@\#\#@->VivadoBitstream_123_PreBitstreamTCL<-@\#\#@->VivadoBitstream_124_rawfile<-@\#\#@->
eclipse.preferences.version=1 eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.VivadoOpt.prefs
View file @ 8bf77f19
VivadoOpt_123_SkipSnapshotOpt=true VivadoOpt_@_SkipSnapshotOpt=true
VivadoOpt_124_SkipSnapshotOpt=true com.elphel.store.context.VivadoOpt=VivadoOpt_@_SkipSnapshotOpt<-@\#\#@->
com.elphel.store.context.VivadoOpt=VivadoOpt_123_SkipSnapshotOpt<-@\#\#@->VivadoOpt_124_SkipSnapshotOpt<-@\#\#@->
eclipse.preferences.version=1 eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.VivadoOptPhys.prefs
View file @ 8bf77f19
VivadoOptPhys_123_SkipSnapshotOptPhys=true VivadoOptPhys_@_SkipSnapshotOptPhys=true
VivadoOptPhys_124_SkipSnapshotOptPhys=true com.elphel.store.context.VivadoOptPhys=VivadoOptPhys_@_SkipSnapshotOptPhys<-@\#\#@->
com.elphel.store.context.VivadoOptPhys=VivadoOptPhys_123_SkipSnapshotOptPhys<-@\#\#@->VivadoOptPhys_124_SkipSnapshotOptPhys<-@\#\#@->
eclipse.preferences.version=1 eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.VivadoOptPower.prefs
View file @ 8bf77f19
VivadoOptPower_124_SkipSnapshotOptPower=true VivadoOptPower_@_SkipSnapshotOptPower=true
VivadoOptPower_125_SkipSnapshotOptPower=true com.elphel.store.context.VivadoOptPower=VivadoOptPower_@_SkipSnapshotOptPower<-@\#\#@->
com.elphel.store.context.VivadoOptPower=VivadoOptPower_124_SkipSnapshotOptPower<-@\#\#@->VivadoOptPower_125_SkipSnapshotOptPower<-@\#\#@->
eclipse.preferences.version=1 eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.VivadoPlace.prefs
View file @ 8bf77f19
VivadoPlace_111_verbose_place=true VivadoPlace_@_SkipSnapshotPlace=true
VivadoPlace_123_SkipSnapshotPlace=true VivadoPlace_@_verbose_place=true
VivadoPlace_124_SkipSnapshotPlace=true com.elphel.store.context.VivadoPlace=VivadoPlace_@_verbose_place<-@\#\#@->VivadoPlace_@_SkipSnapshotPlace<-@\#\#@->
com.elphel.store.context.VivadoPlace=VivadoPlace_111_verbose_place<-@\#\#@->VivadoPlace_123_SkipSnapshotPlace<-@\#\#@->VivadoPlace_124_SkipSnapshotPlace<-@\#\#@->
eclipse.preferences.version=1 eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.VivadoRoute.prefs
View file @ 8bf77f19
VivadoRoute_122_SkipSnapshotRoute=true VivadoRoute_@_SkipSnapshotRoute=true
VivadoRoute_123_SkipSnapshotRoute=true VivadoRoute_@_directive_route=MoreGlobalIterations
VivadoRoute_125_directive_route=MoreGlobalIterations com.elphel.store.context.VivadoRoute=VivadoRoute_@_SkipSnapshotRoute<-@\#\#@->VivadoRoute_@_directive_route<-@\#\#@->
com.elphel.store.context.VivadoRoute=VivadoRoute_122_SkipSnapshotRoute<-@\#\#@->VivadoRoute_123_SkipSnapshotRoute<-@\#\#@->VivadoRoute_125_directive_route<-@\#\#@->
eclipse.preferences.version=1 eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.VivadoSynthesis.prefs
View file @ 8bf77f19
VivadoSynthesis_101_MaxMsg=10000 VivadoSynthesis_@_ConstraintsFiles=x393_global.tcl<-@\#\#@->x393_placement.tcl<-@\#\#@->x393_timing.tcl<-@\#\#@->x393_sata/ahci_timing_frag.xdc<-@\#\#@->
VivadoSynthesis_102_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@-> VivadoSynthesis_@_MaxMsg=20000
VivadoSynthesis_115_flatten_hierarchy=none VivadoSynthesis_@_OtherProblems=Netlist 29-345<-@\#\#@->Board 49-26<-@\#\#@->Synth 8-638<-@\#\#@->Synth 8-256<-@\#\#@->
VivadoSynthesis_121_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@-> VivadoSynthesis_@_PreTCL=set_property USED_IN implementation [get_files "*x393_placement*"]<-@\#\#@->
VivadoSynthesis_121_MaxMsg=5000 VivadoSynthesis_@_ResetProject=true
VivadoSynthesis_122_ConstraintsFiles=x393_hispi.xdc<-@\#\#@->x393_hispi_timing.xdc<-@\#\#@-> VivadoSynthesis_@_ShowInfo=true
VivadoSynthesis_122_SkipSnapshotSynth=true VivadoSynthesis_@_SkipSnapshotSynth=true
VivadoSynthesis_123_ResetProject=true VivadoSynthesis_@_parser_mode=1
VivadoSynthesis_123_SkipSnapshotSynth=true VivadoSynthesis_@_verbose=true
VivadoSynthesis_124_ConstraintsFiles=x393_global.tcl<-@\#\#@->x393_placement.tcl<-@\#\#@->x393_timing.tcl<-@\#\#@->x393_sata/ahci_timing_frag.xdc<-@\#\#@-> com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_@_ShowInfo<-@\#\#@->VivadoSynthesis_@_parser_mode<-@\#\#@->VivadoSynthesis_@_PreTCL<-@\#\#@->VivadoSynthesis_@_verbose<-@\#\#@->VivadoSynthesis_@_OtherProblems<-@\#\#@->VivadoSynthesis_@_MaxMsg<-@\#\#@->VivadoSynthesis_@_SkipSnapshotSynth<-@\#\#@->VivadoSynthesis_@_ConstraintsFiles<-@\#\#@->VivadoSynthesis_@_ResetProject<-@\#\#@->
VivadoSynthesis_127_verbose=true com.elphel.store.version.VivadoSynthesis=1.1
VivadoSynthesis_128_PreTCL=set_property USED_IN implementation [get_files "*x393_placement*"]<-@\#\#@->
VivadoSynthesis_81_parser_mode=1
VivadoSynthesis_93_OtherProblems=Netlist 29-345<-@\#\#@->Board 49-26<-@\#\#@->Synth 8-638<-@\#\#@->Synth 8-256<-@\#\#@->
VivadoSynthesis_95_ShowInfo=true
com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->VivadoSynthesis_115_flatten_hierarchy<-@\#\#@->VivadoSynthesis_101_MaxMsg<-@\#\#@->VivadoSynthesis_127_verbose<-@\#\#@->VivadoSynthesis_93_OtherProblems<-@\#\#@->VivadoSynthesis_81_parser_mode<-@\#\#@->VivadoSynthesis_121_ConstraintsFiles<-@\#\#@->VivadoSynthesis_122_SkipSnapshotSynth<-@\#\#@->VivadoSynthesis_123_ResetProject<-@\#\#@->VivadoSynthesis_123_SkipSnapshotSynth<-@\#\#@->VivadoSynthesis_122_ConstraintsFiles<-@\#\#@->VivadoSynthesis_124_ConstraintsFiles<-@\#\#@->VivadoSynthesis_121_MaxMsg<-@\#\#@->VivadoSynthesis_128_PreTCL<-@\#\#@->
eclipse.preferences.version=1 eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.VivadoTimimgSummaryReportSynthesis.prefs
View file @ 8bf77f19
VivadoTimimgSummaryReportSynthesis_102_DisableVivadoTimingSummary=true VivadoTimimgSummaryReportSynthesis_@_DisableVivadoTimingSummary=true
VivadoTimimgSummaryReportSynthesis_121_DisableVivadoTimingSummary=true com.elphel.store.context.VivadoTimimgSummaryReportSynthesis=VivadoTimimgSummaryReportSynthesis_@_DisableVivadoTimingSummary<-@\#\#@->
com.elphel.store.context.VivadoTimimgSummaryReportSynthesis=VivadoTimimgSummaryReportSynthesis_102_DisableVivadoTimingSummary<-@\#\#@->VivadoTimimgSummaryReportSynthesis_121_DisableVivadoTimingSummary<-@\#\#@->
eclipse.preferences.version=1 eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.VivadoTimingReportImplemented.prefs
View file @ 8bf77f19
VivadoTimingReportImplemented_121_DisableVivadoTiming=true VivadoTimingReportImplemented_@_DisableVivadoTiming=true
VivadoTimingReportImplemented_122_DisableVivadoTiming=true VivadoTimingReportImplemented_@_rawfile=
com.elphel.store.context.VivadoTimingReportImplemented=VivadoTimingReportImplemented_132_rawfile<-@\#\#@->VivadoTimingReportImplemented_121_DisableVivadoTiming<-@\#\#@->VivadoTimingReportImplemented_122_DisableVivadoTiming<-@\#\#@-> com.elphel.store.context.VivadoTimingReportImplemented=VivadoTimingReportImplemented_@_DisableVivadoTiming<-@\#\#@->VivadoTimingReportImplemented_@_rawfile<-@\#\#@->
eclipse.preferences.version=1 eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.VivadoTimingReportSynthesis.prefs
View file @ 8bf77f19
VivadoTimingReportSynthesis_102_DisableVivadoTiming=true VivadoTimingReportSynthesis_@_DisableVivadoTiming=true
VivadoTimingReportSynthesis_121_DisableVivadoTiming=true com.elphel.store.context.VivadoTimingReportSynthesis=VivadoTimingReportSynthesis_@_DisableVivadoTiming<-@\#\#@->
com.elphel.store.context.VivadoTimingReportSynthesis=VivadoTimingReportSynthesis_102_DisableVivadoTiming<-@\#\#@->VivadoTimingReportSynthesis_121_DisableVivadoTiming<-@\#\#@->
eclipse.preferences.version=1 eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.cocotb.prefs
View file @ 8bf77f19
cocotb_107_CocotbDutTopFile=cocotb/x393_dut.v cocotb_@_CocotbDutTopFile=cocotb/x393_dut.v
cocotb_109_CocotbRANDOM_SEED=123 cocotb_@_CocotbExtraFiles=glbl.v<-@\#\#@->
cocotb_111_CocotbMODULE=x393coco_02<-@\#\#@-> cocotb_@_CocotbIncludeDir=${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/x393_sata<-@\#\#@->${verilog_project_loc}/x393_sata/host<-@\#\#@->
cocotb_112_CocotbMODULE=x393coco_02<-@\#\#@-> cocotb_@_CocotbMODULE=x393coco_02<-@\#\#@->
cocotb_112_CocotbTESTCASE=run_test<-@\#\#@-> cocotb_@_CocotbTESTCASE=run_test<-@\#\#@->
cocotb_113_CocotbTESTCASE=run_test<-@\#\#@-> cocotb_@_GTKWaveSavFile=x393_cocotb_02.sav
cocotb_116_GTKWaveSavFile=x393_cocotb_02.sav com.elphel.store.context.cocotb=cocotb_@_CocotbExtraFiles<-@\#\#@->cocotb_@_CocotbMODULE<-@\#\#@->cocotb_@_GTKWaveSavFile<-@\#\#@->cocotb_@_CocotbIncludeDir<-@\#\#@->cocotb_@_CocotbDutTopFile<-@\#\#@->cocotb_@_CocotbTESTCASE<-@\#\#@->
cocotb_117_GTKWaveSavFile=x393_cocotb_02.sav com.elphel.store.version.cocotb=0.8
cocotb_118_CocotbIncludeDir=${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/x393_sata<-@\#\#@->${verilog_project_loc}/x393_sata/host<-@\#\#@->
cocotb_119_CocotbIncludeDir=${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/x393_sata<-@\#\#@->${verilog_project_loc}/x393_sata/host<-@\#\#@->
cocotb_122_CocotbExtraFiles=glbl.v<-@\#\#@->
cocotb_123_CocotbExtraFiles=glbl.v<-@\#\#@->
com.elphel.store.context.cocotb=cocotb_107_CocotbDutTopFile<-@\#\#@->cocotb_116_GTKWaveSavFile<-@\#\#@->cocotb_118_CocotbIncludeDir<-@\#\#@->cocotb_122_CocotbExtraFiles<-@\#\#@->cocotb_111_CocotbMODULE<-@\#\#@->cocotb_112_CocotbTESTCASE<-@\#\#@->cocotb_109_CocotbRANDOM_SEED<-@\#\#@->cocotb_112_CocotbMODULE<-@\#\#@->cocotb_113_CocotbTESTCASE<-@\#\#@->cocotb_117_GTKWaveSavFile<-@\#\#@->cocotb_123_CocotbExtraFiles<-@\#\#@->cocotb_119_CocotbIncludeDir<-@\#\#@->
eclipse.preferences.version=1 eclipse.preferences.version=1
.eclipse_project_setup/.settings/com.elphel.vdt.iverilog.prefs
View file @ 8bf77f19
com.elphel.store.context.iverilog=iverilog_81_TopModulesOther<-@\#\#@->iverilog_83_ExtraFiles<-@\#\#@->iverilog_88_ShowNoProblem<-@\#\#@->iverilog_77_Param_Exe<-@\#\#@->iverilog_78_VVP_Exe<-@\#\#@->iverilog_99_GrepFindErrWarn<-@\#\#@->iverilog_84_IncludeDir<-@\#\#@->iverilog_89_ShowNoProblem<-@\#\#@->iverilog_79_GtkWave_Exe<-@\#\#@->iverilog_98_GTKWaveSavFile<-@\#\#@->iverilog_100_TopModulesOther<-@\#\#@->iverilog_102_ExtraFiles<-@\#\#@->iverilog_103_IncludeDir<-@\#\#@->iverilog_101_TopModulesOther<-@\#\#@->iverilog_103_ExtraFiles<-@\#\#@->iverilog_104_IncludeDir<-@\#\#@->iverilog_113_SaveLogsSimulator<-@\#\#@->iverilog_109_ShowNoProblem<-@\#\#@->iverilog_110_ShowWarnings<-@\#\#@->iverilog_102_TopModulesOther<-@\#\#@->iverilog_104_ExtraFiles<-@\#\#@->iverilog_105_IncludeDir<-@\#\#@->iverilog_110_ShowNoProblem<-@\#\#@->iverilog_113_SaveLogsPreprocessor<-@\#\#@->iverilog_121_GrepFindErrWarn<-@\#\#@->iverilog_114_SaveLogsSimulator<-@\#\#@->iverilog_103_TopModulesOther<-@\#\#@->iverilog_105_ExtraFiles<-@\#\#@->iverilog_106_IncludeDir<-@\#\#@->iverilog_111_ShowNoProblem<-@\#\#@->iverilog_115_SaveLogsSimulator<-@\#\#@->iverilog_120_GTKWaveSavFile<-@\#\#@->iverilog_106_TopModulesOther<-@\#\#@->iverilog_108_ExtraFiles<-@\#\#@->iverilog_123_GTKWaveSavFile<-@\#\#@->iverilog_109_IncludeDir<-@\#\#@-> com.elphel.store.context.iverilog=iverilog_@_ExtraFiles<-@\#\#@->iverilog_@_ShowWarnings<-@\#\#@->iverilog_@_SaveLogsSimulator<-@\#\#@->iverilog_@_ShowNoProblem<-@\#\#@->iverilog_@_IncludeDir<-@\#\#@->iverilog_@_TopModulesOther<-@\#\#@->iverilog_@_GTKWaveSavFile<-@\#\#@->iverilog_@_SaveLogsPreprocessor<-@\#\#@->
com.elphel.store.version.iverilog=1.1
eclipse.preferences.version=1 eclipse.preferences.version=1
iverilog_100_TopModulesOther=glbl<-@\#\#@-> iverilog_@_ExtraFiles=glbl.v<-@\#\#@->
iverilog_101_TopModulesOther=glbl<-@\#\#@-> iverilog_@_GTKWaveSavFile=x393_testbench04.sav
iverilog_102_ExtraFiles=glbl.v<-@\#\#@-> iverilog_@_IncludeDir=${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/x393_sata<-@\#\#@->${verilog_project_loc}/x393_sata/host<-@\#\#@->
iverilog_102_TopModulesOther=glbl<-@\#\#@-> iverilog_@_SaveLogsPreprocessor=false
iverilog_103_ExtraFiles=glbl.v<-@\#\#@-> iverilog_@_SaveLogsSimulator=true
iverilog_103_IncludeDir=${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/includes<-@\#\#@-> iverilog_@_ShowNoProblem=true
iverilog_103_TopModulesOther=glbl<-@\#\#@-> iverilog_@_ShowWarnings=false
iverilog_104_ExtraFiles=glbl.v<-@\#\#@-> iverilog_@_TopModulesOther=glbl<-@\#\#@->
iverilog_104_IncludeDir=${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/includes<-@\#\#@->
iverilog_105_ExtraFiles=glbl.v<-@\#\#@->
iverilog_105_IncludeDir=${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/ddr3<-@\#\#@->
iverilog_106_IncludeDir=${verilog_project_loc}/x393/includes<-@\#\#@->${verilog_project_loc}/x393/ddr3<-@\#\#@->${verilog_project_loc}/x393_sata/includes<-@\#\#@->${verilog_project_loc}/x393_sata/host<-@\#\#@->
iverilog_106_TopModulesOther=glbl<-@\#\#@->
iverilog_108_ExtraFiles=glbl.v<-@\#\#@->
iverilog_109_IncludeDir=${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/x393_sata<-@\#\#@->${verilog_project_loc}/x393_sata/host<-@\#\#@->
iverilog_109_ShowNoProblem=true
iverilog_110_ShowNoProblem=true
iverilog_110_ShowWarnings=false
iverilog_111_ShowNoProblem=true
iverilog_113_SaveLogsPreprocessor=false
iverilog_113_SaveLogsSimulator=true
iverilog_114_SaveLogsSimulator=true
iverilog_115_SaveLogsSimulator=true
iverilog_120_GTKWaveSavFile=x393_testbench04.sav
iverilog_121_GrepFindErrWarn=error|warning|sorry
iverilog_123_GTKWaveSavFile=x393_testbench04.sav
iverilog_77_Param_Exe=/usr/local/bin/iverilog
iverilog_78_VVP_Exe=/usr/local/bin/vvp
iverilog_79_GtkWave_Exe=/usr/local/bin/gtkwave
iverilog_81_TopModulesOther=glbl<-@\#\#@->
iverilog_83_ExtraFiles=glbl.v<-@\#\#@->
iverilog_84_IncludeDir=${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/includes<-@\#\#@->
iverilog_88_ShowNoProblem=true
iverilog_89_ShowNoProblem=true
iverilog_98_GTKWaveSavFile=393_testbench01.sav
iverilog_99_GrepFindErrWarn=error|warning|sorry
.settings/com.elphel.vdt.FPGA_project.prefs
View file @ 8bf77f19
FPGA_project_0_SimulationTopFile=x393_testbench03.tf FPGA_project_@_DUTTopFile=cocotb/x393_dut.v
FPGA_project_1_SimulationTopModule=x393_testbench03 FPGA_project_@_DUTTopModule=x393_dut
FPGA_project_2_DUTTopFile=cocotb/x393_dut.v FPGA_project_@_ImplementationTopFile=x393.v
FPGA_project_2_ImplementationTopFile=x393.v FPGA_project_@_SimulationTopFile=x393_testbench03.tf
FPGA_project_3_DUTTopModule=x393_dut FPGA_project_@_SimulationTopModule=x393_testbench03
FPGA_project_4_part=xc7z030fbg484-1 FPGA_project_@_part=xc7z030fbg484-1
FPGA_project_5_part=xc7z030fbg484-1 com.elphel.store.context.FPGA_project=FPGA_project_@_SimulationTopFile<-@\#\#@->FPGA_project_@_DUTTopModule<-@\#\#@->FPGA_project_@_ImplementationTopFile<-@\#\#@->FPGA_project_@_DUTTopFile<-@\#\#@->FPGA_project_@_SimulationTopModule<-@\#\#@->FPGA_project_@_part<-@\#\#@->
com.elphel.store.context.FPGA_project=FPGA_project_2_ImplementationTopFile<-@\#\#@->FPGA_project_4_part<-@\#\#@->FPGA_project_0_SimulationTopFile<-@\#\#@->FPGA_project_1_SimulationTopModule<-@\#\#@->FPGA_project_5_part<-@\#\#@->FPGA_project_2_DUTTopFile<-@\#\#@->FPGA_project_3_DUTTopModule<-@\#\#@-> com.elphel.store.version.FPGA_project=1.0
eclipse.preferences.version=1 eclipse.preferences.version=1
.settings/com.elphel.vdt.ISExst.prefs
View file @ 8bf77f19
ISExst_170_constraints=ddrc_test01.xcf ISExst_@_OtherProblems=HDLCompiler\:413<-@\#\#@->
ISExst_96_OtherProblems=HDLCompiler\:413<-@\#\#@-> ISExst_@_constraints=ddrc_test01.xcf
com.elphel.store.context.ISExst=ISExst_170_constraints<-@\#\#@->ISExst_96_OtherProblems<-@\#\#@-> com.elphel.store.context.ISExst=ISExst_@_OtherProblems<-@\#\#@->ISExst_@_constraints<-@\#\#@->
eclipse.preferences.version=1 eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoBitstream.prefs
View file @ 8bf77f19
VivadoBitstream_103_PreBitstreamTCL=set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [current_design]<-@\#\#@-> VivadoBitstream_@_PreBitstreamTCL=set_property BITSTREAM.STARTUP.MATCH_CYCLE NoWait [current_design]<-@\#\#@->
VivadoBitstream_105_force=true VivadoBitstream_@_force=true
VivadoBitstream_122_PreBitstreamTCL=set_property "BITSTREAM.STARTUP.MATCH_CYCLE" NoWait [current_design]<-@\#\#@-> VivadoBitstream_@_rawfile=x393_hispi
VivadoBitstream_123_PreBitstreamTCL=set_property "BITSTREAM.STARTUP.MATCH_CYCLE" NoWait [current_design]<-@\#\#@-> com.elphel.store.context.VivadoBitstream=VivadoBitstream_@_rawfile<-@\#\#@->VivadoBitstream_@_force<-@\#\#@->VivadoBitstream_@_PreBitstreamTCL<-@\#\#@->
VivadoBitstream_124_force=true
VivadoBitstream_124_rawfile=x393_hispi
com.elphel.store.context.VivadoBitstream=VivadoBitstream_105_force<-@\#\#@->VivadoBitstream_103_PreBitstreamTCL<-@\#\#@->VivadoBitstream_124_force<-@\#\#@->VivadoBitstream_122_PreBitstreamTCL<-@\#\#@->VivadoBitstream_123_PreBitstreamTCL<-@\#\#@->VivadoBitstream_124_rawfile<-@\#\#@->
eclipse.preferences.version=1 eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoOpt.prefs
View file @ 8bf77f19
VivadoOpt_123_SkipSnapshotOpt=true VivadoOpt_@_SkipSnapshotOpt=true
VivadoOpt_124_SkipSnapshotOpt=true com.elphel.store.context.VivadoOpt=VivadoOpt_@_SkipSnapshotOpt<-@\#\#@->
com.elphel.store.context.VivadoOpt=VivadoOpt_123_SkipSnapshotOpt<-@\#\#@->VivadoOpt_124_SkipSnapshotOpt<-@\#\#@->
eclipse.preferences.version=1 eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoOptPhys.prefs
View file @ 8bf77f19
VivadoOptPhys_123_SkipSnapshotOptPhys=true VivadoOptPhys_@_SkipSnapshotOptPhys=true
VivadoOptPhys_124_SkipSnapshotOptPhys=true com.elphel.store.context.VivadoOptPhys=VivadoOptPhys_@_SkipSnapshotOptPhys<-@\#\#@->
com.elphel.store.context.VivadoOptPhys=VivadoOptPhys_123_SkipSnapshotOptPhys<-@\#\#@->VivadoOptPhys_124_SkipSnapshotOptPhys<-@\#\#@->
eclipse.preferences.version=1 eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoOptPower.prefs
View file @ 8bf77f19
VivadoOptPower_124_SkipSnapshotOptPower=true VivadoOptPower_@_SkipSnapshotOptPower=true
VivadoOptPower_125_SkipSnapshotOptPower=true com.elphel.store.context.VivadoOptPower=VivadoOptPower_@_SkipSnapshotOptPower<-@\#\#@->
com.elphel.store.context.VivadoOptPower=VivadoOptPower_124_SkipSnapshotOptPower<-@\#\#@->VivadoOptPower_125_SkipSnapshotOptPower<-@\#\#@->
eclipse.preferences.version=1 eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoPlace.prefs
View file @ 8bf77f19
VivadoPlace_111_verbose_place=true VivadoPlace_@_SkipSnapshotPlace=true
VivadoPlace_123_SkipSnapshotPlace=true VivadoPlace_@_verbose_place=true
VivadoPlace_124_SkipSnapshotPlace=true com.elphel.store.context.VivadoPlace=VivadoPlace_@_verbose_place<-@\#\#@->VivadoPlace_@_SkipSnapshotPlace<-@\#\#@->
com.elphel.store.context.VivadoPlace=VivadoPlace_111_verbose_place<-@\#\#@->VivadoPlace_123_SkipSnapshotPlace<-@\#\#@->VivadoPlace_124_SkipSnapshotPlace<-@\#\#@->
eclipse.preferences.version=1 eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoRoute.prefs
View file @ 8bf77f19
VivadoRoute_122_SkipSnapshotRoute=true VivadoRoute_@_SkipSnapshotRoute=true
VivadoRoute_123_SkipSnapshotRoute=true VivadoRoute_@_directive_route=MoreGlobalIterations
VivadoRoute_125_directive_route=MoreGlobalIterations com.elphel.store.context.VivadoRoute=VivadoRoute_@_SkipSnapshotRoute<-@\#\#@->VivadoRoute_@_directive_route<-@\#\#@->
com.elphel.store.context.VivadoRoute=VivadoRoute_122_SkipSnapshotRoute<-@\#\#@->VivadoRoute_123_SkipSnapshotRoute<-@\#\#@->VivadoRoute_125_directive_route<-@\#\#@->
eclipse.preferences.version=1 eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoSynthesis.prefs
View file @ 8bf77f19
VivadoSynthesis_101_MaxMsg=10000 VivadoSynthesis_@_ConstraintsFiles=x393_global.tcl<-@\#\#@->x393_placement.tcl<-@\#\#@->x393_timing.tcl<-@\#\#@->x393_sata/ahci_timing_frag.xdc<-@\#\#@->
VivadoSynthesis_102_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@-> VivadoSynthesis_@_MaxMsg=20000
VivadoSynthesis_115_flatten_hierarchy=none VivadoSynthesis_@_OtherProblems=Netlist 29-345<-@\#\#@->Board 49-26<-@\#\#@->Synth 8-638<-@\#\#@->Synth 8-256<-@\#\#@->
VivadoSynthesis_121_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@-> VivadoSynthesis_@_PreTCL=set_property USED_IN implementation [get_files "*x393_placement*"]<-@\#\#@->
VivadoSynthesis_121_MaxMsg=5000 VivadoSynthesis_@_ResetProject=true
VivadoSynthesis_122_ConstraintsFiles=x393_hispi.xdc<-@\#\#@->x393_hispi_timing.xdc<-@\#\#@-> VivadoSynthesis_@_ShowInfo=true
VivadoSynthesis_122_SkipSnapshotSynth=true VivadoSynthesis_@_SkipSnapshotSynth=true
VivadoSynthesis_123_ResetProject=true VivadoSynthesis_@_parser_mode=1
VivadoSynthesis_123_SkipSnapshotSynth=true VivadoSynthesis_@_verbose=true
VivadoSynthesis_124_ConstraintsFiles=x393_global.tcl<-@\#\#@->x393_placement.tcl<-@\#\#@->x393_timing.tcl<-@\#\#@->x393_sata/ahci_timing_frag.xdc<-@\#\#@-> com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_@_ShowInfo<-@\#\#@->VivadoSynthesis_@_parser_mode<-@\#\#@->VivadoSynthesis_@_PreTCL<-@\#\#@->VivadoSynthesis_@_verbose<-@\#\#@->VivadoSynthesis_@_OtherProblems<-@\#\#@->VivadoSynthesis_@_MaxMsg<-@\#\#@->VivadoSynthesis_@_SkipSnapshotSynth<-@\#\#@->VivadoSynthesis_@_ConstraintsFiles<-@\#\#@->VivadoSynthesis_@_ResetProject<-@\#\#@->
VivadoSynthesis_127_verbose=true com.elphel.store.version.VivadoSynthesis=1.1
VivadoSynthesis_128_PreTCL=set_property USED_IN implementation [get_files "*x393_placement*"]<-@\#\#@->
VivadoSynthesis_81_parser_mode=1
VivadoSynthesis_93_OtherProblems=Netlist 29-345<-@\#\#@->Board 49-26<-@\#\#@->Synth 8-638<-@\#\#@->Synth 8-256<-@\#\#@->
VivadoSynthesis_95_ShowInfo=true
com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->VivadoSynthesis_115_flatten_hierarchy<-@\#\#@->VivadoSynthesis_101_MaxMsg<-@\#\#@->VivadoSynthesis_127_verbose<-@\#\#@->VivadoSynthesis_93_OtherProblems<-@\#\#@->VivadoSynthesis_81_parser_mode<-@\#\#@->VivadoSynthesis_121_ConstraintsFiles<-@\#\#@->VivadoSynthesis_122_SkipSnapshotSynth<-@\#\#@->VivadoSynthesis_123_ResetProject<-@\#\#@->VivadoSynthesis_123_SkipSnapshotSynth<-@\#\#@->VivadoSynthesis_122_ConstraintsFiles<-@\#\#@->VivadoSynthesis_124_ConstraintsFiles<-@\#\#@->VivadoSynthesis_121_MaxMsg<-@\#\#@->VivadoSynthesis_128_PreTCL<-@\#\#@->
eclipse.preferences.version=1 eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoTimimgSummaryReportSynthesis.prefs
View file @ 8bf77f19
VivadoTimimgSummaryReportSynthesis_102_DisableVivadoTimingSummary=true VivadoTimimgSummaryReportSynthesis_@_DisableVivadoTimingSummary=true
VivadoTimimgSummaryReportSynthesis_121_DisableVivadoTimingSummary=true com.elphel.store.context.VivadoTimimgSummaryReportSynthesis=VivadoTimimgSummaryReportSynthesis_@_DisableVivadoTimingSummary<-@\#\#@->
com.elphel.store.context.VivadoTimimgSummaryReportSynthesis=VivadoTimimgSummaryReportSynthesis_102_DisableVivadoTimingSummary<-@\#\#@->VivadoTimimgSummaryReportSynthesis_121_DisableVivadoTimingSummary<-@\#\#@->
eclipse.preferences.version=1 eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoTimingReportImplemented.prefs
View file @ 8bf77f19
VivadoTimingReportImplemented_121_DisableVivadoTiming=true VivadoTimingReportImplemented_@_DisableVivadoTiming=true
VivadoTimingReportImplemented_122_DisableVivadoTiming=true VivadoTimingReportImplemented_@_rawfile=
com.elphel.store.context.VivadoTimingReportImplemented=VivadoTimingReportImplemented_132_rawfile<-@\#\#@->VivadoTimingReportImplemented_121_DisableVivadoTiming<-@\#\#@->VivadoTimingReportImplemented_122_DisableVivadoTiming<-@\#\#@-> com.elphel.store.context.VivadoTimingReportImplemented=VivadoTimingReportImplemented_@_DisableVivadoTiming<-@\#\#@->VivadoTimingReportImplemented_@_rawfile<-@\#\#@->
eclipse.preferences.version=1 eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoTimingReportSynthesis.prefs
View file @ 8bf77f19
VivadoTimingReportSynthesis_102_DisableVivadoTiming=true VivadoTimingReportSynthesis_@_DisableVivadoTiming=true
VivadoTimingReportSynthesis_121_DisableVivadoTiming=true com.elphel.store.context.VivadoTimingReportSynthesis=VivadoTimingReportSynthesis_@_DisableVivadoTiming<-@\#\#@->
com.elphel.store.context.VivadoTimingReportSynthesis=VivadoTimingReportSynthesis_102_DisableVivadoTiming<-@\#\#@->VivadoTimingReportSynthesis_121_DisableVivadoTiming<-@\#\#@->
eclipse.preferences.version=1 eclipse.preferences.version=1
.settings/com.elphel.vdt.cocotb.prefs
View file @ 8bf77f19
cocotb_107_CocotbDutTopFile=cocotb/x393_dut.v cocotb_@_CocotbDutTopFile=cocotb/x393_dut.v
cocotb_109_CocotbRANDOM_SEED=123 cocotb_@_CocotbExtraFiles=glbl.v<-@\#\#@->
cocotb_111_CocotbMODULE=x393coco_02<-@\#\#@-> cocotb_@_CocotbIncludeDir=${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/x393_sata<-@\#\#@->${verilog_project_loc}/x393_sata/host<-@\#\#@->
cocotb_112_CocotbMODULE=x393coco_02<-@\#\#@-> cocotb_@_CocotbMODULE=x393coco_02<-@\#\#@->
cocotb_112_CocotbTESTCASE=run_test<-@\#\#@-> cocotb_@_CocotbTESTCASE=run_test<-@\#\#@->
cocotb_113_CocotbTESTCASE=run_test<-@\#\#@-> cocotb_@_GTKWaveSavFile=x393_cocotb_02.sav
cocotb_116_GTKWaveSavFile=x393_cocotb_02.sav com.elphel.store.context.cocotb=cocotb_@_CocotbExtraFiles<-@\#\#@->cocotb_@_CocotbMODULE<-@\#\#@->cocotb_@_GTKWaveSavFile<-@\#\#@->cocotb_@_CocotbIncludeDir<-@\#\#@->cocotb_@_CocotbDutTopFile<-@\#\#@->cocotb_@_CocotbTESTCASE<-@\#\#@->
cocotb_117_GTKWaveSavFile=x393_cocotb_02.sav com.elphel.store.version.cocotb=0.8
cocotb_118_CocotbIncludeDir=${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/x393_sata<-@\#\#@->${verilog_project_loc}/x393_sata/host<-@\#\#@->
cocotb_119_CocotbIncludeDir=${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/x393_sata<-@\#\#@->${verilog_project_loc}/x393_sata/host<-@\#\#@->
cocotb_122_CocotbExtraFiles=glbl.v<-@\#\#@->
cocotb_123_CocotbExtraFiles=glbl.v<-@\#\#@->
com.elphel.store.context.cocotb=cocotb_107_CocotbDutTopFile<-@\#\#@->cocotb_116_GTKWaveSavFile<-@\#\#@->cocotb_118_CocotbIncludeDir<-@\#\#@->cocotb_122_CocotbExtraFiles<-@\#\#@->cocotb_111_CocotbMODULE<-@\#\#@->cocotb_112_CocotbTESTCASE<-@\#\#@->cocotb_109_CocotbRANDOM_SEED<-@\#\#@->cocotb_112_CocotbMODULE<-@\#\#@->cocotb_113_CocotbTESTCASE<-@\#\#@->cocotb_117_GTKWaveSavFile<-@\#\#@->cocotb_123_CocotbExtraFiles<-@\#\#@->cocotb_119_CocotbIncludeDir<-@\#\#@->
eclipse.preferences.version=1 eclipse.preferences.version=1
.settings/com.elphel.vdt.iverilog.prefs
View file @ 8bf77f19
com.elphel.store.context.iverilog=iverilog_81_TopModulesOther<-@\#\#@->iverilog_83_ExtraFiles<-@\#\#@->iverilog_88_ShowNoProblem<-@\#\#@->iverilog_77_Param_Exe<-@\#\#@->iverilog_78_VVP_Exe<-@\#\#@->iverilog_99_GrepFindErrWarn<-@\#\#@->iverilog_84_IncludeDir<-@\#\#@->iverilog_89_ShowNoProblem<-@\#\#@->iverilog_79_GtkWave_Exe<-@\#\#@->iverilog_98_GTKWaveSavFile<-@\#\#@->iverilog_100_TopModulesOther<-@\#\#@->iverilog_102_ExtraFiles<-@\#\#@->iverilog_103_IncludeDir<-@\#\#@->iverilog_101_TopModulesOther<-@\#\#@->iverilog_103_ExtraFiles<-@\#\#@->iverilog_104_IncludeDir<-@\#\#@->iverilog_113_SaveLogsSimulator<-@\#\#@->iverilog_109_ShowNoProblem<-@\#\#@->iverilog_110_ShowWarnings<-@\#\#@->iverilog_102_TopModulesOther<-@\#\#@->iverilog_104_ExtraFiles<-@\#\#@->iverilog_105_IncludeDir<-@\#\#@->iverilog_110_ShowNoProblem<-@\#\#@->iverilog_113_SaveLogsPreprocessor<-@\#\#@->iverilog_121_GrepFindErrWarn<-@\#\#@->iverilog_114_SaveLogsSimulator<-@\#\#@->iverilog_103_TopModulesOther<-@\#\#@->iverilog_105_ExtraFiles<-@\#\#@->iverilog_106_IncludeDir<-@\#\#@->iverilog_111_ShowNoProblem<-@\#\#@->iverilog_115_SaveLogsSimulator<-@\#\#@->iverilog_120_GTKWaveSavFile<-@\#\#@->iverilog_106_TopModulesOther<-@\#\#@->iverilog_108_ExtraFiles<-@\#\#@->iverilog_123_GTKWaveSavFile<-@\#\#@->iverilog_109_IncludeDir<-@\#\#@-> com.elphel.store.context.iverilog=iverilog_@_ExtraFiles<-@\#\#@->iverilog_@_ShowWarnings<-@\#\#@->iverilog_@_SaveLogsSimulator<-@\#\#@->iverilog_@_ShowNoProblem<-@\#\#@->iverilog_@_IncludeDir<-@\#\#@->iverilog_@_TopModulesOther<-@\#\#@->iverilog_@_GTKWaveSavFile<-@\#\#@->iverilog_@_SaveLogsPreprocessor<-@\#\#@->
com.elphel.store.version.iverilog=1.1
eclipse.preferences.version=1 eclipse.preferences.version=1
iverilog_100_TopModulesOther=glbl<-@\#\#@-> iverilog_@_ExtraFiles=glbl.v<-@\#\#@->
iverilog_101_TopModulesOther=glbl<-@\#\#@-> iverilog_@_GTKWaveSavFile=x393_testbench04.sav
iverilog_102_ExtraFiles=glbl.v<-@\#\#@-> iverilog_@_IncludeDir=${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/x393_sata<-@\#\#@->${verilog_project_loc}/x393_sata/host<-@\#\#@->
iverilog_102_TopModulesOther=glbl<-@\#\#@-> iverilog_@_SaveLogsPreprocessor=false
iverilog_103_ExtraFiles=glbl.v<-@\#\#@-> iverilog_@_SaveLogsSimulator=true
iverilog_103_IncludeDir=${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/includes<-@\#\#@-> iverilog_@_ShowNoProblem=true
iverilog_103_TopModulesOther=glbl<-@\#\#@-> iverilog_@_ShowWarnings=false
iverilog_104_ExtraFiles=glbl.v<-@\#\#@-> iverilog_@_TopModulesOther=glbl<-@\#\#@->
iverilog_104_IncludeDir=${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/includes<-@\#\#@->
iverilog_105_ExtraFiles=glbl.v<-@\#\#@->
iverilog_105_IncludeDir=${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/ddr3<-@\#\#@->
iverilog_106_IncludeDir=${verilog_project_loc}/x393/includes<-@\#\#@->${verilog_project_loc}/x393/ddr3<-@\#\#@->${verilog_project_loc}/x393_sata/includes<-@\#\#@->${verilog_project_loc}/x393_sata/host<-@\#\#@->
iverilog_106_TopModulesOther=glbl<-@\#\#@->
iverilog_108_ExtraFiles=glbl.v<-@\#\#@->
iverilog_109_IncludeDir=${verilog_project_loc}/includes<-@\#\#@->${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/x393_sata<-@\#\#@->${verilog_project_loc}/x393_sata/host<-@\#\#@->
iverilog_109_ShowNoProblem=true
iverilog_110_ShowNoProblem=true
iverilog_110_ShowWarnings=false
iverilog_111_ShowNoProblem=true
iverilog_113_SaveLogsPreprocessor=false
iverilog_113_SaveLogsSimulator=true
iverilog_114_SaveLogsSimulator=true
iverilog_115_SaveLogsSimulator=true
iverilog_120_GTKWaveSavFile=x393_testbench04.sav
iverilog_121_GrepFindErrWarn=error|warning|sorry
iverilog_123_GTKWaveSavFile=x393_testbench04.sav
iverilog_77_Param_Exe=/usr/local/bin/iverilog
iverilog_78_VVP_Exe=/usr/local/bin/vvp
iverilog_79_GtkWave_Exe=/usr/local/bin/gtkwave
iverilog_81_TopModulesOther=glbl<-@\#\#@->
iverilog_83_ExtraFiles=glbl.v<-@\#\#@->
iverilog_84_IncludeDir=${verilog_project_loc}/ddr3<-@\#\#@->${verilog_project_loc}/includes<-@\#\#@->
iverilog_88_ShowNoProblem=true
iverilog_89_ShowNoProblem=true
iverilog_98_GTKWaveSavFile=393_testbench01.sav
iverilog_99_GrepFindErrWarn=error|warning|sorry
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