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Commit 8b0a0f11 authored by Andrey Filippov's avatar Andrey Filippov
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made tools run successfully, no timing errors

parent 8e80a731
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.project
View file @ 8b0a0f11
...@@ -62,77 +62,77 @@ ...@@ -62,77 +62,77 @@
<link> <link>
<name>vivado_logs/VivadoBitstream.log</name> <name>vivado_logs/VivadoBitstream.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150722003723406.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150722181016920.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOpt.log</name> <name>vivado_logs/VivadoOpt.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150722003207037.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150722181016920.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPhys.log</name> <name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150722003723406.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150722181016920.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPower.log</name> <name>vivado_logs/VivadoOptPower.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150722003207037.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150722181016920.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoPlace.log</name> <name>vivado_logs/VivadoPlace.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150722003207037.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150722181016920.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoRoute.log</name> <name>vivado_logs/VivadoRoute.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150722003723406.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150722181016920.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoSynthesis.log</name> <name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150722002329036.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150722180528066.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name> <name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150722003723406.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150722181016920.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name> <name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20150722002329036.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20150722180528066.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimingReportImplemented.log</name> <name>vivado_logs/VivadoTimingReportImplemented.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150722003723406.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150722181016920.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name> <name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150722002329036.log</location> <location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150722180528066.log</location>
</link> </link>
<link> <link>
<name>vivado_state/x393-opt-phys.dcp</name> <name>vivado_state/x393-opt-phys.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-opt-phys-20150722003723406.dcp</location> <location>/home/andrey/git/x393/vivado_state/x393-opt-phys-20150722181016920.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393-place.dcp</name> <name>vivado_state/x393-place.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-place-20150722003207037.dcp</location> <location>/home/andrey/git/x393/vivado_state/x393-place-20150722181016920.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393-route.dcp</name> <name>vivado_state/x393-route.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-route-20150722003723406.dcp</location> <location>/home/andrey/git/x393/vivado_state/x393-route-20150722181016920.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/x393-synth.dcp</name> <name>vivado_state/x393-synth.dcp</name>
<type>1</type> <type>1</type>
<location>/home/andrey/git/x393/vivado_state/x393-synth-20150722002329036.dcp</location> <location>/home/andrey/git/x393/vivado_state/x393-synth-20150722180528066.dcp</location>
</link> </link>
</linkedResources> </linkedResources>
</projectDescription> </projectDescription>
.settings/com.elphel.vdt.VivadoSynthesis.prefs
View file @ 8b0a0f11
...@@ -4,6 +4,6 @@ VivadoSynthesis_115_flatten_hierarchy=none ...@@ -4,6 +4,6 @@ VivadoSynthesis_115_flatten_hierarchy=none
VivadoSynthesis_127_verbose=true VivadoSynthesis_127_verbose=true
VivadoSynthesis_81_parser_mode=1 VivadoSynthesis_81_parser_mode=1
VivadoSynthesis_93_OtherProblems=Netlist 29-345<-@\#\#@->Board 49-26<-@\#\#@-> VivadoSynthesis_93_OtherProblems=Netlist 29-345<-@\#\#@->Board 49-26<-@\#\#@->
VivadoSynthesis_95_ShowInfo=false VivadoSynthesis_95_ShowInfo=true
com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->VivadoSynthesis_115_flatten_hierarchy<-@\#\#@->VivadoSynthesis_101_MaxMsg<-@\#\#@->VivadoSynthesis_127_verbose<-@\#\#@->VivadoSynthesis_93_OtherProblems<-@\#\#@->VivadoSynthesis_81_parser_mode<-@\#\#@-> com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->VivadoSynthesis_115_flatten_hierarchy<-@\#\#@->VivadoSynthesis_101_MaxMsg<-@\#\#@->VivadoSynthesis_127_verbose<-@\#\#@->VivadoSynthesis_93_OtherProblems<-@\#\#@->VivadoSynthesis_81_parser_mode<-@\#\#@->
eclipse.preferences.version=1 eclipse.preferences.version=1
compressor_jp/huff_fifo393.v
View file @ 8b0a0f11
...@@ -34,13 +34,16 @@ module huff_fifo393 ( ...@@ -34,13 +34,16 @@ module huff_fifo393 (
input want_read, input want_read,
input want_read_early, input want_read_early,
output reg dav, // FIFO output latch has data (fifo_or_full) output reg dav, // FIFO output latch has data (fifo_or_full)
output reg [15:0] q_latch); // output data `ifdef INFER_LATCHES
output reg [15:0] q_latch
`else
output [15:0] q_latch
`endif
); // output data
reg [9:0] wa; reg [9:0] wa;
reg [9:0] sync_wa; // delayed wa, re_latch-calculated at output clock reg [9:0] sync_wa; // delayed wa, re_latch-calculated at output clock
reg [9:0] ra_r; reg [9:0] ra_r;
reg [9:0] ra_latch;
reg load_q;
wire [15:0] fifo_o; wire [15:0] fifo_o;
reg ds1; // ds delayed by one xclk to give time to block ram to write data. Not needed likely. reg ds1; // ds delayed by one xclk to give time to block ram to write data. Not needed likely.
reg synci; reg synci;
...@@ -49,12 +52,20 @@ module huff_fifo393 ( ...@@ -49,12 +52,20 @@ module huff_fifo393 (
reg en2x; // en sync to xclk2x; reg en2x; // en sync to xclk2x;
reg re_r; reg re_r;
reg re_latch;
reg fifo_dav; // RAM output reg has data reg fifo_dav; // RAM output reg has data
reg dav_and_fifo_dav; reg dav_and_fifo_dav;
wire ram_dav; // RAM has data inside wire ram_dav; // RAM has data inside
reg [9:0] diff_a; reg [9:0] diff_a;
wire next_re; wire next_re;
reg load_q;
`ifdef INFER_LATCHES
reg [9:0] ra_latch;
reg re_latch;
`else
wire [9:0] ra_latch;
wire re_latch;
`endif
always @ (posedge xclk) begin // input stage, no overrun detection always @ (posedge xclk) begin // input stage, no overrun detection
...@@ -90,71 +101,58 @@ module huff_fifo393 ( ...@@ -90,71 +101,58 @@ module huff_fifo393 (
else if (!sync_we && next_re) diff_a[9:0] <= diff_a[9:0]-1; else if (!sync_we && next_re) diff_a[9:0] <= diff_a[9:0]-1;
end end
/*
LD i_re (.Q(re_latch),.G(xclk2x),.D(next_re));
LD i_ra9 (.Q(ra_latch[9]),.G(xclk2x),.D(ra_r[9]));
LD i_ra8 (.Q(ra_latch[8]),.G(xclk2x),.D(ra_r[8]));
LD i_ra7 (.Q(ra_latch[7]),.G(xclk2x),.D(ra_r[7]));
LD i_ra6 (.Q(ra_latch[6]),.G(xclk2x),.D(ra_r[6]));
LD i_ra5 (.Q(ra_latch[5]),.G(xclk2x),.D(ra_r[5]));
LD i_ra4 (.Q(ra_latch[4]),.G(xclk2x),.D(ra_r[4]));
LD i_ra3 (.Q(ra_latch[3]),.G(xclk2x),.D(ra_r[3]));
LD i_ra2 (.Q(ra_latch[2]),.G(xclk2x),.D(ra_r[2]));
LD i_ra1 (.Q(ra_latch[1]),.G(xclk2x),.D(ra_r[1]));
LD i_ra0 (.Q(ra_latch[0]),.G(xclk2x),.D(ra_r[0]));
*/
always @* if (xclk2x) re_latch <= next_re;
always @* if (xclk2x) ra_latch <= ra_r;
always @ (posedge xclk2x) begin always @ (posedge xclk2x) begin
load_q <= dav?want_read_early:re_r; load_q <= dav?want_read_early:re_r;
end end
/*
LD_1 i_q15 (.Q( q_latch[15]),.G(xclk2x),.D(load_q?fifo_o[15]:q_latch[15])); `ifdef INFER_LATCHES
LD_1 i_q14 (.Q( q_latch[14]),.G(xclk2x),.D(load_q?fifo_o[14]:q_latch[14])); always @* if (xclk2x) re_latch <= next_re;
LD_1 i_q13 (.Q( q_latch[13]),.G(xclk2x),.D(load_q?fifo_o[13]:q_latch[13])); always @* if (xclk2x) ra_latch <= ra_r;
LD_1 i_q12 (.Q( q_latch[12]),.G(xclk2x),.D(load_q?fifo_o[12]:q_latch[12])); always @* if (~xclk2x)
LD_1 i_q11 (.Q( q_latch[11]),.G(xclk2x),.D(load_q?fifo_o[11]:q_latch[11]));
LD_1 i_q10 (.Q( q_latch[10]),.G(xclk2x),.D(load_q?fifo_o[10]:q_latch[10]));
LD_1 i_q9 (.Q( q_latch[ 9]),.G(xclk2x),.D(load_q?fifo_o[ 9]:q_latch[ 9]));
LD_1 i_q8 (.Q( q_latch[ 8]),.G(xclk2x),.D(load_q?fifo_o[ 8]:q_latch[ 8]));
LD_1 i_q7 (.Q( q_latch[ 7]),.G(xclk2x),.D(load_q?fifo_o[ 7]:q_latch[ 7]));
LD_1 i_q6 (.Q( q_latch[ 6]),.G(xclk2x),.D(load_q?fifo_o[ 6]:q_latch[ 6]));
LD_1 i_q5 (.Q( q_latch[ 5]),.G(xclk2x),.D(load_q?fifo_o[ 5]:q_latch[ 5]));
LD_1 i_q4 (.Q( q_latch[ 4]),.G(xclk2x),.D(load_q?fifo_o[ 4]:q_latch[ 4]));
LD_1 i_q3 (.Q( q_latch[ 3]),.G(xclk2x),.D(load_q?fifo_o[ 3]:q_latch[ 3]));
LD_1 i_q2 (.Q( q_latch[ 2]),.G(xclk2x),.D(load_q?fifo_o[ 2]:q_latch[ 2]));
LD_1 i_q1 (.Q( q_latch[ 1]),.G(xclk2x),.D(load_q?fifo_o[ 1]:q_latch[ 1]));
LD_1 i_q0 (.Q( q_latch[ 0]),.G(xclk2x),.D(load_q?fifo_o[ 0]:q_latch[ 0]));
*/
always @* if (~xclk2x) begin
if (load_q) q_latch <= fifo_o; if (load_q) q_latch <= fifo_o;
end end
/*
RAMB16_S18_S18 i_fifo ( `else
.DOA(), // Port A 16-bit Data Output latch_g_ce #(
.DOPA(), // Port A 2-bit Parity Output .WIDTH (1),
.ADDRA(wa[9:0]), // Port A 10-bit Address Input .INIT (0),
.CLKA(xclk), // Port A Clock .IS_CLR_INVERTED (0),
.DIA(di[15:0]), // Port A 16-bit Data Input .IS_G_INVERTED (0)
.DIPA(2'b0), // Port A 2-bit parity Input ) latch_re_i (
.ENA(ds), // Port A RAM Enable Input .rst (1'b0), // input
.SSRA(1'b0), // Port A Synchronous Set/Reset Input .g (xclk2x), // input
.WEA(1'b1), // Port A Write Enable Input .ce (1'b1), // input
.d_in (next_re), // input[0:0]
.DOB(fifo_o[15:0]),// Port B 16-bit Data Output .q_out (re_latch) // output[0:0]
.DOPB(), // Port B 2-bit Parity Output
.ADDRB(ra_latch[9:0]), // Port B 10-bit Address Input
.CLKB(xclk2x), // Port B Clock
.DIB(16'b0), // Port B 16-bit Data Input
.DIPB(2'b0), // Port-B 2-bit parity Input
.ENB(re_latch), // PortB RAM Enable Input
.SSRB(1'b0), // Port B Synchronous Set/Reset Input
.WEB(1'b0) // Port B Write Enable Input
); );
*/
latch_g_ce #(
.WIDTH (10),
.INIT (0),
.IS_CLR_INVERTED (0),
.IS_G_INVERTED (0)
) latch_ra_i (
.rst (1'b0), // input
.g (xclk2x), // input
.ce (1'b1), // input
.d_in (ra_r), // input[0:0]
.q_out (ra_latch) // output[0:0]
);
latch_g_ce #(
.WIDTH (16),
.INIT (0),
.IS_CLR_INVERTED (0),
.IS_G_INVERTED (1'b1) // inverted!
) latch_q_i (
.rst (1'b0), // input
.g (xclk2x), // input
.ce (load_q), // input
.d_in (fifo_o), // input[0:0]
.q_out (q_latch) // output[0:0]
);
`endif
ram18_var_w_var_r #( ram18_var_w_var_r #(
.REGISTERS (0), .REGISTERS (0),
......
includes/x393_parameters.vh
View file @ 8b0a0f11
...@@ -433,8 +433,20 @@ ...@@ -433,8 +433,20 @@
parameter IPCLK_PHASE = 0.000, parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000, parameter IPCLK2X_PHASE = 0.000,
parameter BUF_IPCLK = "BUFG", // "BUFR", // parameter BUF_IPCLK = "BUFMR", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X = "BUFG", // "BUFR", // parameter BUF_IPCLK2X = "BUFMR", //G", // "BUFR",
parameter BUF_IPCLK_SENS0 = "BUFR", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS0 = "BUFR", //G", // "BUFR",
parameter BUF_IPCLK_SENS1 = "BUFG", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS1 = "BUFG", // "BUFR",
parameter BUF_IPCLK_SENS2 = "BUFR", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS2 = "BUFR", //G", // "BUFR",
parameter BUF_IPCLK_SENS3 = "BUFG", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS3 = "BUFG", // "BUFR",
parameter SENS_DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN parameter SENS_DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter SENS_REF_JITTER1 = 0.010, // Expectet jitter on CLKIN1 (0.000..0.999) parameter SENS_REF_JITTER1 = 0.010, // Expectet jitter on CLKIN1 (0.000..0.999)
......
memctrl/phy/dq_single.v
View file @ 8b0a0f11
...@@ -121,7 +121,8 @@ iserdes_mem #( ...@@ -121,7 +121,8 @@ iserdes_mem #(
.rst(rst), // reset .rst(rst), // reset
.d_direct(1'b0), // direct input from IOB, normally not used, controlled by IOBDELAY parameter (set to "NONE") .d_direct(1'b0), // direct input from IOB, normally not used, controlled by IOBDELAY parameter (set to "NONE")
.ddly(dq_dly), // serial input from idelay .ddly(dq_dly), // serial input from idelay
.dout(dout[3:0]) // parallel data out .dout(dout[3:0]), // parallel data out
.comb_out() // output
); );
endmodule endmodule
......
sensor/pxd_single.v
View file @ 8b0a0f11
...@@ -52,7 +52,7 @@ module pxd_single#( ...@@ -52,7 +52,7 @@ module pxd_single#(
reg pxd_r; reg pxd_r;
assign pxd_in=pxd_r; assign pxd_in=pxd_r;
assign pxd_async = pxd_iobuf; // assign pxd_async = pxd_iobuf;
always @ (posedge mclk) begin always @ (posedge mclk) begin
if (mrst) pxd_r <= 0; if (mrst) pxd_r <= 0;
else pxd_r <= quadrant[1]?(quadrant[0]? dout[3]: dout[2]) : (quadrant[0]? dout[1]: dout[0]); else pxd_r <= quadrant[1]?(quadrant[0]? dout[3]: dout[2]) : (quadrant[0]? dout[1]: dout[0]);
...@@ -70,8 +70,8 @@ module pxd_single#( ...@@ -70,8 +70,8 @@ module pxd_single#(
.T (!pxd_en) // input .T (!pxd_en) // input
); );
/*
//finedelay not supported by HR banks? //finedelay not supported by HR banks?
/*
idelay_fine_pipe # ( idelay_fine_pipe # (
.IODELAY_GRP (IODELAY_GRP), .IODELAY_GRP (IODELAY_GRP),
.DELAY_VALUE (IDELAY_VALUE), .DELAY_VALUE (IDELAY_VALUE),
...@@ -113,7 +113,8 @@ module pxd_single#( ...@@ -113,7 +113,8 @@ module pxd_single#(
.rst(irst), // reset .rst(irst), // reset
.d_direct(1'b0), // direct input from IOB, normally not used, controlled by IOBDELAY parameter (set to "NONE") .d_direct(1'b0), // direct input from IOB, normally not used, controlled by IOBDELAY parameter (set to "NONE")
.ddly(pxd_delayed), // serial input from idelay .ddly(pxd_delayed), // serial input from idelay
.dout(dout[3:0]) // parallel data out .dout(dout[3:0]), // parallel data out
.comb_out(pxd_async) // output
); );
endmodule endmodule
......
sensor/sens_parallel12.v
View file @ 8b0a0f11
...@@ -361,7 +361,8 @@ module sens_parallel12 #( ...@@ -361,7 +361,8 @@ module sens_parallel12 #(
.ld_idelay (ld_idelay), // input .ld_idelay (ld_idelay), // input
.quadrant (quadrants[1:0]) // input[1:0] .quadrant (quadrants[1:0]) // input[1:0]
); );
// debugging implementation
//assign xfpgatdo = pxd_out[1];
pxd_single #( pxd_single #(
.IODELAY_GRP (IODELAY_GRP), .IODELAY_GRP (IODELAY_GRP),
.IDELAY_VALUE (IDELAY_VALUE), .IDELAY_VALUE (IDELAY_VALUE),
......
sensor/sensors393.v
View file @ 8b0a0f11
...@@ -163,8 +163,19 @@ module sensors393 #( ...@@ -163,8 +163,19 @@ module sensors393 #(
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000) parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000, parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000, parameter IPCLK2X_PHASE = 0.000,
parameter BUF_IPCLK = "BUFR", // parameter BUF_IPCLK = "BUFR",
parameter BUF_IPCLK2X = "BUFR", // parameter BUF_IPCLK2X = "BUFR",
parameter BUF_IPCLK_SENS0 = "BUFR", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS0 = "BUFR", //G", // "BUFR",
parameter BUF_IPCLK_SENS1 = "BUFG", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS1 = "BUFG", // "BUFR",
parameter BUF_IPCLK_SENS2 = "BUFR", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS2 = "BUFR", //G", // "BUFR",
parameter BUF_IPCLK_SENS3 = "BUFG", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
parameter BUF_IPCLK2X_SENS3 = "BUFG", // "BUFR",
parameter SENS_DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN parameter SENS_DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
...@@ -375,8 +386,8 @@ module sensors393 #( ...@@ -375,8 +386,8 @@ module sensors393 #(
.CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR), .CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR),
.IPCLK_PHASE (IPCLK_PHASE), .IPCLK_PHASE (IPCLK_PHASE),
.IPCLK2X_PHASE (IPCLK2X_PHASE), .IPCLK2X_PHASE (IPCLK2X_PHASE),
.BUF_IPCLK (BUF_IPCLK), .BUF_IPCLK ((i & 2) ? ((i & 1) ? BUF_IPCLK_SENS3 : BUF_IPCLK_SENS2) : ((i & 1) ?BUF_IPCLK_SENS1 :BUF_IPCLK_SENS0 )),
.BUF_IPCLK2X (BUF_IPCLK2X), .BUF_IPCLK2X ((i & 2) ? ((i & 1) ? BUF_IPCLK2X_SENS3 : BUF_IPCLK2X_SENS2) : ((i & 1) ?BUF_IPCLK2X_SENS1 :BUF_IPCLK2X_SENS0 )),
.SENS_DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE), .SENS_DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE),
.SENS_REF_JITTER1 (SENS_REF_JITTER1), .SENS_REF_JITTER1 (SENS_REF_JITTER1),
.SENS_REF_JITTER2 (SENS_REF_JITTER2), .SENS_REF_JITTER2 (SENS_REF_JITTER2),
......
system_defines.vh
View file @ 8b0a0f11
...@@ -3,6 +3,8 @@ ...@@ -3,6 +3,8 @@
`define SYSTEM_DEFINES `define SYSTEM_DEFINES
// will not use simultaneous reset in shift registers, just and input data with ~rst // will not use simultaneous reset in shift registers, just and input data with ~rst
`define SHREG_SEQUENTIAL_RESET 1 `define SHREG_SEQUENTIAL_RESET 1
// synthesis does to recognize global clock as G input of the primitive latch
`undef INFER_LATCHES
//`define MEMBRIDGE_DEBUG_READ 1 //`define MEMBRIDGE_DEBUG_READ 1
`define use200Mhz 1 `define use200Mhz 1
`define USE_CMD_ENCOD_TILED_32_RD 1 `define USE_CMD_ENCOD_TILED_32_RD 1
......
wrap/iserdes_mem.v
View file @ 8b0a0f11
...@@ -32,7 +32,8 @@ module iserdes_mem # ...@@ -32,7 +32,8 @@ module iserdes_mem #
input rst, // reset input rst, // reset
input d_direct, // direct input from IOB, normally not used, controlled by IOBDELAY parameter (set to "NONE") input d_direct, // direct input from IOB, normally not used, controlled by IOBDELAY parameter (set to "NONE")
input ddly, // serial input from idelay input ddly, // serial input from idelay
output [3:0] dout output [3:0] dout,
output comb_out // combinatorial output copies selected input to be used in the fabric
); );
`ifndef IVERILOG // Not using simulator - instantiate actual ISERDESE2 (can not be simulated because of encrypted ) `ifndef IVERILOG // Not using simulator - instantiate actual ISERDESE2 (can not be simulated because of encrypted )
...@@ -58,7 +59,7 @@ module iserdes_mem # ...@@ -58,7 +59,7 @@ module iserdes_mem #
) )
iserdes_i iserdes_i
( (
.O (), .O (comb_out),
.Q1 (dout[3]), .Q1 (dout[3]),
.Q2 (dout[2]), .Q2 (dout[2]),
.Q3 (dout[1]), .Q3 (dout[1]),
...@@ -109,7 +110,7 @@ module iserdes_mem # ...@@ -109,7 +110,7 @@ module iserdes_mem #
) )
iserdes_i iserdes_i
( (
.O (), .O (comb_out),
.Q1 (dout[3]), .Q1 (dout[3]),
.Q2 (dout[2]), .Q2 (dout[2]),
.Q3 (dout[1]), .Q3 (dout[1]),
......
x393.v
View file @ 8b0a0f11
...@@ -1451,8 +1451,14 @@ assign axi_grst = axi_rst_pre; ...@@ -1451,8 +1451,14 @@ assign axi_grst = axi_rst_pre;
.CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR), .CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR),
.IPCLK_PHASE (IPCLK_PHASE), .IPCLK_PHASE (IPCLK_PHASE),
.IPCLK2X_PHASE (IPCLK2X_PHASE), .IPCLK2X_PHASE (IPCLK2X_PHASE),
.BUF_IPCLK (BUF_IPCLK), .BUF_IPCLK_SENS0 (BUF_IPCLK_SENS0),
.BUF_IPCLK2X (BUF_IPCLK2X), .BUF_IPCLK2X_SENS0 (BUF_IPCLK2X_SENS0),
.BUF_IPCLK_SENS1 (BUF_IPCLK_SENS1),
.BUF_IPCLK2X_SENS1 (BUF_IPCLK2X_SENS1),
.BUF_IPCLK_SENS2 (BUF_IPCLK_SENS2),
.BUF_IPCLK2X_SENS2 (BUF_IPCLK2X_SENS2),
.BUF_IPCLK_SENS3 (BUF_IPCLK_SENS3),
.BUF_IPCLK2X_SENS3 (BUF_IPCLK2X_SENS3),
.SENS_DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE), .SENS_DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE),
.SENS_REF_JITTER1 (SENS_REF_JITTER1), .SENS_REF_JITTER1 (SENS_REF_JITTER1),
.SENS_REF_JITTER2 (SENS_REF_JITTER2), .SENS_REF_JITTER2 (SENS_REF_JITTER2),
......
x393_timing.xdc
View file @ 8b0a0f11
...@@ -79,6 +79,9 @@ create_generated_clock -name axihp_clk [get_nets clocks393_i/dual_clock_axihp_i/ ...@@ -79,6 +79,9 @@ create_generated_clock -name axihp_clk [get_nets clocks393_i/dual_clock_axihp_i/
create_generated_clock -name xclk [get_nets clocks393_i/dual_clock_xclk_i/clk1x_pre ] create_generated_clock -name xclk [get_nets clocks393_i/dual_clock_xclk_i/clk1x_pre ]
create_generated_clock -name xclk2x [get_nets clocks393_i/dual_clock_xclk_i/clk2x_pre ] create_generated_clock -name xclk2x [get_nets clocks393_i/dual_clock_xclk_i/clk2x_pre ]
#clock for inter - camera synchronization and event logger
create_generated_clock -name sclk [get_nets clocks393_i/dual_clock_sync_clk_i/clk1x_pre ]
create_clock -name ffclk0 -period 41.667 [get_ports {ffclk0p}] create_clock -name ffclk0 -period 41.667 [get_ports {ffclk0p}]
#Generated clocks are assumed to be tied to clkin1 (not 2), so until external ffclk0 is constrained, derivative clocks are not generated #Generated clocks are assumed to be tied to clkin1 (not 2), so until external ffclk0 is constrained, derivative clocks are not generated
create_generated_clock -name pclk [get_nets clocks393_i/dual_clock_pclk_i/clk1x_pre ] create_generated_clock -name pclk [get_nets clocks393_i/dual_clock_pclk_i/clk1x_pre ]
...@@ -105,7 +108,11 @@ set_clock_groups -name ps_async_clock -asynchronous -group {axi_aclk} ...@@ -105,7 +108,11 @@ set_clock_groups -name ps_async_clock -asynchronous -group {axi_aclk}
set_clock_groups -name ps_async_clock_axihp -asynchronous -group {axihp_clk} set_clock_groups -name ps_async_clock_axihp -asynchronous -group {axihp_clk}
set_clock_groups -name compressor_clocks_xclk_xclk2x -asynchronous -group {xclk xclk2x} set_clock_groups -name compressor_clocks_xclk_xclk2x -asynchronous -group {xclk xclk2x}
set_clock_groups -name sensor_clocks_pclk_pclk2x -asynchronous -group {pclk pclk2x} set_clock_groups -name sensor_clocks_pclk_pclk2x -asynchronous -group {pclk pclk2x}
set_clock_groups -name sync_logger_clocks_sclk -asynchronous -group {sclk }
set_clock_groups -name sensor0_clocks_iclk_pclk2x -asynchronous -group {iclk0 iclk2x0} set_clock_groups -name sensor0_clocks_iclk_pclk2x -asynchronous -group {iclk0 iclk2x0}
set_clock_groups -name sensor1_clocks_iclk_pclk2x -asynchronous -group {iclk1 iclk2x1} set_clock_groups -name sensor1_clocks_iclk_pclk2x -asynchronous -group {iclk1 iclk2x1}
set_clock_groups -name sensor2_clocks_iclk_pclk2x -asynchronous -group {iclk2 iclk2x2} set_clock_groups -name sensor2_clocks_iclk_pclk2x -asynchronous -group {iclk2 iclk2x2}
set_clock_groups -name sensor3_clocks_iclk_pclk2x -asynchronous -group {iclk3 iclk2x3} set_clock_groups -name sensor3_clocks_iclk_pclk2x -asynchronous -group {iclk3 iclk2x3}
set_clock_groups -name external_clock_ffclk0 -asynchronous -group {ffclk0}
\ No newline at end of file
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