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x393
Commit 890bad1c authored by Andrey Filippov's avatar Andrey Filippov
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connecting new modules for membridge to top module and test fixture

parent 7a0fa46b
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Showing with 438 additions and 112 deletions
axi/membridge.v
View file @ 890bad1c
......@@ -111,7 +111,7 @@ module membridge#(
output afi_rready,
input [ 5:0] afi_rid, // @SuppressThisWarning VEditor unused
input afi_rlast, // @SuppressThisWarning VEditor unused
input [ 2:0] afi_rresp, // @SuppressThisWarning VEditor unused
input [ 1:0] afi_rresp, // @SuppressThisWarning VEditor unused
// PL extra (non-AXI) signals
input [ 7:0] afi_rcount,
input [ 2:0] afi_racount,
......@@ -558,7 +558,6 @@ module membridge#(
.start (status_start) // input
);
// Port 1rd (read DDR to AFI) buffer, linear
mcntrl_buf_rd #(
.LOG2WIDTH_RD(6) // 64 bit external interface
......@@ -594,7 +593,5 @@ module membridge#(
.data_out (buf_rdata) // output[63:0]
);
endmodule
includes/x393_parameters.vh
View file @ 890bad1c
......@@ -23,8 +23,8 @@
parameter MCONTR_CMD_WR_ADDR = 'h0000, // AXI write to command sequence memory
parameter MCONTR_BUF0_RD_ADDR = 'h0400, // AXI read address from buffer 0 (PS sequence, memory read)
parameter MCONTR_BUF0_WR_ADDR = 'h0400, // AXI write address to buffer 0 (PS sequence, memory write)
parameter MCONTR_BUF1_RD_ADDR = 'h0800, // AXI read address from buffer 1 (PL sequence, scanline, memory read)
parameter MCONTR_BUF1_WR_ADDR = 'h0800, // AXI write address to buffer 1 (PL sequence, scanline, memory write)
// parameter MCONTR_BUF1_RD_ADDR = 'h0800, // AXI read address from buffer 1 (PL sequence, scanline, memory read) // not used - replaced with membridge
// parameter MCONTR_BUF1_WR_ADDR = 'h0800, // AXI write address to buffer 1 (PL sequence, scanline, memory write) // not used - replaced with membridge
parameter MCONTR_BUF2_RD_ADDR = 'h0c00, // AXI read address from buffer 2 (PL sequence, tiles, memory read)
parameter MCONTR_BUF2_WR_ADDR = 'h0c00, // AXI write address to buffer 2 (PL sequence, tiles, memory write)
parameter MCONTR_BUF3_RD_ADDR = 'h1000, // AXI read address from buffer 3 (PL sequence, scanline, memory read)
......@@ -128,7 +128,7 @@
`ifdef use200Mhz
parameter real REFCLK_FREQUENCY = 200.0, // 300.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter CLKIN_PERIOD = 20, // 10, //ns >1.25, 600<Fvco<1200 // Hardware 150MHz , change to | 6.667
parameter CLKIN_PERIOD = 20, // 10, //ns >1.25, 600<Fvco<1200 // Hardware 150MHz , change to | 6.667
parameter CLKFBOUT_MULT = 16, // 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE | 16
parameter CLKFBOUT_MULT_REF = 16, // 18, // 9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE | 6
parameter CLKFBOUT_DIV_REF = 4, // 200Mhz 3, // To get 300MHz for the reference clock
......@@ -246,17 +246,20 @@
parameter MCNTRL_TEST01_STATUS_REG_CHN3_ADDR= 'h3e, // status/readback register for channel 4
parameter MCNTRL_TEST01_STATUS_REG_CHN4_ADDR= 'h3f, // status/readback register for channel 4
// axi_hp_clk_i parameters
parameter CLKFBOUT_MULT_AXIHP = 18,
parameter CLKFBOUT_DIV_AXIHP = 6,
// membridge module parameters
parameter MEMBRIDGE_ADDR= 'h200,
parameter MEMBRIDGE_MASK= 'h3f0,
parameter MEMBRIDGE_CTRL= 'h0,
parameter MEMBRIDGE_CTRL= 'h0, // bit 0 - enable, bits[2:1]: 01 - start, 11 - start and reset address
parameter MEMBRIDGE_STATUS_CNTRL= 'h1,
parameter MEMBRIDGE_RD_LOADDR64= 'h2,
parameter MEMBRIDGE_RD_RUNADDR64= 'h3,
parameter MEMBRIDGE_RD_LEN64= 'h5,
parameter MEMBRIDGE_WR_LOADDR64= 'h2,
parameter MEMBRIDGE_WR_RUNADDR64= 'h3,
parameter MEMBRIDGE_WR_LEN64= 'h5,
parameter MEMBRIDGE_LO_ADDR64= 'h2, // low address of the system memory, in 64-bit words (<<3 to get byte address)
parameter MEMBRIDGE_SIZE64= 'h3, // size of the system memory range (access will roll over to lo_addr
parameter MEMBRIDGE_START64= 'h4, // start address relative to lo_addr
parameter MEMBRIDGE_LEN64= 'h5, // full length of transfer in 64-bit words
parameter MEMBRIDGE_WIDTH64= 'h6, // frame width in 64-bit words (partial last page in each line)
parameter MEMBRIDGE_STATUS_REG= 'h3b,
parameter RSEL= 1'b1, // late/early READ commands (to adjust timing by 1 SDCLK period)
......
memctrl/mcntrl393.v
View file @ 890bad1c
......@@ -27,8 +27,8 @@ module mcntrl393 #(
parameter MCONTR_CMD_WR_ADDR = 'h0000, // AXI write to command sequence memory
parameter MCONTR_BUF0_RD_ADDR = 'h0400, // AXI read address from buffer 0 (PS sequence, memory read)
parameter MCONTR_BUF0_WR_ADDR = 'h0400, // AXI write address to buffer 0 (PS sequence, memory write)
parameter MCONTR_BUF1_RD_ADDR = 'h0800, // AXI read address from buffer 1 (PL sequence, scanline, memory read)
parameter MCONTR_BUF1_WR_ADDR = 'h0800, // AXI write address to buffer 1 (PL sequence, scanline, memory write)
// parameter MCONTR_BUF1_RD_ADDR = 'h0800, // AXI read address from buffer 1 (PL sequence, scanline, memory read) // not used - replaced with membridge
// parameter MCONTR_BUF1_WR_ADDR = 'h0800, // AXI write address to buffer 1 (PL sequence, scanline, memory write) // not used - replaced with membridge
parameter MCONTR_BUF2_RD_ADDR = 'h0c00, // AXI read address from buffer 2 (PL sequence, tiles, memory read)
parameter MCONTR_BUF2_WR_ADDR = 'h0c00, // AXI write address to buffer 2 (PL sequence, tiles, memory write)
parameter MCONTR_BUF3_RD_ADDR = 'h1000, // AXI read address from buffer 3 (PL sequence, scanline, memory read)
......@@ -262,16 +262,34 @@ module mcntrl393 #(
// wire [31:0] port0_rdata; //
// wire [31:0] status_rdata; //
// Channels 2 and 3 control signals
// TODO: move line_unfinished and suspend to internals of this module (and control comparator modes)
// Channel 1 - AFI read/write to system memory with scanline linear mode
input frame_start_chn1, // resets page, x,y, and initiates transfer requests (in write mode will wait for next_page)
input next_page_chn1, // page was read/written from/to 4*1kB on-chip buffer
output cmd_wrmem_chn1, // channel1 in write mode
output page_ready_chn1, // == xfer_done, connect externally | Single-cycle pulse indicating that a page was read/written from/to DDR3 memory
output frame_done_chn1, // single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory
// optional I/O for channel synchronization
output [FRAME_HEIGHT_BITS-1:0] line_unfinished_chn1, // number of the current (ufinished ) line, REALATIVE TO FRAME, NOT WINDOW?.
input suspend_chn1, // suspend transfers (from external line number comparator)
// chn1 buffer interface, DDR3 memory read
output xfer_reset_page1_rd, // input
output buf_wpage_nxt_chn1, // input
output buf_wr_chn1, // input
output [63:0] buf_wdata_chn1,
// chn1 buffer interface, DDR3 memory write
output xfer_reset_page1_wr, // input @ posedge mclk
output rpage_nxt_chn1,
output buf_rd_chn1,
input [63:0] buf_rdata_chn1,
// Channels 2 and 3 control signals
input frame_start_chn2, // resets page, x,y, and initiates transfer requests (in write mode will wait for next_page)
input next_page_chn2, // page was read/written from/to 4*1kB on-chip buffer
output page_ready_chn2, // == xfer_done, connect externally | Single-cycle pulse indicating that a page was read/written from/to DDR3 memory
......@@ -359,13 +377,15 @@ module mcntrl393 #(
wire channel_pgm_en1;
wire seq_done1;
wire page_nxt_chn1;
// routed outside to membredge module
/*
wire buf_wr_chn1;
wire buf_wpage_nxt_chn1;
wire [63:0] buf_wdata_chn1;
wire buf_rd_chn1;
wire rpage_nxt_chn1;
wire [63:0] buf_rdata_chn1;
*/
wire want_rq2;
wire need_rq2;
wire channel_pgm_en2;
......@@ -449,8 +469,8 @@ module mcntrl393 #(
wire select_cmd0_w;
wire select_buf0rd_w;
wire select_buf0wr_w;
wire select_buf1rd_w;
wire select_buf1wr_w;
// wire select_buf1rd_w; // not used - replaced with membridge
// wire select_buf1wr_w; // not used - replaced with membridge
wire select_buf2rd_w;
wire select_buf2wr_w;
wire select_buf3rd_w;
......@@ -461,8 +481,8 @@ module mcntrl393 #(
reg select_cmd0;
reg select_buf0rd;
reg select_buf0wr;
reg select_buf1rd;
reg select_buf1wr;
// reg select_buf1rd; // not used - replaced with membridge
// reg select_buf1wr; // not used - replaced with membridge
reg select_buf2rd;
reg select_buf2wr;
reg select_buf3rd;
......@@ -471,7 +491,7 @@ module mcntrl393 #(
reg select_buf4wr;
reg select_buf0rd_d; // delayed by 1 clock, for combining with regen?
reg select_buf1rd_d;
// reg select_buf1rd_d; // not used - replaced with membridge
reg select_buf2rd_d;
reg select_buf3rd_d;
reg select_buf4rd_d;
......@@ -483,22 +503,22 @@ module mcntrl393 #(
reg [31:0] buf_wdata;
reg cmd_we;
reg buf0wr_we;
reg buf1wr_we;
// reg buf1wr_we; // not used - replaced with membridge
reg buf2wr_we;
reg buf3wr_we;
reg buf4wr_we;
wire [BUFFER_DEPTH32-1:0] buf_raddr;
wire [31:0] buf0_data;
wire [31:0] buf1rd_data;
// wire [31:0] buf1rd_data; // not used - replaced with membridge
wire [31:0] buf2rd_data;
wire [31:0] buf3rd_data;
wire [31:0] buf4rd_data;
wire buf0_rd;
wire buf0_regen;
wire buf1rd_rd;
wire buf1rd_regen;
// wire buf1rd_rd; // not used - replaced with membridge
// wire buf1rd_regen; // not used - replaced with membridge
wire buf2rd_rd;
wire buf2rd_regen;
wire buf3rd_rd;
......@@ -522,9 +542,8 @@ module mcntrl393 #(
wire lin_rw_chn1_partial; // do not increment page in the end, continue current
wire lin_rw_chn1_start_rd; // start generating commands
wire lin_rw_chn1_start_wr; // start generating commands
// wire [1:0] xfer_page2; // "internal" buffer page
wire xfer_reset_page1_wr; // "internal" buffer page reset, @posedge mclk
wire xfer_reset_page1_rd; // "internal" buffer page reset, @negedge mclk
// wire xfer_reset_page1_wr; // not used - replaced with membridge
// wire xfer_reset_page1_rd; // not used - replaced with membridge
wire [2:0] lin_rw_chn3_bank; // bank address
wire [ADDRESS_NUMBER-1:0] lin_rw_chn3_row; // memory row
......@@ -533,7 +552,6 @@ module mcntrl393 #(
wire lin_rw_chn3_partial; // do not increment page in the end, continue current
wire lin_rw_chn3_start_rd; // start generating commands
wire lin_rw_chn3_start_wr; // start generating commands
// wire [1:0] xfer_page3; // "internal" buffer page
wire xfer_reset_page3_wr; // "internal" buffer page reset, @posedge mclk
wire xfer_reset_page3_rd; // "internal" buffer page reset, @negedge mclk
......@@ -627,15 +645,15 @@ module mcntrl393 #(
// For now - combinatorial, maybe add registers (modify axibram_read)
assign buf_raddr=axird_raddr;
assign axird_rdata = (select_buf0rd ? buf0_data : 32'b0) |
(select_buf1rd ? buf1rd_data : 32'b0) |
// (select_buf1rd ? buf1rd_data : 32'b0) | // not used - replaced with membridge
(select_buf2rd ? buf2rd_data : 32'b0) |
(select_buf3rd ? buf3rd_data : 32'b0) |
(select_buf4rd ? buf4rd_data : 32'b0);
assign buf0_rd= axird_ren && select_buf0rd;
assign buf0_regen= axird_regen && select_buf0rd_d;
assign buf1rd_rd= axird_ren && select_buf1rd;
assign buf1rd_regen= axird_regen && select_buf1rd_d;
// assign buf1rd_rd= axird_ren && select_buf1rd; // not used - replaced with membridge
// assign buf1rd_regen= axird_regen && select_buf1rd_d; // not used - replaced with membridge
assign buf2rd_rd= axird_ren && select_buf2rd;
assign buf2rd_regen= axird_regen && select_buf2rd_d;
assign buf3rd_rd= axird_ren && select_buf3rd;
......@@ -654,8 +672,8 @@ module mcntrl393 #(
assign select_cmd0_w = ((axiwr_pre_awaddr ^ MCONTR_CMD_WR_ADDR) & MCONTR_WR_MASK)==0;
assign select_buf0rd_w = ((axird_pre_araddr ^ MCONTR_BUF0_RD_ADDR) & MCONTR_RD_MASK)==0;
assign select_buf0wr_w = ((axiwr_pre_awaddr ^ MCONTR_BUF0_WR_ADDR) & MCONTR_WR_MASK)==0;
assign select_buf1rd_w = ((axird_pre_araddr ^ MCONTR_BUF1_RD_ADDR) & MCONTR_RD_MASK)==0;
assign select_buf1wr_w = ((axiwr_pre_awaddr ^ MCONTR_BUF1_WR_ADDR) & MCONTR_WR_MASK)==0;
// assign select_buf1rd_w = ((axird_pre_araddr ^ MCONTR_BUF1_RD_ADDR) & MCONTR_RD_MASK)==0; // not used - replaced with membridge
// assign select_buf1wr_w = ((axiwr_pre_awaddr ^ MCONTR_BUF1_WR_ADDR) & MCONTR_WR_MASK)==0; // not used - replaced with membridge
assign select_buf2rd_w = ((axird_pre_araddr ^ MCONTR_BUF2_RD_ADDR) & MCONTR_RD_MASK)==0;
assign select_buf2wr_w = ((axiwr_pre_awaddr ^ MCONTR_BUF2_WR_ADDR) & MCONTR_WR_MASK)==0;
assign select_buf3rd_w = ((axird_pre_araddr ^ MCONTR_BUF3_RD_ADDR) & MCONTR_RD_MASK)==0;
......@@ -672,10 +690,10 @@ module mcntrl393 #(
if (axi_rst) select_buf0wr <= 0;
else if (axiwr_start_burst) select_buf0wr <= select_buf0wr_w;
if (axi_rst) select_buf1rd <= 0;
else if (axird_start_burst) select_buf1rd <= select_buf1rd_w;
if (axi_rst) select_buf1wr <= 0;
else if (axiwr_start_burst) select_buf1wr <= select_buf1wr_w;
// if (axi_rst) select_buf1rd <= 0; // not used - replaced with membridge
// else if (axird_start_burst) select_buf1rd <= select_buf1rd_w; // not used - replaced with membridge
// if (axi_rst) select_buf1wr <= 0; // not used - replaced with membridge
// else if (axiwr_start_burst) select_buf1wr <= select_buf1wr_w; // not used - replaced with membridge
if (axi_rst) select_buf2rd <= 0;
else if (axird_start_burst) select_buf2rd <= select_buf2rd_w;
......@@ -694,7 +712,7 @@ module mcntrl393 #(
if (axi_rst) axird_selected_r <= 0;
else if (axird_start_burst) axird_selected_r <= select_buf0rd_w || select_buf1rd_w ||
else if (axird_start_burst) axird_selected_r <= select_buf0rd_w || //select_buf1rd_w || // not used - replaced with membridge
select_buf2rd_w || select_buf3rd_w || select_buf4rd_w;
end
always @ (posedge axi_clk) begin
......@@ -702,13 +720,13 @@ module mcntrl393 #(
if (axiwr_wen) buf_waddr <= axiwr_waddr;
cmd_we <= axiwr_wen && select_cmd0;
buf0wr_we <= axiwr_wen && select_buf0wr;
buf1wr_we <= axiwr_wen && select_buf1wr;
// buf1wr_we <= axiwr_wen && select_buf1wr; // not used - replaced with membridge
buf2wr_we <= axiwr_wen && select_buf2wr;
buf3wr_we <= axiwr_wen && select_buf3wr;
buf4wr_we <= axiwr_wen && select_buf4wr;
select_buf0rd_d <= select_buf0rd;
select_buf1rd_d <= select_buf1rd;
// select_buf1rd_d <= select_buf1rd; // not used - replaced with membridge
select_buf2rd_d <= select_buf2rd;
select_buf3rd_d <= select_buf3rd;
select_buf4rd_d <= select_buf4rd;
......@@ -777,7 +795,8 @@ module mcntrl393 #(
//
// Port memory buffer (4 pages each, R/W fixed, port 0 - AXI read from DDR, port 1 - AXI write to DDR
// Routing out to membridge module
/*
// Port 1rd (read DDR to AXI) buffer, linear
mcntrl_buf_rd #(
.LOG2WIDTH_RD(5)
......@@ -812,7 +831,7 @@ module mcntrl393 #(
.rd (buf_rd_chn1), // input
.data_out (buf_rdata_chn1) // output[63:0]
);
*/
// Port 2rd (read DDR to AXI) buffer, tiled
mcntrl_buf_rd #(
.LOG2WIDTH_RD(5)
......@@ -963,7 +982,7 @@ module mcntrl393 #(
.xfer_done (seq_done1), // input : sequence over
.xfer_page_rst_wr (xfer_reset_page1_wr), // output
.xfer_page_rst_rd (xfer_reset_page1_rd), // output
.cmd_wrmem () // output
.cmd_wrmem (cmd_wrmem_chn1) // output
);
mcntrl_linear_rw #(
......
simulation_modules/simul_axi_hp_rd.v
View file @ 890bad1c
......@@ -45,7 +45,7 @@ module simul_axi_hp_rd #(
input rready,
output [ 5:0] rid,
output rlast,
output [ 2:0] rresp,
output [ 1:0] rresp,
// PL extra (non-AXI) signals
output [ 7:0] rcount,
output [ 2:0] racount,
......
x393.v
View file @ 890bad1c
......@@ -142,7 +142,8 @@ module x393 #(
reg status_selected_regen; // status_selected (set at axird_start_burst) delayed when ren is active, then when regen (normally 2 cycles)
reg mcntrl_axird_selected_regen; // mcntrl_axird_selected (set at axird_start_burst) delayed when ren is active, then when regen (normally 2 cycles)
wire mclk;
wire mclk; // global clock, memory controller, command/status network (currently 200MHz)
wire hclk; // global clock, axi_hp (150MHz) derived from aclk_in = 50MHz
wire [11:0] tmp_debug;
......@@ -172,9 +173,13 @@ module x393 #(
wire status_mcontr_rq; // Memory controller status request
wire status_mcontr_start; // Memory controller status packet transfer start (currently with 0 latency from status_root_rq)
// Not yet connected
wire [7:0] status_other_ad; /// S uppressThisWarning VEditor ****** Other status byte-wide address/data
wire status_other_rq; /// S uppressThisWarning VEditor ****** Other status request
wire status_other_start; /// S =uppressThisWarning VEditor ****** Other status packet transfer start (currently with 0 latency from status_root_rq)
wire [7:0] status_membridge_ad; // membridge (afi to ddr3) status byte-wide address/data
wire status_membridge_rq; // membridge (afi to ddr3) status request
wire status_membridge_start; //membridge (afi to ddr3) status packet transfer start (currently with 0 latency from status_root_rq)
wire [7:0] status_other_ad = 0; // Other status byte-wide address/data
wire status_other_rq = 0; // Other status request
wire status_other_start; // SuppressThisWarning VEditor ****** Other status packet transfer start (currently with 0 latency from status_root_rq)
wire [7:0] status_test01_ad; // Test module status byte-wide address/data
......@@ -187,16 +192,31 @@ module x393 #(
wire cmd_mcontr_stb;
wire [7:0] cmd_test01_ad;
wire cmd_test01_stb;
wire [7:0] cmd_membridge_ad;
wire cmd_membridge_stb;
//mcntrl393_test01
// membridge
wire frame_start_chn1; // input
wire next_page_chn1; // input
wire cmd_wrmem_chn1;
wire page_ready_chn1; // output
wire frame_done_chn1; // output
wire[FRAME_HEIGHT_BITS-1:0] line_unfinished_chn1; // output[15:0]
wire suspend_chn1; // input
wire xfer_reset_page1_rd;
wire buf_wpage_nxt_chn1;
wire buf_wr_chn1;
wire [63:0] buf_wdata_chn1;
wire xfer_reset_page1_wr;
wire rpage_nxt_chn1;
wire buf_rd_chn1;
wire [63:0] buf_rdata_chn1;
//mcntrl393_test01
wire frame_start_chn2; // input
wire next_page_chn2; // input
wire page_ready_chn2; // output
......@@ -245,15 +265,18 @@ module x393 #(
// Clock and reset from PS
assign comb_rst=~frst[0] | frst[1];
// insert register layers if needed
assign cmd_mcontr_ad= cmd_root_ad;
assign cmd_mcontr_stb=cmd_root_stb;
assign cmd_test01_ad= cmd_root_ad;
assign cmd_test01_stb=cmd_root_stb;
assign cmd_membridge_ad= cmd_root_ad;
assign cmd_membridge_stb=cmd_root_stb;
// For now - connect status_test01 to status_other, if needed - increase number of multiplexer inputs)
assign status_other_ad = status_test01_ad;
assign status_other_rq = status_test01_rq;
assign status_test01_start = status_other_start;
// assign status_other_ad = status_test01_ad;
// assign status_other_rq = status_test01_rq;
// assign status_test01_start = status_other_start;
// missing command sequencer:
assign cseq_waddr='bx; // command sequencer write address (output to command multiplexer)
......@@ -323,6 +346,17 @@ module x393 #(
BUFG bufg_axi_rst_i (.O(axi_rst),.I(axi_rst_pre));
BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
axi_hp_clk #(
.CLKIN_PERIOD(CLKIN_PERIOD),
.CLKFBOUT_MULT_AXIHP(CLKFBOUT_MULT_AXIHP),
.CLKFBOUT_DIV_AXIHP(CLKFBOUT_DIV_AXIHP)
) axi_hp_clk_i (
.rst (axi_rst), // input
.clk_in (axi_aclk), // input
.clk_axihp (hclk), // output
.locked_axihp () // output // not controlled?
);
// channel test module
mcntrl393_test01 #(
......@@ -342,7 +376,7 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.MCNTRL_TEST01_STATUS_REG_CHN3_ADDR (MCNTRL_TEST01_STATUS_REG_CHN3_ADDR),
.MCNTRL_TEST01_STATUS_REG_CHN4_ADDR (MCNTRL_TEST01_STATUS_REG_CHN4_ADDR)
) mcntrl393_test01_i (
.rst(axi_rst), // input
.rst (axi_rst), // input
.mclk (mclk), // input
.cmd_ad (cmd_test01_ad), // input[7:0]
.cmd_stb (cmd_test01_stb), // input
......@@ -444,15 +478,24 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
);
// mux status info from the memory controller and other modules
status_router2 status_router2_top_i (
status_router4 status_router4_top_i (
.rst (axi_rst), // input
.clk (mclk), // input
.db_in0 (status_mcontr_ad), // input[7:0]
.rq_in0 (status_mcontr_rq), // input
.start_in0 (status_mcontr_start), // output
.db_in1 (status_other_ad), // input[7:0]
.rq_in1 (status_other_rq), // input
.start_in1 (status_other_start), // output
.db_in1 (status_test01_ad), // input[7:0]
.rq_in1 (status_test01_rq), // input
.start_in1 (status_test01_start), // output
.db_in2 (status_membridge_ad), // input[7:0]
.rq_in2 (status_membridge_rq), // input
.start_in2 (status_membridge_start), // output
.db_in3 (status_other_ad), // input[7:0]
.rq_in3 (status_other_rq), // input
.start_in3 (status_other_start), // output
.db_out (status_root_ad), // output[7:0]
.rq_out (status_root_rq), // output
.start_out (status_root_start) // input
......@@ -465,8 +508,8 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.MCONTR_CMD_WR_ADDR (MCONTR_CMD_WR_ADDR),
.MCONTR_BUF0_RD_ADDR (MCONTR_BUF0_RD_ADDR),
.MCONTR_BUF0_WR_ADDR (MCONTR_BUF0_WR_ADDR),
.MCONTR_BUF1_RD_ADDR (MCONTR_BUF1_RD_ADDR),
.MCONTR_BUF1_WR_ADDR (MCONTR_BUF1_WR_ADDR),
// .MCONTR_BUF1_RD_ADDR (MCONTR_BUF1_RD_ADDR), // not used - replaced with membridge
// .MCONTR_BUF1_WR_ADDR (MCONTR_BUF1_WR_ADDR), // not used - replaced with membridge
.MCONTR_BUF2_RD_ADDR (MCONTR_BUF2_RD_ADDR),
.MCONTR_BUF2_WR_ADDR (MCONTR_BUF2_WR_ADDR),
.MCONTR_BUF3_RD_ADDR (MCONTR_BUF3_RD_ADDR),
......@@ -616,10 +659,20 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
//TODO:
.frame_start_chn1 (frame_start_chn1), // input
.next_page_chn1 (next_page_chn1), // input
.cmd_wrmem_chn1 (cmd_wrmem_chn1), // output
.page_ready_chn1 (page_ready_chn1), // output
.frame_done_chn1 (frame_done_chn1), // output
.line_unfinished_chn1 (line_unfinished_chn1), // output[15:0]
.line_unfinished_chn1 (line_unfinished_chn1), // output[15:0]
.suspend_chn1 (suspend_chn1), // input
.xfer_reset_page1_rd (xfer_reset_page1_rd), // output
.buf_wpage_nxt_chn1 (buf_wpage_nxt_chn1), // output
.buf_wr_chn1 (buf_wr_chn1), // output
.buf_wdata_chn1 (buf_wdata_chn1[63:0]), // output[63:0]
.xfer_reset_page1_wr (xfer_reset_page1_wr), // output
.rpage_nxt_chn1 (rpage_nxt_chn1), // output
.buf_rd_chn1 (buf_rd_chn1), // output
.buf_rdata_chn1 (buf_rdata_chn1[63:0]), // input[63:0]
.frame_start_chn2 (frame_start_chn2), // input
.next_page_chn2 (next_page_chn2), // input
.page_ready_chn2 (page_ready_chn2), // output
......@@ -659,6 +712,139 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.tmp_debug (tmp_debug) // output[11:0]
);
wire [31:0] afi0_awaddr; // output[31:0]
wire afi0_awvalid; // output
wire afi0_awready; // input
wire [ 5:0] afi0_awid; // output[5:0]
wire [ 1:0] afi0_awlock; // output[1:0]
wire [ 3:0] afi0_awcache; // output[3:0]
wire [ 2:0] afi0_awprot; // output[2:0]
wire [ 3:0] afi0_awlen; // output[3:0]
wire [ 2:0] afi0_awsize; // output[2:0]
wire [ 1:0] afi0_awburst; // output[1:0]
wire [ 3:0] afi0_awqos; // output[3:0]
wire [63:0] afi0_wdata; // output[63:0]
wire afi0_wvalid; // output
wire afi0_wready; // input
wire [ 5:0] afi0_wid; // output[5:0]
wire afi0_wlast; // output
wire [ 7:0] afi0_wstrb; // output[7:0]
wire afi0_bvalid; // input
wire afi0_bready; // output
wire [ 5:0] afi0_bid; // input[5:0]
wire [ 1:0] afi0_bresp; // input[1:0]
wire [ 7:0] afi0_wcount; // input[7:0]
wire [ 5:0] afi0_wacount; // input[5:0]
wire afi0_wrissuecap1en; // output
wire [31:0] afi0_araddr; // output[31:0]
wire afi0_arvalid; // output
wire afi0_arready; // input
wire [ 5:0] afi0_arid; // output[5:0]
wire [ 1:0] afi0_arlock; // output[1:0]
wire [ 3:0] afi0_arcache; // output[3:0]
wire [ 2:0] afi0_arprot; // output[2:0]
wire [ 3:0] afi0_arlen; // output[3:0]
wire [ 2:0] afi0_arsize; // output[2:0]
wire [ 1:0] afi0_arburst; // output[1:0]
wire [ 3:0] afi0_arqos; // output[3:0]
wire [63:0] afi0_rdata; // input[63:0]
wire afi0_rvalid; // input
wire afi0_rready; // output
wire [ 5:0] afi0_rid; // input[5:0]
wire afi0_rlast; // input
wire [ 1:0] afi0_rresp; // input[2:0]
wire [ 7:0] afi0_rcount; // input[7:0]
wire [ 2:0] afi0_racount; // input[2:0]
wire afi0_rdissuecap1en; // output
// DDR3 frame memory to system memory bridge over axi_hp
membridge #(
.MEMBRIDGE_ADDR (MEMBRIDGE_ADDR),
.MEMBRIDGE_MASK (MEMBRIDGE_MASK),
.MEMBRIDGE_CTRL (MEMBRIDGE_CTRL),
.MEMBRIDGE_STATUS_CNTRL (MEMBRIDGE_STATUS_CNTRL),
.MEMBRIDGE_LO_ADDR64 (MEMBRIDGE_LO_ADDR64),
.MEMBRIDGE_SIZE64 (MEMBRIDGE_SIZE64),
.MEMBRIDGE_START64 (MEMBRIDGE_START64),
.MEMBRIDGE_LEN64 (MEMBRIDGE_LEN64),
.MEMBRIDGE_WIDTH64 (MEMBRIDGE_WIDTH64),
.MEMBRIDGE_STATUS_REG (MEMBRIDGE_STATUS_REG),
.FRAME_HEIGHT_BITS (FRAME_HEIGHT_BITS),
.FRAME_WIDTH_BITS (FRAME_WIDTH_BITS)
) membridge_i (
.rst (axi_rst), // input
.mclk (mclk), // input
.hclk (hclk), // input
.cmd_ad (cmd_membridge_ad), // input[7:0]
.cmd_stb (cmd_membridge_stb), // input
.status_ad (status_membridge_ad[7:0]), // output[7:0]
.status_rq (status_membridge_rq), // output
.status_start (status_membridge_start), // input
.frame_start_chn (frame_start_chn1), // output
.next_page_chn (next_page_chn1), // output
.cmd_wrmem (cmd_wrmem_chn1), // input
.page_ready_chn (page_ready_chn1), // input
.frame_done_chn (frame_done_chn1), // input
.line_unfinished_chn1 (line_unfinished_chn1), // input[15:0]
.suspend_chn1 (suspend_chn1), // output
.xfer_reset_page_rd (xfer_reset_page1_rd), // input
.buf_wpage_nxt (buf_wpage_nxt_chn1), // input
.buf_wr (buf_wr_chn1), // input
.buf_wdata (buf_wdata_chn1[63:0]), // input[63:0]
.xfer_reset_page_wr (xfer_reset_page1_wr), // input
.buf_rpage_nxt (rpage_nxt_chn1), // input
.buf_rd (buf_rd_chn1), // input
.buf_rdata (buf_rdata_chn1[63:0]), // output[63:0]
.afi_awaddr (afi0_awaddr), // output[31:0]
.afi_awvalid (afi0_awvalid), // output
.afi_awready (afi0_awready), // input
.afi_awid (afi0_awid), // output[5:0]
.afi_awlock (afi0_awlock), // output[1:0]
.afi_awcache (afi0_awcache), // output[3:0]
.afi_awprot (afi0_awprot), // output[2:0]
.afi_awlen (afi0_awlen), // output[3:0]
.afi_awsize (afi0_awsize), // output[2:0]
.afi_awburst (afi0_awburst), // output[1:0]
.afi_awqos (afi0_awqos), // output[3:0]
.afi_wdata (afi0_wdata), // output[63:0]
.afi_wvalid (afi0_wvalid), // output
.afi_wready (afi0_wready), // input
.afi_wid (afi0_wid), // output[5:0]
.afi_wlast (afi0_wlast), // output
.afi_wstrb (afi0_wstrb), // output[7:0]
.afi_bvalid (afi0_bvalid), // input
.afi_bready (afi0_bready), // output
.afi_bid (afi0_bid), // input[5:0]
.afi_bresp (afi0_bresp), // input[1:0]
.afi_wcount (afi0_wcount), // input[7:0]
.afi_wacount (afi0_wacount), // input[5:0]
.afi_wrissuecap1en (afi0_wrissuecap1en), // output
.afi_araddr (afi0_araddr), // output[31:0]
.afi_arvalid (afi0_arvalid), // output
.afi_arready (afi0_arready), // input
.afi_arid (afi0_arid), // output[5:0]
.afi_arlock (afi0_arlock), // output[1:0]
.afi_arcache (afi0_arcache), // output[3:0]
.afi_arprot (afi0_arprot), // output[2:0]
.afi_arlen (afi0_arlen), // output[3:0]
.afi_arsize (afi0_arsize), // output[2:0]
.afi_arburst (afi0_arburst), // output[1:0]
.afi_arqos (afi0_arqos), // output[3:0]
.afi_rdata (afi0_rdata), // input[63:0]
.afi_rvalid (afi0_rvalid), // input
.afi_rready (afi0_rready), // output
.afi_rid (afi0_rid), // input[5:0]
.afi_rlast (afi0_rlast), // input
.afi_rresp (afi0_rresp), // input[2:0]
.afi_rcount (afi0_rcount), // input[7:0]
.afi_racount (afi0_racount), // input[2:0]
.afi_rdissuecap1en (afi0_rdissuecap1en) // output
);
/*
{
frst[3]?{
......@@ -1280,57 +1466,57 @@ assign DUMMY_TO_KEEP = frst[2] && MEMCLK; // 1'b0; // dbg_toggle[0];
// AXI PS Slave HP0
// AXI PS Slave HP0: Clock, Reset
.SAXIHP0ACLK(), // AXI PS Slave HP0 Clock , input
.SAXIHP0ARESETN(), // AXI PS Slave HP0 Reset, output
.SAXIHP0ACLK (hclk), // AXI PS Slave HP0 Clock , input
.SAXIHP0ARESETN (), // AXI PS Slave HP0 Reset, output
// AXI PS Slave HP0: Read Address
.SAXIHP0ARADDR(), // AXI PS Slave HP0 ARADDR[31:0], input
.SAXIHP0ARVALID(), // AXI PS Slave HP0 ARVALID, input
.SAXIHP0ARREADY(), // AXI PS Slave HP0 ARREADY, output
.SAXIHP0ARID(), // AXI PS Slave HP0 ARID[5:0], input
.SAXIHP0ARLOCK(), // AXI PS Slave HP0 ARLOCK[1:0], input
.SAXIHP0ARCACHE(), // AXI PS Slave HP0 ARCACHE[3:0], input
.SAXIHP0ARPROT(), // AXI PS Slave HP0 ARPROT[2:0], input
.SAXIHP0ARLEN(), // AXI PS Slave HP0 ARLEN[3:0], input
.SAXIHP0ARSIZE(), // AXI PS Slave HP0 ARSIZE[2:0], input
.SAXIHP0ARBURST(), // AXI PS Slave HP0 ARBURST[1:0], input
.SAXIHP0ARQOS(), // AXI PS Slave HP0 ARQOS[3:0], input
.SAXIHP0ARADDR (afi0_araddr), // AXI PS Slave HP0 ARADDR[31:0], input
.SAXIHP0ARVALID (afi0_arvalid), // AXI PS Slave HP0 ARVALID, input
.SAXIHP0ARREADY (afi0_arready), // AXI PS Slave HP0 ARREADY, output
.SAXIHP0ARID (afi0_arid), // AXI PS Slave HP0 ARID[5:0], input
.SAXIHP0ARLOCK (afi0_arlock), // AXI PS Slave HP0 ARLOCK[1:0], input
.SAXIHP0ARCACHE (afi0_arcache), // AXI PS Slave HP0 ARCACHE[3:0], input
.SAXIHP0ARPROT (afi0_arprot), // AXI PS Slave HP0 ARPROT[2:0], input
.SAXIHP0ARLEN (afi0_arlen), // AXI PS Slave HP0 ARLEN[3:0], input
.SAXIHP0ARSIZE (afi0_arsize), // AXI PS Slave HP0 ARSIZE[2:0], input
.SAXIHP0ARBURST (afi0_arburst), // AXI PS Slave HP0 ARBURST[1:0], input
.SAXIHP0ARQOS (afi0_arqos), // AXI PS Slave HP0 ARQOS[3:0], input
// AXI PS Slave HP0: Read Data
.SAXIHP0RDATA(), // AXI PS Slave HP0 RDATA[63:0], output
.SAXIHP0RVALID(), // AXI PS Slave HP0 RVALID, output
.SAXIHP0RREADY(), // AXI PS Slave HP0 RREADY, input
.SAXIHP0RID(), // AXI PS Slave HP0 RID[5:0], output
.SAXIHP0RLAST(), // AXI PS Slave HP0 RLAST, output
.SAXIHP0RRESP(), // AXI PS Slave HP0 RRESP[1:0], output
.SAXIHP0RCOUNT(), // AXI PS Slave HP0 RCOUNT[7:0], output
.SAXIHP0RACOUNT(), // AXI PS Slave HP0 RACOUNT[2:0], output
.SAXIHP0RDISSUECAP1EN(), // AXI PS Slave HP0 RDISSUECAP1EN, input
.SAXIHP0RDATA (afi0_rdata), // AXI PS Slave HP0 RDATA[63:0], output
.SAXIHP0RVALID (afi0_rvalid), // AXI PS Slave HP0 RVALID, output
.SAXIHP0RREADY (afi0_rready), // AXI PS Slave HP0 RREADY, input
.SAXIHP0RID (afi0_rid), // AXI PS Slave HP0 RID[5:0], output
.SAXIHP0RLAST (afi0_rlast), // AXI PS Slave HP0 RLAST, output
.SAXIHP0RRESP (afi0_rresp), // AXI PS Slave HP0 RRESP[1:0], output
.SAXIHP0RCOUNT (afi0_rcount), // AXI PS Slave HP0 RCOUNT[7:0], output
.SAXIHP0RACOUNT (afi0_racount), // AXI PS Slave HP0 RACOUNT[2:0], output
.SAXIHP0RDISSUECAP1EN (afi0_rdissuecap1en), // AXI PS Slave HP0 RDISSUECAP1EN, input
// AXI PS Slave HP0: Write Address
.SAXIHP0AWADDR(), // AXI PS Slave HP0 AWADDR[31:0], input
.SAXIHP0AWVALID(), // AXI PS Slave HP0 AWVALID, input
.SAXIHP0AWREADY(), // AXI PS Slave HP0 AWREADY, output
.SAXIHP0AWID(), // AXI PS Slave HP0 AWID[5:0], input
.SAXIHP0AWLOCK(), // AXI PS Slave HP0 AWLOCK[1:0], input
.SAXIHP0AWCACHE(), // AXI PS Slave HP0 AWCACHE[3:0], input
.SAXIHP0AWPROT(), // AXI PS Slave HP0 AWPROT[2:0], input
.SAXIHP0AWLEN(), // AXI PS Slave HP0 AWLEN[3:0], input
.SAXIHP0AWSIZE(), // AXI PS Slave HP0 AWSIZE[1:0], input
.SAXIHP0AWBURST(), // AXI PS Slave HP0 AWBURST[1:0], input
.SAXIHP0AWQOS(), // AXI PS Slave HP0 AWQOS[3:0], input
.SAXIHP0AWADDR (afi0_awaddr), // AXI PS Slave HP0 AWADDR[31:0], input
.SAXIHP0AWVALID (afi0_awvalid), // AXI PS Slave HP0 AWVALID, input
.SAXIHP0AWREADY (afi0_awready), // AXI PS Slave HP0 AWREADY, output
.SAXIHP0AWID (afi0_awid), // AXI PS Slave HP0 AWID[5:0], input
.SAXIHP0AWLOCK (afi0_awlock), // AXI PS Slave HP0 AWLOCK[1:0], input
.SAXIHP0AWCACHE (afi0_awcache), // AXI PS Slave HP0 AWCACHE[3:0], input
.SAXIHP0AWPROT (afi0_awprot), // AXI PS Slave HP0 AWPROT[2:0], input
.SAXIHP0AWLEN (afi0_awlen), // AXI PS Slave HP0 AWLEN[3:0], input
.SAXIHP0AWSIZE (afi0_awsize), // AXI PS Slave HP0 AWSIZE[1:0], input
.SAXIHP0AWBURST (afi0_awburst), // AXI PS Slave HP0 AWBURST[1:0], input
.SAXIHP0AWQOS (afi0_awqos), // AXI PS Slave HP0 AWQOS[3:0], input
// AXI PS Slave HP0: Write Data
.SAXIHP0WDATA(), // AXI PS Slave HP0 WDATA[63:0], input
.SAXIHP0WVALID(), // AXI PS Slave HP0 WVALID, input
.SAXIHP0WREADY(), // AXI PS Slave HP0 WREADY, output
.SAXIHP0WID(), // AXI PS Slave HP0 WID[5:0], input
.SAXIHP0WLAST(), // AXI PS Slave HP0 WLAST, input
.SAXIHP0WSTRB(), // AXI PS Slave HP0 WSTRB[7:0], input
.SAXIHP0WCOUNT(), // AXI PS Slave HP0 WCOUNT[7:0], output
.SAXIHP0WACOUNT(), // AXI PS Slave HP0 WACOUNT[5:0], output
.SAXIHP0WRISSUECAP1EN(), // AXI PS Slave HP0 WRISSUECAP1EN, input
.SAXIHP0WDATA (afi0_wdata), // AXI PS Slave HP0 WDATA[63:0], input
.SAXIHP0WVALID (afi0_wvalid), // AXI PS Slave HP0 WVALID, input
.SAXIHP0WREADY (afi0_wready), // AXI PS Slave HP0 WREADY, output
.SAXIHP0WID (afi0_wid), // AXI PS Slave HP0 WID[5:0], input
.SAXIHP0WLAST (afi0_wlast), // AXI PS Slave HP0 WLAST, input
.SAXIHP0WSTRB (afi0_wstrb), // AXI PS Slave HP0 WSTRB[7:0], input
.SAXIHP0WCOUNT (afi0_wcount), // AXI PS Slave HP0 WCOUNT[7:0], output
.SAXIHP0WACOUNT (afi0_wacount), // AXI PS Slave HP0 WACOUNT[5:0], output
.SAXIHP0WRISSUECAP1EN (afi0_wrissuecap1en), // AXI PS Slave HP0 WRISSUECAP1EN, input
// AXI PS Slave HP0: Write Responce
.SAXIHP0BVALID(), // AXI PS Slave HP0 BVALID, output
.SAXIHP0BREADY(), // AXI PS Slave HP0 BREADY, input
.SAXIHP0BID(), // AXI PS Slave HP0 BID[5:0], output
.SAXIHP0BRESP(), // AXI PS Slave HP0 BRESP[1:0], output
.SAXIHP0BVALID (afi0_bvalid), // AXI PS Slave HP0 BVALID, output
.SAXIHP0BREADY (afi0_bready), // AXI PS Slave HP0 BREADY, input
.SAXIHP0BID (afi0_bid), // AXI PS Slave HP0 BID[5:0], output
.SAXIHP0BRESP (afi0_bresp), // AXI PS Slave HP0 BRESP[1:0], output
// AXI PS Slave HP1
// AXI PS Slave 1: Clock, Reset
......
x393_testbench01.tf
View file @ 890bad1c
......@@ -80,6 +80,36 @@ module x393_testbench01 #(
wire DUMMY_TO_KEEP; // output to keep PS7 signals from "optimization" // SuppressThisWarning all - not used
// wire MEMCLK;
// axi_hp simulation signals
reg [31:0] afi_reg_addr;
reg afi_reg_wr;
reg afi_reg_rd;
reg [31:0] afi_reg_din;
wire [31:0] afi_reg_dout;
wire [31:0] afi_sim_rd_address; // output[31:0]
wire [ 5:0] afi_sim_rid; // output[5:0]
reg afi_sim_rd_valid; // input
wire afi_sim_rd_ready; // output
reg [63:0] afi_sim_rd_data; // input[63:0]
wire [ 2:0] afi_sim_rd_cap; // output[2:0]
wire [ 3:0] afi_sim_rd_qos; // output[3:0]
reg [ 1:0] afi_sim_rd_resp; // input[1:0]
wire [31:0] afi_sim_wr_address; // output[31:0]
wire [ 5:0] afi_sim_wid; // output[5:0]
wire afi_sim_wr_valid; // output
reg afi_sim_wr_ready; // input
wire [63:0] afi_sim_wr_data; // output[63:0]
wire [ 7:0] afi_sim_wr_stb; // output[7:0]
reg [ 3:0] afi_sim_bresp_latency; // input[3:0]
wire [ 2:0] afi_sim_wr_cap; // output[2:0]
wire [ 3:0] afi_sim_wr_qos; // output[3:0]
reg [639:0] TEST_TITLE;
// Simulation signals
reg [11:0] ARID_IN_r;
......@@ -548,8 +578,8 @@ assign bresp= x393_i.ps7_i.MAXIGP0BRESP;
.MCONTR_CMD_WR_ADDR (MCONTR_CMD_WR_ADDR),
.MCONTR_BUF0_RD_ADDR (MCONTR_BUF0_RD_ADDR),
.MCONTR_BUF0_WR_ADDR (MCONTR_BUF0_WR_ADDR),
.MCONTR_BUF1_RD_ADDR (MCONTR_BUF1_RD_ADDR),
.MCONTR_BUF1_WR_ADDR (MCONTR_BUF1_WR_ADDR),
// .MCONTR_BUF1_RD_ADDR (MCONTR_BUF1_RD_ADDR),
// .MCONTR_BUF1_WR_ADDR (MCONTR_BUF1_WR_ADDR),
.MCONTR_BUF2_RD_ADDR (MCONTR_BUF2_RD_ADDR),
.MCONTR_BUF2_WR_ADDR (MCONTR_BUF2_WR_ADDR),
.MCONTR_BUF3_RD_ADDR (MCONTR_BUF3_RD_ADDR),
......@@ -1072,6 +1102,97 @@ simul_axi_read #(
.addr_out(SIMUL_AXI_ADDR_W[SIMUL_AXI_READ_WIDTH-1:0]),
.burst(), // burst in progress - just debug
.err_out()); // data last does not match predicted or FIFO over/under run - just debug
simul_axi_hp_rd #(
.HP_PORT(0)
) simul_axi_hp_rd_i (
.rst (RST), // input
.aclk (x393_i.ps7_i.SAXIHP0ACLK), // input
.aresetn (), // output
.araddr (x393_i.ps7_i.SAXIHP0ARADDR[31:0]), // input[31:0]
.arvalid (x393_i.ps7_i.SAXIHP0ARVALID), // input
.arready (x393_i.ps7_i.SAXIHP0ARREADY), // output
.arid (x393_i.ps7_i.SAXIHP0ARID), // input[5:0]
.arlock (x393_i.ps7_i.SAXIHP0ARLOCK), // input[1:0]
.arcache (x393_i.ps7_i.SAXIHP0ARCACHE), // input[3:0]
.arprot (x393_i.ps7_i.SAXIHP0ARPROT), // input[2:0]
.arlen (x393_i.ps7_i.SAXIHP0ARLEN), // input[3:0]
.arsize (x393_i.ps7_i.SAXIHP0ARSIZE), // input[2:0]
.arburst (x393_i.ps7_i.SAXIHP0ARBURST), // input[1:0]
.arqos (x393_i.ps7_i.SAXIHP0ARQOS), // input[3:0]
.rdata (x393_i.ps7_i.SAXIHP0RDATA), // output[63:0]
.rvalid (x393_i.ps7_i.SAXIHP0RVALID), // output
.rready (x393_i.ps7_i.SAXIHP0RREADY), // input
.rid (x393_i.ps7_i.SAXIHP0RID), // output[5:0]
.rlast (x393_i.ps7_i.SAXIHP0RLAST), // output
.rresp (x393_i.ps7_i.SAXIHP0RRESP), // output[1:0]
.rcount (x393_i.ps7_i.SAXIHP0RCOUNT), // output[7:0]
.racount (x393_i.ps7_i.SAXIHP0RACOUNT), // output[2:0]
.rdissuecap1en (x393_i.ps7_i.SAXIHP0RDISSUECAP1EN), // input
.sim_rd_address (afi_sim_rd_address), // output[31:0]
.sim_rid (afi_sim_rid), // output[5:0]
.sim_rd_valid (afi_sim_rd_valid), // input
.sim_rd_ready (afi_sim_rd_ready), // output
.sim_rd_data (afi_sim_rd_data), // input[63:0]
.sim_rd_cap (afi_sim_rd_cap), // output[2:0]
.sim_rd_qos (afi_sim_rd_qos), // output[3:0]
.sim_rd_resp (afi_sim_rd_resp), // input[1:0]
.reg_addr (afi_reg_addr), // input[31:0]
.reg_wr (afi_reg_wr), // input
.reg_rd (afi_reg_rd), // input
.reg_din (afi_reg_din), // input[31:0]
.reg_dout (afi_reg_dout) // output[31:0]
);
simul_axi_hp_wr #(
.HP_PORT(0)
) simul_axi_hp_wr_i (
.rst (), // input
.aclk (x393_i.ps7_i.SAXIHP0ACLK), // input
.aresetn (), // output
.awaddr (x393_i.ps7_i.SAXIHP0AWADDR), // input[31:0]
.awvalid (x393_i.ps7_i.SAXIHP0AWVALID), // input
.awready (x393_i.ps7_i.SAXIHP0AWREADY), // output
.awid (x393_i.ps7_i.SAXIHP0AWID), // input[5:0]
.awlock (x393_i.ps7_i.SAXIHP0AWLOCK), // input[1:0]
.awcache (x393_i.ps7_i.SAXIHP0AWCACHE), // input[3:0]
.awprot (x393_i.ps7_i.SAXIHP0AWPROT), // input[2:0]
.awlen (x393_i.ps7_i.SAXIHP0AWLEN), // input[3:0]
.awsize (x393_i.ps7_i.SAXIHP0AWSIZE), // input[2:0]
.awburst (x393_i.ps7_i.SAXIHP0AWBURST), // input[1:0]
.awqos (x393_i.ps7_i.SAXIHP0AWQOS), // input[3:0]
.wdata (x393_i.ps7_i.SAXIHP0WDATA), // input[63:0]
.wvalid (x393_i.ps7_i.SAXIHP0WVALID), // input
.wready (x393_i.ps7_i.SAXIHP0WREADY), // output
.wid (x393_i.ps7_i.SAXIHP0WID), // input[5:0]
.wlast (x393_i.ps7_i.SAXIHP0WLAST), // input
.wstrb (x393_i.ps7_i.SAXIHP0WSTRB), // input[7:0]
.bvalid (x393_i.ps7_i.SAXIHP0BVALID), // output
.bready (x393_i.ps7_i.SAXIHP0BREADY), // input
.bid (x393_i.ps7_i.SAXIHP0BID), // output[5:0]
.bresp (x393_i.ps7_i.SAXIHP0BRESP), // output[1:0]
.wcount (x393_i.ps7_i.SAXIHP0WCOUNT), // output[7:0]
.wacount (x393_i.ps7_i.SAXIHP0WACOUNT), // output[5:0]
.wrissuecap1en (x393_i.ps7_i.SAXIHP0WRISSUECAP1EN), // input
.sim_wr_address (afi_sim_wr_address), // output[31:0]
.sim_wid (afi_sim_wid), // output[5:0]
.sim_wr_valid (afi_sim_wr_valid), // output
.sim_wr_ready (afi_sim_wr_ready), // input
.sim_wr_data (afi_sim_wr_data), // output[63:0]
.sim_wr_stb (afi_sim_wr_stb), // output[7:0]
.sim_bresp_latency(afi_sim_bresp_latency), // input[3:0]
.sim_wr_cap (afi_sim_wr_cap), // output[2:0]
.sim_wr_qos (afi_sim_wr_qos), // output[3:0]
.reg_addr (afi_reg_addr), // input[31:0]
.reg_wr (afi_reg_wr), // input
.reg_rd (afi_reg_rd), // input
.reg_din (afi_reg_din), // input[31:0]
.reg_dout (afi_reg_dout) // output[31:0]
);
// wire [ 3:0] SIMUL_ADD_ADDR;
always @ (posedge CLK) begin
......
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