got first jpeg-compressed image

.project

@@ -62,42 +62,42 @@
 		<link>
 			<name>vivado_logs/VivadoBitstream.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150912133316882.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150915011906545.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoOpt.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150912133316882.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150915011906545.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoOptPhys.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150912133316882.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150915011906545.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoOptPower.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150912133316882.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150915011906545.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoPlace.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150912133316882.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150915011906545.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoRoute.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150912133316882.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150915011906545.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoSynthesis.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150912132805424.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150915011906545.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150912133316882.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150915011906545.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>

axi/histogram_saxi.v

@@ -240,8 +240,8 @@ module  histogram_saxi#(
         .debug_sl   (debug_sl),      // input
         .debug_do   (debug_do), // output
         .rd_data   ({
-          num_addr_saxi,
-          num_data_saxi,
+          num_addr_saxi[15:0],
+          num_data_saxi[15:0],
         
           extra_wa[7:0],page_wa[7:0],
           extra_ra[7:0],page_ra[7:0],

compressor_jp/cmprs_macroblock_buf_iface.v

@@ -54,7 +54,10 @@ module  cmprs_macroblock_buf_iface (
     output [ 6:0] macroblock_x,       // macroblock left pixel x relative to a tile (page) Maximal page - 128 bytes wide
     output reg    first_mb,           // during first macroblock (valid @mb_pre_start_out)
     output        last_mb             // during last macroblock (valid @mb_pre_start_out)
-    
+`ifdef DEBUG_RING
+    ,output [ 1:0] dbg_add_invalid,
+    output         dbg_mb_release_buf
+`endif    
 );
 
     wire          reset_page_rd;
@@ -96,6 +99,10 @@ module  cmprs_macroblock_buf_iface (
     reg           frame_pre_run;
     reg     [1:0] frame_may_start;
     
+`ifdef DEBUG_RING
+    assign  dbg_add_invalid = add_invalid;
+    assign  dbg_mb_release_buf = mb_release_buf;
+`endif
     assign frame_en_w = frame_en && frame_go;
     
     assign mbl_x={mbl_x_r[6:3], left_marg[2:0]};

compressor_jp/encoderDCAC393.v

@@ -42,7 +42,13 @@ module encoderDCAC393(
     input             zds,            // strobe - one ahead of the DC component output
     output reg        last,           //
     output reg [15:0] do,
-    output reg        dv);
+    output reg        dv,
+    // just for debug
+    output comp_lastinmbo,
+    output [2:0] dbg_block_mem_ra,
+    output [2:0] dbg_block_mem_wa,
+    output [2:0] dbg_block_mem_wa_save
+    );
 
 
 // 8x13  DC storage memory
@@ -72,7 +78,7 @@ module encoderDCAC393(
     wire    [2:0] comp_numbero;   // [2:0] component number 0..2 in color, 0..3 - in jp4diff, >= 4 - don't use
     wire          comp_firsto;    // first this component in a frame (reset DC)
     wire          comp_coloro;    // use color - huffman?
-    wire          comp_lastinmbo; // last component in a macroblock
+//    wire          comp_lastinmbo; // last component in a macroblock
     wire          lasto;          // last macroblock in a frame
     reg     [2:0] block_mem_ra;
     reg     [2:0] block_mem_wa;
@@ -85,6 +91,11 @@ module encoderDCAC393(
     assign comp_coloro=       block_mem_o[4];
     assign comp_lastinmbo=    block_mem_o[5];
     assign lasto=             block_mem_o[6];
+    
+    assign dbg_block_mem_ra = block_mem_ra;
+    assign dbg_block_mem_wa = block_mem_wa;
+    assign dbg_block_mem_wa_save = block_mem_wa_save;
+    
     always @ (posedge clk) begin
         if (stb) block_mem_ram[block_mem_wa[2:0]] <= {lasti, comp_lastinmbi, comp_colori,comp_firsti,comp_numberi[2:0]};
         if      (!en) block_mem_wa[2:0] <= 3'h0;

compressor_jp/huffman393.v

@@ -47,7 +47,8 @@ module huffman393    (
     output reg        test_lbw,
     output            gotLastBlock,   // last block done - flush the rest bits
     input             clk_flush,      // other clock to generate synchronized 1-cycle flush_clk output   
-    output            flush_clk       // 1-cycle flush output @ clk_flush
+    output            flush_clk,       // 1-cycle flush output @ clk_flush
+    output            fifo_or_full     // FIFO output register full - just for debuging
 );
 `ifdef INFER_LATCHES
     reg    [15:0] hcode_latch;    // table output huffman code (1..16 bits)
@@ -55,14 +56,14 @@ module huffman393    (
     reg    [ 7:0] haddr70_latch;
     reg           haddr8_latch;
     reg           tables_re_latch;
-    reg           stuffer_was_rdy_early_latch;
+//    reg           stuffer_was_rdy_early_latch;
 `else
     wire   [15:0] hcode_latch;    // table output huffman code (1..16 bits)
     wire   [ 3:0] hlen_latch;        // table - code length only 4 LSBs are used
     wire   [ 7:0] haddr70_latch;
     wire          haddr8_latch;
     wire          tables_re_latch;
-    wire          stuffer_was_rdy_early_latch;
+//    wire          stuffer_was_rdy_early_latch;
 `endif
     wire   [31:0] tables_out; // Only [19:0] are used
     reg    [ 7:0] haddr_r;    // index in huffman table    
@@ -97,7 +98,7 @@ module huffman393    (
 
     reg    [15:0] out_bits;    // bits to send
     reg     [3:0] out_len;        // length of bits to send (4'h0 means 16)
-    wire          fifo_or_full;    // fifo output register full read_next
+//    wire          fifo_or_full;    // fifo output register full read_next
     wire          will_read;
     wire   [10:0] var_do;
     wire    [3:0] var_dl;
@@ -135,14 +136,14 @@ module huffman393    (
     assign gotColor= fifo_o[13];
 
     always @(negedge xclk2x) stuffer_was_rdy <= !en2x || rdy; // stuffer ready shoud be on if !en (move to register?)for now]
-    wire          want_read_early;
+//    wire          want_read_early;
    
 
 
     assign read_next= en2x && ((!steps[0] && !rll[5]) || eob ) && fifo_or_full; // fifo will never have data after the last block...
     assign will_read= stuffer_was_rdy && fifo_or_full && en2x && ((!steps[0] && !rll[5]) || eob ); // fifo will never have data after the last block...
     assign want_read= stuffer_was_rdy &&                         ((!steps[0] && !rll[5]) || eob ); // for FIFO
-    assign want_read_early= stuffer_was_rdy_early_latch && ((!steps[0] && !rll[5]) || eob ); // for FIFO
+//    assign want_read_early= stuffer_was_rdy_early_latch && ((!steps[0] && !rll[5]) || eob ); // for FIFO
 
     always @ (negedge xclk2x) if (stuffer_was_rdy) begin
         eob <= read_next && gotEOB;// will be 1 only during step[0]
@@ -153,7 +154,11 @@ module huffman393    (
                                    (read_next && !(gotRLL && (fifo_o[5:4]==2'b00))) || rll[5] }; // will not start if it was <16, waiting for AC
     end
     always @ (negedge xclk2x)    begin
-        last_block <= en2x && (last_block?(!flush):(stuffer_was_rdy && will_read && gotLastBlock));
+//        last_block <= en2x && (last_block?(!flush):(stuffer_was_rdy && will_read && gotLastBlock));
+        
+        if      (!en2x || flush)                               last_block <= 0;
+        else if (stuffer_was_rdy && will_read && gotLastBlock) last_block <= 1;
+        
         ready_to_flush <= en2x && (ready_to_flush?(!flush):(stuffer_was_rdy && last_block &&  will_read && gotLastWord));
         test_lbw <= en2x && last_block &&  gotLastWord;
 // did not work if flush was just after not ready?
@@ -199,7 +204,7 @@ module huffman393    (
 `ifdef INFER_LATCHES
     always @* if (~xclk2x) hlen_latch <=  tables_out[19:16];
     always @* if (~xclk2x) hcode_latch <= tables_out[15:0];
-    always @* if (xclk2x)  stuffer_was_rdy_early_latch <= !en2x || rdy;
+//    always @* if (xclk2x)  stuffer_was_rdy_early_latch <= !en2x || rdy;
     always @* if (xclk2x)  tables_re_latch <= en2x && rdy;
 
     always @* if (xclk2x) begin
@@ -238,7 +243,7 @@ module huffman393    (
         .d_in    (tables_out[15:0]),   // input[0:0] 
         .q_out   (hcode_latch)         // output[0:0] 
     );
-
+/*
     latch_g_ce #(
         .WIDTH           (1),
         .INIT            (0),
@@ -251,7 +256,7 @@ module huffman393    (
         .d_in    (!en2x || rdy),                // input[0:0] 
         .q_out   (stuffer_was_rdy_early_latch)  // output[0:0] 
     );
-
+*/
     latch_g_ce #(
         .WIDTH           (1),
         .INIT            (0),
@@ -342,15 +347,16 @@ module huffman393    (
   
 
     huff_fifo393 i_huff_fifo (
-        .xclk(xclk), // input
-        .xclk2x(xclk2x), // input
-        .en(en), // input
-        .di(di[15:0]), // input[15:0] data in (sync to xclk)
-        .ds(ds), // input din valid (sync to xclk)
-        .want_read(want_read), // input
-        .want_read_early(want_read_early), // input
-        .dav(fifo_or_full), // output reg FIFO output register has data 
-        .q_latch(fifo_o[15:0])); // output[15:0] reg data (will add extra buffering if needed)
+        .xclk            (xclk),            // input
+        .xclk2x          (xclk2x),          // input
+        .en              (en),              // input
+        .di              (di[15:0]),        // input[15:0] data in (sync to xclk)
+        .ds              (ds),              // input din valid (sync to xclk)
+        .want_read       (want_read),       // input
+//        .want_read_early (want_read_early), // input
+        .dav             (fifo_or_full),    // output reg FIFO output register has data 
+//        .q_latch         (fifo_o[15:0]));   // output[15:0] reg data (will add extra buffering if needed)
+        .q               (fifo_o[15:0]));   // output[15:0] reg data (will add extra buffering if needed)
 
     varlen_encode393 i_varlen_encode(
         .clk      (xclk2x),           // input

compressor_jp/jp_channel.v

@@ -344,21 +344,114 @@ module  jp_channel#(
 //    assign buf_regen = buf_rd[1];
 
 `ifdef DEBUG_RING
-    reg [15:0] debug_fifo_in;
-    reg [15:0] debug_fifo_out;
+    reg [31:0] debug_fifo_in;
+    reg [31:0] debug_fifo_out;
+    reg [15:0] pre_start_cntr;
+    reg [15:0] pre_end_cntr;
+    reg        debug_frame_done;
+    reg [15:0] pages_requested;
+    reg [15:0] pages_got;
+    wire [1:0] dbg_add_invalid;
+    wire       dbg_mb_release_buf;
+    reg [15:0] pages_needed;  // count number requested
+    reg [15:0] page_requests; // count regardless of how many requested
+    reg        dbg_stuffer_ext_running;
+    reg        dbg_reset_fifo;
+    wire [3:0] etrax_dma;
+    wire       dbg_flushing;
+    reg        dbg_flush_hclk;
+    reg        dbg_en_hclk;
+    
+    wire       dbg_last_block;
+    reg        dbg_en_n2x;
+    reg        dbg_last_block_persist;
+    wire       dbg_test_lbw;
+    wire       dbg_gotLastBlock;
+    wire       dbg_frame_start_hclk;
+    wire       dbg_last_DCAC;
+    reg        dbg_gotLastBlock_persist;
+    reg        dbg_lastBlock_sent;
+    wire       dbg_fifo_or_full;
+    wire       dbg_comp_lastinmbo;
+    wire [2:0] dbg_block_mem_ra;
+    reg [15:0] dbg_stb_cntr;
+    reg [15:0] dbg_zds_cntr;
+    wire [2:0] dbg_block_mem_wa;
+    wire [2:0] dbg_block_mem_wa_save;
+    
+    
+    
+// cmprs_standalone - use to reset flush     
     always @ (posedge ~xclk2x) begin
-        if      (xrst2xn)    debug_fifo_in <= 0;
+        dbg_reset_fifo <= fifo_rst;
+        if (xrst2xn || dbg_reset_fifo) debug_fifo_in <= 0;
         else if (stuffer_dv)           debug_fifo_in <= debug_fifo_in + 1;
+        
+        dbg_en_n2x <= stuffer_en;
+        
+        if      (!dbg_en_n2x)    dbg_last_block_persist <= 0;
+        else if (dbg_last_block) dbg_last_block_persist <= 1;
+
+        if      (!dbg_en_n2x)      dbg_gotLastBlock_persist <= 0;
+        else if (dbg_gotLastBlock) dbg_gotLastBlock_persist <= 1;
+        
+//dbg_last_block_persist        
     end
     always @ (posedge hclk) begin
         if      (hrst)     debug_fifo_out <= 0;
-        else if (fifo_rst) debug_fifo_out <= debug_fifo_in;
+        else if (fifo_rst) debug_fifo_out <= 0; // debug_fifo_in >> 2;
         else if (fifo_ren) debug_fifo_out <= debug_fifo_out + 1;
+        
+        dbg_en_hclk <= cmprs_en_mclk;
+        
+        if (!dbg_en_hclk || dbg_frame_start_hclk) dbg_flush_hclk <= 0;
+        else if (flush_hclk)                      dbg_flush_hclk <= 1;
+    end
+    
+    always @ (posedge mclk) begin
+        if      (!cmprs_en_mclk) pages_requested <= 0;
+        else if  (next_page_chn) pages_requested <= pages_requested + 1;
+        
+        if      (!cmprs_en_mclk) pages_got <= 0;
+        else if (page_ready_chn) pages_got <= pages_got + 1;
+        
+        if      (!cmprs_en_mclk) debug_frame_done <= 0;
+        else if (frame_done_dst) debug_frame_done <= 1;
+        
+        if      (!cmprs_en_mclk || stuffer_done_mclk) dbg_stuffer_ext_running <= 0;
+        else if (stuffer_running_mclk)                dbg_stuffer_ext_running <= 1;
+        
+    end
+    
+    always @ (posedge xclk) begin
+        if         (!frame_en) pre_start_cntr <= 0;
+        else if (mb_pre_start) pre_start_cntr <= pre_start_cntr + 1;
+
+        if       (!frame_en) pre_end_cntr <= 0;
+        else if (mb_pre_end) pre_end_cntr <= pre_end_cntr + 1;
+        
+        if      (!frame_en)          pages_needed <= 0;
+        else if (dbg_mb_release_buf) pages_needed <= pages_needed + {14'b0,dbg_add_invalid};
+        
+        if      (!frame_en)          page_requests <= 0;
+        else if (dbg_mb_release_buf) page_requests <= page_requests + 1;
+        
+        if (!frame_en)                                              dbg_lastBlock_sent <= 0;
+        else if (enc_dv && enc_do[15] && enc_do[14] && enc_do[12] ) dbg_lastBlock_sent <= 1;
+//        else if enc_do[15:0]
+        
+        if      (!frame_en) dbg_stb_cntr <= 0;
+        else if (dct_start) dbg_stb_cntr <= dbg_stb_cntr + 1;
+        
+        if      (!frame_en) dbg_zds_cntr <= 0;
+        else if  (focus_ds) dbg_zds_cntr <= dbg_zds_cntr + 1;
+
     end
+//frame_start_dst
     
     debug_slave #(
-        .SHIFT_WIDTH       (128),
-        .READ_WIDTH        (128),
+        .SHIFT_WIDTH       (320),
+        .READ_WIDTH        (320),
         .WRITE_WIDTH       (32),
         .DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
     ) debug_slave_i (
@@ -368,11 +461,21 @@ module  jp_channel#(
         .debug_sl   (debug_sl),      // input
         .debug_do   (debug_do), // output
         .rd_data   ({
-        debug_fifo_out[15:0],
-        debug_fifo_in[15:0],
-        16'b0,
+        26'h0, dbg_block_mem_wa_save[2:0],dbg_block_mem_wa[2:0],
+        dbg_zds_cntr[15:0],
+        dbg_stb_cntr[15:0],
+        pages_needed[15:0],
+        page_requests[15:0],
+        pre_end_cntr[15:0],
+        pre_start_cntr[15:0],
+        pages_got[15:0],
+        pages_requested[15:0],
+        dbg_comp_lastinmbo, dbg_block_mem_ra[2:0], debug_fifo_out[27:0],
+        debug_fifo_in[31:0],
+        color_last, dbg_last_block_persist, dbg_gotLastBlock, dbg_test_lbw, dbg_last_block,
+         dbg_flush_hclk, dbg_flushing, stuffer_rdy, etrax_dma[3:0], dbg_stuffer_ext_running, stuffer_running_mclk, debug_frame_done, reading_frame,
         fifo_count[7:0],
-        6'b0, sigle_frame_buf, suspend,
+        2'b0, dbg_fifo_or_full, dbg_gotLastBlock_persist, dbg_lastBlock_sent, dbg_last_DCAC, sigle_frame_buf, suspend,
         frame_number_dst[15:0],
         line_unfinished_dst[15:0],
         frame_number_src[15:0],
@@ -381,6 +484,18 @@ module  jp_channel#(
         .wr_data    (), // output[31:0]  - not used
         .stb        () // output  - not used
     );
+//    wire [2:0] dbg_block_mem_wa;
+//    wire [2:0] dbg_block_mem_wa_save;
+    
+    pulse_cross_clock dbg_fs_hclk_i (
+        .rst       (!cmprs_en_mclk),
+        .src_clk   (mclk),
+        .dst_clk   (hclk),
+        .in_pulse  (frame_start_dst),
+        .out_pulse (dbg_frame_start_hclk),
+        .busy      ());
+    
+    
 `endif    
 
     cmd_deser #(
@@ -615,7 +730,10 @@ module  jp_channel#(
         .macroblock_x       (macroblock_x),       // output[6:0] 
         .first_mb           (first_mb),           // output reg 
         .last_mb            (last_mb)             // output
-        
+`ifdef DEBUG_RING
+        ,.dbg_add_invalid   (dbg_add_invalid),
+        .dbg_mb_release_buf (dbg_mb_release_buf)
+`endif        
     );
 
     cmprs_pixel_buf_iface #(
@@ -890,12 +1008,28 @@ module  jp_channel#(
         .zdi                (focus_do[12:0]),         // input[12:0] - zigzag-reordered data input
         .first_blockz       (first_block_quant),      // input - first block input (@zds)
         .zds                (focus_ds),               // input - strobe - one ahead of the DC component output
-///        .last               (enc_last),               // output reg 
+`ifdef DEBUG_RING
+        .last               (dbg_last_DCAC),                       // output reg - not used
+`else
         .last               (),                       // output reg - not used
+`endif
         .do                 (enc_do[15:0]),           // output[15:0] reg 
         .dv                 (enc_dv)                  // output reg 
+`ifdef DEBUG_RING
+        ,.comp_lastinmbo               (dbg_comp_lastinmbo)
+        ,.dbg_block_mem_ra             (dbg_block_mem_ra)
+        ,.dbg_block_mem_wa             (dbg_block_mem_wa)
+        ,.dbg_block_mem_wa_save        (dbg_block_mem_wa_save)
+`else
+        ,.comp_lastinmbo               ()
+        ,.dbg_block_mem_ra             ()
+       ,.dbg_block_mem_wa              ()
+        ,.dbg_block_mem_wa_save        ()
+`endif
     );
 
+//    wire [2:0] dbg_block_mem_wa;
+//    wire [2:0] dbg_block_mem_wa_save;
 
     huffman393 i_huffman (
         .xclk               (xclk),                   // input
@@ -912,14 +1046,22 @@ module  jp_channel#(
         .dl                 (huff_dl[3:0]),           // output[3:0] reg 
         .dv                 (huff_dv),                // output reg 
         .flush              (flush),                  // output reg 
-///        .last_block(last_block), // output reg 
+`ifdef DEBUG_RING
+        .last_block         (dbg_last_block), // output reg unused does not get out
+        .test_lbw           (dbg_test_lbw), // output reg ??
+        .gotLastBlock       (dbg_gotLastBlock), // output ?? - unused (was for debug)
+`else
         .last_block         (), // output reg unused
         .test_lbw           (), // output reg ??
-///        .gotLastBlock(test_lbw) // output ??
         .gotLastBlock       (), // output ?? - unused (was for debug)
+`endif        
         .clk_flush          (hclk), // input
-        .flush_clk          (flush_hclk) // output
-        
+        .flush_clk          (flush_hclk), // output
+`ifdef DEBUG_RING
+        .fifo_or_full       (dbg_fifo_or_full)     // FIFO output register full - just for debuging
+`else        
+        .fifo_or_full       ()     // FIFO output register full - just for debuging
+`endif        
     );
     
 
@@ -945,9 +1087,15 @@ module  jp_channel#(
         .q                   (stuffer_do),             // output[15:0] reg - output data
         .qv                  (stuffer_dv),             // output reg - output data valid
         .done                (stuffer_done),           // output 
+`ifdef DEBUG_RING
+        .flushing            (dbg_flushing),                       // output reg Not used?
+`else
         .flushing            (),                       // output reg Not used?
+`endif        
         .running             (stuffer_running)         // from registering timestamp until done
-        
+`ifdef DEBUG_RING
+,        .dbg_etrax_dma     (etrax_dma)
+`endif        
 `ifdef debug_stuffer
        ,.etrax_dma_r(tst_stuf_etrax[3:0]) // [3:0] just for testing
        ,.test_cntr(test_cntr[3:0])

compressor_jp/stuffer393.v

@@ -71,13 +71,17 @@ module stuffer393 (
 ///    output reg  [23:0] imgptr,      // [23:0]image pointer in 32-byte chunks 
     output reg         flushing,
     output reg         running      // from registering timestamp until done
+`ifdef DEBUG_RING
+,   output reg [3:0]  dbg_etrax_dma
+`endif        
+    
 `ifdef debug_stuffer
-,      output reg   [3:0] etrax_dma_r, // [3:0] just for testing
-       output reg   [3:0] test_cntr,
+,      output reg   [3:0] etrax_dma_r // [3:0] just for testing
+,       output reg   [3:0] test_cntr,
        output reg   [7:0] test_cntr1
 `endif
 );
-
+//etrax_dma[3:0]
 `ifdef debug_stuffer
     reg           en_d;
 `endif
@@ -364,6 +368,10 @@ end
         else if (qv) etrax_dma[3:0] <= etrax_dma[3:0] + 1;
 
 // just for testing
+`ifdef DEBUG_RING
+   dbg_etrax_dma <= etrax_dma[3:0];
+`endif        
+
 `ifdef debug_stuffer
         en_d<= en;
         if (en) etrax_dma_r[3:0] <= etrax_dma[3:0];

fpga_version.vh

-    parameter FPGA_VERSION =          32'h03930029;
+    parameter FPGA_VERSION =          32'h03930033;
\ No newline at end of file

py393/x393_jpeg.py

@@ -569,7 +569,7 @@ class X393Jpeg(object):
                            y_quality = 80,
                            c_quality = None,
                            portrait =  False,
-                           height =    1944,
+                           height =    1936,
                            width =     2592,
                            color_mode = 0,
                            byrshift   = 0,

py393/x393_mcntrl_adjust.py

@@ -5266,6 +5266,13 @@ write_settings= {
                 # TODO: print function name and used arguments
                 task_item['func'](**task_item['params'])
                 last_task_start_time=tim
+        if any (x in "CWARPOB" for x in tasks):
+            print ("Restoring delays after running adjustments")
+#            self.x393_mcntrl_timing.axi_set_delays() # set all individual delays, aslo runs axi_set_phase()
+#            self.x393_mcntrl_timing.axi_set_wbuf_delay(vrlg.WBUF_DLY_DFLT)
+            #TODO: find why the 2 calls above are not enough (memory read gets 4 leading garbage bytes)
+            #The one below seems enough
+            self.x393_pio_sequences.task_set_up(dqs_pattern = dqs_pattern)
         tim=time.time()
         if quiet < 5:
             print ("[%.3f/+%.3f] %s"%(tim-start_time,tim-last_task_start_time,"All Done"))