got first jpeg-compressed image (8555bdd3) · Commits · Elphel / x393

.project

+8 −8

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	@@ -62,42 +62,42 @@
	<link>		<link>
	<name>vivado_logs/VivadoBitstream.log</name>		<name>vivado_logs/VivadoBitstream.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150912133316882.log</location>		<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150915011906545.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoOpt.log</name>		<name>vivado_logs/VivadoOpt.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150912133316882.log</location>		<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150915011906545.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoOptPhys.log</name>		<name>vivado_logs/VivadoOptPhys.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150912133316882.log</location>		<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150915011906545.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoOptPower.log</name>		<name>vivado_logs/VivadoOptPower.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150912133316882.log</location>		<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150915011906545.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoPlace.log</name>		<name>vivado_logs/VivadoPlace.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150912133316882.log</location>		<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150915011906545.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoRoute.log</name>		<name>vivado_logs/VivadoRoute.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150912133316882.log</location>		<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150915011906545.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoSynthesis.log</name>		<name>vivado_logs/VivadoSynthesis.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150912132805424.log</location>		<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150915011906545.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>		<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150912133316882.log</location>		<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150915011906545.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>		<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>

axi/histogram_saxi.v

+2 −2

Original line number	Original line	Diff line number	Diff line
	@@ -240,8 +240,8 @@ module histogram_saxi#(
	.debug_sl (debug_sl), // input		.debug_sl (debug_sl), // input
	.debug_do (debug_do), // output		.debug_do (debug_do), // output
	.rd_data ({		.rd_data ({
	num_addr_saxi,		num_addr_saxi[15:0],
	num_data_saxi,		num_data_saxi[15:0],

	extra_wa[7:0],page_wa[7:0],		extra_wa[7:0],page_wa[7:0],
	extra_ra[7:0],page_ra[7:0],		extra_ra[7:0],page_ra[7:0],

compressor_jp/cmprs_macroblock_buf_iface.v

+9 −2

Original line number	Original line	Diff line number	Diff line
	@@ -54,7 +54,10 @@ module cmprs_macroblock_buf_iface (
	output [ 6:0] macroblock_x, // macroblock left pixel x relative to a tile (page) Maximal page - 128 bytes wide		output [ 6:0] macroblock_x, // macroblock left pixel x relative to a tile (page) Maximal page - 128 bytes wide
	output reg first_mb, // during first macroblock (valid @mb_pre_start_out)		output reg first_mb, // during first macroblock (valid @mb_pre_start_out)
	output last_mb // during last macroblock (valid @mb_pre_start_out)		output last_mb // during last macroblock (valid @mb_pre_start_out)
			`ifdef DEBUG_RING
			,output [ 1:0] dbg_add_invalid,
			output dbg_mb_release_buf
			`endif
	);		);

	wire reset_page_rd;		wire reset_page_rd;
	@@ -96,6 +99,10 @@ module cmprs_macroblock_buf_iface (
	reg frame_pre_run;		reg frame_pre_run;
	reg [1:0] frame_may_start;		reg [1:0] frame_may_start;

			`ifdef DEBUG_RING
			assign dbg_add_invalid = add_invalid;
			assign dbg_mb_release_buf = mb_release_buf;
			`endif
	assign frame_en_w = frame_en && frame_go;		assign frame_en_w = frame_en && frame_go;

	assign mbl_x={mbl_x_r[6:3], left_marg[2:0]};		assign mbl_x={mbl_x_r[6:3], left_marg[2:0]};

compressor_jp/encoderDCAC393.v

+13 −2

Original line number	Original line	Diff line number	Diff line
	@@ -42,7 +42,13 @@ module encoderDCAC393(
	input zds, // strobe - one ahead of the DC component output		input zds, // strobe - one ahead of the DC component output
	output reg last, //		output reg last, //
	output reg [15:0] do,		output reg [15:0] do,
	output reg dv);		output reg dv,
			// just for debug
			output comp_lastinmbo,
			output [2:0] dbg_block_mem_ra,
			output [2:0] dbg_block_mem_wa,
			output [2:0] dbg_block_mem_wa_save
			);


	// 8x13 DC storage memory		// 8x13 DC storage memory
	@@ -72,7 +78,7 @@ module encoderDCAC393(
	wire [2:0] comp_numbero; // [2:0] component number 0..2 in color, 0..3 - in jp4diff, >= 4 - don't use		wire [2:0] comp_numbero; // [2:0] component number 0..2 in color, 0..3 - in jp4diff, >= 4 - don't use
	wire comp_firsto; // first this component in a frame (reset DC)		wire comp_firsto; // first this component in a frame (reset DC)
	wire comp_coloro; // use color - huffman?		wire comp_coloro; // use color - huffman?
	wire comp_lastinmbo; // last component in a macroblock		// wire comp_lastinmbo; // last component in a macroblock
	wire lasto; // last macroblock in a frame		wire lasto; // last macroblock in a frame
	reg [2:0] block_mem_ra;		reg [2:0] block_mem_ra;
	reg [2:0] block_mem_wa;		reg [2:0] block_mem_wa;
	@@ -85,6 +91,11 @@ module encoderDCAC393(
	assign comp_coloro= block_mem_o[4];		assign comp_coloro= block_mem_o[4];
	assign comp_lastinmbo= block_mem_o[5];		assign comp_lastinmbo= block_mem_o[5];
	assign lasto= block_mem_o[6];		assign lasto= block_mem_o[6];

			assign dbg_block_mem_ra = block_mem_ra;
			assign dbg_block_mem_wa = block_mem_wa;
			assign dbg_block_mem_wa_save = block_mem_wa_save;

	always @ (posedge clk) begin		always @ (posedge clk) begin
	if (stb) block_mem_ram[block_mem_wa[2:0]] <= {lasti, comp_lastinmbi, comp_colori,comp_firsti,comp_numberi[2:0]};		if (stb) block_mem_ram[block_mem_wa[2:0]] <= {lasti, comp_lastinmbi, comp_colori,comp_firsti,comp_numberi[2:0]};
	if (!en) block_mem_wa[2:0] <= 3'h0;		if (!en) block_mem_wa[2:0] <= 3'h0;

compressor_jp/huffman393.v

+26 −20

Original line number	Original line	Diff line number	Diff line
	@@ -47,7 +47,8 @@ module huffman393 (
	output reg test_lbw,		output reg test_lbw,
	output gotLastBlock, // last block done - flush the rest bits		output gotLastBlock, // last block done - flush the rest bits
	input clk_flush, // other clock to generate synchronized 1-cycle flush_clk output		input clk_flush, // other clock to generate synchronized 1-cycle flush_clk output
	output flush_clk // 1-cycle flush output @ clk_flush		output flush_clk, // 1-cycle flush output @ clk_flush
			output fifo_or_full // FIFO output register full - just for debuging
	);		);
	`ifdef INFER_LATCHES		`ifdef INFER_LATCHES
	reg [15:0] hcode_latch; // table output huffman code (1..16 bits)		reg [15:0] hcode_latch; // table output huffman code (1..16 bits)
	@@ -55,14 +56,14 @@ module huffman393 (
	reg [ 7:0] haddr70_latch;		reg [ 7:0] haddr70_latch;
	reg haddr8_latch;		reg haddr8_latch;
	reg tables_re_latch;		reg tables_re_latch;
	reg stuffer_was_rdy_early_latch;		// reg stuffer_was_rdy_early_latch;
	`else		`else
	wire [15:0] hcode_latch; // table output huffman code (1..16 bits)		wire [15:0] hcode_latch; // table output huffman code (1..16 bits)
	wire [ 3:0] hlen_latch; // table - code length only 4 LSBs are used		wire [ 3:0] hlen_latch; // table - code length only 4 LSBs are used
	wire [ 7:0] haddr70_latch;		wire [ 7:0] haddr70_latch;
	wire haddr8_latch;		wire haddr8_latch;
	wire tables_re_latch;		wire tables_re_latch;
	wire stuffer_was_rdy_early_latch;		// wire stuffer_was_rdy_early_latch;
	`endif		`endif
	wire [31:0] tables_out; // Only [19:0] are used		wire [31:0] tables_out; // Only [19:0] are used
	reg [ 7:0] haddr_r; // index in huffman table		reg [ 7:0] haddr_r; // index in huffman table
	@@ -97,7 +98,7 @@ module huffman393 (

	reg [15:0] out_bits; // bits to send		reg [15:0] out_bits; // bits to send
	reg [3:0] out_len; // length of bits to send (4'h0 means 16)		reg [3:0] out_len; // length of bits to send (4'h0 means 16)
	wire fifo_or_full; // fifo output register full read_next		// wire fifo_or_full; // fifo output register full read_next
	wire will_read;		wire will_read;
	wire [10:0] var_do;		wire [10:0] var_do;
	wire [3:0] var_dl;		wire [3:0] var_dl;
	@@ -135,14 +136,14 @@ module huffman393 (
	assign gotColor= fifo_o[13];		assign gotColor= fifo_o[13];

	always @(negedge xclk2x) stuffer_was_rdy <= !en2x \|\| rdy; // stuffer ready shoud be on if !en (move to register?)for now]		always @(negedge xclk2x) stuffer_was_rdy <= !en2x \|\| rdy; // stuffer ready shoud be on if !en (move to register?)for now]
	wire want_read_early;		// wire want_read_early;



	assign read_next= en2x && ((!steps[0] && !rll[5]) \|\| eob ) && fifo_or_full; // fifo will never have data after the last block...		assign read_next= en2x && ((!steps[0] && !rll[5]) \|\| eob ) && fifo_or_full; // fifo will never have data after the last block...
	assign will_read= stuffer_was_rdy && fifo_or_full && en2x && ((!steps[0] && !rll[5]) \|\| eob ); // fifo will never have data after the last block...		assign will_read= stuffer_was_rdy && fifo_or_full && en2x && ((!steps[0] && !rll[5]) \|\| eob ); // fifo will never have data after the last block...
	assign want_read= stuffer_was_rdy && ((!steps[0] && !rll[5]) \|\| eob ); // for FIFO		assign want_read= stuffer_was_rdy && ((!steps[0] && !rll[5]) \|\| eob ); // for FIFO
	assign want_read_early= stuffer_was_rdy_early_latch && ((!steps[0] && !rll[5]) \|\| eob ); // for FIFO		// assign want_read_early= stuffer_was_rdy_early_latch && ((!steps[0] && !rll[5]) \|\| eob ); // for FIFO

	always @ (negedge xclk2x) if (stuffer_was_rdy) begin		always @ (negedge xclk2x) if (stuffer_was_rdy) begin
	eob <= read_next && gotEOB;// will be 1 only during step[0]		eob <= read_next && gotEOB;// will be 1 only during step[0]
	@@ -153,7 +154,11 @@ module huffman393 (
	(read_next && !(gotRLL && (fifo_o[5:4]==2'b00))) \|\| rll[5] }; // will not start if it was <16, waiting for AC		(read_next && !(gotRLL && (fifo_o[5:4]==2'b00))) \|\| rll[5] }; // will not start if it was <16, waiting for AC
	end		end
	always @ (negedge xclk2x) begin		always @ (negedge xclk2x) begin
	last_block <= en2x && (last_block?(!flush):(stuffer_was_rdy && will_read && gotLastBlock));		// last_block <= en2x && (last_block?(!flush):(stuffer_was_rdy && will_read && gotLastBlock));

			if (!en2x \|\| flush) last_block <= 0;
			else if (stuffer_was_rdy && will_read && gotLastBlock) last_block <= 1;

	ready_to_flush <= en2x && (ready_to_flush?(!flush):(stuffer_was_rdy && last_block && will_read && gotLastWord));		ready_to_flush <= en2x && (ready_to_flush?(!flush):(stuffer_was_rdy && last_block && will_read && gotLastWord));
	test_lbw <= en2x && last_block && gotLastWord;		test_lbw <= en2x && last_block && gotLastWord;
	// did not work if flush was just after not ready?		// did not work if flush was just after not ready?
	@@ -199,7 +204,7 @@ module huffman393 (
	`ifdef INFER_LATCHES		`ifdef INFER_LATCHES
	always @* if (~xclk2x) hlen_latch <= tables_out[19:16];		always @* if (~xclk2x) hlen_latch <= tables_out[19:16];
	always @* if (~xclk2x) hcode_latch <= tables_out[15:0];		always @* if (~xclk2x) hcode_latch <= tables_out[15:0];
	always @* if (xclk2x) stuffer_was_rdy_early_latch <= !en2x \|\| rdy;		// always @* if (xclk2x) stuffer_was_rdy_early_latch <= !en2x \|\| rdy;
	always @* if (xclk2x) tables_re_latch <= en2x && rdy;		always @* if (xclk2x) tables_re_latch <= en2x && rdy;

	always @* if (xclk2x) begin		always @* if (xclk2x) begin
	@@ -238,7 +243,7 @@ module huffman393 (
	.d_in (tables_out[15:0]), // input[0:0]		.d_in (tables_out[15:0]), // input[0:0]
	.q_out (hcode_latch) // output[0:0]		.q_out (hcode_latch) // output[0:0]
	);		);
			/*
	latch_g_ce #(		latch_g_ce #(
	.WIDTH (1),		.WIDTH (1),
	.INIT (0),		.INIT (0),
	@@ -251,7 +256,7 @@ module huffman393 (
	.d_in (!en2x \|\| rdy), // input[0:0]		.d_in (!en2x \|\| rdy), // input[0:0]
	.q_out (stuffer_was_rdy_early_latch) // output[0:0]		.q_out (stuffer_was_rdy_early_latch) // output[0:0]
	);		);
			*/
	latch_g_ce #(		latch_g_ce #(
	.WIDTH (1),		.WIDTH (1),
	.INIT (0),		.INIT (0),
	@@ -348,9 +353,10 @@ module huffman393 (
	.di (di[15:0]), // input[15:0] data in (sync to xclk)		.di (di[15:0]), // input[15:0] data in (sync to xclk)
	.ds (ds), // input din valid (sync to xclk)		.ds (ds), // input din valid (sync to xclk)
	.want_read (want_read), // input		.want_read (want_read), // input
	.want_read_early(want_read_early), // input		// .want_read_early (want_read_early), // input
	.dav (fifo_or_full), // output reg FIFO output register has data		.dav (fifo_or_full), // output reg FIFO output register has data
	.q_latch(fifo_o[15:0])); // output[15:0] reg data (will add extra buffering if needed)		// .q_latch (fifo_o[15:0])); // output[15:0] reg data (will add extra buffering if needed)
			.q (fifo_o[15:0])); // output[15:0] reg data (will add extra buffering if needed)

	varlen_encode393 i_varlen_encode(		varlen_encode393 i_varlen_encode(
	.clk (xclk2x), // input		.clk (xclk2x), // input

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