multiple changes, synchronizing simulation with hardware (82e11ec7) · Commits · Elphel / x393

.gitignore

+9 −0

Original line number	Original line	Diff line number	Diff line
	@@ -2,6 +2,9 @@ unisims
	vivado_*		vivado_*
	syntax_*		syntax_*
	simulation/*		simulation/*
			simulation_data/*
			www/*
			constraints/*
	ise_*		ise_*
	attic/*		attic/*
	hardware_tests/*		hardware_tests/*
	@@ -31,3 +34,9 @@ x393_testbench01_debug_membridge.sav
	x393_testbench02-0.sav		x393_testbench02-0.sav
	py393/generated		py393/generated
	*.pickle		*.pickle
			py393/i2c.py

			py393/x393_i2c.py.test
			py393/x393_init_usb_hub.py
			py393/x393_mcntrl_adjust.py.dbg
			x393_testbench03_01.sav

.project

+11 −11

Original line number	Original line	Diff line number	Diff line
	@@ -62,52 +62,52 @@
	<link>		<link>
	<name>vivado_logs/VivadoBitstream.log</name>		<name>vivado_logs/VivadoBitstream.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20160417175241357.log</location>		<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20160502180852175.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoOpt.log</name>		<name>vivado_logs/VivadoOpt.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20160417175241357.log</location>		<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20160502180852175.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoOptPhys.log</name>		<name>vivado_logs/VivadoOptPhys.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160417175241357.log</location>		<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20160502180852175.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoOptPower.log</name>		<name>vivado_logs/VivadoOptPower.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20160417175241357.log</location>		<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20160502180852175.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoPlace.log</name>		<name>vivado_logs/VivadoPlace.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20160417175241357.log</location>		<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20160502180852175.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoRoute.log</name>		<name>vivado_logs/VivadoRoute.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20160417175241357.log</location>		<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20160502180852175.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoSynthesis.log</name>		<name>vivado_logs/VivadoSynthesis.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160417173535326.log</location>		<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20160502180258922.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>		<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20160417175241357.log</location>		<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20160502180852175.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>		<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160417173535326.log</location>		<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20160502180258922.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_logs/VivadoTimingReportSynthesis.log</name>		<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20160417173535326.log</location>		<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20160502180258922.log</location>
	</link>		</link>
	<link>		<link>
	<name>vivado_state/x393-opt-phys.dcp</name>		<name>vivado_state/x393-opt-phys.dcp</name>
	@@ -127,7 +127,7 @@
	<link>		<link>
	<name>vivado_state/x393-synth.dcp</name>		<name>vivado_state/x393-synth.dcp</name>
	<type>1</type>		<type>1</type>
	<location>/home/andrey/git/x393/vivado_state/x393-synth-20160417173535326.dcp</location>		<location>/home/andrey/git/x393/vivado_state/x393-synth-20160502180258922.dcp</location>
	</link>		</link>
	</linkedResources>		</linkedResources>
	</projectDescription>		</projectDescription>

axi/membridge.v

+47 −15

Original line number	Original line	Diff line number	Diff line
	@@ -291,6 +291,8 @@ module membridge#(
	reg [4:0] rd_id;		reg [4:0] rd_id;
	reg [4:0] wr_id;		reg [4:0] wr_id;

			reg read_no_more; // after frame_done - no more requests for new pages to read

	assign afi_arid={1'b1,rd_id};		assign afi_arid={1'b1,rd_id};
	assign afi_awid={1'b1,wr_id};		assign afi_awid={1'b1,wr_id};
	assign afi_wid= {1'b1,wr_id};		assign afi_wid= {1'b1,wr_id};
	@@ -324,7 +326,7 @@ module membridge#(
	if (hrst) wr_start <= 0;		if (hrst) wr_start <= 0;
	else wr_start <= rdwr_start[2] && wr_mode;		else wr_start <= rdwr_start[2] && wr_mode;

	page_ready_rd <= page_ready && !wr_mode;		// page_ready_rd <= page_ready && !wr_mode && !read_no_more;

	if (hrst) rd_id <= 0;		if (hrst) rd_id <= 0;
	else if (rd_start) rd_id <= rd_id +1;		else if (rd_start) rd_id <= rd_id +1;
	@@ -429,7 +431,7 @@ module membridge#(
	afi_len <= (\|left64[28:4])?4'hf : (left64[3:0]-1);		afi_len <= (\|left64[28:4])?4'hf : (left64[3:0]-1);
	afi_len_plus1 <= (\|left64[28:4]) ? 5'h10 : {1'b0,left64[3:0]};		afi_len_plus1 <= (\|left64[28:4]) ? 5'h10 : {1'b0,left64[3:0]};

	page_ready_rd <= page_ready && !wr_mode;		page_ready_rd <= page_ready && !wr_mode && !read_no_more;
	page_ready_wr <= page_ready && wr_mode;		page_ready_wr <= page_ready && wr_mode;

	if (!rw_in_progress) buf_left64 <= len64;		if (!rw_in_progress) buf_left64 <= len64;
	@@ -450,12 +452,13 @@ module membridge#(
	//rdwr_en		//rdwr_en
	reg [7:0] axi_arw_requested; // 64-bit words to be read/written over axi queued to AR/AW channels		reg [7:0] axi_arw_requested; // 64-bit words to be read/written over axi queued to AR/AW channels
	reg [7:0] axi_bursts_requested; // number of bursts requested		reg [7:0] axi_bursts_requested; // number of bursts requested
	reg [7:0] wresp_conf; // number of 64-bit words confirmed through axi b channel		reg [7:0] wresp_conf; // number of 64-bit words confirmed through axi b channel (wrong confirmed only bursts)!
	wire [7:0] axi_wr_pending; // Number of words qued to AW but not yet confirmed through B-channel;		wire [7:0] axi_wr_pending; // Number of bursts queued to AW but not yet confirmed through B-channel;
			reg [7:0] axi_wr_left; // Number of bursts queued through AW but not sent over W;
	wire [7:0] axi_rd_pending;		wire [7:0] axi_rd_pending;

	reg [7:0] axi_rd_received;		reg [7:0] axi_rd_received;
	assign axi_rd_pending= axi_arw_requested - axi_rd_received;		assign axi_rd_pending= axi_arw_requested - axi_rd_received; // WRONG! - use bursts, not words!
	// assign axi_wr_pending= axi_arw_requested - wresp_conf;		// assign axi_wr_pending= axi_arw_requested - wresp_conf;
	assign axi_wr_pending= axi_bursts_requested - wresp_conf;		assign axi_wr_pending= axi_bursts_requested - wresp_conf;

	@@ -520,12 +523,12 @@ module membridge#(

	if (hrst) read_page <= 0;		if (hrst) read_page <= 0;
	else if (reset_page_rd) read_page <= 0;		else if (reset_page_rd) read_page <= 0;
	else if (next_page_rd_w) read_page <= read_page + 1;		else if (done_page_rd_w) read_page <= read_page + 1;

	if (hrst) read_pages_ready <= 0;		if (hrst) read_pages_ready <= 0;
	else if (!read_busy) read_pages_ready <= 0;		else if (!read_busy) read_pages_ready <= 0;
	else if ( page_ready_rd && !next_page_rd_w) read_pages_ready <= read_pages_ready +1;		else if ( page_ready_rd && !done_page_rd_w) read_pages_ready <= read_pages_ready +1;
	else if (!page_ready_rd && next_page_rd_w) read_pages_ready <= read_pages_ready -1;		else if (!page_ready_rd && done_page_rd_w) read_pages_ready <= read_pages_ready -1;

	if (hrst) afi_wd_safe_not_full <= 0;		if (hrst) afi_wd_safe_not_full <= 0;
	else afi_wd_safe_not_full <= rdwr_en && (!afi_wcount[7] && !(&afi_wcount[6:3]));		else afi_wd_safe_not_full <= rdwr_en && (!afi_wcount[7] && !(&afi_wcount[6:3]));
	@@ -544,6 +547,12 @@ module membridge#(
	else if (pre_done) done <= 1;		else if (pre_done) done <= 1;
	else if (rdwr_start) done <= 0;		else if (rdwr_start) done <= 0;

			if (hrst ) read_no_more <= 0;
			else if (!read_busy) read_no_more <= 0;
			else if (frame_done) read_no_more <= 1;



	end		end

	// handle interaction with the buffer, advance addresses, keep track of partial (last) pages in each line		// handle interaction with the buffer, advance addresses, keep track of partial (last) pages in each line
	@@ -557,17 +566,29 @@ module membridge#(
	wire is_last_in_page;		wire is_last_in_page;
	wire next_page_rd_w;		wire next_page_rd_w;
	wire next_page_wr_w;		wire next_page_wr_w;
			wire done_page_rd_w;
			wire safe_some_left_rd_w;
			reg left_was_1; // was <=1 (0 does not matter) valid next after buffer address
			reg left_many;


	// assign next_page_rd_w = read_started && !busy_next_page && is_last_in_page && bufrd_rd[0];		// assign next_page_rd_w = read_started && !busy_next_page && is_last_in_page && bufrd_rd[0];
	assign next_page_rd_w = read_started && is_last_in_page && bufrd_rd[0];		assign done_page_rd_w = read_started && is_last_in_page && bufrd_rd[0];
			assign next_page_rd_w = done_page_rd_w && !read_no_more;
	assign is_last_in_line = buf_in_line64 == last_in_line64;		assign is_last_in_line = buf_in_line64 == last_in_line64;
	assign is_last_in_page = is_last_in_line \|\| (&buf_in_line64[6:0]);		assign is_last_in_page = is_last_in_line \|\| (&buf_in_line64[6:0]);
			// assign safe_some_left_rd_w = (axi_wr_left[7:1]!=0) \|\| (axi_wr_left[0] && !bufrd_rd[0]);
			assign safe_some_left_rd_w = left_many \|\| (\|buf_left64[1:0] && !(\|bufrd_rd)); // Fine tune
	`ifdef MEMBRIDGE_DEBUG_READ		`ifdef MEMBRIDGE_DEBUG_READ
	assign bufrd_rd_w = afi_wd_safe_not_full && (\|read_pages_ready[2:1] \|\| (read_pages_ready[0] && !is_last_in_page)) && debug_w_ready;		assign bufrd_rd_w = safe_some_left_rd_w && !read_over && afi_wd_safe_not_full &&
			(\|read_pages_ready[2:1] \|\| (read_pages_ready[0] && (!is_last_in_page \|\| read_no_more))) && debug_w_ready;
	`else		`else
	assign bufrd_rd_w = afi_wd_safe_not_full && (\|read_pages_ready[2:1] \|\| (read_pages_ready[0] && !is_last_in_page));		// assign bufrd_rd_w = afi_wd_safe_not_full && (\|read_pages_ready[2:1] \|\| (read_pages_ready[0] && !is_last_in_page));

			assign bufrd_rd_w = safe_some_left_rd_w && !read_over && afi_wd_safe_not_full &&
			(\|read_pages_ready[2:1] \|\| (read_pages_ready[0] && (!is_last_in_page \|\| read_no_more)));
	`endif		`endif
	//last_in_line64 - last word number in scan line		//last_in_line64 - last word number in scan line
	reg left_was_1; // was <=1 (0 does not matter) valid next after buffer address
	reg [3:0] src_wcntr;		reg [3:0] src_wcntr;
	// reg [2:0] wlast_in_burst;		// reg [2:0] wlast_in_burst;
	reg wlast; // valid 2 after buffer address, same as wvalid		reg wlast; // valid 2 after buffer address, same as wvalid
	@@ -581,6 +602,12 @@ module membridge#(
	if (!rw_in_progress) left_was_1 <= 0;		if (!rw_in_progress) left_was_1 <= 0;
	else if (buf_rdwr) left_was_1 <= !(\|buf_left64[28:1]);		else if (buf_rdwr) left_was_1 <= !(\|buf_left64[28:1]);

			/* if (!rw_in_progress) left_many <= 0;
			else if (buf_rdwr) */

			left_many <= \|buf_left64[28:2];


	if (!read_started) src_wcntr <= 0;		if (!read_started) src_wcntr <= 0;
	else if (bufrd_rd[0]) src_wcntr <= src_wcntr+1;		else if (bufrd_rd[0]) src_wcntr <= src_wcntr+1;

	@@ -643,6 +670,11 @@ module membridge#(
	else if (!write_busy) axi_rd_received <= 0;		else if (!write_busy) axi_rd_received <= 0;
	else if (bufwr_we[0]) axi_rd_received <= axi_rd_received + 1;		else if (bufwr_we[0]) axi_rd_received <= axi_rd_received + 1;

			if (hrst) axi_wr_left <= 0;
			else if (!read_started) axi_wr_left <= 0;
			else if ( advance_rel_addr && !(wlast && afi_wvalid)) axi_wr_left <= axi_wr_left + 1;
			else if (!advance_rel_addr && (wlast && afi_wvalid)) axi_wr_left <= axi_wr_left - 1;


	if (hrst) afi_rd_safe_not_empty <= 0;		if (hrst) afi_rd_safe_not_empty <= 0;
	// allow 1 cycle latency, no continuous reads when FIFO is low (like in the very end of the transfer)		// allow 1 cycle latency, no continuous reads when FIFO is low (like in the very end of the transfer)

compressor_jp/cmprs_frame_sync.v

+3 −2

Original line number	Original line	Diff line number	Diff line
	@@ -78,7 +78,8 @@ module cmprs_frame_sync#(
	output reg force_flush_long, // force flush (abort frame), can be any clock and may last until stuffer_done_mclk		output reg force_flush_long, // force flush (abort frame), can be any clock and may last until stuffer_done_mclk
	// stuffer will re-clock and extract 0->1 transition		// stuffer will re-clock and extract 0->1 transition
	output stuffer_running_mclk,		output stuffer_running_mclk,
	output reading_frame		output reading_frame,
			output frame_started_mclk // use to store frame number
	);		);
	/*		/*
	Abort frame (force flush) if:		Abort frame (force flush) if:
	@@ -87,7 +88,7 @@ module cmprs_frame_sync#(
	Abort frame lasts until flush end or timeout expire		Abort frame lasts until flush end or timeout expire
	*/		*/
	// wire vsync_late_mclk; // single mclk cycle, reclocked from vsync_late		// wire vsync_late_mclk; // single mclk cycle, reclocked from vsync_late
	wire frame_started_mclk;		// wire frame_started_mclk;
	reg bonded_mode;		reg bonded_mode;
	reg frame_start_dst_r;		reg frame_start_dst_r;
	reg frames_differ; // src and dest point to different frames (single-frame buffer mode), disregard line_unfinished_*		reg frames_differ; // src and dest point to different frames (single-frame buffer mode), disregard line_unfinished_*

compressor_jp/cmprs_status.v

+23 −16

Original line number	Original line	Diff line number	Diff line
	@@ -33,15 +33,18 @@
	*******************************************************************************/		*******************************************************************************/
	`timescale 1ns/1ps		`timescale 1ns/1ps

	module cmprs_status(		module cmprs_status #(
			parameter NUM_FRAME_BITS = 4
			) (
	input mrst,		input mrst,
	input mclk, // system clock		input mclk, // system clock
	input eof_written,		input eof_written,
	input stuffer_running,		input stuffer_running,
	input reading_frame,		input reading_frame,
			input [NUM_FRAME_BITS - 1:0] frame_num_compressed,
	input set_interrupts,		input set_interrupts,
	input [1:0] data_in,		input [1:0] data_in,
	output [4:0] status,		output [NUM_FRAME_BITS+7:0] status,
	output irq		output irq
	);		);

	@@ -49,9 +52,11 @@ module cmprs_status(
	reg flushing_fifo;		reg flushing_fifo;
	reg is_r; // interrupt status (not masked)		reg is_r; // interrupt status (not masked)
	reg im_r; // interrupt mask		reg im_r; // interrupt mask
			reg [NUM_FRAME_BITS - 1:0] frame_irq;

			assign status = {frame_irq,
	assign status = {flushing_fifo,		3'b0,
			flushing_fifo,
	stuffer_running_r,		stuffer_running_r,
	reading_frame,		reading_frame,
	im_r, is_r};		im_r, is_r};
	@@ -65,6 +70,8 @@ module cmprs_status(
	else if (eof_written) is_r <= 1;		else if (eof_written) is_r <= 1;
	else if (set_interrupts && (data_in == 1)) is_r <= 0;		else if (set_interrupts && (data_in == 1)) is_r <= 0;

			if (eof_written) frame_irq <= frame_num_compressed;

	stuffer_running_r <= stuffer_running;		stuffer_running_r <= stuffer_running;

	if (stuffer_running_r && !stuffer_running) flushing_fifo <= 1;		if (stuffer_running_r && !stuffer_running) flushing_fifo <= 1;

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