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Commit 7c906860 authored by Andrey Filippov's avatar Andrey Filippov
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testing/debugging for different intervals between tiles

parent fd65cb8c
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dsp/mclt16x16_bayer3.v
View file @ 7c906860
......@@ -54,12 +54,13 @@ module mclt16x16_bayer3#(
parameter DSP_A_WIDTH = 25,
parameter DSP_P_WIDTH = 48,
parameter DEAD_CYCLES = 14, // start next block immedaitely, or with longer pause
parameter OUTS_AT_ONCE = 1 // 0: outputs with lowest latency, 1: all at once (with green)
parameter OUTS_AT_ONCE = 1, // 0: outputs with lowest latency, 1: all at once (with green)
parameter TILE_PAGE_BITS = 2 // 1 or 2 only: number of bits in tile counter (>=2 for simultaneous rotated readout, limited by red)
)(
input clk, //!< system clock, posedge
input rst, //!< sync reset
input start, //!< start convertion of the next 256 samples
input page, //!< parameter page number (valid @ start)
input [TILE_PAGE_BITS-1:0] page, //!< parameter page number (valid @ start)
input [1:0] tile_size, //!< o: 16x16, 1 - 18x18, 2 - 20x20, 3 - 22x22 (max for 9-bit addr)
input [1:0] color_wa, //!< color index to apply parameters to (0 - R, 1 - B, 2 - G)
input inv_checker, //!< 0 - includes main diagonal (symmetrical DTT), 1 - antisymmetrical DTT
......@@ -215,7 +216,7 @@ module mclt16x16_bayer3#(
wire signed [WND_WIDTH-1:0] window_w;
wire var_pre2_first; //
wire pre_last_in_w;
wire pre_last_in_w = run_r && (in_cntr[7:0] == 'hfe);
wire green_late;
wire signed [DTT_IN_WIDTH-1:0] data_dtt_in; // multiplexed DTT input data
reg dtt_we;
......@@ -223,7 +224,8 @@ module mclt16x16_bayer3#(
reg [7:0] dtt_in_precntr; //
reg [8:0] dtt_in_wa;
assign pre_busy = pre_busy_r || start || (!pre_last_in_w && phases[0]);
// assign pre_busy = pre_busy_r || start || (!pre_last_in_w && phases[0]);
assign pre_busy = pre_busy_r || start || (!pre_last_in_w && run_r);
assign pre_last_in = pre_last_in_w;
mclt_bayer_fold_rgb #(
......@@ -251,7 +253,7 @@ module mclt16x16_bayer3#(
.phases (phases), // output[7:0]
// make it always 0 or 1 for R/B, then if use only not-in-series, use D -input for twice value
.var_pre2_first(var_pre2_first), // output
.pre_last_in (pre_last_in_w),// output reg
.pre_last_in (), // pre_last_in_w),// output reg
.green_late (green_late) // output reg
);
......@@ -326,16 +328,19 @@ module mclt16x16_bayer3#(
wire dtt_start_red = (dtt_start16 & dtt_r_cntr[7:6] == 1); // after
wire dtt_start_blue = (dtt_start16 & dtt_r_cntr[7:6] == 2); // after
wire dtt_start_green = (dtt_start16 & dtt_r_cntr[7:6] == 3); // after
reg [4:0] dtt_out_ram_cntr;
reg [4:0] dtt_out_ram_wah;
reg [TILE_PAGE_BITS + 3:0] dtt_out_ram_cntr;
reg [TILE_PAGE_BITS + 3:0] dtt_out_ram_wah;
wire dtt_start_fill; // some data available in DTT output buffer, OK to start consecutive readout
reg dtt_start_red_fill;
reg dtt_start_blue_fill;
reg dtt_start_green_fill;
wire [8:0] dtt_out_ram_wa = {dtt_out_ram_wah,dtt_out_wa16};
wire [TILE_PAGE_BITS + 7:0] dtt_out_ram_wa = {dtt_out_ram_wah,dtt_out_wa16};
wire [8:0] dtt_out_ram_wa_rb = {2'b0,dtt_out_ram_wa[8],dtt_out_ram_wa[5:0]};
wire [8:0] dtt_out_ram_wa_rb =
{{3-TILE_PAGE_BITS{1'b0}},dtt_out_ram_wa[8 +:TILE_PAGE_BITS],dtt_out_ram_wa[5:0]};
// Green does not need >2 pages in the pre-rotattion buffer
wire [8:0] dtt_out_ram_wa_g = {1'b0,dtt_out_ram_wa[8],dtt_out_ram_wa[6:0]};
wire dtt_out_we_r = dtt_out_we & ~dtt_out_ram_wa[7] & ~dtt_out_ram_wa[6];
......@@ -359,12 +364,12 @@ module mclt16x16_bayer3#(
wire dtt_blue_quad_out = dtt_out_ram_cntr[3:2] == 1;
wire dtt_green_quad_out = dtt_out_ram_cntr[3:2] == 2;
wire ram_wpage_r = dtt_out_ram_cntr[4]; // dtt_out_ram_wah[4];
reg ram_wpage_b;
reg ram_wpage_g;
wire [TILE_PAGE_BITS-1:0] ram_wpage_r = dtt_out_ram_cntr[4+:TILE_PAGE_BITS]; // dtt_out_ram_wah[4];
reg [TILE_PAGE_BITS-1:0] ram_wpage_b;
reg [TILE_PAGE_BITS-1:0] ram_wpage_g;
wire [6:0] dtt_rd_ra_r;
wire [6:0] dtt_rd_ra_b;
wire [TILE_PAGE_BITS+5:0] dtt_rd_ra_r; // 6 or 7
wire [TILE_PAGE_BITS+5:0] dtt_rd_ra_b;
wire [7:0] dtt_rd_ra_g;
......@@ -447,7 +452,8 @@ module mclt16x16_bayer3#(
.LOG2WIDTH_RD(5)
) ram18p_var_w_var_r_dtt_out_r_i (
.rclk (clk), // input
.raddr ({2'b0,dtt_rd_ra_r}), // input[8:0]
// .raddr ({2'b0,dtt_rd_ra_r}), // input[8:0]
.raddr ({{3-TILE_PAGE_BITS{1'b0}},dtt_rd_ra_r}), // input[8:0]
.ren (dtt_rd_regen_r[0]), // input
.regen (dtt_rd_regen_r[1]), // input
.data_out (dtt_rd_data_r_w), // output[35:0]
......@@ -464,7 +470,7 @@ module mclt16x16_bayer3#(
.LOG2WIDTH_RD(5)
) ram18p_var_w_var_r_dtt_out_b_i (
.rclk (clk), // input
.raddr ({2'b0,dtt_rd_ra_b}), // input[8:0]
.raddr ({{3-TILE_PAGE_BITS{1'b0}},dtt_rd_ra_b}), // input[8:0]
.ren (dtt_rd_regen_b[0]), // input
.regen (dtt_rd_regen_b[1]), // input
.data_out (dtt_rd_data_b_w), // output[35:0]
......@@ -500,7 +506,8 @@ module mclt16x16_bayer3#(
.DSP_A_WIDTH (DSP_A_WIDTH),
.DSP_P_WIDTH (DSP_P_WIDTH),
.GREEN (0),
.START_DELAY (DTT_OUT_DELAY_R)
.START_DELAY (DTT_OUT_DELAY_R),
.TILE_PAGE_BITS(TILE_PAGE_BITS)
) phase_rotator_r_i (
.clk (clk), // input
.rst (rst), // input
......@@ -528,7 +535,8 @@ module mclt16x16_bayer3#(
.DSP_A_WIDTH (DSP_A_WIDTH),
.DSP_P_WIDTH (DSP_P_WIDTH),
.GREEN (0),
.START_DELAY (DTT_OUT_DELAY_B)
.START_DELAY (DTT_OUT_DELAY_B),
.TILE_PAGE_BITS(TILE_PAGE_BITS)
) phase_rotator_b_i (
.clk (clk), // input
.rst (rst), // input
......@@ -554,14 +562,14 @@ module mclt16x16_bayer3#(
.DSP_B_WIDTH (DSP_B_WIDTH),
.DSP_A_WIDTH (DSP_A_WIDTH),
.DSP_P_WIDTH (DSP_P_WIDTH),
// .COEFF_WIDTH(COEFF_WIDTH),
.GREEN (1),
.START_DELAY (DTT_OUT_DELAY_G)
.START_DELAY (DTT_OUT_DELAY_G),
.TILE_PAGE_BITS(1)
) phase_rotator_g_i (
.clk (clk), // input
.rst (rst), // input
.start (dtt_start_green_fill), // input
.wpage (ram_wpage_g), // input
.wpage (ram_wpage_g[0]), // input
.shift_h (x_shft_rot_ram_reg), // input[6:0] signed
.shift_v (y_shft_rot_ram_reg), // input[6:0] signed
.inv_checker (inv_checker_rot_ram_reg), // input
......
dsp/mclt_test_06.tf
View file @ 7c906860
......@@ -78,6 +78,7 @@ module mclt_test_06 ();
parameter DEAD_CYCLES = 14; // start next block immedaitely, or with longer pause
// parameter OUTS_AT_ONCE = 0; // 0: outputs with lowest latency, 1: all at once (with green)
parameter OUTS_AT_ONCE = 1; // 0: outputs with lowest latency, 1: all at once (with green)
parameter TILE_PAGE_BITS = 2; // 1 or 2 only: number of bits in tile counter (>=2 for simultaneous rotated readout, limited by red)
reg RST = 1'b1;
reg CLK = 1'b0;
......@@ -257,15 +258,19 @@ module mclt_test_06 ();
end
reg START;
reg [8:0] in_cntr;
reg PRE_BUSY;
reg [7:0] in_cntr;
reg in_run;
wire pre_last_count = (in_cntr == 'h17e);
wire pre_last_count = (in_cntr == 'hfe);
reg last_count_r;
wire pre_last_128 = (in_cntr[6:0] == 'h7e);
// wire pre_last_128 = (in_cntr[6:0] == 'h7e);
// reg last_128_r;
// wire start = START | (last_128_r && ! in_cntr[8]);
reg PAGE; // full page, 192 clocks
reg [2:0] SUB_PAGE; // single color page
// reg PAGE; // full page, 192 clocks
integer PAGE; // full page, 192 clocks
// reg [2:0] SUB_PAGE; // single color page
// reg PIX_PAGE;
// wire [9:0] PIX_ADDR10 = {PIX_PAGE,PIX_ADDR9}; // SuppressThisWarning VEditor debug output
......@@ -281,13 +286,17 @@ module mclt_test_06 ();
else in_cntr <= in_cntr + 1;
if (RST) PAGE <= 0;
else if (pre_last_count) PAGE <= PAGE + 1;
// else if (pre_last_count) PAGE <= PAGE + 1;
else if (in_cntr == 'hf0) PAGE <= PAGE + 1;
if (RST) SUB_PAGE <= 0;
else if (pre_last_128) SUB_PAGE <= SUB_PAGE + 1;
// if (RST) SUB_PAGE <= 0;
// else if (pre_last_128) SUB_PAGE <= SUB_PAGE + 1;
// if (PIX_COPY_PAGE) PIX_PAGE <= PAGE;
if (RST) PRE_BUSY <= 0;
else if (START) PRE_BUSY <= 1;
else if (in_cntr == 'hf0) PRE_BUSY <= 0;
......@@ -306,15 +315,19 @@ module mclt_test_06 ();
@(posedge CLK)
#1 START = 0;
for (n = 0; n < 1; n = n+1) begin
if (n >= 0) LATE = 1;
while (!in_cntr[8]) begin
if (n >= 1) LATE = 1;
// if (n >= 0) LATE = 1;
// while (!in_cntr[8]) begin
while (!in_cntr[7]) begin
@(posedge CLK);
#1;
end
//PRE_BUSY
// while (pre_busy || LATE) begin
while (pre_busy3 || LATE) begin
if (!pre_busy3) LATE = 0;
/// while (pre_busy3 || LATE) begin
/// if (!pre_busy3) LATE = 0;
while (PRE_BUSY || LATE) begin
if (!PRE_BUSY) LATE = 0;
@(posedge CLK);
#1;
end
......@@ -472,8 +485,8 @@ module mclt_test_06 ();
integer n6, cntr6, diff6r, diff6b, diff6g; // SuppressThisWarning VEditor : assigned in $readmem() system task
wire [6:0] dtt_rd_ra_r = mclt16x16_bayer3_i.dtt_rd_ra_r;
wire [6:0] dtt_rd_ra_b = mclt16x16_bayer3_i.dtt_rd_ra_b;
wire [TILE_PAGE_BITS+5:0] dtt_rd_ra_r = mclt16x16_bayer3_i.dtt_rd_ra_r;
wire [TILE_PAGE_BITS+5:0] dtt_rd_ra_b = mclt16x16_bayer3_i.dtt_rd_ra_b;
wire [7:0] dtt_rd_ra_g = mclt16x16_bayer3_i.dtt_rd_ra_g;
wire [1:0] dtt_rd_regen_r = mclt16x16_bayer3_i.dtt_rd_regen_r;
wire [1:0] dtt_rd_regen_b = mclt16x16_bayer3_i.dtt_rd_regen_b;
......@@ -620,18 +633,19 @@ module mclt_test_06 ();
wire PIX_RE3; // SuppressThisWarning VEditor : debug only
wire [8:0] PIX_ADDR93;
reg PIX_PAGE3;
reg [TILE_PAGE_BITS-1:0] PIX_PAGE3;
wire [9:0] PIX_ADDR103 = {PIX_PAGE3,PIX_ADDR93}; // SuppressThisWarning VEditor debug output
wire PIX_COPY_PAGE3; // copy page address // SuppressThisWarning VEditor - not yet used
wire [PIXEL_WIDTH-1 : 0] PIX_D3;
reg start3;
reg page3; // 1/2-nd bayer tile
reg [TILE_PAGE_BITS-1 : 0] page3; // 1/2-nd bayer tile
reg pre_run;
reg [1:0] pre_run_cntr;
wire [2:0] color_page = pre_run_cntr + 3 * page3; // SuppressThisWarning VEditor - VDT bug (used as index)
reg pending;
always @ (posedge CLK) begin
if (START) page3 <= (SUB_PAGE > 2);
if (START) page3 <= PAGE[TILE_PAGE_BITS-1:0]; // (SUB_PAGE > 2);
if (RST) pre_run <= 0;
else if (START) pre_run <= 1;
......@@ -642,7 +656,11 @@ module mclt_test_06 ();
if (PIX_COPY_PAGE3) PIX_PAGE3 <= page3;
start3 <= (pre_run_cntr == 2);
if (RST) pending <= 0;
else if (pre_run_cntr == 1) pending <= 1;
else if (!pre_busy3) pending <= 0;
start3 <= pending && !pre_busy3; // (pre_run_cntr == 2);
end
......@@ -662,7 +680,8 @@ module mclt_test_06 ();
.DSP_A_WIDTH (DSP_A_WIDTH),
.DSP_P_WIDTH (DSP_P_WIDTH),
.DEAD_CYCLES (DEAD_CYCLES),
.OUTS_AT_ONCE (OUTS_AT_ONCE)
.OUTS_AT_ONCE (OUTS_AT_ONCE),
.TILE_PAGE_BITS (TILE_PAGE_BITS)
) mclt16x16_bayer3_i (
.clk (CLK), // input
.rst (RST), // input
......
dsp/phase_rotator_rgb.v
View file @ 7c906860
......@@ -46,18 +46,20 @@ module phase_rotator_rgb#(
parameter DSP_P_WIDTH = 48,
parameter COEFF_WIDTH = 17, // = DSP_B_WIDTH - 1 or positive numbers,
parameter GREEN = 1, // 0: use 1 DTT block (R,B), 1: use two DTT blocks (G)
parameter START_DELAY = 128 // delay start of input memory readout
parameter START_DELAY = 128, // delay start of input memory readout
parameter TILE_PAGE_BITS = 1 // 1 or 2 only: number of bits in tile counter (>=2 for simultaneous rotated readout, limited by red)
)(
input clk, //!< system clock, posedge
input rst, //!< sync reset
input start, //!< start of delay
input wpage, //!< page (64 for R,B, 128 for G) last being written (may need delay?)
input [TILE_PAGE_BITS-1:0] wpage, //!< page (64 for R,B, 128 for G) last being written (may need delay?)
input signed [SHIFT_WIDTH-1:0] shift_h, //!< subpixel shift horizontal
input signed [SHIFT_WIDTH-1:0] shift_v, //!< subpixel shift vertical
input inv_checker, //!< negate 2-nd and fourth samples (for handling inverted checkerboard)
input odd_rows, //!< when not GEEN (R or B) 0: even (first) rows non-zero, 1: odd (second)
// input data CC,CS,SC,SS in column scan order (matching DTT)
output [GREEN + 6:0] in_addr, //!< input buffer address
// output [GREEN + 6:0] in_addr, //!< input buffer address
output [GREEN + TILE_PAGE_BITS + 5:0] in_addr, //!< input buffer address
output [1:0] in_re, //!< input buffer re/regen
input signed [FD_WIDTH-1:0] fd_din, //!< frequency domain data in, LATENCY=3 from start
output signed [FD_WIDTH-1:0] fd_out, //!< frequency domain data in
......@@ -69,7 +71,7 @@ module phase_rotator_rgb#(
reg signed [SHIFT_WIDTH-1:0] shift_h_r;
reg signed [SHIFT_WIDTH-1:0] shift_v_r;
reg wpage_r;
reg [TILE_PAGE_BITS-1:0] wpage_r;
reg [2:0] inv;
reg [1:0] dtt_start_out;
reg [7:0] dtt_dly_cntr;
......@@ -77,7 +79,7 @@ module phase_rotator_rgb#(
reg [8:0] dtt_rd_cntr_pre; // 1 ahead of the former counter for dtt readout to rotator
reg [7:0] in_addr_r; //!< input buffer address
reg [8:0] out_addr_r;
assign in_addr = in_addr_r[GREEN + 6:0];
assign in_addr = in_addr_r[GREEN + TILE_PAGE_BITS + 5:0];
assign in_re = dtt_rd_regen_dv[2:1];
// assign fd_wa = {out_addr_r[8], out_addr_r[0],out_addr_r[1],out_addr_r[4:2],out_addr_r[7:5]};
assign fd_wa = {out_addr_r[8], out_addr_r[1],out_addr_r[0],out_addr_r[4:2],out_addr_r[7:5]};
......@@ -119,7 +121,7 @@ module phase_rotator_rgb#(
(dtt_rd_cntr_pre[0] ? (~dtt_rd_cntr_pre[7:2]) : {~dtt_rd_cntr_pre[7:5],dtt_rd_cntr_pre[4:2]}):
(dtt_rd_cntr_pre[0] ? {dtt_rd_cntr_pre[7:5],~dtt_rd_cntr_pre[4:2]} : dtt_rd_cntr_pre[7:2])};
if (pre_first_out) out_addr_r <= {wpage_r,8'b0};
if (pre_first_out) out_addr_r <= {wpage_r[0],8'b0};
else if (fd_dv) out_addr_r <= out_addr_r + 1;
pre_last_out <= out_addr_r[7:0] == 8'hfe;
......
mclt_test_06.sav
View file @ 7c906860
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