more debugging (7c5ab53d) · Commits · Elphel / x393

axi/axibram_read.v

+2 −1

Original line number	Original line	Diff line number	Diff line
	@@ -134,7 +134,8 @@ module axibram_read #(

	`ifdef USE_SHORT_REN_REGEN		`ifdef USE_SHORT_REN_REGEN
	reg bram_regen_r;		reg bram_regen_r;
	assign bram_ren = bram_reg_re_w && !pre_last_in_burst_r ; // read port enable		// assign bram_ren = bram_reg_re_w && !pre_last_in_burst_r ; // read port enable
			assign bram_ren = read_in_progress;
	assign bram_regen = bram_regen_r; // output register enable		assign bram_regen = bram_regen_r; // output register enable
	`else		`else
	assign bram_ren = bram_reg_re_w; // read port enable		assign bram_ren = bram_reg_re_w; // read port enable

includes/x393_tasks_mcntrl_buffers.vh

+2 −1

Original line number	Original line	Diff line number	Diff line
	@@ -27,6 +27,7 @@ task write_block_scanline_chn; // S uppressThisWarning VEditor : may be unused
	input integer startY;		input integer startY;
	reg [29:0] start_addr;		reg [29:0] start_addr;
	begin		begin
			$display("====== write_block_scanline_chn:%d page: %x X=0x%x Y=0x%x num=%d @%t", chn, page, startX, startY,num_words, $time);
	case (chn)		case (chn)
	1: start_addr=MCONTR_BUF1_WR_ADDR + (page << 8);		1: start_addr=MCONTR_BUF1_WR_ADDR + (page << 8);
	3: start_addr=MCONTR_BUF3_WR_ADDR + (page << 8);		3: start_addr=MCONTR_BUF3_WR_ADDR + (page << 8);
	@@ -35,7 +36,7 @@ task write_block_scanline_chn; // S uppressThisWarning VEditor : may be unused
	start_addr = MCONTR_BUF1_WR_ADDR+ (page << 8);		start_addr = MCONTR_BUF1_WR_ADDR+ (page << 8);
	end		end
	endcase		endcase
	write_block_incremtal (start_addr, num_words, startX+startY<<16);		write_block_incremtal (start_addr, num_words, (startX<<2) + (startY<<16)); // 1 of startX is 8x16 bit, 16 bytes or 4 32-bit words
	end		end
	endtask		endtask

memctrl/cmd_encod_linear_rd.v

+5 −2

Original line number	Original line	Diff line number	Diff line
	@@ -119,10 +119,13 @@ module cmd_encod_linear_rd #(

	always @ (posedge clk) if (start) begin		always @ (posedge clk) if (start) begin
	row<=row_in;		row<=row_in;
	col <= start_col;		// col <= start_col;
	bank <= bank_in;		bank <= bank_in;
	skip_next_page <= skip_next_page_in;		skip_next_page <= skip_next_page_in;
			end
			always @ (posedge clk) begin
			if (start) col <= start_col;
			else if (rom_cmd==ENC_CMD_READ) col <= col+1;
	end		end

	// ROM-based (registered output) encoded sequence		// ROM-based (registered output) encoded sequence

memctrl/cmd_encod_linear_wr.v

+6 −1

Original line number	Original line	Diff line number	Diff line
	@@ -131,11 +131,16 @@ module cmd_encod_linear_wr #(

	always @ (posedge clk) if (start) begin		always @ (posedge clk) if (start) begin
	row<=row_in;		row<=row_in;
	col <= start_col;		// col <= start_col;
	bank <= bank_in;		bank <= bank_in;
	skip_next_page <= skip_next_page_in;		skip_next_page <= skip_next_page_in;
	end		end

			always @ (posedge clk) begin
			if (start) col <= start_col;
			else if (rom_cmd==ENC_CMD_WRITE) col <= col+1;
			end

	// ROM-based (registered output) encoded sequence		// ROM-based (registered output) encoded sequence
	// TODO: Remove last ENC_BUF_RD		// TODO: Remove last ENC_BUF_RD
	always @ (posedge rst or posedge clk) begin		always @ (posedge rst or posedge clk) begin

memctrl/mcntrl_linear_rw.v

+46 −17

Original line number	Original line	Diff line number	Diff line
	@@ -79,7 +79,7 @@ module mcntrl_linear_rw #(
	);		);
	localparam NUM_RC_BURST_BITS=ADDRESS_NUMBER+COLADDR_NUMBER-3; //to spcify row and col8 == 22		localparam NUM_RC_BURST_BITS=ADDRESS_NUMBER+COLADDR_NUMBER-3; //to spcify row and col8 == 22
	localparam MPY_WIDTH= NUM_RC_BURST_BITS; // 22		localparam MPY_WIDTH= NUM_RC_BURST_BITS; // 22
	localparam PAR_MOD_LATENCY= 7; // TODO: Find actual worst-case latency for:		localparam PAR_MOD_LATENCY= 9; // TODO: Find actual worst-case latency for:
	reg [FRAME_WIDTH_BITS-1:0] curr_x; // (calculated) start of transfer x (relative to window left)		reg [FRAME_WIDTH_BITS-1:0] curr_x; // (calculated) start of transfer x (relative to window left)
	reg [FRAME_HEIGHT_BITS-1:0] curr_y; // (calculated) start of transfer y (relative to window top)		reg [FRAME_HEIGHT_BITS-1:0] curr_y; // (calculated) start of transfer y (relative to window top)
	reg [FRAME_HEIGHT_BITS:0] next_y; // (calculated) next row number		reg [FRAME_HEIGHT_BITS:0] next_y; // (calculated) next row number
	@@ -96,6 +96,7 @@ module mcntrl_linear_rw #(
	reg [FRAME_WIDTH_BITS:0] row_left; // number of 8-bursts left in the current row		reg [FRAME_WIDTH_BITS:0] row_left; // number of 8-bursts left in the current row
	reg last_in_row;		reg last_in_row;
	reg [COLADDR_NUMBER-3:0] mem_page_left; // number of 8-bursts left in the pointed memory page		reg [COLADDR_NUMBER-3:0] mem_page_left; // number of 8-bursts left in the pointed memory page
			reg [COLADDR_NUMBER-4:0] line_start_page_left; // number of 8-burst left in the memory page from the start of the frame line
	reg [NUM_XFER_BITS:0] lim_by_xfer; // number of bursts left limited by the longest transfer (currently 64)		reg [NUM_XFER_BITS:0] lim_by_xfer; // number of bursts left limited by the longest transfer (currently 64)
	// reg [MAX_TILE_WIDTH:0] lim_by_tile_width; // number of bursts left limited by the longest transfer (currently 64)		// reg [MAX_TILE_WIDTH:0] lim_by_tile_width; // number of bursts left limited by the longest transfer (currently 64)
	wire [COLADDR_NUMBER-3:0] remainder_in_xfer ;//remainder_tile_width; // number of bursts postponed to the next partial tile (because of the page crossing) MSB-sign		wire [COLADDR_NUMBER-3:0] remainder_in_xfer ;//remainder_tile_width; // number of bursts postponed to the next partial tile (because of the page crossing) MSB-sign
	@@ -107,7 +108,7 @@ module mcntrl_linear_rw #(
	reg [NUM_XFER_BITS:0] xfer_num128_r; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8		reg [NUM_XFER_BITS:0] xfer_num128_r; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8
	// reg [NUM_XFER_BITS-1:0] xfer_num128_m1_r; // number of 128-bit words to transfer minus 1 (8*16 bits) - full bursts of 8		// reg [NUM_XFER_BITS-1:0] xfer_num128_m1_r; // number of 128-bit words to transfer minus 1 (8*16 bits) - full bursts of 8
	wire pgm_param_w; // program one of the parameters, invalidate calculated results for PAR_MOD_LATENCY		wire pgm_param_w; // program one of the parameters, invalidate calculated results for PAR_MOD_LATENCY
	reg [2:0] xfer_start_r;		reg [2:0] xfer_start_r; // 1 hot started by xfer start only (not by parameter change)
	reg [PAR_MOD_LATENCY-1:0] par_mod_r;		reg [PAR_MOD_LATENCY-1:0] par_mod_r;
	reg [PAR_MOD_LATENCY-1:0] recalc_r; // 1-hot CE for re-calculating registers		reg [PAR_MOD_LATENCY-1:0] recalc_r; // 1-hot CE for re-calculating registers
	wire calc_valid; // calculated registers have valid values		wire calc_valid; // calculated registers have valid values
	@@ -142,9 +143,9 @@ module mcntrl_linear_rw #(
	wire set_window_wh_w;		wire set_window_wh_w;
	wire set_window_x0y0_w;		wire set_window_x0y0_w;
	wire set_window_start_w;		wire set_window_start_w;
	wire lsw13_zero=!cmd_data[FRAME_WIDTH_BITS-1:0]; // LSW 13 (FRAME_WIDTH_BITS) low bits are all 0 - set carry bit		wire lsw13_zero=!(\|cmd_data[FRAME_WIDTH_BITS-1:0]); // LSW 13 (FRAME_WIDTH_BITS) low bits are all 0 - set carry bit
	wire msw13_zero=!cmd_data[FRAME_WIDTH_BITS+15:16]; // MSW 13 (FRAME_WIDTH_BITS) low bits are all 0 - set carry bit		// wire msw13_zero=!(\|cmd_data[FRAME_WIDTH_BITS+15:16]); // MSW 13 (FRAME_WIDTH_BITS) low bits are all 0 - set carry bit
	wire msw_zero= !cmd_data[31:16]; // MSW all bits are 0 - set carry bit		wire msw_zero= !(\|cmd_data[31:16]); // MSW all bits are 0 - set carry bit


	// reg [4:0] mode_reg;//mode register: {extra_pages[1:0],write_mode,enable,!reset}		// reg [4:0] mode_reg;//mode register: {extra_pages[1:0],write_mode,enable,!reset}
	@@ -180,7 +181,7 @@ module mcntrl_linear_rw #(
	else if (set_start_addr_w) start_addr <= cmd_data[NUM_RC_BURST_BITS-1:0];		else if (set_start_addr_w) start_addr <= cmd_data[NUM_RC_BURST_BITS-1:0];

	if (rst) frame_full_width <= 0;		if (rst) frame_full_width <= 0;
	else if (set_frame_width_w) frame_full_width <= {msw13_zero,cmd_data[FRAME_WIDTH_BITS-1:0]};		else if (set_frame_width_w) frame_full_width <= {lsw13_zero,cmd_data[FRAME_WIDTH_BITS-1:0]};

	if (rst) begin		if (rst) begin
	window_width <= 0;		window_width <= 0;
	@@ -252,8 +253,10 @@ module mcntrl_linear_rw #(
	next_y <= curr_y + 1;		next_y <= curr_y + 1;
	row_left <= window_width - curr_x; // 14 bits - 13 bits		row_left <= window_width - curr_x; // 14 bits - 13 bits
	end		end
			/*
	if (recalc_r[1]) begin // cycle 2		if (recalc_r[1]) begin // cycle 2
	mem_page_left <= (1 << (COLADDR_NUMBER-3)) - frame_x[COLADDR_NUMBER-4:0];		mem_page_left <= {1'b1,line_start_page_left} - frame_x[COLADDR_NUMBER-4:0];

	lim_by_xfer <= (\|row_left[FRAME_WIDTH_BITS:NUM_XFER_BITS])?		lim_by_xfer <= (\|row_left[FRAME_WIDTH_BITS:NUM_XFER_BITS])?
	(1<<NUM_XFER_BITS):		(1<<NUM_XFER_BITS):
	row_left[NUM_XFER_BITS:0]; // 7 bits, max 'h40		row_left[NUM_XFER_BITS:0]; // 7 bits, max 'h40
	@@ -266,27 +269,53 @@ module mcntrl_linear_rw #(
	mem_page_left[NUM_XFER_BITS:0]:		mem_page_left[NUM_XFER_BITS:0]:
	lim_by_xfer[NUM_XFER_BITS:0]);		lim_by_xfer[NUM_XFER_BITS:0]);
	leftover <= remainder_in_xfer[NUM_XFER_BITS-1:0];		leftover <= remainder_in_xfer[NUM_XFER_BITS-1:0];
	// xfer_num128_r<= (mem_page_left < {{COLADDR_NUMBER-3-NUM_XFER_BITS{1'b0}},lim_by_xfer})?
	// mem_page_left[NUM_XFER_BITS:0]:
	// lim_by_xfer[NUM_XFER_BITS:0];
	end		end
	if (recalc_r[3]) begin // cycle 4		if (recalc_r[3]) begin // cycle 4
	last_in_row <= last_in_row_w;		last_in_row <= last_in_row_w; //(row_left=={{(FRAME_WIDTH_BITS-NUM_XFER_BITS){1'b0}},xfer_num128_r});
	end		end
			*/
	// registers to be absorbed in DSP block		// registers to be absorbed in DSP block
	frame_y8_r <= frame_y[FRAME_HEIGHT_BITS-1:3]; // lat=2		frame_y8_r <= frame_y[FRAME_HEIGHT_BITS-1:3]; // lat=2
	frame_full_width_r <= frame_full_width;		frame_full_width_r <= frame_full_width;
	start_addr_r <= start_addr;		start_addr_r <= start_addr;
	mul_rslt <= mul_rslt_w[MPY_WIDTH-1:0]; // frame_y8_r * frame_width_r; // 7 bits will be discarded lat=3;		mul_rslt <= mul_rslt_w[MPY_WIDTH-1:0]; // frame_y8_r * frame_width_r; // 7 bits will be discarded lat=3;
	line_start_addr <= start_addr_r+mul_rslt; // lat=4		line_start_addr <= start_addr_r+mul_rslt; // lat=4

	// TODO: Verify MPY/register timing above		// TODO: Verify MPY/register timing above
	if (recalc_r[5]) begin // cycle 6		if (recalc_r[5]) begin // cycle 6
	row_col_r <= line_start_addr+frame_x;		row_col_r <= line_start_addr+frame_x;
			// line_start_page_left <= {COLADDR_NUMBER-3{1'b0}} - line_start_addr[COLADDR_NUMBER-4:0]; // 7 bits
			line_start_page_left <= - line_start_addr[COLADDR_NUMBER-4:0]; // 7 bits
	end		end
	bank_reg[0] <= frame_y[2:0]; //TODO: is it needed - a pipeline for the bank? - remove!		bank_reg[0] <= frame_y[2:0]; //TODO: is it needed - a pipeline for the bank? - remove!
	for (i=0;i<2; i = i+1)		for (i=0;i<2; i = i+1)
	bank_reg[i+1] <= bank_reg[i];		bank_reg[i+1] <= bank_reg[i];


			if (recalc_r[6]) begin // cycle 7
			mem_page_left <= {1'b1,line_start_page_left} - frame_x[COLADDR_NUMBER-4:0];

			lim_by_xfer <= (\|row_left[FRAME_WIDTH_BITS:NUM_XFER_BITS])?
			(1<<NUM_XFER_BITS):
			row_left[NUM_XFER_BITS:0]; // 7 bits, max 'h40
			end
			if (recalc_r[7]) begin // cycle 8
			xfer_limited_by_mem_page_r <= xfer_limited_by_mem_page && !continued_xfer;
			xfer_num128_r<= continued_xfer?
			{EXTRA_BITS,leftover}:
			(xfer_limited_by_mem_page?
			mem_page_left[NUM_XFER_BITS:0]:
			lim_by_xfer[NUM_XFER_BITS:0]);
			//xfer_num128_r depends on leftover only if continued_xfer (after first shortened actual xfer and will not change w/o xfers)
			// and (next) leftover is only set if continued_xfer==0, so multiple runs without chnge of continued_xfer will not differ
			if (!continued_xfer) leftover <= remainder_in_xfer[NUM_XFER_BITS-1:0]; // {EXTRA_BITS, lim_by_xfer}-mem_page_left;
			end

			if (recalc_r[8]) begin // cycle 9
			last_in_row <= last_in_row_w; //(row_left=={{(FRAME_WIDTH_BITS-NUM_XFER_BITS){1'b0}},xfer_num128_r});
			end


	end		end
	wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;		wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
	// now have row start address, bank and row_left ;		// now have row start address, bank and row_left ;
	@@ -364,10 +393,10 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;

	if (rst) pending_xfers <= 0;		if (rst) pending_xfers <= 0;
	else if (chn_rst \|\| !busy_r) pending_xfers <= 0;		else if (chn_rst \|\| !busy_r) pending_xfers <= 0;
	// else if ( xfer_start_r[0] && !xfer_done) pending_xfers <= pending_xfers + 1;		else if ( xfer_start_r[0] && !xfer_done) pending_xfers <= pending_xfers + 1;
	// else if (!xfer_start_r[0] && xfer_done) pending_xfers <= pending_xfers - 1;		else if (!xfer_start_r[0] && xfer_done) pending_xfers <= pending_xfers - 1;
	else if ( start_not_partial && !xfer_done) pending_xfers <= pending_xfers + 1;		// else if ( start_not_partial && !xfer_done) pending_xfers <= pending_xfers + 1;
	else if (!start_not_partial && xfer_done) pending_xfers <= pending_xfers - 1;		// else if (!start_not_partial && xfer_done) pending_xfers <= pending_xfers - 1;

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