modifying timestamps/triggering

cocotb/x393_dut.v

@@ -1773,6 +1773,8 @@ assign x393_i.ps7_i.FCLKRESETN=     {RST,~RST,RST,~RST};
 
 `define TEST_IMU
 `define TEST_EXT_INT
+
+`define ODOMETER_PULSE_6
 assign #10 gpio_pins[7] = gpio_pins[8];
 `ifndef TEST_IMU
     assign #10 gpio_pins[9] = gpio_pins[6]; 
@@ -1922,7 +1924,9 @@ assign #10 gpio_pins[7] = gpio_pins[8];
       end
       assign gpio_pins[4]=SERIAL_BIT;
       assign gpio_pins[5]=GPS1SEC;
-//      assign gpio_pins[6]=ODOMETER_PULSE;
+`ifdef ODOMETER_PULSE_6
+      assign gpio_pins[6]=ODOMETER_PULSE;
+`endif
       assign gpio_pins[9]=ODOMETER_PULSE;
       oneshot i_oneshot  (.trigger(IMU_NMOSI),
                           .out(IMU_ACTIVE));

logger/event_logger.v

@@ -240,7 +240,7 @@ module  event_logger#(
 
     assign pre_message_trig = ext_di16[config_msg[3:0]];
 
-    assign message_trig= config_msg[4]^pre_message_trig;
+    assign message_trig= config_msg[4] ^ pre_message_trig;
 
     assign timestamp_request[1]=config_gps[3]? (config_gps[2]?nmea_sent_start:gps_ts_stb):gps_pulse1sec_single;
  

logger/imu_timestamps393.v

@@ -51,6 +51,7 @@ module  imu_timestamps393(
     output                 [15:0] dout);// output data
     reg           ts_rcv;
     reg           ts_busy;
+    reg           ts_busy_d; 
     reg     [1:0] chn; // channel for which timestamp is bein requested/received
     wire    [3:0] rq_pri; // 1-hot prioritized timestamp request
     wire    [1:0] rq_enc; // encoded request channel
@@ -70,7 +71,7 @@ module  imu_timestamps393(
     assign rq_enc = {rq_pri[3] | rq_pri[2],
                      rq_pri[3] | rq_pri[1]};
                      
-    assign pre_snap = (|ts_rq) && !ts_busy; 
+    assign pre_snap = (|ts_rq) && !ts_busy && !ts_busy_d; 
     assign chn1hot = {chn[1] & chn[0], chn[1] & ~chn[0], ~chn[1] & chn[0], ~chn[1] & ~chn[0]};
     assign pre_ackn = ts_rcv && (cntr == 3'h6);
     
@@ -87,6 +88,8 @@ module  imu_timestamps393(
         else if (pre_snap)                 ts_busy <= 1;
         else if (ts_rcv && (cntr == 3'h6)) ts_busy <= 0; // adjust 6?
         
+        ts_busy_d <= ts_busy;
+        
         rcv_last <= ts_rcv && (cntr == 3'h6);
         
         if      (rst)       ts_rcv <= 0;

logger/logger_arbiter393.v

@@ -129,8 +129,8 @@ module  logger_arbiter393(
     
         seq_cntr_last <= (seq_cntr[4:0]=='h1e);
     
-    
-        if      (wstart)              ts_en_r <=1'b1;
+        if      (rst)                 ts_en_r <=1'b0;
+        else if (wstart)              ts_en_r <=1'b1;
         else if (seq_cntr[1:0]==2'h3) ts_en_r <=1'b0;
         
         if (!ts_en_r) ts_sel_r[1:0] <= 2'h0;

timing/timing393.v

@@ -140,6 +140,12 @@ module  timing393       #(
     wire   [3:0] ts_local_stb;   // 1 clk before ts_snd_data is valid
     wire  [31:0] ts_local_data;  // byte-wide serialized timestamp message  
 
+    wire         ts_master_snap; // ts_snap_mclk make a timestamp pulse  single @(posedge pclk)
+    wire         ts_master_stb;  // 1 clk before ts_snd_data is valid
+    wire   [7:0] ts_master_data; // byte-wide serialized timestamp message  
+
+
+
     wire   [3:0] ts_stb;        // 1 clk before ts_snd_data is valid
     wire  [31:0] ts_data;       // byte-wide serialized timestamp message (channels concatenated)
     
@@ -238,6 +244,18 @@ module  timing393       #(
         .ts_data               (ts_local_data[3 * 8 +: 8]) // output[7:0] reg 
     );
 
+    timestamp_snapshot timestamp_snapshot_master_i ( // timestamp to send over the sync network
+        .tclk                  (mclk),                     // input
+        .sec                   (live_sec),                 // input[31:0] 
+        .usec                  (live_usec),                // input[19:0] 
+        .sclk                  (mclk),                     // input
+        .srst                  (mrst),                     // input
+        .snap                  (ts_master_snap),           // input
+        .pre_stb               (ts_master_stb),            // output
+        .ts_data               (ts_master_data[7:0])       // output[7:0] reg 
+    );
+
+
     camsync393 #(
         .CAMSYNC_ADDR           (CAMSYNC_ADDR),
         .CAMSYNC_MASK           (CAMSYNC_MASK),
@@ -294,6 +312,9 @@ module  timing393       #(
         .ts_snap_mclk_chn3 (ts_local_snap[3]),          // output
         .ts_snd_stb_chn3   (ts_local_stb[3]),           // input
         .ts_snd_data_chn3  (ts_local_data[3 * 8 +: 8]), // input[7:0] 
+        .ts_master_snap    (ts_master_snap),            // output
+        .ts_master_stb     (ts_master_stb),             // input
+        .ts_master_data    (ts_master_data),            // input[7:0] 
         .ts_rcv_stb_chn0   (ts_stb[0]),                 // output
         .ts_rcv_data_chn0  (ts_data[0 * 8 +: 8]),       // output[7:0] 
         .ts_rcv_stb_chn1   (ts_stb[1]),                 // output