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Commit 7a4e8e08 authored by Andrey Filippov's avatar Andrey Filippov
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done with testing sensor channles, starting debugging compressor

parent 608bcbd9
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Showing with 44 additions and 37 deletions
.project
View file @ 7a4e8e08
......@@ -62,42 +62,42 @@
<link>
<name>vivado_logs/VivadoBitstream.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150906141832703.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150906235148933.log</location>
</link>
<link>
<name>vivado_logs/VivadoOpt.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150906141832703.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150906235148933.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150906141832703.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150906235148933.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPower.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150906141832703.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150906235148933.log</location>
</link>
<link>
<name>vivado_logs/VivadoPlace.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150906141832703.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150906235148933.log</location>
</link>
<link>
<name>vivado_logs/VivadoRoute.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150906141832703.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150906235148933.log</location>
</link>
<link>
<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150906141832703.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150906235148933.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150906141832703.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150906235148933.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
......
axi/cmprs_afi_mux.v
View file @ 7a4e8e08
......@@ -276,8 +276,8 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop),
assign afi_wrissuecap1en = 1'b0;
`ifdef DEBUG_RING
debug_slave #(
.SHIFT_WIDTH (32),
.READ_WIDTH (32),
.SHIFT_WIDTH (64),
.READ_WIDTH (64),
.WRITE_WIDTH (32),
.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
) debug_slave_i (
......@@ -287,8 +287,9 @@ each group of 4 bits per channel : bits [1:0] - select, bit[2] - sset (0 - nop),
.debug_sl (debug_sl), // input
.debug_do (debug_do), // output
.rd_data ({
32'b0
left_to_eof[31:0],
24'b0,
fifo_count0[7:0]
}), // input[31:0]
.wr_data (), // output[31:0] - not used
.stb () // output - not used
......
compressor_jp/cmprs_frame_sync.v
View file @ 7a4e8e08
......@@ -127,14 +127,15 @@ module cmprs_frame_sync#(
else if (cmprs_standalone) bonded_mode <= 0;
if (!cmprs_en || !cmprs_run || vsync_late) frames_differ <= 0;
else if (frame_done_src) frames_differ <= 1'b1;
else if (frame_done_src) frames_differ <= 1'b1;
frames_numbers_differ <= frame_number_src != frame_number;
line_numbers_sync <= (line_unfinished_src > line_unfinished);
// suspend <= !bonded_mode && ((sigle_frame_buf ? frames_differ : frames_numbers_differ) || line_numbers_sync);
suspend <= bonded_mode && ((sigle_frame_buf ? frames_differ : frames_numbers_differ) || !line_numbers_sync);
// suspend <= bonded_mode && ((sigle_frame_buf ? frames_differ : frames_numbers_differ) || !line_numbers_sync);
suspend <= bonded_mode && !((sigle_frame_buf ? frames_differ : frames_numbers_differ) || line_numbers_sync);
end
......
compressor_jp/jp_channel.v
View file @ 7a4e8e08
......@@ -345,8 +345,8 @@ module jp_channel#(
`ifdef DEBUG_RING
debug_slave #(
.SHIFT_WIDTH (32),
.READ_WIDTH (32),
.SHIFT_WIDTH (96),
.READ_WIDTH (96),
.WRITE_WIDTH (32),
.DEBUG_CMD_LATENCY (DEBUG_CMD_LATENCY)
) debug_slave_i (
......@@ -356,8 +356,13 @@ module jp_channel#(
.debug_sl (debug_sl), // input
.debug_do (debug_do), // output
.rd_data ({
32'b0
16'b0,
fifo_count[7:0],
6'b0, sigle_frame_buf, suspend,
frame_number_dst[15:0],
line_unfinished_dst[15:0],
frame_number_src[15:0],
line_unfinished_src[15:0]
}), // input[31:0]
.wr_data (), // output[31:0] - not used
.stb () // output - not used
......
fpga_version.vh
View file @ 7a4e8e08
parameter FPGA_VERSION = 32'h0393001d;
\ No newline at end of file
parameter FPGA_VERSION = 32'h0393001e;
\ No newline at end of file
py393/x393_cmprs.py
View file @ 7a4e8e08
......@@ -140,31 +140,31 @@ class X393Cmprs(object):
"""
data = 0;
if not run_mode is None:
data |= (1 << vrlg.CMPRS_CBIT_RUN_BITS)
data |= (1 << vrlg.CMPRS_CBIT_RUN)
data |= (run_mode & ((1 << vrlg.CMPRS_CBIT_RUN_BITS) - 1)) << (vrlg.CMPRS_CBIT_RUN - vrlg.CMPRS_CBIT_RUN_BITS)
if not qbank is None:
data |= (1 << vrlg.CMPRS_CBIT_QBANK_BITS)
data |= (1 << vrlg.CMPRS_CBIT_QBANK)
data |= (qbank & ((1 << vrlg.CMPRS_CBIT_QBANK_BITS) - 1)) << (vrlg.CMPRS_CBIT_QBANK - vrlg.CMPRS_CBIT_QBANK_BITS)
if not dc_sub is None:
data |= (1 << vrlg.CMPRS_CBIT_DCSUB_BITS)
data |= (1 << vrlg.CMPRS_CBIT_DCSUB)
data |= (dc_sub & ((1 << vrlg.CMPRS_CBIT_DCSUB_BITS) - 1)) << (vrlg.CMPRS_CBIT_DCSUB - vrlg.CMPRS_CBIT_DCSUB_BITS)
if not cmode is None:
data |= (1 << vrlg.CMPRS_CBIT_CMODE_BITS)
data |= (1 << vrlg.CMPRS_CBIT_CMODE)
data |= (cmode & ((1 << vrlg.CMPRS_CBIT_CMODE_BITS) - 1)) << (vrlg.CMPRS_CBIT_CMODE - vrlg.CMPRS_CBIT_CMODE_BITS)
if not multi_frame is None:
data |= (1 << vrlg.CMPRS_CBIT_FRAMES_BITS)
data |= (1 << vrlg.CMPRS_CBIT_FRAMES)
data |= (multi_frame & ((1 << vrlg.CMPRS_CBIT_FRAMES_BITS) - 1)) << (vrlg.CMPRS_CBIT_FRAMES - vrlg.CMPRS_CBIT_FRAMES_BITS)
if not bayer is None:
data |= (1 << vrlg.CMPRS_CBIT_BAYER_BITS)
data |= (1 << vrlg.CMPRS_CBIT_BAYER)
data |= (bayer & ((1 << vrlg.CMPRS_CBIT_BAYER_BITS) - 1)) << (vrlg.CMPRS_CBIT_BAYER - vrlg.CMPRS_CBIT_BAYER_BITS)
if not focus_mode is None:
data |= (1 << vrlg.CMPRS_CBIT_FOCUS_BITS)
data |= (1 << vrlg.CMPRS_CBIT_FOCUS)
data |= (focus_mode & ((1 << vrlg.CMPRS_CBIT_FOCUS_BITS) - 1)) << (vrlg.CMPRS_CBIT_FOCUS - vrlg.CMPRS_CBIT_FOCUS_BITS)
return data
......@@ -324,17 +324,17 @@ class X393Cmprs(object):
self.x393_axi_tasks.write_control_register(
base_addr + vrlg.MCNTRL_TILED_MODE,
mode);
def compressor_run(self, # may use compressor_control with the same arguments
num_sensor,
run_mode):
"""
Compressor reset.run/single (alias of compressor_control)
@param num_sensor - sensor port number (0..3)
@param run_mode - 0 - reset, 2 - run single from memory, 3 - run repetitive
"""
self.compressor_control(
num_sensor = num_sensor, # sensor channel number (0..3)
run_mode = run_mode) #0 - reset, 2 - run single from memory, 3 - run repetitive
# def compressor_run(self, # may use compressor_control with the same arguments
# num_sensor,
# run_mode):
# """
# Compressor reset.run/single (alias of compressor_control)
# @param num_sensor - sensor port number (0..3)
# @param run_mode - 0 - reset, 2 - run single from memory, 3 - run repetitive
# """
# self.compressor_control(
# num_sensor = num_sensor, # sensor channel number (0..3)
# run_mode = run_mode) #0 - reset, 2 - run single from memory, 3 - run repetitive
def setup_compressor_channel (self,
num_sensor,
......
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