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Commit 7a0b9347 authored by Andrey Filippov's avatar Andrey Filippov
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testing hardware, adding related code

parent e6bc87ee
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Showing with 585 additions and 243 deletions
.project
View file @ 7a0b9347
......@@ -107,7 +107,7 @@
<link>
<name>vivado_logs/VivadoTimingReportImplemented.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150314001725869.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150316202414190.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
......
.settings/com.elphel.vdt.VivadoTimingReportImplemented.prefs 0 → 100644
View file @ 7a0b9347
com.elphel.store.context.VivadoTimingReportImplemented=VivadoTimingReportImplemented_132_rawfile<-@\#\#@->
eclipse.preferences.version=1
includes/x393_tasks01.vh
View file @ 7a0b9347
......@@ -81,6 +81,9 @@
input [29:0] address;
input [31:0] data;
begin
`ifdef DEBUG_WR_SINGLE
$display("axi_write_single_w %h:%h @ %t",address,data,$time);
`endif
axi_write_single ({address,2'b0},data);
end
endtask
......@@ -89,9 +92,6 @@
input [31:0] address;
input [31:0] data;
begin
`ifdef DEBUG_WR_SINGLE
$display("axi_write_single %h:%h @ %t",address,data,$time);
`endif
axi_write_addr_data(
GLOBAL_WRITE_ID, // id
// address << 2, // addr
......
py393/test_mcntrl.py
View file @ 7a0b9347
......@@ -170,6 +170,7 @@ USAGE
''' % (program_shortdesc, __author__,str(__date__))
preDefines={}
preParameters={}
showResult=False
try:
# Setup argument parser
parser = ArgumentParser(description=program_license, formatter_class=RawDescriptionHelpFormatter,fromfile_prefix_chars='@')
......@@ -353,6 +354,9 @@ USAGE
line =""
while True:
line=raw_input('x393%s--> '%('','(simulated)')[args.simulated]).strip()
#remove comment from the input line
if line.find("#") > 0:
line=line[:line.find("#")]
lineList=line.split()
if not line:
print ('Use "quit" to exit, "help" - for help')
......@@ -365,7 +369,18 @@ USAGE
print ("Usage: %s %s"%(name,sFuncArgs))
print ('\n"parameters" and "defines" list known defined parameters and macros')
print ("args.exception=%d, QUIET=%d"%(args.exceptions,QUIET))
print ("Enter 'R' to toggle show/hide command results, now it is %s"%(("OFF","ON")[showResult]))
elif lineList[0].upper() == 'R':
if len(lineList)>1:
if (lineList[1].upper() == "ON") or (lineList[1].upper() == "1") or (lineList[1].upper() == "TRUE"):
showResult=True
elif (lineList[1].upper() == "OFF") or (lineList[1].upper() == "0") or (lineList[1].upper() == "FALSE"):
showResult=False
else:
print ("Unrecognized parameter %s for 'R' command"%lineList[1])
else:
showResult = not showResult
print ("Show results mode is now %s"%(("OFF","ON")[showResult]))
# elif (len(line) > len("help")) and (line[:len("help")]=='help'):
elif lineList[0] == 'help':
# helpFilter=line[len('help'):].strip()
......@@ -431,6 +446,7 @@ USAGE
else:
cmdLine=line.split()
rslt= execTask(cmdLine)
if showResult:
print (' Result: '+hx(rslt))
#http://stackoverflow.com/questions/11781265/python-using-getattr-to-call-function-with-variable-parameters
#*getattr(foo,bar)(*params)
......
py393/verilog_utils.py
View file @ 7a0b9347
......@@ -127,9 +127,9 @@ def hexMultiple(data):
subResult=[]
for subItem in item:
try:
rslt.append("0x%x"%subItem)
subResult.append("0x%x"%subItem)
except:
rslt.append(str(subItem))
subResult.append(str(subItem))
rslt.append(subResult)
else:
try:
......@@ -144,3 +144,29 @@ def hexMultiple(data):
rslt = str(item)
return rslt
def checkIntArgs(names,var_dict):
for name in names:
try:
v=var_dict[name]
except:
raise Exception("ERROR: '%s' is not among %s"%(name,str(var_dict.keys())))
if not isinstance(v,int):
print ("Expected an integer for '%s', got '%s"%(name,v))
try:
d=int(v,16)
print ("Did you mean 0x%x ?"%d)
except:
pass
raise Exception("Not a number for '%s' : '%s'"%(name,v))
def smooth2d(arr2d):
smooth=[]
l=len(arr2d)-1
for i in range(l+1):
im=(0,i-1)[i>0]
ip=(l,i+1)[i<l]
row=[]
for j in range(len(arr2d[i])):
row.append(0.5*arr2d[i][j]+0.25*(arr2d[ip][j]+arr2d[im][j]))
smooth.append(row)
return smooth
\ No newline at end of file
py393/x393_mcntrl_adjust.py
View file @ 7a0b9347
This diff is collapsed.
py393/x393_mcntrl_buffers.py
View file @ 7a0b9347
......@@ -90,16 +90,21 @@ class X393McntrlBuffers(object):
<start_word_address> full register address in AXI space (in 32-bit words, not bytes)
<num_words_or_data_list> number of 32-bit words to generate/write or a list with integer data
"""
xor=0
if (isinstance (num_words_or_data_list,list) or isinstance (num_words_or_data_list,tuple)) and (len(num_words_or_data_list) == 2):
xor=num_words_or_data_list[1]
num_words_or_data_list=num_words_or_data_list[0]
if isinstance (num_words_or_data_list,int):
data=[]
for i in range(num_words_or_data_list):
data.append(i | (((i + 7) & 0xff) << 8) | (((i + 23) & 0xff) << 16) | (((i + 31) & 0xff) << 24))
data.append(xor ^(i | (((i + 7) & 0xff) << 8) | (((i + 23) & 0xff) << 16) | (((i + 31) & 0xff) << 24)))
else:
data=num_words_or_data_list
if self.verbose>0:
print("**** write_block_buf, start_word_address=0x%x, num+words=0x%x"%(start_word_address,len(data)))
for i,d in enumerate(data):
d= i | (((i + 7) & 0xff) << 8) | (((i + 23) & 0xff) << 16) | (((i + 31) & 0xff) << 24)
# d= i | (((i + 7) & 0xff) << 8) | (((i + 23) & 0xff) << 16) | (((i + 31) & 0xff) << 24)
if self.verbose>2:
print(" write_block_buf 0x%x:0x%x"%(start_word_address+i,d))
self.x393_mem.axi_write_single_w(start_word_address+i, d)
......@@ -131,6 +136,13 @@ class X393McntrlBuffers(object):
<page> 2-bit buffer page to write to
<num_words_or_data_list> number of 32-bit words to generate/write or a list with integer data
"""
print("===write_block_buf_chn() chn=0x%x, page=0x%x"%(chn,page), end=" ")
if isinstance (num_words_or_data_list,list):
try:
print("=== [0x%x,0x%x,0x%x,0x%x,0x%x,0x%x,0x%x,0x%x,...]"%tuple(num_words_or_data_list[:8]),end="")
except:
print("=== [%s]"%str(num_words_or_data_list))
print("===")
start_addr=-1
if chn==0:start_addr=self.MCONTR_BUF0_WR_ADDR + (page << 8)
elif chn==1:start_addr=self.MCONTR_BUF1_WR_ADDR + (page << 8)
......@@ -140,6 +152,7 @@ class X393McntrlBuffers(object):
else:
print("**** ERROR: Invalid channel for write buffer = %d"% chn)
start_addr = self.MCONTR_BUF0_WR_ADDR+ (page << 8)
self.write_block_buf (start_addr, num_words_or_data_list)
def read_block_buf(self,
......@@ -153,7 +166,7 @@ class X393McntrlBuffers(object):
<show_rslt> print buffer data read
"""
if self.verbose>0:
if (self.verbose>1) or show_rslt:
print("**** read_block_buf, start_word_address=0x%x, num_read=0x%x "%(start_word_address,num_read))
result=[]
for i in range(num_read): #for (i = 0; i < num_read; i = i + 16) begin
......
py393/x393_mcntrl_tests.py
View file @ 7a0b9347
......@@ -37,6 +37,7 @@ from x393_axi_control_status import X393AxiControlStatus
from x393_pio_sequences import X393PIOSequences
from x393_mcntrl_timing import X393McntrlTiming
from x393_mcntrl_buffers import X393McntrlBuffers
from x393_mcntrl_adjust import X393McntrlAdjust
#from verilog_utils import * # concat, bits
#from verilog_utils import hx, concat, bits, getParWidth
from verilog_utils import concat #, getParWidth
......@@ -59,6 +60,7 @@ class X393McntrlTests(object):
self.x393_pio_sequences= X393PIOSequences(debug_mode,dry_mode)
self.x393_mcntrl_timing= X393McntrlTiming(debug_mode,dry_mode)
self.x393_mcntrl_buffers= X393McntrlBuffers(debug_mode,dry_mode)
self.x393_mcntrl_adjust= X393McntrlAdjust(debug_mode,dry_mode)
self.__dict__.update(VerilogParameters.__dict__["_VerilogParameters__shared_state"]) # Add verilog parameters to the class namespace
try:
self.verbose=self.VERBOSE
......@@ -245,11 +247,11 @@ class X393McntrlTests(object):
norm_dqs_odly=self.DLY_DQS_ODELAY
# Set special values for DQS idelay for write leveling
self.x393_pio_sequences.wait_ps_pio_done(self.DEFAULT_STATUS_MODE,1); # not no interrupt running cycle - delays are changed immediately
self.x393_mcntrl_timing.axi_set_dqs_idelay_wlv()
## self.x393_mcntrl_timing.axi_set_dqs_idelay_wlv()
# Set write buffer (from DDR3) WE signal delay for write leveling mode
self.x393_mcntrl_timing.axi_set_wbuf_delay(self.WBUF_DLY_WLV)
## self.x393_mcntrl_timing.axi_set_wbuf_delay(self.WBUF_DLY_WLV)
# TODO: Set configurable delay time instead of #80
self.x393_mcntrl_timing.axi_set_dqs_odelay(wlev_dqs_dly) # 'h80); # 'h80 - inverted, 'h60 - not - 'h80 will cause warnings during simulation
## self.x393_mcntrl_timing.axi_set_dqs_odelay(wlev_dqs_dly) # 'h80); # 'h80 - inverted, 'h60 - not - 'h80 will cause warnings during simulation
self.x393_pio_sequences.schedule_ps_pio (# schedule software-control memory operation (may need to check FIFO status first)
self.WRITELEV_OFFSET, # input [9:0] seq_addr; # sequence start address
0, # input [1:0] page; # buffer page number
......@@ -265,9 +267,9 @@ class X393McntrlTests(object):
rslt[i & 1]+=(buf[i] & 1) + ((buf[i] >> 8) & 1) + ((buf[i] >> 16) & 1) + ((buf[i] >> 24) & 1)
for i in range(2):
rslt[i]/=2*numBufWords
self.x393_mcntrl_timing.axi_set_dqs_idelay_nominal()
self.x393_mcntrl_timing.axi_set_dqs_odelay(norm_dqs_odly) # 'h78);
self.x393_mcntrl_timing.axi_set_wbuf_delay(self.WBUF_DLY_DFLT); #DFLT_WBUF_DELAY
## self.x393_mcntrl_timing.axi_set_dqs_idelay_nominal()
## self.x393_mcntrl_timing.axi_set_dqs_odelay(norm_dqs_odly) # 'h78);
## self.x393_mcntrl_timing.axi_set_wbuf_delay(self.WBUF_DLY_DFLT); #DFLT_WBUF_DELAY
return rslt
def test_read_pattern(self,
......@@ -290,11 +292,19 @@ class X393McntrlTests(object):
1, # show_rslt,
wait_complete) # # Wait for operation to complete
def test_write_block(self,
wait_complete): # Wait for operation to complete
dq_odelay=None,
dqs_odelay=None,
wait_complete=1): # Wait for operation to complete
"""
Test write block in PS PIO mode
<dq_odelay> set DQ output delays if provided ([] - skip, single number - both lanes, 2 element list - per/lane)
<dqs odelay> set DQS output delays if provided ([] - skip, single number - both lanes, 2 element list - per/lane)
<wait_complete> wait write block operation to complete (0 - may initiate multiple PS PIO operations)
"""
if (not dq_odelay is None) and (dq_odelay != []):
self.x393_mcntrl_timing.axi_set_dq_odelay(dq_odelay)
if (not dqs_odelay is None) and (dqs_odelay != []):
self.x393_mcntrl_timing.axi_set_dqs_odelay(dqs_odelay)
return self.x393_pio_sequences.write_block(wait_complete) # Wait for operation to complete
def test_read_block(self,
......@@ -312,10 +322,51 @@ class X393McntrlTests(object):
self.x393_mcntrl_timing.axi_set_dq_idelay(dq_idelay)
if (not dqs_idelay is None) and (dqs_idelay != []):
self.x393_mcntrl_timing.axi_set_dqs_idelay(dqs_idelay)
return self.x393_pio_sequences.read_block(self,
rd_buf = self.x393_pio_sequences.read_block(
256, # num,
1, # show_rslt,
0, # show_rslt,
wait_complete) # Wait for operation to complete
sum_rd_buf=0
for d in rd_buf:
sum_rd_buf+=d
print("read buffer: (0x%x):"%sum_rd_buf)
for i in range(len(rd_buf)):
if (i & 0xf) == 0:
print("\n%03x:"%i,end=" ")
print("%08x"%rd_buf[i],end=" ")
print("\n")
return rd_buf
def test_read_block16(self,
dq_idelay=None,
dqs_idelay=None,
wait_complete=1): # Wait for operation to complete
"""
Test read block in PS PIO mode, convert data to match DDR3 16-bit output words
<dq_idelay> set DQ input delays if provided ([] - skip, single number - both lanes, 2 element list - per/lane)
<dqs_idelay> set DQS input delays if provided ([] - skip, single number - both lanes, 2 element list - per/lane)
<wait_complete> wait read block operation to complete (0 - may initiate multiple PS PIO operations)
returns list of the read data
"""
if (not dq_idelay is None) and (dq_idelay != []):
self.x393_mcntrl_timing.axi_set_dq_idelay(dq_idelay)
if (not dqs_idelay is None) and (dqs_idelay != []):
self.x393_mcntrl_timing.axi_set_dqs_idelay(dqs_idelay)
rd_buf = self.x393_pio_sequences.read_block(
256, # num,
0, # show_rslt,
wait_complete) # Wait for operation to complete
read16=self.x393_mcntrl_adjust.convert_w32_to_mem16(rd_buf) # 512x16 bit, same as DDR3 DQ over time
sum_read16=0
for d in read16:
sum_read16+=d
print("read16 (0x%x):"%sum_read16)
for i in range(len(read16)):
if (i & 0x1f) == 0:
print("\n%03x:"%i,end=" ")
print("%04x"%read16[i],end=" ")
print("\n")
return read16
def test_scanline_write(self, #
channel, # input [3:0] channel;
......
py393/x393_mcntrl_timing.py
View file @ 7a0b9347
......@@ -177,6 +177,8 @@ class X393McntrlTiming(object):
<delay> 8-bit (5+3) delay value to use or a tuple/list with a pair for (lane0, lane1)
Each of the two elements in the delay tuple/list may be a a common integer or a list/tuple itself
"""
# print("====axi_set_dq_idelay %s"%str(delay))
if delay is None: return # Do nothing, that's OK
if isinstance(delay,int):
delay=(delay,delay)
......@@ -321,6 +323,7 @@ class X393McntrlTiming(object):
<delay> 8-bit (5+3) delay value to use or list/tuple containing individual values
List elements may be None, those values will not be overwritten
"""
# print ("===axi_set_multiple_delays(0x%x,%d,%s"%(reg_addr,number,delay))
if delay is None: return # Do nothing, that's OK
if isinstance(delay,int):
delay=(delay,)*number
......@@ -349,29 +352,81 @@ class X393McntrlTiming(object):
print("SET WBUF DELAY=0x%x"%delay)
self.x393_axi_tasks.write_contol_register(self.MCONTR_PHY_16BIT_ADDR+self.MCONTR_PHY_16BIT_WBUF_DELAY, delay & 0xf) # {28'h0, delay});
#set dq /dqs tristate on/off patterns
def axi_set_tristate_patterns(self):
def axi_set_tristate_patterns(self,
strPattern=None):
"""
Set sequencer patterns for the tristate ON/OFF (defined by parameters)
"""
# may fail if some of the parameters used have undefined width
print("DQTRI_FIRST=%s, DQTRI_FIRST__TYPE=%s"%(str(self.DQTRI_FIRST),str(self.DQTRI_FIRST__TYPE)))
print("DQTRI_LAST=%s, DQTRI_LAST__TYPE=%s"%(str(self.DQTRI_LAST),str(self.DQTRI_LAST__TYPE)))
<strPattern> - optional up to 4-letter pattern. Each letter is one of 3:
'E'- early, "N" - nominal and 'L' - late, first for DQ start,
second - for DQS start, then DQ end and DQS end. If no pattern
is provided, all will be set to Verilog parameter values (DQ*TRI_*),
if only 1 - it will be applied to all, if 2 - it will be
repeated twice, 3 will use the same value for DQS end as for DQS start
"""
modes={'E':0,'N':1,'L':2}
evNames=('DQ_FIRST', 'DQS_FIRST', 'DQ_LAST','DQS_LAST')
patVals={evNames[0]: (0x3,0x7,0xf), # DQ_FIRST: early, nominal, late
evNames[1]: (0x1,0x3,0x7), # DQS_FIRST: early, nominal, late
evNames[2]: (0xf,0xe,0xc), # DQ_LAST: early, nominal, late
evNames[3]: (0xe,0xc,0x8)} # DQS_LAST: early, nominal, late
if not strPattern:
delays=concat(((0,16), # {16'h0,
(self.DQSTRI_LAST, getParWidth(self.DQSTRI_LAST__TYPE)), # DQSTRI_LAST,
(self.DQSTRI_FIRST,getParWidth(self.DQSTRI_FIRST__TYPE)), # DQSTRI_FIRST,
(self.DQTRI_LAST, getParWidth(self.DQTRI_LAST__TYPE)), # DQTRI_LAST,
(self.DQTRI_FIRST, getParWidth(self.DQTRI_FIRST__TYPE))) # DQTRI_FIRST});
)[0]
else:
strPattern=strPattern.upper()
if len(strPattern) == 1:
strPattern*=4
elif len(strPattern) == 2:
strPattern*=2
elif len(strPattern) == 3:
strPattern+=strPattern[1]
strPattern=strPattern[:4]
vals={}
for i,n in enumerate(evNames):
try:
vals[n]=patVals[n][modes[strPattern[i]]]
except:
msg="axi_set_tristate_patterns(%s): Failed to determine delay mode for %s, got %s"%(strPattern,n,strPattern[i])
print (msg)
Exception(msg)
print ("axi_set_tristate_patterns(%s) : %s"%(strPattern,str(vals)))
delays=concat(((0,16), # {16'h0,
(vals['DQS_LAST'],4), # self.DQSTRI_LAST, getParWidth(self.DQSTRI_LAST__TYPE)), # DQSTRI_LAST,
(vals['DQS_FIRST'],4), # self.DQSTRI_FIRST,getParWidth(self.DQSTRI_FIRST__TYPE)), # DQSTRI_FIRST,
(vals['DQ_LAST'],4), # self.DQTRI_LAST, getParWidth(self.DQTRI_LAST__TYPE)), # DQTRI_LAST,
(vals['DQ_FIRST'],4)) # self.DQTRI_FIRST, getParWidth(self.DQTRI_FIRST__TYPE))) # DQTRI_FIRST});
)[0]
# may fail if some of the parameters used have undefined width
print("DQTRI_FIRST=%s, DQTRI_FIRST__TYPE=%s"%(str(self.DQTRI_FIRST),str(self.DQTRI_FIRST__TYPE)))
print("DQTRI_LAST=%s, DQTRI_LAST__TYPE=%s"%(str(self.DQTRI_LAST),str(self.DQTRI_LAST__TYPE)))
# delays=concat(((0,16), # {16'h0,
# (self.DQSTRI_LAST, getParWidth(self.DQSTRI_LAST__TYPE)), # DQSTRI_LAST,
# (self.DQSTRI_FIRST,getParWidth(self.DQSTRI_FIRST__TYPE)), # DQSTRI_FIRST,
# (self.DQTRI_LAST, getParWidth(self.DQTRI_LAST__TYPE)), # DQTRI_LAST,
# (self.DQTRI_FIRST, getParWidth(self.DQTRI_FIRST__TYPE))) # DQTRI_FIRST});
# )[0]
if self.DEBUG_MODE > 1:
print("SET TRISTATE PATTERNS, combined delays=%s"%str(delays))
print("SET TRISTATE PATTERNS, combined delays=0x%x"%delays)
self.x393_axi_tasks.write_contol_register(self.MCONTR_PHY_16BIT_ADDR +self.MCONTR_PHY_16BIT_PATTERNS_TRI, delays) # DQSTRI_LAST, DQSTRI_FIRST, DQTRI_LAST, DQTRI_FIRST});
def axi_set_dqs_dqm_patterns(self):
def axi_set_dqs_dqm_patterns(self,
patt=None):
"""
Set sequencer patterns for the DQ lines ON/OFF (defined by parameters)
<patt> DQS toggle pattern (if None - use MCONTR_PHY_16BIT_PATTERNS (currently 0x55)
"""
if patt is None:
patt=self.MCONTR_PHY_16BIT_PATTERNS
if self.DEBUG_MODE > 1:
print("SET DQS+DQM PATTERNS")
print("SET DQS+DQM PATTERNS, patt= 0x%x"%patt)
# set patterns for DM (always 0) and DQS - always the same (may try different for write lev.)
self.x393_axi_tasks.write_contol_register(self.MCONTR_PHY_16BIT_ADDR + self.MCONTR_PHY_16BIT_PATTERNS, 0x55) # 32'h0055);
self.x393_axi_tasks.write_contol_register(self.MCONTR_PHY_16BIT_ADDR + self.MCONTR_PHY_16BIT_PATTERNS, patt) # 32'h0055);
py393/x393_mem.py
View file @ 7a0b9347
......@@ -150,12 +150,15 @@ class X393Mem(object):
'''
Read/write slave AXI using 32-bit word addresses (same as in Verilog code)
'''
def axi_write_single_w(self,addr,data):
def axi_write_single_w(self,addr,data,verbose=0):
"""
Write 32-bit word to the slave AXI address range, using 32-word address
<addr> - 32-bit word (register) address relative to the slave AXI memory region
<data> - 32-bit data to write
<verbose> print data being written (default: 0)
"""
if verbose:
print("axi_write_single_w(0x%x,0x%08x)"%(addr,data))
self.axi_write_single(addr<<2,data)
def axi_read_addr_w(self,addr):
......
py393/x393_pio_sequences.py
View file @ 7a0b9347
This diff is collapsed.
x393_testbench01.sav
View file @ 7a0b9347
[*]
[*] GTKWave Analyzer v3.3.64 (w)1999-2014 BSI
[*] Sat Mar 14 20:12:55 2015
[*] Tue Mar 17 07:18:15 2015
[*]
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench01-20150314012414854.lxt"
[dumpfile_mtime] "Sat Mar 14 07:40:45 2015"
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench01-20150316202414190.lxt"
[dumpfile_mtime] "Tue Mar 17 02:39:38 2015"
[dumpfile_size] 982556355
[savefile] "/home/andrey/git/x393/x393_testbench01.sav"
[timestart] 45034520
[timestart] 47475610
[size] 1823 1180
[pos] 2062 0
*-12.698502 45069640 157271875 157546875 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-11.698502 47485628 157271875 157546875 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_testbench01.
[treeopen] x393_testbench01.x393_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.
......@@ -37,12 +37,15 @@
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.status_router2_top_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_test01_i.
[treeopen] x393_testbench01.x393_i.mcntrl393_test01_i.status_router4_i.
[sst_width] 423
[signals_width] 462
[sst_width] 264
[signals_width] 310
[sst_expanded] 1
[sst_vpaned_height] 631
@800200
......@@ -254,12 +257,47 @@ x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.clk_div[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.mclk[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.iclk[0]
@29
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.iclk[0]
@1000200
-mem_clocks
@200
@800200
-write_delays
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.din[31:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.din_dqs[3:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.ndqs[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq[7:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.din[3:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.din[3:0]
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.d_ser[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.d_ser[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dq_data_dly[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.d_ser[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.dqs_data_dly[0]
@1000200
-write_delays
@800200
-read_delays
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.dqs_di[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.dqs_received_dly[0]
@201
-
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.iclk[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.clk[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.clk_div[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dq[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dq_dly[0]
@22
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[0].dq_i.dout[3:0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq_block[1].dq_i.dout[3:0]
@1000200
-read_delays
@c00200
-axi
@28
......@@ -934,7 +972,7 @@ x393_testbench01.x393_i.axibram_read_i.bram_ren[0]
-
@1401200
-axibram_read
@800200
@c00200
-refresh
@28
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.run_busy[0]
......@@ -961,7 +999,7 @@ x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.refresh_period[7:0
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.rst[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.set[0]
x393_testbench01.x393_i.mcntrl393_i.memctrl16_i.ddr_refresh_i.want[0]
@1000200
@1401200
-refresh
@800200
-DDR3
......
x393_testbench01.tf
View file @ 7a0b9347
......@@ -27,7 +27,7 @@
`define SET_PER_PIN_DELAYS 1 // set individual (including per-DQ pin delays)
`define PS_PIO_WAIT_COMPLETE 0 // wait until PS PIO module finished transaction before starting a new one
// Disabled already passed test to speedup simulation
//`define TEST_WRITE_LEVELLING 1
`define TEST_WRITE_LEVELLING 1
`define TEST_READ_PATTERN 1
`define TEST_WRITE_BLOCK 1
`define TEST_READ_BLOCK 1
......
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