debugging JP4 mode, got correct JP4 image

.project

@@ -62,42 +62,42 @@
 		<link>
 			<name>vivado_logs/VivadoBitstream.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151111121710210.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151115001220264.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoOpt.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151111121710210.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151115001220264.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoOptPhys.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151111121710210.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151115001220264.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoOptPower.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151111121710210.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151115001220264.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoPlace.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151111121710210.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151115001220264.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoRoute.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151111121710210.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151115001220264.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoSynthesis.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151111121710210.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151115000630414.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151111121710210.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151115001220264.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>

axi/membridge.v

@@ -749,6 +749,7 @@ wire [63:0] afi_wdata0;
         .ext_rd       (bufrd_rd[0]),                    // input
         .ext_regen    (bufrd_rd[1]),                    // input
         .ext_data_out (afi_wdata0),                     // output[63:0]
+//        .emul64       (1'b0),                           // input Modify buffer addresses (used for JP4 until a 64-wide mode is implemented)
         .wclk         (!mclk),                          // input
         .wpage_in     (2'b0),                           // input[1:0] 
         .wpage_set    (xfer_reset_page_rd),             // input  TODO: Generate @ negedge mclk on frame start

compressor_jp/cmprs_pixel_buf_iface.v

@@ -67,9 +67,11 @@ module  cmprs_pixel_buf_iface #(
                                       // controller this can just be the same as mb_pre_end_in        
     input             mb_pre_start,       // 1 clock cycle before stream of addresses to the buffer
     input      [ 1:0] start_page,         // page to read next tile from (or first of several pages)
-    input      [ 6:0] macroblock_x,       // macroblock left pixel x relative to a tile (page) Maximal page - 128 bytes wide
+    input      [ 6:0] macroblock_x,       // macroblock left pixel x relative to a tile (page) Maximal page - 128 bytes wide.
+                                          //  valid 3 cycles before mb_pre_start
     output reg [ 7:0] data_out,           //
     output            pre_first_out,      // For each macroblock in a frame
+    output            pre2_first_out,     // 1 cycle before pre_first_out
     output reg        data_valid          //
 );
     localparam PERIOD_COLOR18 = 384; // >18*18, limited by 6*64 (macroblocks)
@@ -105,8 +107,13 @@ module  cmprs_pixel_buf_iface #(
     reg    [ 8:0] period_cntr;
     reg           mb_pre_end_r;
     reg           mb_release_buf_r;
-    reg           pre_first_out_r;
+    reg [CMPRS_BUF_EXTRA_LATENCY+2:0]  pre_first_out_r;
     
+    reg    [ 2:0] mb_col_number; // number of tile column where macrobloc starts - valid 2 cycles before mb_pre_start
+    wire   [ 9:0] extra_start_addr_w = mb_col_number * mb_h_m1; //added to mb_start_addr when non-zero column
+    reg    [ 5:0] extra_start_addr_r;
+//    reg    [ 5:0] mb_h;          // macroblock height (lost MSB - OK)
+    reg    [ 9:0] mb_start_addr; // was macroblock_x, noccrected for multi-column. valid with mb_pre_start
          
     assign buf_ra = bufa_r;
     assign tile_width_or=      tile_width[1]?(tile_width[0]?0:'h40):(tile_width[0]?'h60:'h70);
@@ -119,21 +126,31 @@ module  cmprs_pixel_buf_iface #(
     assign mb_release_buf =    mb_release_buf_r;
     assign buf_rd =            buf_re[1:0];
 //    assign data_out =          do_r;
-    assign pre_first_out =     pre_first_out_r;
+    assign pre_first_out =     pre_first_out_r[0];
+    assign pre2_first_out =    pre_first_out_r[1];
 
     always @(posedge xclk) begin
+//        mb_h <= mb_h_m1+1;     // macroblock height
+        mb_col_number <= {macroblock_x[6:5],tile_col_width?1'b0:macroblock_x[4]};
+        extra_start_addr_r <= extra_start_addr_w[5:0];
+        mb_start_addr <= {3'b0,macroblock_x} + {extra_start_addr_r,4'b0};
+    
         if      (!frame_en)     buf_re[0] <= 0;
         else if (mb_pre_start)  buf_re[0] <= 1'b1;
         else if (addr_run_end)  buf_re[0] <= 1'b0;
         
         if      (!frame_en)     buf_re[CMPRS_BUF_EXTRA_LATENCY+3:1] <= 0;
-        else                    buf_re[CMPRS_BUF_EXTRA_LATENCY+3:1] <= {buf_re[CMPRS_BUF_EXTRA_LATENCY+2:0]};
+        else                    buf_re[CMPRS_BUF_EXTRA_LATENCY+3:1] <= {buf_re[CMPRS_BUF_EXTRA_LATENCY + 2:0]};
 
         // Buffer data read:
         if (buf_re[CMPRS_BUF_EXTRA_LATENCY+2]) data_out <= buf_di;
-        
+//mb_pre_start        
         if (!frame_en) pre_first_out_r <= 0;
-        else pre_first_out_r <= buf_re[CMPRS_BUF_EXTRA_LATENCY+1] && ! buf_re[CMPRS_BUF_EXTRA_LATENCY+2];
+        else           pre_first_out_r <= {mb_pre_start, pre_first_out_r[CMPRS_BUF_EXTRA_LATENCY + 2 : 1]}; 
+//        else pre_first_out_r <= buf_re[CMPRS_BUF_EXTRA_LATENCY+1] && ! buf_re[CMPRS_BUF_EXTRA_LATENCY+2];
+        
+//        if (!frame_en) pre2_first_out <= 0;
+//        else           pre2_first_out <= buf_re[CMPRS_BUF_EXTRA_LATENCY + 0] && ! buf_re[CMPRS_BUF_EXTRA_LATENCY + 1];
 
         if      (mb_pre_start) rows_left <= mb_h_m1;
         else if (last_col)     rows_left <= rows_left - 1;
@@ -153,7 +170,8 @@ module  cmprs_pixel_buf_iface #(
 
         first_col <= (mb_pre_start || (last_col && !last_row));
         
-        if   (mb_pre_start) row_sa <= {start_page,3'b0,macroblock_x};
+//        if   (mb_pre_start) row_sa <= {start_page,3'b0,mb_start_addr}; // macroblock_x};
+        if   (mb_pre_start) row_sa <= {start_page,mb_start_addr}; // macroblock_x};
         else if (first_col) row_sa <= row_sa + (tile_col_width ? 12'h20:12'h10);
 
         if  (mb_pre_start) tile_sa <= 0;
@@ -172,7 +190,8 @@ module  cmprs_pixel_buf_iface #(
         else if (last_in_tile)          bufa_r[11:10] <= bufa_r[11:10] + 1;
         
         // Most time critical - calculation of the buffer address
-        if  (mb_pre_start)              bufa_r[9:0] <= {3'b0,macroblock_x};
+//        if  (mb_pre_start)              bufa_r[9:0] <= {3'b0,mb_start_addr}; // macroblock_x};
+        if  (mb_pre_start)              bufa_r[9:0] <= {mb_start_addr}; // macroblock_x};
         else if (last_col)              bufa_r[9:0] <= row_sa[9:0]; // 'bx next cycle after AFTER mb_pre_start
         else if (last_in_tile)          bufa_r[9:0] <= tile_sa;
         else if (buf_re[0])             bufa_r[9:0] <= bufa_r[9:0] + {last_in_col?col_inc[9:4]:6'b0,4'b1};  

compressor_jp/csconvert.v

@@ -55,7 +55,7 @@ module  csconvert#(
          input      [ 9:0] m_cr,         // [9:0] scale for CB - default 0.713 (10'hb6)
          input      [ 7:0] mb_din,       // input bayer data in scanline sequence, GR/BG sequence
          input      [ 1:0] bayer_phase,
-         input             pre_first_in, // marks the first input pixel
+         input             pre2_first_in, // marks the first input pixel (2 cycles ahead)
          
          output reg [ 8:0] signed_y,     //  - now signed char, -128(black) to +127 (white)
          output reg [ 8:0] signed_c,            // new, q is just signed char
@@ -69,7 +69,7 @@ module  csconvert#(
 //         output reg        ccv_out_start,     //TODO: adjust to minimal latency?
          output reg [ 7:0] n000, // not clear how they are used, make them just with latency1 from old
          output reg [ 7:0] n255);
-
+    reg            pre_first_in;
     // outputs to be multiplexed:
     wire   [7:0]   conv18_signed_y, conv20_signed_y, mono16_signed_y, jp4_signed_y;
     wire   [8:0]   jp4diff_signed_y, conv18_signed_c, conv20_signed_c;
@@ -100,7 +100,8 @@ module  csconvert#(
     reg [5:0]  component_firstsS; // first_r this component in a frame (DC absolute, otherwise - difference to previous)
 */
     always @ (posedge xclk) begin
-        if (pre_first_in) begin
+        pre_first_in <= pre2_first_in;
+        if (pre2_first_in) begin
             converter_type_r [2:0] <= converter_type[2:0];
             ignore_color_r         <= ignore_color;
 //            jp4_dc_improved_r      <= jp4_dc_improved;
@@ -117,22 +118,22 @@ module  csconvert#(
     
         // generate one-hot converter enable  
         if      (!frame_en)      en_converters[CMPRS_COLOR18] <= 0;
-        else if (pre_first_in)  en_converters[CMPRS_COLOR18] <= converter_type == CMPRS_COLOR18;
+        else if (pre2_first_in)  en_converters[CMPRS_COLOR18] <= converter_type == CMPRS_COLOR18;
         
         if       (!frame_en)     en_converters[CMPRS_COLOR20] <= 0;
-        else  if (pre_first_in) en_converters[CMPRS_COLOR20] <= converter_type == CMPRS_COLOR20;
+        else  if (pre2_first_in) en_converters[CMPRS_COLOR20] <= converter_type == CMPRS_COLOR20;
         
         if      (!frame_en)      en_converters[CMPRS_MONO16] <=  0;
-        else if (pre_first_in)  en_converters[CMPRS_MONO16] <=  converter_type == CMPRS_MONO16;
+        else if (pre2_first_in)  en_converters[CMPRS_MONO16] <=  converter_type == CMPRS_MONO16;
         
         if      (!frame_en)      en_converters[CMPRS_JP4] <=     0;
-        else if (pre_first_in)  en_converters[CMPRS_JP4] <=     converter_type == CMPRS_JP4;
+        else if (pre2_first_in)  en_converters[CMPRS_JP4] <=     converter_type == CMPRS_JP4;
         
         if      (!frame_en)      en_converters[CMPRS_JP4DIFF] <= 0;
-        else if (pre_first_in)  en_converters[CMPRS_JP4DIFF] <= converter_type == CMPRS_JP4DIFF;
+        else if (pre2_first_in)  en_converters[CMPRS_JP4DIFF] <= converter_type == CMPRS_JP4DIFF;
         
         if      (!frame_en)      en_converters[CMPRS_MONO8] <=   0;
-        else if (pre_first_in)  en_converters[CMPRS_MONO8] <=   converter_type == CMPRS_MONO8;
+        else if (pre2_first_in)  en_converters[CMPRS_MONO8] <=   converter_type == CMPRS_MONO8;
     end
 
 

compressor_jp/jp_channel.v

@@ -262,6 +262,7 @@ module  jp_channel#(
     // signals connecting modules: chn_rd_buf_i and ???:
     wire   [ 7:0] mb_data_out;       // Macroblock data out in scanline order 
     wire          mb_pre_first_out;  // Macroblock data out strobe - 1 cycle just before data valid
+    wire          mb_pre2_first_out;  // Macroblock data out strobe - 2 cycles just before data valid
 //    wire          mb_data_valid;     // Macroblock data out valid
     
     wire           limit_diff     = 1'b1;  // as in the prototype - just a constant 1
@@ -421,15 +422,15 @@ module  jp_channel#(
     wire [2:0] dbg_block_mem_wa_save;
   `ifndef  USE_XCLK2X
         // temporarily assigning unused debug signals to 0
-        assign dbg_add_invalid =    0;
-        assign dbg_mb_release_buf = 0;
-        assign etrax_dma =          0;
-        assign dbg_ts_rstb =        0; // output
-        assign dbg_ts_dout =        0; //output [7:0]
-        assign dbg_flushing =       0;
-        assign dbg_test_lbw =       0;
-        assign dbg_gotLastBlock =   0;
-        assign dbg_fifo_or_full =   0;
+//        assign dbg_add_invalid =    0;
+//        assign dbg_mb_release_buf = 0;
+//        assign etrax_dma =          0;
+//        assign dbg_ts_rstb =        0; // output
+//        assign dbg_ts_dout =        0; //output [7:0]
+        assign dbg_flushing =       0; // still not used in huffman_stuffer_meta 
+//        assign dbg_test_lbw =       0;
+//        assign dbg_gotLastBlock =   0;
+        assign dbg_fifo_or_full =   0; // still not used in huffman_stuffer_meta
        
   `endif    
     timestamp_to_parallel dbg_timestamp_to_parallel_i (
@@ -612,7 +613,13 @@ module  jp_channel#(
         .start            (status_start)          // input
     );
 //hifreq
-// Port buffer - TODO: Move to memory controller
+// Not needed?
+//    reg   emul64;
+//    always @ (negedge mclk) begin
+//        emul64 <= tile_width[1]; // will not work for monochrome (128 pixel wide) - chnge to 64?
+//    end
+    
+
     mcntrl_buf_rd #(
         .LOG2WIDTH_RD(3) // 64 bit external interface
     ) chn_rd_buf_i (
@@ -621,6 +628,7 @@ module  jp_channel#(
         .ext_rd       (buf_rd[0]),          // input
         .ext_regen    (buf_rd[1]),          // input
         .ext_data_out (buf_pxd),            // output[7:0]
+//        .emul64       (1'b0), //emul64),             // input Modify buffer addresses (used for JP4 until a 64-wide mode is implemented)
         .wclk         (!mclk),              // input
         .wpage_in     (2'b0),               // input[1:0] 
         .wpage_set    (xfer_reset_page_rd), // input  TODO: Generate @ negedge mclk on frame start
@@ -837,7 +845,8 @@ module  jp_channel#(
         .data_out           (mb_data_out),      // output[7:0] // Macroblock data out in scanline order
         .pre_first_out      (mb_pre_first_out), // output // Macroblock data out strobe - 1 cycle just before data valid  == old pre_first_pixel?
 //        .data_valid         (mb_data_valid) // output     // Macroblock data out valid
-        .data_valid         () // output        // Macroblock data out valid Unused
+        .pre2_first_out     (mb_pre2_first_out), // output reg  
+        .data_valid         () // output reg     // Macroblock data out valid Unused
     );
 
     csconvert #(
@@ -859,7 +868,7 @@ module  jp_channel#(
         .m_cr           (m_cr),             // input[9:0] 
         .mb_din         (mb_data_out),      // input[7:0] 
         .bayer_phase    (bayer_phase),      // input[1:0] 
-        .pre_first_in   (mb_pre_first_out), // input
+        .pre2_first_in  (mb_pre2_first_out),// input
         .signed_y       (signed_y),         // output[8:0] reg 
         .signed_c       (signed_c),         // output[8:0] reg 
         .yaddrw         (yaddrw),           // output[7:0] reg 

fpga_version.vh

@@ -31,7 +31,9 @@
  * contains all the components and scripts required to completely simulate it
  * with at least one of the Free Software programs.
  *******************************************************************************/
-    parameter FPGA_VERSION =          32'h0393006e; // Trying lane switch again after bug fix, failing 1 in  ddr3_mclk -> ddr3_clk_div by  -0.023
+    parameter FPGA_VERSION =          32'h0393006f;  // Fixing JP4 mode - xcl -0.002 -0.004 2, utilization 15144 (77.07 %)
+//    parameter FPGA_VERSION =          32'h0393006f; // Fixing JP4 mode - xclk -0.209/-2.744/23, utilization  15127 (76.98%)
+//    parameter FPGA_VERSION =          32'h0393006e; // Trying lane switch again after bug fix, failing 1 in  ddr3_mclk -> ddr3_clk_div by  -0.023
 //    parameter FPGA_VERSION =          32'h0393006d; // -1 with lane switch - does not work
 //    parameter FPGA_VERSION =          32'h0393006d; // Reversing pixels/lanes order xclk violated -0.154
 //    parameter FPGA_VERSION =          32'h0393006c; // will try debug for HiSPi.  xclk violated by -0.030, slices 15062 (76.65%)

includes/x393_simulation_parameters.vh

@@ -59,6 +59,29 @@
     parameter SENSOR_IMAGE_TYPE1 =        "RUN1",
     parameter SENSOR_IMAGE_TYPE2 =        "NORM", // "RUN1",
     parameter SENSOR_IMAGE_TYPE3 =        "RUN1",
+    
+    parameter SIMULATE_CMPRS_CMODE0 =     CMPRS_CBIT_CMODE_JPEG18,
+    parameter SIMULATE_CMPRS_CMODE1 =     CMPRS_CBIT_CMODE_JPEG18,
+    parameter SIMULATE_CMPRS_CMODE2 =     CMPRS_CBIT_CMODE_JP4,
+    parameter SIMULATE_CMPRS_CMODE3 =     CMPRS_CBIT_CMODE_JP4,
+//        CMPRS_CBIT_CMODE_JPEG18, //input [31:0] cmode;   //  [13:9] color mode:
+//        parameter CMPRS_CBIT_CMODE_JPEG18 =   4'h0, // color 4:2:0
+//        parameter CMPRS_CBIT_CMODE_MONO6 =    4'h1, // mono 4:2:0 (6 blocks)
+//        parameter CMPRS_CBIT_CMODE_JP46 =     4'h2, // jp4, 6 blocks, original
+//        parameter CMPRS_CBIT_CMODE_JP46DC =   4'h3, // jp4, 6 blocks, dc -improved
+//        parameter CMPRS_CBIT_CMODE_JPEG20 =   4'h4, // mono, 4 blocks (but still not actual monochrome JPEG as the blocks are scanned in 2x2 macroblocks)
+//        parameter CMPRS_CBIT_CMODE_JP4 =      4'h5, // jp4,  4 blocks, dc-improved
+//        parameter CMPRS_CBIT_CMODE_JP4DC =    4'h6, // jp4,  4 blocks, dc-improved
+//        parameter CMPRS_CBIT_CMODE_JP4DIFF =  4'h7, // jp4,  4 blocks, differential
+//        parameter CMPRS_CBIT_CMODE_JP4DIFFHDR =  4'h8, // jp4,  4 blocks, differential, hdr
+//        parameter CMPRS_CBIT_CMODE_JP4DIFFDIV2 = 4'h9, // jp4,  4 blocks, differential, divide by 2
+//        parameter CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2 = 4'ha, // jp4,  4 blocks, differential, hdr,divide by 2
+//        parameter CMPRS_CBIT_CMODE_MONO1 =    4'hb, // mono JPEG (not yet implemented)
+//        parameter CMPRS_CBIT_CMODE_MONO4 =    4'he, // mono 4 blocks
+
+    
+    
+    
     parameter SENSOR12BITS_NGPL =        8,   // bpf to hact
     parameter SENSOR12BITS_NVLO =        1,   // VACT=0 in video mode (clocks)
     //parameter tMD   =   14;    //

memctrl/mcntrl393.v

@@ -947,6 +947,7 @@ module  mcntrl393 #(
         .ext_rd       (buf2rd_rd), // input
         .ext_regen    (buf2rd_regen), // input
         .ext_data_out (buf2rd_data), // output[31:0] 
+//        .emul64       (1'b0),                           // input Modify buffer addresses (used for JP4 until a 64-wide mode is implemented)
         .wclk         (!mclk), // input
         .wpage_in     (2'b0), // input[1:0] 
         .wpage_set    (xfer_reset_page2_rd), // input  TODO: Generate @ negedge mclk on frame start
@@ -982,6 +983,7 @@ module  mcntrl393 #(
         .ext_rd       (buf3rd_rd), // input
         .ext_regen    (buf3rd_regen), // input
         .ext_data_out (buf3rd_data), // output[31:0] 
+//        .emul64       (1'b0),                // input Modify buffer addresses (used for JP4 until a 64-wide mode is implemented)
         .wclk         (!mclk), // input
         .wpage_in     (2'b0), // input[1:0] 
         .wpage_set    (xfer_reset_page3_rd), // input @ negedge mclk
@@ -1017,6 +1019,7 @@ module  mcntrl393 #(
         .ext_rd       (buf4rd_rd), // input
         .ext_regen    (buf4rd_regen), // input
         .ext_data_out (buf4rd_data), // output[31:0] 
+//        .emul64       (1'b0),                // input Modify buffer addresses (used for JP4 until a 64-wide mode is implemented)
         .wclk         (!mclk), // input
         .wpage_in     (2'b0), // input[1:0] 
         .wpage_set    (xfer_reset_page4_rd), // input  @ negedge mclk

memctrl/mcntrl_buf_rd.v

@@ -43,6 +43,8 @@ module  mcntrl_buf_rd #(
       input                            ext_regen,    // output register enable
       output [(1 << LOG2WIDTH_RD)-1:0] ext_data_out, // data out
       
+//      input                            emul64,       // emulate 64 pixel wide reads with actual 32-wide columns
+                                                     // in the future - use rd64/wr64 for JP4 mode
       input                            wclk,         // !mclk (inverted)
       input                      [1:0] wpage_in,     // will register to wclk, input OK with mclk
       input                            wpage_set,    // set internal write page to wpage_in 
@@ -54,6 +56,9 @@ module  mcntrl_buf_rd #(
     reg  [1:0] page_r;
     reg  [6:0] waddr;
     assign page=page_r;
+//    wire [4:0] next62_norm = waddr[6:2] + 1;
+//    wire [4:0] next62_rot =  {waddr[2],waddr[6:3]} + 1;
+//    wire [4:0] next62_emul64 = {next62_rot[3:0],next62_rot[4]};
     always @ (posedge wclk) begin
     
         if      (wpage_set) page_r <= wpage_in;
@@ -61,6 +66,13 @@ module  mcntrl_buf_rd #(
 
         if      (page_next || wpage_set) waddr <= 0;
         else if (we)                     waddr <= waddr+1;
+
+//        if      (page_next || wpage_set) waddr[1:0] <= 0;
+//        else if (we)                     waddr[1:0] <= waddr[1:0] + 1;
+
+//        if      (page_next || wpage_set) waddr[6:2] <= 0;
+//        else if (we && (&waddr[1:0]))    waddr[6:2] <= emul64 ? next62_emul64 : next62_norm;
+
     end
 //    ram_512x64w_1kx32r #(
     ram_var_w_var_r #(

memctrl/mcntrl_ps_pio.v

@@ -252,9 +252,10 @@ fifo_same_clock   #(
         .ext_rd       (port0_re),           // input
         .ext_regen    (port0_regen),        // input
         .ext_data_out (port0_data),         // output[31:0] 
+//        .emul64       (1'b0),               // input Modify buffer addresses (used for JP4 until a 64-wide mode is implemented)
         .wclk         (!mclk),              // input
         .wpage_in     (page_out_r_negedge), // page_neg), // input[1:0] 
-        .wpage_set    (page_w_set_negedge), //wpage_set_chn0_neg), // input 
+        .wpage_set    (page_w_set_negedge), // wpage_set_chn0_neg), // input 
         .page_next    (buf_wpage_nxt),      // input
         .page         (),                   // output[1:0]
         .we           (buf_wr),             // input
@@ -270,7 +271,7 @@ fifo_same_clock   #(
         .ext_we       (port1_we),           // input
         .ext_data_in  (port1_data),         // input[31:0] 
         .rclk         (mclk),               // input
-        .rpage_in     (page_out_r), //page), // input[1:0] 
+        .rpage_in     (page_out_r),         // page), // input[1:0] 
         .rpage_set    (page_r_set),         // rpage_set_chn1), // input 
         .page_next    (buf_rpage_nxt),      // input
         .page         (),                   // output[1:0]
@@ -287,9 +288,9 @@ fifo_same_clock   #(
         .sync_rst  (mrst || !nreset_page_fifo), // synchronously reset fifo;
         .we        (channel_pgm_en),
         .re        (buf_run),
-        .data_in   ({cmd_wr,cmd_page}), //page),
+        .data_in   ({cmd_wr,cmd_page}),         // page),
         .data_out  ({cmd_wr_out,page_out}),
-        .nempty    (), //page_fifo1_nempty),
+        .nempty    (),                          // page_fifo1_nempty),
         .half_full ()
     );
 

py393/x393_cmprs.py

@@ -279,6 +279,8 @@ class X393Cmprs(object):
                                  window_top,
                                  byte32,
                                  tile_width,
+                                 tile_vstep, # = 16
+                                 tile_height, #= 18
                                  extra_pages,
                                  disable_need):
         """
@@ -294,11 +296,13 @@ class X393Cmprs(object):
         @param window_top -       16-bit window top margin (in scan lines
         @param byte32 -           32-byte columns
         @param tile_width         tile width,
+        @param tile_vstep         tile vertical step in pixel rows (JPEG18/jp4 = 16)
+        @param tile_height        tile height: 18 for color JPEG, 16 fore JP$ flavors,
         @param extra_pages        extra pages needed (1)
         @param disable_need       disable need (preference to sensor channels - they can not wait
         """
-        tile_vstep = 16
-        tile_height= 18
+#        tile_vstep = 16
+#        tile_height= 18
         base_addr = vrlg.MCONTR_CMPRS_BASE + vrlg.MCONTR_CMPRS_INC * num_sensor;
         mode=   x393_mcntrl.func_encode_mode_scan_tiled(
                                    skip_too_late = False,
@@ -352,7 +356,7 @@ class X393Cmprs(object):
 #            run_mode = run_mode)      #0 - reset, 2 - run single from memory, 3 - run repetitive
         
     def setup_compressor_channel (self,
-                                  num_sensor,
+                                  chn,
                                   qbank,
                                   dc_sub,
                                   cmode,
@@ -367,7 +371,7 @@ class X393Cmprs(object):
                                   coring,
                                   verbose=0):
         """
-        @param num_sensor -       sensor port number (0..3)
+        @param chn -        compressor channel (0..3)
         @param qbank -       quantization table page (0..15)
         @param dc_sub -      True - subtract DC before running DCT, False - no subtraction, convert as is,
         @param cmode -       color mode:
@@ -397,7 +401,7 @@ class X393Cmprs(object):
         """
         if verbose > 0:
             print("COMPRESSOR_SETUP")
-            print (   "num_sensor = ",num_sensor)
+            print (   "num_sensor = ",chn)
             print (   "qbank = ",qbank)
             print (   "dc_sub = ",dc_sub)
             print (   "cmode = ",cmode)
@@ -405,7 +409,7 @@ class X393Cmprs(object):
             print (   "bayer = ",bayer)
             print (   "focus_mode = ",focus_mode)
         self.compressor_control(
-            chn =         num_sensor,  # sensor channel number (0..3)
+            chn =         chn,         # compressor channel number (0..3)
             qbank =       qbank,       # [6:3] quantization table page
             dc_sub =      dc_sub,      # [8:7] subtract DC
             cmode =       cmode,       #  [13:9] color mode:
@@ -414,18 +418,18 @@ class X393Cmprs(object):
             focus_mode =  focus_mode)  # [23:21] Set focus mode
             
         self.compressor_format(
-            chn =               num_sensor,        # sensor channel number (0..3)
+            chn =               chn,        # compressor channel number (0..3)
             num_macro_cols_m1 = num_macro_cols_m1, # number of macroblock colums minus 1
             num_macro_rows_m1 = num_macro_rows_m1, # number of macroblock rows minus 1
             left_margin =       left_margin)      # left margin of the first pixel (0..31) for 32-pixel wide colums in memory access
     
         self.compressor_color_saturation(
-            chn =          num_sensor,    # sensor channel number (0..3)
+            chn =           chn,           # compressor channel number (0..3)
             colorsat_blue = colorsat_blue, # color saturation for blue (10 bits) #'h90 for 100%
             colorsat_red =  colorsat_red)  # color saturation for red (10 bits)   # 'b6 for 100%
 
         self.compressor_coring(
-            chn =        num_sensor,    # sensor channel number (0..3)
+            chn =        chn,           # compressor channel number (0..3)
             coring =     coring);       # coring value
 
 

py393/x393_jpeg.py

@@ -416,7 +416,7 @@ class X393Jpeg(object):
                            portrait =  False,
                            height =    1936,
                            width =     2592,
-                           color_mode = 0,
+                           color_mode = vrlg.CMPRS_CBIT_CMODE_JPEG18,
                            byrshift   = 0,
                            verbose    = 1):
         """
@@ -633,7 +633,7 @@ class X393Jpeg(object):
                    y_quality = 100, #80,
                    c_quality = None,
                    portrait =  False,
-                   color_mode = 0,
+#                   color_mode = None, # vrlg.CMPRS_CBIT_CMODE_JPEG18, # read it from the saved
                    byrshift   = 0,
                    server_root = "/www/pages/",
                    verbose    = 1):
@@ -644,7 +644,6 @@ class X393Jpeg(object):
         @param y_quality - 1..100 - quantization quality for Y component
         @param c_quality - 1..100 - quantization quality for color components (None - use y_quality)
         @param portrait - False - use normal order, True - transpose for portrait mode images
-        @param color_mode - one of the image formats (jpeg, jp4,)
         @param byrshift - Bayer shift
         @param server_root - files ystem path to the web server root directory
         @param verbose - verbose level
@@ -657,6 +656,11 @@ class X393Jpeg(object):
                 allFiles = True
         except:
             pass
+        window = self.x393_sens_cmprs.specify_window()
+        if   window["cmode"] == vrlg.CMPRS_CBIT_CMODE_JP4:
+            file_path = file_path.replace(".jpeg",".jp4")
+        elif window["cmode"] == vrlg.CMPRS_CBIT_CMODE_JP46:
+            file_path = file_path.replace(".jpeg",".jp46")
         if allFiles:        
             html_text = """
 <html>
@@ -689,7 +693,7 @@ class X393Jpeg(object):
                                  y_quality = y_quality, #80,
                                  c_quality = c_quality,
                                  portrait =  portrait,
-                                 color_mode = color_mode,
+                                 color_mode = window["cmode"], #
                                  byrshift   = byrshift,
                                  verbose    = verbose)
             html_text += html_text_finish
@@ -705,14 +709,18 @@ class X393Jpeg(object):
                 with open (server_root+html_name, "w+b") as bf:
                     bf.write(html_text)
             return
-        
+        if verbose > 0 :
+            print ("window[height]",window["height"])
+            print ("window[width]",window["width"])
+            print ("window[cmode]",window["cmode"])
+            print ("window=",window)
         jpeg_data = self.jpegheader_create (
                            y_quality = y_quality,
                            c_quality = c_quality,
                            portrait =  portrait,
-                           height =    x393_sens_cmprs.GLBL_WINDOW["height"] & 0xfff0,
-                           width =     x393_sens_cmprs.GLBL_WINDOW["width"] & 0xfff0,
-                           color_mode = color_mode,
+                           height =    window["height"] & 0xfff0, # x393_sens_cmprs.GLBL_WINDOW["height"] & 0xfff0,
+                           width =     window["width"] & 0xfff0, # x393_sens_cmprs.GLBL_WINDOW["width"] & 0xfff0,
+                           color_mode = window["cmode"], #color_mode,
                            byrshift   = byrshift,
                            verbose    = verbose - 1)
         meta = self.x393_cmprs_afi.afi_mux_get_image_meta(
@@ -819,6 +827,12 @@ class X393Jpeg(object):
 ff d9
 """        
 """
+
+JP46: demuxing...
+Corrupt JPEG data: bad Huffman code
+Corrupt JPEG data: bad Huffman code
+Corrupt JPEG data: bad Huffman code
+
 #should be no MSB first (0x31c68400)
 
 cd /usr/local/verilog/; test_mcntrl.py @hargs
@@ -865,6 +879,14 @@ compressor_control 0 2
 jpeg_write  "img.jpeg" 0
 
 
+#default gain = 0xa, set red and blue (outdoors)
+write_sensor_i2c  0 1 0 0x30280014
+write_sensor_i2c  0 1 0 0x302c001a
+write_sensor_i2c  0 1 0 0x302e0020
+
+write_sensor_i2c  0 1 0 0x3028001e
+write_sensor_i2c  0 1 0 0x302c0021
+write_sensor_i2c  0 1 0 0x302e0030
 
 
 Camera compressors testing sequence

util_modules/debug_master.v

@@ -67,6 +67,7 @@ module  debug_master #(
     reg           ld_r;
     reg           cmd; //command stae (0 - idle)  
     reg [DEBUG_CMD_LATENCY : 0] cmd_reg;
+    wire    [3:0] debug_latency_plus1 = DEBUG_CMD_LATENCY+1;
     
     wire          set_status_w = cmd_we && (cmd_a == DEBUG_SET_STATUS);
     wire          shift32_w =    cmd_we && (cmd_a == DEBUG_SHIFT_DATA);
@@ -104,7 +105,7 @@ module  debug_master #(
     ) dly_16_i (
         .clk   (mclk),                // input
         .rst   (1'b0),                // input
-        .dly   (DEBUG_CMD_LATENCY+1), // input[3:0] 
+        .dly   (debug_latency_plus1), // DEBUG_CMD_LATENCY+1), // input[3:0] 
         .din   (&cntr),               // input[0:0] 
         .dout  (shift_done)           // output[0:0] 
     );