done connecting sensor and compressor subsystems to the memory controller

sensor/sensor_membuf.v

@@ -32,7 +32,8 @@ module  sensor_membuf #(
     input         rpage_set,    // set internal read page to rpage_in (reset pointers)
     input         rpage_next,   // advance to next page (and reset lower bits to 0)
     input         buf_rd,       // read buffer to memory, increment read address (regester enable will be delayed)
-    output [63:0] buf_dout      // data out
+    output [63:0] buf_dout,     // data out
+    output reg    page_written  // buffer page (full or partial) is written to the memory buffer 
               
 
 );
@@ -43,7 +44,9 @@ module  sensor_membuf #(
     reg                    sim_rst = 1; // jsut for simulation - reset from system reset to the first rpage_set
     reg              [2:0] rst_pntr;
     wire                   rst_wpntr;
+    wire                   inc_wpage_w;
     
+    assign inc_wpage_w = px_valid && (last_in_line || (&waddr));
     always @ (posedge mclk) begin
         rst_pntr <= {rst_pntr[1] &~rst_pntr[0], rst_pntr[0], rpage_set};
         if (rpage_set) sim_rst <= 0;
@@ -54,7 +57,7 @@ module  sensor_membuf #(
         else if (px_valid)                           waddr <= waddr + 1;
         
         if      (rst_wpntr)   wpage <= 0;
-        else if (px_valid && (last_in_line || (&waddr))) wpage <=  wpage + 1;
+        else if (inc_wpage_w) wpage <=  wpage + 1;
     end 
 
     pulse_cross_clock  rst_wpntr_i (
@@ -66,6 +69,15 @@ module  sensor_membuf #(
             .busy       ()
      );
 
+    pulse_cross_clock  page_written_i (
+            .rst        (sim_rst),
+            .src_clk    (pclk),
+            .dst_clk    (mclk),
+            .in_pulse   (inc_wpage_w),
+            .out_pulse  (page_written),
+            .busy       ()
+     );
+
 
     mcntrl_buf_wr #(
          .LOG2WIDTH_WR(4)  // 64 bit external interface

sensor/sensors393.v

@@ -230,6 +230,7 @@ module  sensors393 #(
     input    [3:0] rpage_next,   // advance to next page (and reset lower bits to 0)
     input    [3:0] buf_rd,       // read buffer to memory, increment read address (regester enable will be delayed)
     output [255:0] buf_dout,     // data out 
+    output   [3:0] page_written, // single mclk pulse: buffer page (full or partial) is written to the memory buffer 
     
     // Lower bits of frame numbers to use with the histograms, get from the sequencers
     // trigger inputs
@@ -448,7 +449,8 @@ module  sensors393 #(
                 .rpage_set    (rpage_set[i]),            // input
                 .rpage_next   (rpage_next[i]),           // input
                 .buf_rd       (buf_rd[i]),               // input
-                .buf_dout     (buf_dout[64*i +: 64]) // output[63:0] 
+                .buf_dout     (buf_dout[64*i +: 64]),    // output[63:0]
+                .page_written(page_written[i]) // output reg  single mclk pulse: buffer page (full or partial) is written to the memory buffer 
             );
         end
     endgenerate

x393.v

@@ -360,13 +360,16 @@ module  x393 #(
     wire                  [3:0] sens_rpage_next; //    (), // input
     wire                  [3:0] sens_buf_rd;     //    (), // input
     wire                [255:0] sens_buf_dout;   //    (), // output[63:0] 
-        
+    wire                  [3:0] sens_page_written;     //   single mclk pulse: buffer page (full or partial) is written to the memory buffer 
     wire                        trigger_mode; //       (), // input
     wire                  [3:0] trig_in;                  // input[3:0] 
         
     wire                  [3:0] sof_out_pclk; //       (), // output[3:0] 
     wire                  [3:0] eof_out_pclk; //       (), // output[3:0] 
-    wire                  [3:0] sof_out_mclk; //       (), // output[3:0] 
+    wire                  [3:0] sof_out_mclk; // Use for sequencer and to start memory write
+// if sof_out_mclk is applied to both sequencer and memory controller (as it is now) reprogramming of the sensor->memory
+// parameters will be applied to the next frame TODO: Verify that sequencer will always be later than memory controller
+// handling this pulse (should be so). Make sure parameters are applied in ASAP in single-trigger mode
     wire                  [3:0] sof_late_mclk; //      (), // output[3:0] 
         
     wire [NUM_FRAME_BITS - 1:0] frame_num0; //         (), // input[3:0] 
@@ -962,11 +965,12 @@ BUFG bufg_axi_aclk_i  (.O(axi_aclk),.I(fclk[0]));
         .axird_selected            (mcntrl_axird_selected), // output 
 
 // sensors interface
+        .sens_sof                  (sof_out_mclk),               // input[3:0]  // Early start of frame pulses (@mclk)
         .sens_rpage_set            (sens_rpage_set),             // output[3:0] 
         .sens_rpage_next           (sens_rpage_next),            // output[3:0] 
         .sens_buf_rd               (sens_buf_rd),                // output[3:0] 
         .sens_buf_dout             (sens_buf_dout),              // input[255:0] 
-
+        .sens_page_written         (sens_page_written),          // input [3:0] single mclk pulse: buffer page (full or partial) is written to the memory buffer 
 
 // compressor interface
         .cmprs_xfer_reset_page_rd  (cmprs_xfer_reset_page_rd),   // output[3:0] 
@@ -1364,6 +1368,7 @@ BUFG bufg_axi_aclk_i  (.O(axi_aclk),.I(fclk[0]));
         .rpage_next         (sens_rpage_next),     // input
         .buf_rd             (sens_buf_rd),         // input
         .buf_dout           (sens_buf_dout),       // output[63:0]
+        .page_written       (sens_page_written),   // output[3:0]
         
         .trigger_mode       (trigger_mode),        // input
         .trig_in            (trig_in),             // input[3:0]