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x393
Commit 71f603b7 authored by Andrey Filippov's avatar Andrey Filippov
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Fixed generate that instantiated 4*4 histogram modules (including disables),... 

Fixed generate that instantiated 4*4 histogram modules (including disables), tried with single histogram per channel - added 8% of all slices
parent 9c457ded
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Showing with 16 additions and 14 deletions
.project
View file @ 71f603b7
......@@ -62,42 +62,42 @@
<link>
<name>vivado_logs/VivadoBitstream.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151103114104932.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151105184905573.log</location>
</link>
<link>
<name>vivado_logs/VivadoOpt.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151103114104932.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151105184905573.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151103114104932.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151105184905573.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPower.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151103114104932.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151105184905573.log</location>
</link>
<link>
<name>vivado_logs/VivadoPlace.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151103114104932.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151105184905573.log</location>
</link>
<link>
<name>vivado_logs/VivadoRoute.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151103114104932.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151105184905573.log</location>
</link>
<link>
<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151103114104932.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151105184905573.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151103114104932.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151105184905573.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
......
fpga_version.vh
View file @ 71f603b7
parameter FPGA_VERSION = 32'h03930065; // (same rev) all met, using "old" (non-inverted) phase - OK (full phase range)
parameter FPGA_VERSION = 32'h03930066; // trying just one histogram to watch utilization - with 4 was: Slice 15913 (80.98%), now Slice = 14318 (72.87%)
// parameter FPGA_VERSION = 32'h03930065; // (same rev) all met, using "old" (non-inverted) phase - OK (full phase range)
// parameter FPGA_VERSION = 32'h03930065; // switch phy_top.v (all met) - OK with inverted phase control (reduced phase range)
// parameter FPGA_VERSION = 32'h03930064; // switch mcomtr_sequencer.v (xclk not met) - wrong!
// parameter FPGA_VERSION = 32'h03930063; // switch mcntrl_linear_rw.v (met) good, worse mem valid phases
......
includes/x393_parameters.vh
View file @ 71f603b7
......@@ -332,7 +332,7 @@
parameter SENSI2C_STATUS_REG_INC = 2, // increment to the next sensor
parameter SENSI2C_STATUS_REG_REL = 0, // 4 locations" 'h20, 'h22, 'h24, 'h26
parameter SENSIO_STATUS_REG_REL = 1, // 4 locations" 'h21, 'h23, 'h25, 'h27
parameter SENSOR_NUM_HISTOGRAM= 3, // number of histogram channels
parameter SENSOR_NUM_HISTOGRAM= 1, //was 3 trying just one histogram (see utilization) 3, // number of histogram channels
parameter HISTOGRAM_RAM_MODE = "BUF32", // "NOBUF", // valid: "NOBUF" (32-bits, no buffering), "BUF18", "BUF32"
parameter SENS_NUM_SUBCHN = 3, // number of subchannels for his sensor ports (1..4)
parameter SENS_GAMMA_BUFFER = 0, // 1 - use "shadow" table for clean switching, 0 - single table per channel
......
sensor/sensor_channel.v
View file @ 71f603b7
......@@ -998,7 +998,7 @@ module sensor_channel#(
// TODO: Use generate to generate 1-4 histogram modules
generate
if (HISTOGRAM_ADDR0 >=0)
if (HISTOGRAM_ADDR0 != -1)
`ifdef USE_PCLK2X
sens_histogram #(
.HISTOGRAM_RAM_MODE (HISTOGRAM_RAM_MODE),
......@@ -1097,7 +1097,7 @@ module sensor_channel#(
generate
if (HISTOGRAM_ADDR1 >=0)
if (HISTOGRAM_ADDR1 != -1)
`ifdef USE_PCLK2X
sens_histogram #(
.HISTOGRAM_RAM_MODE (HISTOGRAM_RAM_MODE),
......@@ -1192,7 +1192,7 @@ module sensor_channel#(
endgenerate
generate
if (HISTOGRAM_ADDR2 >=0)
if (HISTOGRAM_ADDR2 != -1)
`ifdef USE_PCLK2X
sens_histogram #(
.HISTOGRAM_RAM_MODE (HISTOGRAM_RAM_MODE),
......@@ -1287,7 +1287,7 @@ module sensor_channel#(
endgenerate
generate
if (HISTOGRAM_ADDR3 >=0)
if (HISTOGRAM_ADDR3 != -1)
`ifdef USE_PCLK2X
sens_histogram #(
.HISTOGRAM_RAM_MODE (HISTOGRAM_RAM_MODE),
......
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