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started implementation of 8-point DCT-IV

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/*!
* <b>Module:</b>dct_iv8_1d
* @file dct_iv8_1d.v
* @date 2016-12-02
* @author Andrey Filippov
*
* @brief 1d 8-point DCT type IV for lapped mdct 16->8, operates in 16 clock cycles
* Uses 2 DSP blocks
*
* @copyright Copyright (c) 2016 Elphel, Inc.
*
* <b>License:</b>
*
*dct_iv8_1d.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* dct_iv8_1d.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module dct_iv8_1d#(
parameter WIDTH = 24, // input data width
parameter OUT_WIDTH = 16, // output deata width
parameter OUT_RSHIFT = 3, // overall right shift of the result from input, aligned by MSB (>=3 will never cause saturation)
parameter B_WIDTH = 18,
parameter A_WIDTH = 25,
parameter P_WIDTH = 48,
// parameter M_WIDTH = 43, // actual multiplier width (== (A_WIDTH +B_WIDTH)
// parameter ROUND_OUT = 8, // cut these number of LSBs on the output, round result (in addition to COSINE_SHIFT)
parameter COSINE_SHIFT= 17,
parameter COS_01_32 = 130441, // (1<<17) * cos( 1*pi/32)
parameter COS_03_32 = 125428, // (1<<17) * cos( 3*pi/32)
parameter COS_04_32 = 121095, // (1<<17) * cos( 4*pi/32)
parameter COS_05_32 = 115595, // (1<<17) * cos( 5*pi/32)
parameter COS_07_32 = 101320, // (1<<17) * cos( 7*pi/32)
parameter COS_08_32 = 92682, // (1<<17) * cos( 8*pi/32)
parameter COS_09_32 = 83151, // (1<<17) * cos( 9*pi/32)
parameter COS_11_32 = 61787, // (1<<17) * cos(11*pi/32)
parameter COS_12_32 = 50159, // (1<<17) * cos(12*pi/32)
parameter COS_13_32 = 38048, // (1<<17) * cos(13*pi/32)
parameter COS_15_32 = 12847 // (1<<17) * cos(15*pi/32)
)(
input clk,
input rst,
input en,
input [WIDTH -1:0] d_in, // X6-X7-X5-X2-X1-X3-X0-X4-*-X5-X1-X2-*-X4-X7-*
input start, // one cycle before first X6 input
output [OUT_WIDTH -1:0] dout,
output reg pre2_start_out, // 2 clock cycle before Y0 output, full dout sequence
// start_out-x-Y0-x-Y7-x-Y1-x-Y6-x-Y3-x-Y4-x-Y2-x-Y5
output reg en_out // valid at the same time slot as pre2_start_out (goes active with pre2_start_out)
);
// localparam TOTAL_RSHIFT= COSINE_SHIFT + ROUND_OUT;
// localparam BEFORE_SAT_WIDTH = P_WIDTH - TOTAL_RSHIFT;
localparam RSHIFT1 = 2; // safe right shift for stage 1
localparam STAGE1_RSHIFT = COSINE_SHIFT + (WIDTH - A_WIDTH) + RSHIFT1; // divide by 4 in stage 1 - never saturates
localparam STAGE2_RSHIFT = COSINE_SHIFT + (OUT_WIDTH - WIDTH) +(OUT_RSHIFT-RSHIFT1); // divide by 4 in stage 1 - never saturates
// STAGE2_RSHIFT should be >0 ( >=1 ) for rounding
// TODO: Add rounding to stage 1
// register files on the D-inputs of DSPs
reg signed [A_WIDTH-1:0] dsp_din_1_ram[0:1] ; // just two registers
reg signed [A_WIDTH-1:0] dsp_din_2_ram[0:3] ; // 4 registers registers
reg dsp_din_1_wa;
reg dsp_din_1_ra;
reg dsp_din_1_we;
reg dsp_din_2_we;
reg [1:0] dsp_din_2_wa;
reg [1:0] dsp_din_2_ra;
reg signed [B_WIDTH-1:0] dsp_bin;
reg dsp_ceb1_1; // load b1 register
reg dsp_ceb2_1; // load b2 register
reg dsp_selb_1; // 0 - select b1, 1 - select b2
wire signed [A_WIDTH-1:0] dsp_ain_1;
reg dsp_cea1_1;
reg dsp_cea2_1;
wire signed [A_WIDTH-1:0] dsp_din_1;
reg dsp_ced_1;
reg dsp_sela_1;
// reg dsp_en_a_1; // Not used here 0: +/- D, 1: A or A +/- D
// reg dsp_en_d_1; // Not used here 0: A, 1: D or A +/- D
reg dsp_sub_a_1; //
reg dsp_neg_m_1; // 1 - negate multiplier result
reg dsp_accum_1; // 0 - use multiplier result, 1 add to accumulator
wire signed [P_WIDTH-1:0] dsp_cin_1;
reg dsp_cec_1;
reg dsp_post_add_1; // 0 - use multiplier or add to accumulator, 1 - add C and multiplier
wire signed [P_WIDTH-1:0] dsp_p_1;
reg dsp_ceb1_2; // load b1 register
reg dsp_ceb2_2; // load b2 register
reg dsp_selb_2; // 0 - select b1, 1 - select b2
wire signed [A_WIDTH-1:0] dsp_ain_2;
reg dsp_cea1_2;
reg dsp_cea2_2;
wire signed [A_WIDTH-1:0] dsp_din_2;
reg dsp_sela_2; // 0 - select a1, 1 - select a2
reg dsp_sub_a_2; //
reg dsp_neg_m_2; // 1 - negate multiplier result
reg dsp_accum_2; // 0 - use multiplier result, 1 add to accumulator
wire signed [P_WIDTH-1:0] dsp_p_2;
reg [7:0] phase;
reg [3:0] phase_cnt;
reg [OUT_WIDTH -1:0] dout_r;
reg [2:0] per_type; // idle/last:0, first cycle - 1, 2-nd - 2, other - 3,... ~en->6 ->7 -> 0 (to generate pre2_start_out)
// Temporarily adding 1 extra latency cycle for rounding/saturation. TODO: Remove when moved to DSP itself
reg pre3_start_out; // 3 clock cycle before F4 output, full dout sequence
// start_out-X-F4-X-F2-X-F6-F5-F0-F3-X-F1-X-F7
reg pre_en_out; // valid at the same time slot as pre2_start_out (goes active with pre2_start_out)
assign dsp_ain_2 = dsp_p_1 [STAGE1_RSHIFT +: A_WIDTH];
assign dout = dout_r;
generate
if (A_WIDTH > WIDTH) assign dsp_ain_1 = {{A_WIDTH-WIDTH{d_in[WIDTH-1]}},d_in};
else assign dsp_ain_1 = d_in; // SuppressThisWarning VEditor (not implemented)
endgenerate
assign dsp_cin_1 = {{P_WIDTH-WIDTH{d_in[WIDTH-1]}},d_in};
//register files
assign dsp_din_1 = dsp_din_1_ram[dsp_din_1_ra];
assign dsp_din_2 = dsp_din_2_ram[dsp_din_2_ra];
always @ (posedge clk) begin
if (dsp_din_1_we) dsp_din_1_ram[dsp_din_1_wa] <= dsp_ain_1;
if (dsp_din_2_we) dsp_din_2_ram[dsp_din_2_wa] <= dsp_ain_2;
end
always @ (posedge clk) begin
if (rst) per_type <= 0;
else if (start) per_type <= 3'h1;
else if (phase[7]) begin
if (!per_type[2] && !en) per_type <= 3'h7;
else if ((per_type != 0) && (per_type != 3)) per_type <= per_type + 1;
end
phase <= {phase[6:0], start | (phase[7] & (|per_type))};
//TODO:
if (rst || start || phase[7]) phase_cnt <= 0;
else if (|phase[6:0]) phase_cnt <= phase_cnt + 1;
// Cosine table, defined to fit into 17 bits for 18-bit signed DSP B-operand
case (phase_cnt)
4'h0: dsp_bin <= COS_07_32;
4'h1: dsp_bin <= COS_09_32;
4'h2: dsp_bin <= COS_04_32;
4'h3: dsp_bin <= COS_08_32;
4'h4: dsp_bin <= COS_05_32;
4'h5: dsp_bin <= COS_11_32;
4'h6: dsp_bin <= COS_12_32;
4'h7: dsp_bin <= 'bx;
4'h8: dsp_bin <= COS_13_32;
4'h9: dsp_bin <= COS_03_32;
4'ha: dsp_bin <= 'bx;
4'hb: dsp_bin <= COS_08_32;
4'hc: dsp_bin <= COS_15_32;
4'hd: dsp_bin <= COS_01_32;
4'he: dsp_bin <= COS_12_32;
4'hf: dsp_bin <= 'bx;
endcase
dout_r <= dsp_p_2 [STAGE2_RSHIFT +: OUT_WIDTH] + dsp_p_2 [STAGE2_RSHIFT - 1];
if (rst) pre3_start_out <= 0;
else pre3_start_out <= (per_type == 2) && phase[3];
pre2_start_out <=pre3_start_out;
if (rst || !(en || (|phase))) pre_en_out <= 0;
else if (phase[3]) begin
if (per_type == 2) pre_en_out <= 1;
else if (per_type[2:0]==0) pre_en_out <= 0;
end
en_out <= pre_en_out;
end
// Control signals for each phase
wire p00 = phase[3:0] == 0;
wire p01 = phase[3:0] == 1;
wire p02 = phase[3:0] == 2;
wire p03 = phase[3:0] == 3;
wire p04 = phase[3:0] == 4;
wire p05 = phase[3:0] == 5;
wire p06 = phase[3:0] == 6;
wire p07 = phase[3:0] == 7;
wire p08 = phase[3:0] == 8;
wire p09 = phase[3:0] == 9;
wire p10 = phase[3:0] == 10;
wire p11 = phase[3:0] == 11;
wire p12 = phase[3:0] == 12;
wire p13 = phase[3:0] == 13;
wire p14 = phase[3:0] == 14;
wire p15 = phase[3:0] == 15;
always @ (posedge clk) begin
// p00 | p01 | p02 | p03 | p04 | p05 | p06 | p07 | p08 | p09 | p10 | p11 | p12 | p13 | p14 | p15 ;
dsp_din_1_we <= p01 | p03 | p08 | p15 | start;
dsp_din_1_wa <= p15 | start;
dsp_din_1_ra <= p06 | p14 ;
dsp_cea1_1 <= p06 | p10 | p12 ;
dsp_cea2_1 <= p02 | p04 ;
dsp_ced_1 <= p00 | p02 | p05 | p06 | p08 | p09 | p13 | p14 ;
dsp_sela_1 <= p00 | p01 | p02 | p03 | p04 | p05 | p08 | p13 ;
dsp_sub_a_1 <= p00 | p01 | p02 | p04 | p05 | p06 | p11 | p15 ;
dsp_ceb1_1 <= p01 ;
dsp_ceb2_1 <= p02 | p05 | p10 | p13 ;
dsp_selb_1 <= p01 | p02 | p03 | p04 | p07 | p09 | p10 | p11 | p12 | p15 ;
dsp_cec_1 <= p00 | p05 | p13 ;
dsp_neg_m_1 <= p00 | p01 | p02 | p08 | p11 | p12 | p13 ;
dsp_accum_1 <= p00 | p02 | p08 | p10 | p11 | p12 | p13 | p14 | p15 ;
dsp_post_add_1 <= p04 | p05 | p12 | p13 ;
dsp_din_2_we <= | p06 | p07 | p14 | p15 ;
dsp_din_2_wa[0] <= p06 | p15 ;
dsp_din_2_wa[1] <= p14 | p15 ;
dsp_din_2_ra[0] <= p01 | p04 | p06 | p08 | p10 | p11 | p13 | p15 ;
dsp_din_2_ra[1] <= p03 | p04 | p05 | p06 | p07 | p08 | p09 | p10 ;
dsp_cea1_2 <= p02 | p10 ;
dsp_cea2_2 <= p04 | p12 ;
dsp_sela_2 <= p00 | p02 | p04 | p06 | p08 | p10 | p12 | p14 ; //~phase[0]
dsp_sub_a_2 <= p00 | p01 | p02 | p07 | p08 | p09 | p10 | p15 ;
dsp_ceb1_2 <= p00 | p03 | p08 | p11 ;
dsp_ceb2_2 <= p04 | p07 | p12 | p15 ;
dsp_selb_2 <= p00 | p03 | p05 | p06 | p08 | p11 | p13 | p14 ;
dsp_neg_m_2 <= p03 | p08 | p12 | p15 ; //~phase[0]
dsp_accum_2 <= p00 | p02 | p04 | p06 | p08 | p10 | p12 | p14 ;
end
dsp_ma_preadd_c #(
.B_WIDTH (B_WIDTH),
.A_WIDTH (A_WIDTH),
.P_WIDTH (P_WIDTH)
) dsp_ma_preadd_c_1_i (
.clk (clk), // input
.rst (rst), // input
.bin (dsp_bin), // input[17:0] signed
.ceb1 (dsp_ceb1_1), // input
.ceb2 (dsp_ceb2_1), // input
.selb (dsp_selb_1), // input
.ain (dsp_din_1), // input[24:0] signed
.cea1 (dsp_cea1_1), // input
.cea2 (dsp_cea2_1), // input
.din (dsp_din_1), // input[24:0] signed
.ced (dsp_ced_1), // input
.cin (dsp_cin_1), // input[47:0] signed
.cec (dsp_cec_1), // input
.cead (1'b1), // input
.sela (dsp_sela_1), // input
.en_a (1'b1), // input
.en_d (1'b1), // input
.sub_a (dsp_sub_a_1), // input
.neg_m (dsp_neg_m_1), // input
.accum (dsp_accum_1), // input
.post_add (dsp_post_add_1), // input
.pout (dsp_p_1) // output[47:0] signed
);
dsp_ma_preadd_c #(
.B_WIDTH (B_WIDTH),
.A_WIDTH (A_WIDTH),
.P_WIDTH (P_WIDTH)
) dsp_ma_preadd_c_2_i (
.clk (clk), // input
.rst (rst), // input
.bin (dsp_bin), // input[17:0] signed
.ceb1 (dsp_ceb1_2), // input
.ceb2 (dsp_ceb2_2), // input
.selb (dsp_selb_2), // input
.ain (dsp_din_2), // input[24:0] signed
.cea1 (dsp_cea1_2), // input
.cea2 (dsp_cea2_2), // input
.din (dsp_din_2), // input[24:0] signed
.ced (1'b1), // input
.cin ({P_WIDTH{1'b1}}),// input[47:0] signed
.cec (1'b0), // input
.cead (1'b1), // input
.sela (dsp_sela_2), // input
.en_a (1'b1), // input
.en_d (1'b1), // input
.sub_a (dsp_sub_a_2), // input
.neg_m (dsp_neg_m_2), // input
.accum (dsp_accum_2), // input
.post_add (1'b0), // input
.pout (dsp_p_2) // output[47:0] signed
);
endmodule
dsp/dsp_ma_preadd_c.v 0 → 100644
View file @ 71577936
/*!
* dsp_ma_preadd_c
* @file dsp_ma_preadd.v
* @date 2016-06-05
* @author Andrey Filippov
*
* @brief DSP with multi-input multiplier and accumulator with pre-adder
* and post-adder
*
* @copyright Copyright (c) 2016 Elphel, Inc.
*
* <b>License:</b>
*
* dsp_ma_preadd.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* dsp_ma_preadd.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
//`undef INSTANTIATE_DSP48E1
module dsp_ma_preadd_c #(
parameter B_WIDTH = 18,
parameter A_WIDTH = 25,
parameter P_WIDTH = 48)
(
input clk,
input rst,
input signed [B_WIDTH-1:0] bin,
input ceb1, // load b1 register
input ceb2, // load b2 register
input selb, // 0 - select b1, 1 - select b2
input signed [A_WIDTH-1:0] ain,
input cea1, // clock enable a1 reg
input cea2, // clock enable a2 reg
input signed [A_WIDTH-1:0] din,
input ced, // enable d-reg
input signed [P_WIDTH-1:0] cin, // c - input
input cec, // enable c-reg
input cead, // enable ad register (after pre-adder)
input sela, // 0 - select a1, 1 - select a2
input en_a, // 1 - enable a input (0 - zero) ~inmode[1]
input en_d, // 1 - enable d input (0 - zero) ~inmode[2]
input sub_a, // 0 - pre-add (D+A), 1 - pre-subtract (D-A)
input neg_m, // 1 - negate multiplier result
input accum, // 0 - use multiplier result, 1 add to accumulator
input post_add, // 0 - use multiplier or add to accumulator, 1 - add C and multiplier
output signed [P_WIDTH-1:0] pout
);
`ifdef INSTANTIATE_DSP48E1
wire [4:0] inmode = {~selb,
sub_a,
en_d,
~en_a,
~sela};
wire [3:0] alumode = {2'b0,
neg_m,
neg_m};
wire [6:0] opmode = {1'b0,
accum | post_add,
post_add,
2'b01,
2'b01};
DSP48E1 #(
.ACASCREG (1),
.ADREG (1),
.ALUMODEREG (1),
.AREG (1), // 2), // (1) - means number in series, so "2" always reads the second
.AUTORESET_PATDET ("NO_RESET"),
.A_INPUT ("DIRECT"),
.BCASCREG (1),
.BREG (1), // (2), // (1) - means number in series, so "2" always reads the second
.B_INPUT ("DIRECT"),
.CARRYINREG (1),
.CARRYINSELREG (1),
.CREG (1), //(0),
.DREG (1),
.INMODEREG (1),
.IS_ALUMODE_INVERTED (4'b0),
.IS_CARRYIN_INVERTED (1'b0),
.IS_CLK_INVERTED (1'b0),
.IS_INMODE_INVERTED (5'b0),
.IS_OPMODE_INVERTED (7'b0),
.MASK (48'hffffffffffff),
.MREG (1),
.OPMODEREG (1),
.PATTERN (48'h000000000000),
.PREG (1),
.SEL_MASK ("MASK"),
.SEL_PATTERN ("PATTERN"),
.USE_DPORT ("TRUE"), //("FALSE"),
.USE_MULT ("MULTIPLY"),
.USE_PATTERN_DETECT ("NO_PATDET"),
.USE_SIMD ("ONE48")
) DSP48E1_i (
.ACOUT (), // output[29:0]
.BCOUT (), // output[17:0]
.CARRYCASCOUT (), // output
.CARRYOUT (), // output[3:0]
.MULTSIGNOUT (), // output
.OVERFLOW (), // output
.P (pout), // output[47:0]
.PATTERNBDETECT (), // output
.PATTERNDETECT (), // output
.PCOUT (), // output[47:0]
.UNDERFLOW (), // output
.A ({{30-A_WIDTH{ain[A_WIDTH-1]}}, ain}), // input[29:0]
.ACIN (30'b0), // input[29:0]
.ALUMODE (alumode), // input[3:0]
.B (bin), // input[17:0]
.BCIN (18'b0), // input[17:0]
.C (cin), // input[47:0]
.CARRYCASCIN (1'b0), // input
.CARRYIN (1'b0), // input
.CARRYINSEL (3'h0), // input[2:0] // later modify?
.CEA1 (cea1), // input
.CEA2 (cea2), // input
.CEAD (cead), // input
.CEALUMODE (1'b1), // input
.CEB1 (ceb1), // input
.CEB2 (ceb2), // input
.CEC (cec), // input
.CECARRYIN (1'b0), // input
.CECTRL (1'b1), // input
.CED (ced), // input
.CEINMODE (1'b1), // input
.CEM (1'b1), // input
.CEP (1'b1), // input
.CLK (clk), // input
.D (din), // input[24:0]
.INMODE (inmode), // input[4:0]
.MULTSIGNIN (1'b0), // input
.OPMODE (opmode), // input[6:0]
.PCIN (48'b0), // input[47:0]
.RSTA (rst), // input
.RSTALLCARRYIN (rst), // input
.RSTALUMODE (rst), // input
.RSTB (rst), // input
.RSTC (rst), // input
.RSTCTRL (rst), // input
.RSTD (rst), // input
.RSTINMODE (rst), // input
.RSTM (rst), // input
.RSTP (rst) // input
);
`else
// Will try to make it infer DSP48e1
reg signed [B_WIDTH-1:0] b1_reg;
reg signed [B_WIDTH-1:0] b2_reg;
reg signed [A_WIDTH-1:0] a1_reg;
reg signed [A_WIDTH-1:0] a2_reg;
reg signed [A_WIDTH-1:0] d_reg;
reg signed [P_WIDTH-1:0] c_reg;
reg signed [A_WIDTH-1:0] ad_reg;
reg signed [P_WIDTH-1:0] m_reg;
reg signed [P_WIDTH-1:0] p_reg;
wire signed [A_WIDTH+B_WIDTH-1:0] m_wire;
wire signed [B_WIDTH-1:0] b_wire;
wire signed [A_WIDTH-1:0] a_wire;
wire signed [A_WIDTH-1:0] d_wire;
reg selb_r;
reg sela_r;
reg en_a_r;
reg en_d_r;
reg sub_a_r;
reg neg_m_r;
reg accum_r;
reg post_add_r;
wire signed [P_WIDTH-1:0] m_reg_pm;
wire signed [P_WIDTH-1:0] p_reg_cond;
/*
input signed [P_WIDTH-1:0] cin, // c - input
input cec, // enable c-reg
input post_add, // 0 - use multiplier or add to accumulator, 1 - add C and multiplier
*/
assign pout = p_reg;
assign b_wire = selb_r ? b2_reg : b1_reg;
assign a_wire = en_a_r ? (sela_r ? a2_reg : a1_reg) : {A_WIDTH{1'b0}};
// assign d_wire = en_d_r ? (sub_a_r ? -d_reg : d_reg) : {A_WIDTH{1'b0}};
assign d_wire = en_d_r ? d_reg : {A_WIDTH{1'b0}};
assign m_wire = ad_reg * b_wire;
assign m_reg_pm = neg_m_r ? - m_reg : m_reg;
// assign p_reg_cond = accum_r ? p_reg : 0;
assign p_reg_cond = post_add_r? c_reg: (accum_r ? p_reg : 0);
always @ (posedge clk) begin
if (rst) b1_reg <= 0;
else if (ceb1) b1_reg <= bin;
if (rst) b2_reg <= 0;
else if (ceb2) b2_reg <= bin;
if (rst) a1_reg <= 0;
else if (cea1) a1_reg <= ain;
if (rst) a2_reg <= 0;
else if (cea2) a2_reg <= ain;
if (rst) d_reg <= 0;
else if (ced) d_reg <= din;
if (rst) c_reg <= 0;
else if (cec) c_reg <= cin;
if (rst) ad_reg <= 0;
else if (cead) ad_reg <= sub_a_r? (d_wire - a_wire): (d_wire + a_wire);
neg_m_r <= neg_m;
accum_r <= accum;
post_add_r <= post_add;
selb_r <= selb;
sela_r <= sela;
en_a_r <= en_a;
en_d_r <= en_d;
sub_a_r <= sub_a;
m_reg <= {{P_WIDTH - A_WIDTH - B_WIDTH{1'b0}}, m_wire};
p_reg <= p_reg_cond + m_reg_pm;
end
`endif
endmodule
py393/x393_jpeg.py
View file @ 71577936
......@@ -2563,6 +2563,10 @@ set_camsync_inout 0 7 0
#reset_camsync_inout 0 # start with internal trigger
#set_camsync_mode <en=None> <en_snd=None> <en_ts_external=None> <triggered_mode=None> <master_chn=None> <chn_en=None>
set_camsync_mode 1 1 1 1 0 0xf
set_camsync_period 10000 # 100 usec # and start
......@@ -2621,6 +2625,7 @@ r
read_status 0x21
r
jpeg_sim_multi 4
r
read_status 0x21
r
......
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