started porting imu_logger.v - split original file into single-module ones

/*******************************************************************************

 * Module: buf_xclk_mclk16_393

 * Date:2015-07-06  

 * Author: andrey     

 * Description: move data from xclk to mclk domain

 *

 * Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .

 * buf_xclk_mclk16_393.v is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation, either version 3 of the License, or

 * (at your option) any later version.

 *

 *  buf_xclk_mclk16_393.v is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program.  If not, see <http://www.gnu.org/licenses/> .

 *******************************************************************************/

`timescale 1ns/1ps

module  buf_xclk_mclk16_393(

                          xclk, // posedge

                          mclk, // posedge

                          rst,  // @posedge xclk

                          din,

                          din_stb,

                          dout,

                          dout_stb);

  input         xclk;  // half frequency (80 MHz nominal)

  input         mclk;  // system clock - frequency (160 MHz nominal)

  input         rst;   // reset module

  input  [15:0] din;

  input         din_stb;

  output [15:0] dout;

  output        dout_stb;

  reg   [1:0] wa;

  reg   [1:0] wa_mclk;

  reg   [1:0] wa_mclk_d;

  reg         rst_mclk;

  reg   [1:0] ra;

  reg   [1:0] ra_next;

  reg         inc_ra;

  wire [15:0] pre_dout;

  reg  [15:0] dout;

  reg         dout_stb;

  always @ (posedge xclk) begin

    if      (rst)     wa[1:0] <= 2'h0;

    else if (din_stb) wa[1:0] <={wa[0],~wa[1]};

  end

  always @ (posedge mclk) begin

    wa_mclk[1:0]   <= wa[1:0];

    wa_mclk_d[1:0] <= wa_mclk[1:0];

    rst_mclk<= rst;

    if (rst_mclk) ra[1:0] <= 2'h0;

    else          ra[1:0] <= inc_ra?{ra[0],~ra[1]}:{ra[1],ra[0]};

    if (rst_mclk) ra_next[1:0] <= 2'h1;

    else          ra_next[1:0] <= inc_ra?{~ra[1],~ra[0]}:{ra[0],~ra[1]};

    inc_ra <= !rst && (ra[1:0]!=wa_mclk_d[1:0]) && (!inc_ra || (ra_next[1:0]!=wa_mclk_d[1:0]));

    dout_stb <= inc_ra;

    if (inc_ra) dout[15:0] <= pre_dout[15:0];

  end

  myRAM_WxD_D #( .DATA_WIDTH(16),.DATA_DEPTH(2))

            i_fifo_4x16   (.D(din[15:0]),

                             .WE(din_stb),

                             .clk(xclk),

                             .AW(wa[1:0]),

                             .AR(ra[1:0]),

                             .QW(),

                             .QR(pre_dout[15:0]));

endmodule

endmodule

/*******************************************************************************

 * Module: imu_exttime393

 * Date:2015-07-06  

 * Author: andrey     

 * Description: get external timestamp (for image)

 *

 * Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .

 * imu_exttime393.v is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation, either version 3 of the License, or

 * (at your option) any later version.

 *

 *  imu_exttime393.v is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program.  If not, see <http://www.gnu.org/licenses/> .

 *******************************************************************************/

`timescale 1ns/1ps

/*

logs frame synchronization data from other camera (same as frame sync)

*/

module  imu_exttime393(

                       xclk,  // half frequency (80 MHz nominal)

                       en,    // enable module operation, if 0 - reset

                       trig,  // external time stamp updated

                       usec,  // microseconds from external timestamp (should not chnage after trig for 10 xclk)

                       sec,   // seconds from external timestamp

                       ts,    // timestamop request

                       rdy,    // data ready

                       rd_stb, // data read strobe (increment address)

                       rdata); // data out (16 bits)

  input         xclk;  // half frequency (80 MHz nominal)

  input         en;    // enable

  input         trig;  // external time stamp updated

  input  [19:0] usec;  // microseconds from external timestamp

  input  [31:0] sec;   // seconds from external timestamp

  output        ts;    // timestamp request

  output        rdy;   // encoded nmea data ready

  input         rd_stb;// encoded nmea data read strobe (increment address)

  output [15:0] rdata; // encoded data (16 bits)

  reg  [ 4:0]   raddr;

  reg           rdy=1'b0;

  reg           we, pre_we;

  reg  [ 3:0]   pre_waddr;

  reg  [ 1:0]   waddr;

  reg  [ 2:0]   trig_d;

  reg           pre_ts,ts;

  reg  [15:0]   time_mux;

  always @ (posedge xclk) begin

    if  (!en) trig_d[2:0] <= 3'h0;

    else      trig_d[2:0] <= {trig_d[1:0], trig};

    pre_ts <= !trig_d[2] && trig_d[1];

    ts <= pre_ts; // delayed so arbiter will enable ts to go through

    if      (!en || pre_ts)     pre_waddr[3:0] <= 4'b0;

    else if (!pre_waddr[3]) pre_waddr[3:0] <= pre_waddr[3:0] + 1;

    if (pre_waddr[0]) waddr[1:0] <=pre_waddr[2:1];

    if (pre_waddr[0] && !pre_waddr[3]) case (pre_waddr[2:1])

      2'b00: time_mux[15:0] <= usec[15:0];

      2'b01: time_mux[15:0] <= {12'h0,usec[19:16]};

      2'b10: time_mux[15:0] <= sec[15:0];

      2'b11: time_mux[15:0] <= sec[31:16];

    endcase

    pre_we<=pre_waddr[0] && !pre_waddr[3];

    we <= pre_we;

    if (!en || pre_ts)   raddr[4:0] <= 5'h0;

    else if (rd_stb)    raddr[4:0] <= raddr[4:0] + 1;

    if  (pre_ts || (rd_stb && (raddr[1:0]==2'h3)) || !en) rdy <= 1'b0;

    else if (we && (waddr[1:0]==2'h3))                rdy <= 1'b1;

  end

  myRAM_WxD_D #( .DATA_WIDTH(16),.DATA_DEPTH(2))

            i_odbuf (.D(time_mux[15:0]),

                     .WE(we),

                     .clk(xclk),

                     .AW(waddr[1:0]),

                     .AR(raddr[1:0]),

                     .QW(),

                     .QR(rdata[15:0]));

endmodule

endmodule

/*******************************************************************************

 * Module: imu_message393

 * Date:2015-07-06  

 * Author: andrey     

 * Description: 

 *

 * Copyright (c) 2015 <set up in Preferences-Verilog/VHDL Editor-Templates> .

 * imu_message393.v is free software; you can redistribute it and/or modify

 * it under the terms of the GNU General Public License as published by

 * the Free Software Foundation, either version 3 of the License, or

 * (at your option) any later version.

 *

 *  imu_message393.v is distributed in the hope that it will be useful,

 * but WITHOUT ANY WARRANTY; without even the implied warranty of

 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the

 * GNU General Public License for more details.

 *

 * You should have received a copy of the GNU General Public License

 * along with this program.  If not, see <http://www.gnu.org/licenses/> .

 *******************************************************************************/

`timescale 1ns/1ps

/*

logs events from odometer (can be software triggered), includes 56-byte message written to the buffer

So it is possible to assert trig input (will request timestamp), write message by software, then

de-assert the trig input - message with the timestamp will be logged

fixed-length de-noise circuitry with latency 256*T(xclk) (~3usec)

*/

module  imu_message393 ( sclk,   // system clock, negedge

                       xclk,  // half frequency (80 MHz nominal)

                       we,    // write enable for registers to log (@negedge sclk), with lower data half

                       wa,    // write address for register (4 bits, @negedge sclk)

                       di,    // 16-bit data in  multiplexed 

                       en,    // enable module operation, if 0 - reset

                       trig,  // leading edge - sample time, trailing set rdy

                       ts,    // timestamop request

                       rdy,    // data ready

                       rd_stb, // data read strobe (increment address)

                       rdata); // data out (16 bits)

  input         sclk;   // system clock, negedge

  input         xclk;  // half frequency (80 MHz nominal)

  input         we;    // write enable for registers to log (@negedge sclk)

  input  [3:0]  wa;    // write address for register (4 bits, @negedge sclk)

  input  [15:0] di;    // 16-bit data in (32 multiplexed)

  input         en;    // enable

  input         trig;  // leading edge - sample time, trailing set rdy

  output        ts;    // timestamp request

  output        rdy;    // encoded nmea data ready

  input         rd_stb; // encoded nmea data read strobe (increment address)

  output [15:0] rdata;  // encoded data (16 bits)

  reg  [ 4:0]   raddr;

  reg           rdy=1'b0;

  reg           we_d;

  reg  [ 4:1]   waddr;

  reg  [ 2:0]   trig_d;

  reg  [ 7:0]   denoise_count;

  reg  [ 1:0]   trig_denoise;

  reg           ts;

  reg    [15:0] di_d;

  always @ (negedge sclk) begin

    di_d[15:0] <= di[15:0];

    waddr[4:1] <= wa[3:0];

    we_d <=we;

  end

  always @ (posedge xclk) begin

    if  (!en) trig_d[2:0] <= 3'h0;

    else      trig_d[2:0] <= {trig_d[1:0], trig};

    if      (!en)                      trig_denoise[0] <= 1'b0;

    else if (denoise_count[7:0]==8'h0) trig_denoise[0] <= trig_d[2];

    if (trig_d[2]==trig_denoise[0]) denoise_count[7:0] <= 8'hff;

    else                            denoise_count[7:0] <= denoise_count[7:0] - 1;

    trig_denoise[1] <= trig_denoise[0];

    ts <= !trig_denoise[1] && trig_denoise[0];

    if (!en || ts)   raddr[4:0] <= 5'h0;

    else if (rd_stb)    raddr[4:0] <= raddr[4:0] + 1;

    if  (ts || (rd_stb && (raddr[4:0]==5'h1b)) || !en) rdy <= 1'b0;

    else if (trig_denoise[1] && !trig_denoise[0])     rdy <= 1'b1;

  end

  myRAM_WxD_D #( .DATA_WIDTH(16),.DATA_DEPTH(5))

            i_odbuf (.D(di_d[15:0]),

                     .WE(we | we_d),

                     .clk(~sclk),

                     .AW({waddr[4:1],we_d}),

                     .AR(raddr[4:0]),

                     .QW(),

                     .QR(rdata[15:0]));

endmodule

endmodule