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x393
Commit 6f36f6d1 authored by Andrey Filippov's avatar Andrey Filippov
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connecting sensor subsystem to the top module

parent d4f2714d
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includes/x393_parameters.vh
View file @ 6f36f6d1
......@@ -290,5 +290,155 @@
parameter MEMBRIDGE_STATUS_REG= 'h3b,
parameter RSEL= 1'b1, // late/early READ commands (to adjust timing by 1 SDCLK period)
parameter WSEL= 1'b0 // late/early WRITE commands (to adjust timing by 1 SDCLK period)
parameter WSEL= 1'b0, // late/early WRITE commands (to adjust timing by 1 SDCLK period)
parameter SENSOR_GROUP_ADDR = 'h400, // sensor registers base address
parameter SENSOR_BASE_INC = 'h040, // increment for sesor channel
parameter HIST_SAXI_ADDR_REL = 'h100, // histograms control addresses (16 locations) relative to SENSOR_GROUP_ADDR
parameter HIST_SAXI_MODE_ADDR_REL = 'h110, // histograms mode address (1 locatios) relative to SENSOR_GROUP_ADDR
parameter SENSI2C_STATUS_REG_BASE = 'h30, // 4 locations" x30, x32, x34, x36
parameter SENSI2C_STATUS_REG_INC = 2, // increment to the next sensor
parameter SENSI2C_STATUS_REG_REL = 0, // 4 locations" 'h30, 'h32, 'h34, 'h36
parameter SENSIO_STATUS_REG_REL = 1, // 4 locations" 'h31, 'h33, 'h35, 'h37
parameter SENSOR_NUM_HISTOGRAM= 3, // number of histogram channels
parameter HISTOGRAM_RAM_MODE = "NOBUF", // valid: "NOBUF" (32-bits, no buffering), "BUF18", "BUF32"
parameter SENS_GAMMA_NUM_CHN = 3, // number of subchannels for his sensor ports (1..4)
parameter SENS_GAMMA_BUFFER = 0, // 1 - use "shadow" table for clean switching, 0 - single table per channel
// parameters defining address map
parameter SENSOR_CTRL_RADDR = 0, // relative to SENSOR_GROUP_ADDR
parameter SENSOR_CTRL_ADDR_MASK = 'h7ff, //
// bits of the SENSOR mode register
parameter SENSOR_MODE_WIDTH = 9,
parameter SENSOR_HIST_EN_BIT = 0, // 0..3 1 - enable histogram modules, disable after processing the started frame
parameter SENSOR_HIST_NRST_BIT = 4, // 0 - immediately reset all histogram modules
parameter SENSOR_16BIT_BIT = 8, // 0 - 8 bpp mode, 1 - 16 bpp (bypass gamma). Gamma-processed data is still used for histograms
parameter SENSI2C_CTRL_RADDR = 2, // 302..'h303
parameter SENSI2C_CTRL_MASK = 'h7fe,
// sensor_i2c_io relative control register addresses
parameter SENSI2C_CTRL = 'h0,
parameter SENSI2C_STATUS = 'h1,
parameter SENS_SYNC_RADDR = 'h4,
parameter SENS_SYNC_MASK = 'h7fc,
// 2 locations reserved for control/status (if they will be needed)
parameter SENS_SYNC_MULT = 'h2, // relative register address to write number of frames to combine in one (minus 1, '0' - each farme)
parameter SENS_SYNC_LATE = 'h3, // number of lines to delay late frame sync
parameter SENS_GAMMA_RADDR = 'h38, // 'h38..'h3b was 4,
parameter SENS_GAMMA_ADDR_MASK = 'h7fc,
// sens_gamma registers
parameter SENS_GAMMA_CTRL = 'h0,
parameter SENS_GAMMA_ADDR_DATA = 'h1, // bit 20 ==1 - table address, bit 20==0 - table data (18 bits)
parameter SENS_GAMMA_HEIGHT01 = 'h2, // bits [15:0] - height minus 1 of image 0, [31:16] - height-1 of image1
parameter SENS_GAMMA_HEIGHT2 = 'h3, // bits [15:0] - height minus 1 of image 2 ( no need for image 3)
// bits of the SENS_GAMMA_CTRL mode register
parameter SENS_GAMMA_MODE_WIDTH = 5, // does not include trig
parameter SENS_GAMMA_MODE_BAYER = 0,
parameter SENS_GAMMA_MODE_PAGE = 2,
parameter SENS_GAMMA_MODE_EN = 3,
parameter SENS_GAMMA_MODE_REPET = 4,
parameter SENS_GAMMA_MODE_TRIG = 5,
parameter SENSIO_RADDR = 8, //'h308 .. 'h30c
parameter SENSIO_ADDR_MASK = 'h7f8,
// sens_parallel12 registers
parameter SENSIO_CTRL = 'h0,
// SENSIO_CTRL register bits
parameter SENS_CTRL_MRST = 0, // 1: 0
parameter SENS_CTRL_ARST = 2, // 3: 2
parameter SENS_CTRL_ARO = 4, // 5: 4
parameter SENS_CTRL_RST_MMCM = 6, // 7: 6
parameter SENS_CTRL_EXT_CLK = 8, // 9: 8
parameter SENS_CTRL_LD_DLY = 10, // 10
parameter SENS_CTRL_QUADRANTS = 12, // 17:12, enable - 20
parameter SENSIO_STATUS = 'h1,
parameter SENSIO_JTAG = 'h2,
// SENSIO_JTAG register bits
parameter SENS_JTAG_PGMEN = 8,
parameter SENS_JTAG_PROG = 6,
parameter SENS_JTAG_TCK = 4,
parameter SENS_JTAG_TMS = 2,
parameter SENS_JTAG_TDI = 0,
parameter SENSIO_WIDTH = 'h3, // 1.. 2^16, 0 - use HACT
parameter SENSIO_DELAYS = 'h4, // 'h4..'h7
// 4 of 8-bit delays per register
// sensor_i2c_io command/data write registers s (relative to SENSOR_GROUP_ADDR)
parameter SENSI2C_ABS_RADDR = 'h10, // 'h310..'h31f
parameter SENSI2C_REL_RADDR = 'h20, // 'h320..'h32f
parameter SENSI2C_ADDR_MASK = 'h7f0, // both for SENSI2C_ABS_ADDR and SENSI2C_REL_ADDR
// sens_hist registers (relative to SENSOR_GROUP_ADDR)
parameter HISTOGRAM_RADDR0 = 'h30, //
parameter HISTOGRAM_RADDR1 = 'h32, //
parameter HISTOGRAM_RADDR2 = 'h34, //
parameter HISTOGRAM_RADDR3 = 'h36, //
parameter HISTOGRAM_ADDR_MASK = 'h7fe, // for each channel
// sens_hist registers
parameter HISTOGRAM_LEFT_TOP = 'h0,
parameter HISTOGRAM_WIDTH_HEIGHT = 'h1, // 1.. 2^16, 0 - use HACT
//sensor_i2c_io other parameters
parameter integer SENSI2C_DRIVE= 12,
parameter SENSI2C_IBUF_LOW_PWR= "TRUE",
parameter SENSI2C_IOSTANDARD = "DEFAULT",
parameter SENSI2C_SLEW = "SLOW",
//sensor_fifo parameters
parameter SENSOR_DATA_WIDTH = 12,
parameter SENSOR_FIFO_2DEPTH = 4,
parameter SENSOR_FIFO_DELAY = 7,
// other parameters for histogram_saxi module
parameter HIST_SAXI_ADDR_MASK = 'h7f0,
parameter HIST_SAXI_MODE_WIDTH = 8,
parameter HIST_SAXI_EN = 0,
parameter HIST_SAXI_NRESET = 1,
parameter HIST_CONFIRM_WRITE = 2, // wait write confirmation for each block
parameter HIST_SAXI_AWCACHE = 4'h3, //..7 cache mode (4 bits, default 4'h3)
parameter HIST_SAXI_MODE_ADDR_MASK = 'h7ff,
parameter NUM_FRAME_BITS = 4, // number of bits use for frame number
// Other parameters
parameter SENS_SYNC_FBITS = 16, // number of bits in a frame counter for linescan mode
parameter SENS_SYNC_LBITS = 16, // number of bits in a line counter for sof_late output (limited by eof)
parameter SENS_SYNC_LATE_DFLT = 15, // number of lines to delay late frame sync
parameter SENS_SYNC_MINBITS = 8, // number of bits to enforce minimal frame period
parameter SENS_SYNC_MINPER = 130, // minimal frame period (in pclk/mclk?)
// sens_parallel12 other parameters
// parameter IODELAY_GRP ="IODELAY_SENSOR", // may need different for different channels?
parameter integer IDELAY_VALUE = 0,
parameter integer PXD_DRIVE = 12,
parameter PXD_IBUF_LOW_PWR = "TRUE",
parameter PXD_IOSTANDARD = "DEFAULT",
parameter PXD_SLEW = "SLOW",
parameter real SENS_REFCLK_FREQUENCY = 300.0,
parameter SENS_HIGH_PERFORMANCE_MODE = "FALSE",
parameter SENS_PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
parameter SENS_PCLK_PERIOD = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"
parameter CLKFBOUT_MULT_SENSOR = 8, // 100 MHz --> 800 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
parameter SENS_DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter SENS_REF_JITTER1 = 0.010, // Expectet jitter on CLKIN1 (0.000..0.999)
parameter SENS_REF_JITTER2 = 0.010,
parameter SENS_SS_EN = "FALSE", // Enables Spread Spectrum mode
parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
parameter SENS_SS_MOD_PERIOD = 10000 // integer 4000-40000 - SS modulation period in ns
\ No newline at end of file
memctrl/mcntrl393.v
View file @ 6f36f6d1
......@@ -220,6 +220,7 @@ module mcntrl393 #(
input rst_in,
input clk_in,
output mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port
output ref_clk, // global clock for idelay_ctrl calibration
// programming interface
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
input cmd_stb, // strobe (with first byte) for the command a/d
......@@ -1466,6 +1467,7 @@ module mcntrl393 #(
.rst_in (rst_in), // input
.clk_in (clk_in), // input
.mclk (mclk), // output
.ref_clk (ref_clk), // output
.cmd_ad (cmd_mcontr_ad), // input[7:0]
.cmd_stb (cmd_mcontr_stb), // input
.status_ad (status_mcontr_ad[7:0]), // output[7:0]
......
memctrl/memctrl16.v
View file @ 6f36f6d1
......@@ -141,6 +141,7 @@ module memctrl16 #(
input rst_in,
input clk_in,
output mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port
output ref_clk, // global clock for idelay_ctrl calibration
// programming interface
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
input cmd_stb, // strobe (with first byte) for the command a/d
......@@ -913,6 +914,7 @@ end
.clk_in (clk_in), // axi_aclk), // input
.rst_in (rst_in), // axi_rst), // input TODO: move buffer outside?
.mclk (mclk), // output
.ref_clk (ref_clk), // output
.cmd0_clk (cmd0_clk), // input
.cmd0_we (cmd0_we), // input
......
memctrl/phy/mcontr_sequencer.v
View file @ 6f36f6d1
......@@ -115,6 +115,7 @@ module mcontr_sequencer #(
input clk_in,
input rst_in,
output mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port
output ref_clk, // global clock for idelay_ctrl calibration
// command port 0 (filled by software - 32w->32r) - used for mode set, refresh, write levelling, ...
input cmd0_clk,
input cmd0_we,
......@@ -581,6 +582,7 @@ module mcontr_sequencer #(
.clk_in (clk_in), // input
.rst_in (rst_in), // input
.mclk (mclk), // output
.ref_clk (ref_clk), // output
.dly_data (dly_data[7:0]), // input[7:0]
.dly_addr (dly_addr[6:0]), // input[6:0]
.ld_delay (ld_delay), // input
......
memctrl/phy/phy_cmd.v
View file @ 6f36f6d1
......@@ -71,6 +71,7 @@ module phy_cmd#(
input clk_in,
input rst_in,
output mclk, // global clock, half DDR3 clock, synchronizes all I/O through the command port
output ref_clk, // global clock for idelay_ctrl calibration
// inteface to control I/O delays and mmcm
input [7:0] dly_data, // delay value (3 LSB - fine delay)
input [6:0] dly_addr, // select which delay to program
......@@ -426,6 +427,7 @@ module phy_cmd#(
.clk (), // output
.clk_div (clk_div), // output
.mclk (mclk), // output
.ref_clk (ref_clk), // output
.rst_in (rst_in), // input
.ddr_rst (ddr_rst), // input
......
memctrl/phy/phy_top.v
View file @ 6f36f6d1
......@@ -75,6 +75,7 @@ module phy_top #(
output clk, // free-running system clock, same frequency as iclk (shared for R/W), BUFR output
output clk_div, // free-running half clk frequency, front aligned to clk (shared for R/W), BUFR output
output mclk, // same as clk_div, through separate BUFG and static phase adjust
output ref_clk, // global clock for idelay_ctrl calibration
input rst_in, // reset delays/serdes
input ddr_rst, // active high - generate NRST to memory
input dci_rst, // active high - reset DCI circuitry
......@@ -126,7 +127,7 @@ module phy_top #(
wire ld_cmda = (dly_addr[6:5] == 2'h2) && ld_delay ;
wire ld_mmcm= (dly_addr[6:0] == 7'h60) && ld_delay ;
wire clkfb_ref, clk_ref_pre;
wire clk_ref; // 200MHz/300Mhz to calibrate I/O delays
// wire ref_clk; // 200MHz/300Mhz to calibrate I/O delays
// wire locked_mmcm,locked_pll, dly_ready, dci_ready;
// assign locked=locked_mmcm && locked_pll && dly_ready && dci_ready; // both PLL ready, I/O delay calibrated
wire clkin_stopped_mmcm;
......@@ -290,10 +291,10 @@ wire clk_pre, clk_div_pre, sdclk_pre, mclk_pre, clk_fb;
BUFR clk_bufr_i (.O(clk), .CE(), .CLR(), .I(clk_pre));
BUFR clk_div_bufr_i (.O(clk_div), .CE(), .CLR(), .I(clk_div_pre));
BUFIO iclk_bufio_i (.O(sdclk), .I(sdclk_pre) );
//BUFIO clk_ref_i (.O(clk_ref), .I(clk_ref_pre));
//assign clk_ref=clk_ref_pre;
//BUFH clk_ref_i (.O(clk_ref), .I(clk_ref_pre));
BUFG clk_ref_i (.O(clk_ref), .I(clk_ref_pre));
//BUFIO clk_ref_i (.O(ref_clk), .I(clk_ref_pre));
//assign ref_clk=clk_ref_pre;
//BUFH clk_ref_i (.O(ref_clk), .I(clk_ref_pre));
BUFG clk_ref_i (.O(ref_clk), .I(clk_ref_pre));
BUFG mclk_i (.O(mclk),.I(mclk_pre) );
mmcm_phase_cntr #(
.PHASE_WIDTH (PHASE_WIDTH),
......@@ -390,7 +391,7 @@ BUFG mclk_i (.O(mclk),.I(mclk_pre) );
idelay_ctrl# (
.IODELAY_GRP("IODELAY_MEMORY")
) idelay_ctrl_i (
.refclk(clk_ref),
.refclk(ref_clk),
.rst(rst || dly_rst),
.rdy(dly_ready)
);
......
sensor/sens_parallel12.v
View file @ 6f36f6d1
......@@ -52,25 +52,25 @@ module sens_parallel12 #(
parameter PXD_IBUF_LOW_PWR = "TRUE",
parameter PXD_IOSTANDARD = "DEFAULT",
parameter PXD_SLEW = "SLOW",
parameter real REFCLK_FREQUENCY = 300.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter real SENS_REFCLK_FREQUENCY = 300.0,
parameter SENS_HIGH_PERFORMANCE_MODE = "FALSE",
parameter PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
parameter PCLK_PERIOD = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"
parameter SENS_PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
parameter SENS_PCLK_PERIOD = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"
parameter CLKFBOUT_MULT_SENSOR = 8, // 100 MHz --> 800 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
parameter DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter REF_JITTER1 = 0.010, // Expectet jitter on CLKIN1 (0.000..0.999)
parameter REF_JITTER2 = 0.010,
parameter SS_EN = "FALSE", // Enables Spread Spectrum mode
parameter SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
parameter SS_MOD_PERIOD = 10000 // integer 4000-40000 - SS modulation period in ns
parameter SENS_DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter SENS_REF_JITTER1 = 0.010, // Expectet jitter on CLKIN1 (0.000..0.999)
parameter SENS_REF_JITTER2 = 0.010,
parameter SENS_SS_EN = "FALSE", // Enables Spread Spectrum mode
parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
parameter SENS_SS_MOD_PERIOD = 10000 // integer 4000-40000 - SS modulation period in ns
)(
input rst,
......@@ -328,8 +328,8 @@ module sens_parallel12 #(
.PXD_IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.PXD_IOSTANDARD (PXD_IOSTANDARD),
.PXD_SLEW (PXD_SLEW),
.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE)
.REFCLK_FREQUENCY (SENS_REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE (SENS_HIGH_PERFORMANCE_MODE)
) pxd_pxd0_i (
.pxd (pxd[0]), // inout
.pxd_out (xfpgatdi), // input
......@@ -353,8 +353,8 @@ module sens_parallel12 #(
.PXD_IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.PXD_IOSTANDARD (PXD_IOSTANDARD),
.PXD_SLEW (PXD_SLEW),
.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE)
.REFCLK_FREQUENCY (SENS_REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE (SENS_HIGH_PERFORMANCE_MODE)
) pxd_pxd1_i (
.pxd (pxd[1]), // inout
.pxd_out (1'b0), // input
......@@ -381,8 +381,8 @@ module sens_parallel12 #(
.PXD_IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.PXD_IOSTANDARD (PXD_IOSTANDARD),
.PXD_SLEW (PXD_SLEW),
.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE)
.REFCLK_FREQUENCY (SENS_REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE (SENS_HIGH_PERFORMANCE_MODE)
) pxd_pxd1_i (
.pxd (pxd[i]), // inout
.pxd_out (1'b0), // input
......@@ -408,8 +408,8 @@ module sens_parallel12 #(
.PXD_IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.PXD_IOSTANDARD (PXD_IOSTANDARD),
.PXD_SLEW (PXD_SLEW),
.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE)
.REFCLK_FREQUENCY (SENS_REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE (SENS_HIGH_PERFORMANCE_MODE)
) pxd_hact_i (
.pxd (hact), // inout
.pxd_out (1'b0), // input
......@@ -433,8 +433,8 @@ module sens_parallel12 #(
.PXD_IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.PXD_IOSTANDARD (PXD_IOSTANDARD),
.PXD_SLEW (PXD_SLEW),
.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE)
.REFCLK_FREQUENCY (SENS_REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE (SENS_HIGH_PERFORMANCE_MODE)
) pxd_vact_i (
.pxd (vact), // inout
.pxd_out (1'b0), // input
......@@ -458,8 +458,8 @@ module sens_parallel12 #(
.PXD_IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.PXD_IOSTANDARD (PXD_IOSTANDARD),
.PXD_SLEW (PXD_SLEW),
.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE)
.REFCLK_FREQUENCY (SENS_REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE (SENS_HIGH_PERFORMANCE_MODE)
) pxd_clock_i (
.pxclk (bpf), // inout
.pxclk_out (1'b0), // input
......@@ -555,11 +555,11 @@ module sens_parallel12 #(
// generate phase-shifterd pixel clock (and 2x version) from either the internal clock (that is output to the sensor) or from the clock
// received from the sensor (may need to reset MMCM after resetting sensor)
mmcm_phase_cntr #(
.PHASE_WIDTH (PHASE_WIDTH),
.CLKIN_PERIOD (PCLK_PERIOD),
.BANDWIDTH (BANDWIDTH),
.PHASE_WIDTH (SENS_PHASE_WIDTH),
.CLKIN_PERIOD (SENS_PCLK_PERIOD),
.BANDWIDTH (SENS_BANDWIDTH),
.CLKFBOUT_MULT_F (CLKFBOUT_MULT_SENSOR), //8
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE_SENSOR),
.CLKOUT0_PHASE (IPCLK_PHASE),
.CLKOUT1_PHASE (IPCLK2X_PHASE),
......@@ -584,11 +584,11 @@ module sens_parallel12 #(
// .CLKOUT5_DIVIDE(1),
// .CLKOUT6_DIVIDE(1),
.COMPENSATION ("ZHOLD"),
.REF_JITTER1 (REF_JITTER1),
.REF_JITTER2 (REF_JITTER2),
.SS_EN (SS_EN),
.SS_MODE (SS_MODE),
.SS_MOD_PERIOD (SS_MOD_PERIOD),
.REF_JITTER1 (SENS_REF_JITTER1),
.REF_JITTER2 (SENS_REF_JITTER2),
.SS_EN (SENS_SS_EN),
.SS_MODE (SENS_SS_MODE),
.SS_MOD_PERIOD (SENS_SS_MOD_PERIOD),
.STARTUP_WAIT ("FALSE")
) mmcm_phase_cntr_i (
.clkin1 (pclk), // input
......
sensor/sensor_channel.v
View file @ 6f36f6d1
......@@ -135,25 +135,25 @@ module sensor_channel#(
parameter PXD_IBUF_LOW_PWR = "TRUE",
parameter PXD_IOSTANDARD = "DEFAULT",
parameter PXD_SLEW = "SLOW",
parameter real REFCLK_FREQUENCY = 300.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter real SENS_REFCLK_FREQUENCY = 300.0,
parameter SENS_HIGH_PERFORMANCE_MODE = "FALSE",
parameter PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
parameter PCLK_PERIOD = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"
parameter SENS_PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
parameter SENS_PCLK_PERIOD = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"
parameter CLKFBOUT_MULT_SENSOR = 8, // 100 MHz --> 800 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
parameter DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter REF_JITTER1 = 0.010, // Expectet jitter on CLKIN1 (0.000..0.999)
parameter REF_JITTER2 = 0.010,
parameter SS_EN = "FALSE", // Enables Spread Spectrum mode
parameter SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
parameter SS_MOD_PERIOD = 10000 // integer 4000-40000 - SS modulation period in ns
parameter SENS_DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter SENS_REF_JITTER1 = 0.010, // Expectet jitter on CLKIN1 (0.000..0.999)
parameter SENS_REF_JITTER2 = 0.010,
parameter SENS_SS_EN = "FALSE", // Enables Spread Spectrum mode
parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
parameter SENS_SS_MOD_PERIOD = 10000 // integer 4000-40000 - SS modulation period in ns
) (
input rst,
......@@ -402,21 +402,21 @@ module sensor_channel#(
.PXD_IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.PXD_IOSTANDARD (PXD_IOSTANDARD),
.PXD_SLEW (PXD_SLEW),
.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.PHASE_WIDTH (PHASE_WIDTH),
.PCLK_PERIOD (PCLK_PERIOD),
.BANDWIDTH (BANDWIDTH),
.SENS_REFCLK_FREQUENCY (SENS_REFCLK_FREQUENCY),
.SENS_HIGH_PERFORMANCE_MODE (SENS_HIGH_PERFORMANCE_MODE),
.SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
.SENS_PCLK_PERIOD (SENS_PCLK_PERIOD),
.SENS_BANDWIDTH (SENS_BANDWIDTH),
.CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR),
.CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR),
.IPCLK_PHASE (IPCLK_PHASE),
.IPCLK2X_PHASE (IPCLK2X_PHASE),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.REF_JITTER1 (REF_JITTER1),
.REF_JITTER2 (REF_JITTER2),
.SS_EN (SS_EN),
.SS_MODE (SS_MODE),
.SS_MOD_PERIOD (SS_MOD_PERIOD)
.SENS_DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE),
.SENS_REF_JITTER1 (SENS_REF_JITTER1),
.SENS_REF_JITTER2 (SENS_REF_JITTER2),
.SENS_SS_EN (SENS_SS_EN),
.SENS_SS_MODE (SENS_SS_MODE),
.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD)
) sens_parallel12_i (
.rst (rst), // input
.pclk (pclk), // input
......
sensor/sensors393.v
View file @ 6f36f6d1
......@@ -152,12 +152,12 @@ module sensors393 #(
parameter PXD_IBUF_LOW_PWR = "TRUE",
parameter PXD_IOSTANDARD = "DEFAULT",
parameter PXD_SLEW = "SLOW",
parameter real REFCLK_FREQUENCY = 300.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter real SENS_REFCLK_FREQUENCY = 300.0,
parameter SENS_HIGH_PERFORMANCE_MODE = "FALSE",
parameter PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
parameter PCLK_PERIOD = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"
parameter SENS_PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
parameter SENS_PCLK_PERIOD = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"
parameter CLKFBOUT_MULT_SENSOR = 8, // 100 MHz --> 800 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
......@@ -165,16 +165,18 @@ module sensors393 #(
parameter IPCLK2X_PHASE = 0.000,
parameter DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter REF_JITTER1 = 0.010, // Expectet jitter on CLKIN1 (0.000..0.999)
parameter REF_JITTER2 = 0.010,
parameter SS_EN = "FALSE", // Enables Spread Spectrum mode
parameter SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
parameter SS_MOD_PERIOD = 10000 // integer 4000-40000 - SS modulation period in ns
parameter SENS_DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter SENS_REF_JITTER1 = 0.010, // Expectet jitter on CLKIN1 (0.000..0.999)
parameter SENS_REF_JITTER2 = 0.010,
parameter SENS_SS_EN = "FALSE", // Enables Spread Spectrum mode
parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
parameter SENS_SS_MOD_PERIOD = 10000 // integer 4000-40000 - SS modulation period in ns
) (
input rst,
// will generate it here
// will generate it here
input ref_clk, // IODELAY calibration
input dly_rst,
input pclk, // global clock input, pixel rate (96MHz for MT9P006)
input pclk2x, // global clock input, double pixel rate (192MHz for MT9P006)
......@@ -404,27 +406,27 @@ module sensors393 #(
.SENSOR_DATA_WIDTH (SENSOR_DATA_WIDTH),
.SENSOR_FIFO_2DEPTH (SENSOR_FIFO_2DEPTH),
.SENSOR_FIFO_DELAY (SENSOR_FIFO_DELAY),
.IODELAY_GRP ("IODELAY_SENSOR_12"),
.IODELAY_GRP ((i & 2)?"IODELAY_SENSOR_34":"IODELAY_SENSOR_12"),
.IDELAY_VALUE (IDELAY_VALUE),
.PXD_DRIVE (PXD_DRIVE),
.PXD_IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.PXD_IOSTANDARD (PXD_IOSTANDARD),
.PXD_SLEW (PXD_SLEW),
.REFCLK_FREQUENCY (REFCLK_FREQUENCY),
.HIGH_PERFORMANCE_MODE (HIGH_PERFORMANCE_MODE),
.PHASE_WIDTH (PHASE_WIDTH),
.PCLK_PERIOD (PCLK_PERIOD),
.BANDWIDTH (BANDWIDTH),
.SENS_REFCLK_FREQUENCY (SENS_REFCLK_FREQUENCY),
.SENS_HIGH_PERFORMANCE_MODE (SENS_HIGH_PERFORMANCE_MODE),
.SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
.SENS_PCLK_PERIOD (SENS_PCLK_PERIOD),
.SENS_BANDWIDTH (SENS_BANDWIDTH),
.CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR),
.CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR),
.IPCLK_PHASE (IPCLK_PHASE),
.IPCLK2X_PHASE (IPCLK2X_PHASE),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.REF_JITTER1 (REF_JITTER1),
.REF_JITTER2 (REF_JITTER2),
.SS_EN (SS_EN),
.SS_MODE (SS_MODE),
.SS_MOD_PERIOD (SS_MOD_PERIOD)
.SENS_DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE),
.SENS_REF_JITTER1 (SENS_REF_JITTER1),
.SENS_REF_JITTER2 (SENS_REF_JITTER2),
.SENS_SS_EN (SENS_SS_EN),
.SENS_SS_MODE (SENS_SS_MODE),
.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD)
) sensor_channel_i (
.rst (rst), // input
.pclk (pclk), // input
......@@ -562,11 +564,29 @@ module sensors393 #(
.rq_out (status_rq), // output
.start_out (status_start) // input
);
idelay_ctrl# (
.IODELAY_GRP("IODELAY_SENSOR_12")
) idelay_ctrl_sensor12_i (
.refclk(ref_clk),
.rst(dly_rst), //rst || dly_rst
.rdy()
);
idelay_ctrl# (
.IODELAY_GRP("IODELAY_SENSOR_34")
) idelay_ctrl_sensor34_i (
.refclk(ref_clk),
.rst(dly_rst), //rst || dly_rst
.rdy()
);
endmodule
// TODO: if that works, move it to util_modules
/*
.IODELAY_GRP ((i & 2)?"IODELAY_SENSOR_34":"IODELAY_SENSOR_12"),
module my_alias #(
parameter WIDTH=1
) (a,a);
......
x393.v
View file @ 6f36f6d1
......@@ -149,6 +149,7 @@ module x393 #(
reg mcntrl_axird_selected_regen; // mcntrl_axird_selected (set at axird_start_burst) delayed when ren is active, then when regen (normally 2 cycles)
wire mclk; // global clock, memory controller, command/status network (currently 200MHz)
wire ref_clk; // global clock for idelay_ctrl calibration
wire hclk; // global clock, axi_hp (150MHz) derived from aclk_in = 50MHz
wire [11:0] tmp_debug;
......@@ -202,9 +203,9 @@ module x393 #(
wire status_membridge_rq; // membridge (afi to ddr3) status request
wire status_membridge_start; //membridge (afi to ddr3) status packet transfer start (currently with 0 latency from status_root_rq)
wire [7:0] status_other_ad = 0; // Other status byte-wide address/data
wire status_other_rq = 0; // Other status request
wire status_other_start; // SuppressThisWarning VEditor ****** Other status packet transfer start (currently with 0 latency from status_root_rq)
// wire [7:0] status_other_ad = 0; // Other status byte-wide address/data
// wire status_other_rq = 0; // Other status request
// wire status_other_start; // SuppressThisWarning VEditor ****** Other status packet transfer start (currently with 0 latency from status_root_rq)
wire [7:0] status_test01_ad; // Test module status byte-wide address/data
......@@ -212,14 +213,50 @@ module x393 #(
wire status_test01_start; // Test module status packet transfer start (currently with 0 latency from status_root_rq)
wire [7:0] status_sensor_ad; // Other status byte-wide address/data
wire status_sensor_rq; // Other status request
wire status_sensor_start; // S uppressThisWarning VEditor ****** Other status packet transfer start (currently with 0 latency from status_root_rq)
wire [7:0] status_compressor_ad; // Other status byte-wide address/data
wire status_compressor_rq; // Other status request
wire status_compressor_start; // S uppressThisWarning VEditor ****** Other status packet transfer start (currently with 0 latency from status_root_rq)
wire [7:0] status_sequencer_ad; // Other status byte-wide address/data
wire status_sequencer_rq; // Other status request
wire status_sequencer_start; // S uppressThisWarning VEditor ****** Other status packet transfer start (currently with 0 latency from status_root_rq)
wire [7:0] status_logger_ad; // Other status byte-wide address/data
wire status_logger_rq; // Other status request
wire status_logger_start; // S uppressThisWarning VEditor ****** Other status packet transfer start (currently with 0 latency from status_root_rq)
wire [7:0] status_timing_ad; // Other status byte-wide address/data
wire status_timing_rq; // Other status request
wire status_timing_start; // S uppressThisWarning VEditor ****** Other status packet transfer start (currently with 0 latency from status_root_rq)
// Insert register layer if needed
wire [7:0] cmd_mcontr_ad;
wire cmd_mcontr_stb;
wire [7:0] cmd_test01_ad;
wire cmd_test01_stb;
wire [7:0] cmd_membridge_ad;
wire cmd_membridge_stb;
reg [7:0] cmd_mcontr_ad;
reg cmd_mcontr_stb;
reg [7:0] cmd_test01_ad;
reg cmd_test01_stb;
reg [7:0] cmd_membridge_ad;
reg cmd_membridge_stb;
reg [7:0] cmd_sensor_ad;
reg cmd_sensor_stb;
reg [7:0] cmd_compressor_ad;
reg cmd_compressor_stb;
reg [7:0] cmd_sequencer_ad;
reg cmd_sequencer_stb;
reg [7:0] cmd_logger_ad;
reg cmd_logger_stb;
reg [7:0] cmd_timing_ad;
reg cmd_timing_stb;
// membridge
wire frame_start_chn1; // input
......@@ -296,12 +333,31 @@ module x393 #(
assign comb_rst=~frst[0] | frst[1];
// insert register layers if needed
assign cmd_mcontr_ad= cmd_root_ad;
assign cmd_mcontr_stb=cmd_root_stb;
assign cmd_test01_ad= cmd_root_ad;
assign cmd_test01_stb=cmd_root_stb;
assign cmd_membridge_ad= cmd_root_ad;
assign cmd_membridge_stb=cmd_root_stb;
always @ (posedge mclk) begin
cmd_mcontr_ad <= cmd_root_ad;
cmd_mcontr_stb <= cmd_root_stb;
cmd_test01_ad <= cmd_root_ad;
cmd_test01_stb <= cmd_root_stb;
cmd_membridge_ad <= cmd_root_ad;
cmd_membridge_stb <= cmd_root_stb;
cmd_sensor_ad <= cmd_root_ad;
cmd_sensor_stb <= cmd_root_stb;
cmd_compressor_ad <= cmd_root_ad;
cmd_compressor_stb <= cmd_root_stb;
cmd_sequencer_ad <= cmd_root_ad;
cmd_sequencer_stb <= cmd_root_stb;
cmd_logger_ad <= cmd_root_ad;
cmd_logger_stb <= cmd_root_stb;
cmd_timing_ad <= cmd_root_ad;
cmd_timing_stb <= cmd_root_stb;
end
// For now - connect status_test01 to status_other, if needed - increase number of multiplexer inputs)
// assign status_other_ad = status_test01_ad;
......@@ -593,12 +649,13 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
);
// mux status info from the memory controller and other modules
status_router4 status_router4_top_i (
status_router8 status_router8_top_i (
.rst (axi_rst), // input
.clk (mclk), // input
.db_in0 (status_mcontr_ad), // input[7:0]
.rq_in0 (status_mcontr_rq), // input
.start_in0 (status_mcontr_start), // output
.db_in1 (status_test01_ad), // input[7:0]
.rq_in1 (status_test01_rq), // input
.start_in1 (status_test01_start), // output
......@@ -607,9 +664,29 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.rq_in2 (status_membridge_rq), // input
.start_in2 (status_membridge_start), // output
.db_in3 (status_other_ad), // input[7:0]
.rq_in3 (status_other_rq), // input
.start_in3 (status_other_start), // output
// .db_in3 (status_other_ad), // input[7:0]
// .rq_in3 (status_other_rq), // input
// .start_in3 (status_other_start), // output
.db_in3 (status_sensor_ad), // input[7:0]
.rq_in3 (status_sensor_rq), // input
.start_in3 (status_sensor_start), // output
.db_in4 (status_compressor_ad), // input[7:0]
.rq_in4 (status_compressor_rq), // input
.start_in4 (status_compressor_start), // output
.db_in5 (status_sequencer_ad), // input[7:0]
.rq_in5 (status_sequencer_rq), // input
.start_in5 (status_sequencer_start), // output
.db_in6 (status_logger_ad), // input[7:0]
.rq_in6 (status_logger_rq), // input
.start_in6 (status_logger_start), // output
.db_in7 (status_timing_ad), // input[7:0]
.rq_in7 (status_timing_rq), // input
.start_in7 (status_timing_start), // output
.db_out (status_root_ad), // output[7:0]
.rq_out (status_root_rq), // output
......@@ -750,6 +827,7 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.rst_in (axi_rst), // input
.clk_in (axi_aclk), // == axird_bram_rclk SuppressThisWarning VivadoSynthesis: [Synth 8-3295] tying undriven pin #mcntrl393_i:clk_in to constant 0
.mclk (mclk), // output
.ref_clk (ref_clk), // output
.cmd_ad (cmd_mcontr_ad), // input[7:0]
.cmd_stb (cmd_mcontr_stb), // input
.status_ad (status_mcontr_ad[7:0]), // output[7:0]
......@@ -965,89 +1043,208 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.afi_rdissuecap1en (afi0_rdissuecap1en) // output
);
/*
{
frst[3]?{
16'b0,
1'b1, // 1
1'b0, //MEMCLK, // 1/0? - external clock
1'b0, //
1'b0, //
frst[1], // 0 (follows)
fclk[1:0], // 2'bXX (toggle)
axird_dev_busy, // 0
sensors393 #(
.SENSOR_GROUP_ADDR (SENSOR_GROUP_ADDR),
.SENSOR_BASE_INC (SENSOR_BASE_INC),
.HIST_SAXI_ADDR_REL (HIST_SAXI_ADDR_REL),
.HIST_SAXI_MODE_ADDR_REL (HIST_SAXI_MODE_ADDR_REL),
.SENSI2C_STATUS_REG_BASE (SENSI2C_STATUS_REG_BASE),
.SENSI2C_STATUS_REG_INC (SENSI2C_STATUS_REG_INC),
.SENSI2C_STATUS_REG_REL (SENSI2C_STATUS_REG_REL),
.SENSIO_STATUS_REG_REL (SENSIO_STATUS_REG_REL),
.SENSOR_NUM_HISTOGRAM (SENSOR_NUM_HISTOGRAM),
.HISTOGRAM_RAM_MODE (HISTOGRAM_RAM_MODE),
.SENS_GAMMA_NUM_CHN (SENS_GAMMA_NUM_CHN),
.SENS_GAMMA_BUFFER (SENS_GAMMA_BUFFER),
.SENSOR_CTRL_RADDR (SENSOR_CTRL_RADDR),
.SENSOR_CTRL_ADDR_MASK (SENSOR_CTRL_ADDR_MASK),
.SENSOR_MODE_WIDTH (SENSOR_MODE_WIDTH),
.SENSOR_HIST_EN_BIT (SENSOR_HIST_EN_BIT),
.SENSOR_HIST_NRST_BIT (SENSOR_HIST_NRST_BIT),
.SENSOR_16BIT_BIT (SENSOR_16BIT_BIT),
.SENSI2C_CTRL_RADDR (SENSI2C_CTRL_RADDR),
.SENSI2C_CTRL_MASK (SENSI2C_CTRL_MASK),
.SENSI2C_CTRL (SENSI2C_CTRL),
.SENSI2C_STATUS (SENSI2C_STATUS),
.SENS_SYNC_RADDR (SENS_SYNC_RADDR),
.SENS_SYNC_MASK (SENS_SYNC_MASK),
.SENS_SYNC_MULT (SENS_SYNC_MULT),
.SENS_SYNC_LATE (SENS_SYNC_LATE),
.SENS_GAMMA_RADDR (SENS_GAMMA_RADDR),
.SENS_GAMMA_ADDR_MASK (SENS_GAMMA_ADDR_MASK),
.SENS_GAMMA_CTRL (SENS_GAMMA_CTRL),
.SENS_GAMMA_ADDR_DATA (SENS_GAMMA_ADDR_DATA),
.SENS_GAMMA_HEIGHT01 (SENS_GAMMA_HEIGHT01),
.SENS_GAMMA_HEIGHT2 (SENS_GAMMA_HEIGHT2),
.SENS_GAMMA_MODE_WIDTH (SENS_GAMMA_MODE_WIDTH),
.SENS_GAMMA_MODE_BAYER (SENS_GAMMA_MODE_BAYER),
.SENS_GAMMA_MODE_PAGE (SENS_GAMMA_MODE_PAGE),
.SENS_GAMMA_MODE_EN (SENS_GAMMA_MODE_EN),
.SENS_GAMMA_MODE_REPET (SENS_GAMMA_MODE_REPET),
.SENS_GAMMA_MODE_TRIG (SENS_GAMMA_MODE_TRIG),
.SENSIO_RADDR (SENSIO_RADDR),
.SENSIO_ADDR_MASK (SENSIO_ADDR_MASK),
.SENSIO_CTRL (SENSIO_CTRL),
.SENS_CTRL_MRST (SENS_CTRL_MRST),
.SENS_CTRL_ARST (SENS_CTRL_ARST),
.SENS_CTRL_ARO (SENS_CTRL_ARO),
.SENS_CTRL_RST_MMCM (SENS_CTRL_RST_MMCM),
.SENS_CTRL_EXT_CLK (SENS_CTRL_EXT_CLK),
.SENS_CTRL_LD_DLY (SENS_CTRL_LD_DLY),
.SENS_CTRL_QUADRANTS (SENS_CTRL_QUADRANTS),
.SENSIO_STATUS (SENSIO_STATUS),
.SENSIO_JTAG (SENSIO_JTAG),
.SENS_JTAG_PGMEN (SENS_JTAG_PGMEN),
.SENS_JTAG_PROG (SENS_JTAG_PROG),
.SENS_JTAG_TCK (SENS_JTAG_TCK),
.SENS_JTAG_TMS (SENS_JTAG_TMS),
.SENS_JTAG_TDI (SENS_JTAG_TDI),
.SENSIO_WIDTH (SENSIO_WIDTH),
.SENSIO_DELAYS (SENSIO_DELAYS),
.SENSI2C_ABS_RADDR (SENSI2C_ABS_RADDR),
.SENSI2C_REL_RADDR (SENSI2C_REL_RADDR),
.SENSI2C_ADDR_MASK (SENSI2C_ADDR_MASK),
.HISTOGRAM_RADDR0 (HISTOGRAM_RADDR0),
.HISTOGRAM_RADDR1 (HISTOGRAM_RADDR1),
.HISTOGRAM_RADDR2 (HISTOGRAM_RADDR2),
.HISTOGRAM_RADDR3 (HISTOGRAM_RADDR3),
.HISTOGRAM_ADDR_MASK (HISTOGRAM_ADDR_MASK),
.HISTOGRAM_LEFT_TOP (HISTOGRAM_LEFT_TOP),
.HISTOGRAM_WIDTH_HEIGHT (HISTOGRAM_WIDTH_HEIGHT),
.SENSI2C_DRIVE (SENSI2C_DRIVE),
.SENSI2C_IBUF_LOW_PWR (SENSI2C_IBUF_LOW_PWR),
.SENSI2C_IOSTANDARD (SENSI2C_IOSTANDARD),
.SENSI2C_SLEW (SENSI2C_SLEW),
.SENSOR_DATA_WIDTH (SENSOR_DATA_WIDTH),
.SENSOR_FIFO_2DEPTH (SENSOR_FIFO_2DEPTH),
.SENSOR_FIFO_DELAY (SENSOR_FIFO_DELAY),
.HIST_SAXI_ADDR_MASK (HIST_SAXI_ADDR_MASK),
.HIST_SAXI_MODE_WIDTH (HIST_SAXI_MODE_WIDTH),
.HIST_SAXI_EN (HIST_SAXI_EN),
.HIST_SAXI_NRESET (HIST_SAXI_NRESET),
.HIST_CONFIRM_WRITE (HIST_CONFIRM_WRITE),
.HIST_SAXI_AWCACHE (HIST_SAXI_AWCACHE),
.HIST_SAXI_MODE_ADDR_MASK (HIST_SAXI_MODE_ADDR_MASK),
.NUM_FRAME_BITS (NUM_FRAME_BITS),
.SENS_SYNC_FBITS (SENS_SYNC_FBITS),
.SENS_SYNC_LBITS (SENS_SYNC_LBITS),
.SENS_SYNC_LATE_DFLT (SENS_SYNC_LATE_DFLT),
.SENS_SYNC_MINBITS (SENS_SYNC_MINBITS),
.SENS_SYNC_MINPER (SENS_SYNC_MINPER),
.IDELAY_VALUE (IDELAY_VALUE),
.PXD_DRIVE (PXD_DRIVE),
.PXD_IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
.PXD_IOSTANDARD (PXD_IOSTANDARD),
.PXD_SLEW (PXD_SLEW),
.SENS_REFCLK_FREQUENCY (SENS_REFCLK_FREQUENCY),
.SENS_HIGH_PERFORMANCE_MODE (SENS_HIGH_PERFORMANCE_MODE),
.SENS_PHASE_WIDTH (SENS_PHASE_WIDTH),
.SENS_PCLK_PERIOD (SENS_PCLK_PERIOD),
.SENS_BANDWIDTH (SENS_BANDWIDTH),
.CLKFBOUT_MULT_SENSOR (CLKFBOUT_MULT_SENSOR),
.CLKFBOUT_PHASE_SENSOR (CLKFBOUT_PHASE_SENSOR),
.IPCLK_PHASE (IPCLK_PHASE),
.IPCLK2X_PHASE (IPCLK2X_PHASE),
.SENS_DIVCLK_DIVIDE (SENS_DIVCLK_DIVIDE),
.SENS_REF_JITTER1 (SENS_REF_JITTER1),
.SENS_REF_JITTER2 (SENS_REF_JITTER2),
.SENS_SS_EN (SENS_SS_EN),
.SENS_SS_MODE (SENS_SS_MODE),
.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD)
) sensors393_i (
.rst (axi_rst), // input
.pclk (), // input
.pclk2x (), // input
.ref_clk (ref_clk), // input
.dly_rst (axi_rst), // input
.mclk (mclk), // input
.cmd_ad_in (cmd_sensor_ad), // input[7:0]
.cmd_stb_in (cmd_sensor_stb), // input
.status_ad (status_sensor_ad), // output[7:0]
.status_rq (status_sensor_rq), // output
.status_start (status_sensor_start), // input
.sns1_dp(), // inout[7:0]
.sns1_dn(), // inout[7:0]
.sns1_clkp(), // inout
.sns1_clkn(), // inout
.sns1_scl(), // inout
.sns1_sda(), // inout
.sns1_ctl(), // inout
.sns1_pg(), // inout
.sns2_dp(), // inout[7:0]
.sns2_dn(), // inout[7:0]
.sns2_clkp(), // inout
.sns2_clkn(), // inout
.sns2_scl(), // inout
.sns2_sda(), // inout
.sns2_ctl(), // inout
.sns2_pg(), // inout
.sns3_dp(), // inout[7:0]
.sns3_dn(), // inout[7:0]
.sns3_clkp(), // inout
.sns3_clkn(), // inout
.sns3_scl(), // inout
.sns3_sda(), // inout
.sns3_ctl(), // inout
.sns3_pg(), // inout
.sns4_dp(), // inout[7:0]
.sns4_dn(), // inout[7:0]
.sns4_clkp(), // inout
.sns4_clkn(), // inout
.sns4_scl(), // inout
.sns4_sda(), // inout
.sns4_ctl(), // inout
.sns4_pg(), // inout
.rpage_set0(), // input
.rpage_next0(), // input
.buf_rd0(), // input
.buf_dout0(), // output[63:0]
.rpage_set1(), // input
.rpage_next1(), // input
.buf_rd1(), // input
.buf_dout1(), // output[63:0]
.rpage_set2(), // input
.rpage_next2(), // input
.buf_rd2(), // input
.buf_dout2(), // output[63:0]
.rpage_set3(), // input
.rpage_next3(), // input
.buf_rd3(), // input
.buf_dout3(), // output[63:0]
.trigger_mode(), // input
.trig_in(), // input[3:0]
.sof_out_pclk(), // output[3:0]
.eof_out_pclk(), // output[3:0]
.sof_out_mclk(), // output[3:0]
.sof_late_mclk(), // output[3:0]
.frame_num0(), // input[3:0]
.frame_num1(), // input[3:0]
.frame_num2(), // input[3:0]
.frame_num3(), // input[3:0]
.aclk(), // input
.saxi_awaddr(), // output[31:0]
.saxi_awvalid(), // output
.saxi_awready(), // input
.saxi_awid(), // output[5:0]
.saxi_awlock(), // output[1:0]
.saxi_awcache(), // output[3:0]
.saxi_awprot(), // output[2:0]
.saxi_awlen(), // output[3:0]
.saxi_awsize(), // output[1:0]
.saxi_awburst(), // output[1:0]
.saxi_awqos(), // output[3:0]
.saxi_wdata(), // output[31:0]
.saxi_wvalid(), // output
.saxi_wready(), // input
.saxi_wid(), // output[5:0]
.saxi_wlast(), // output
.saxi_wstrb(), // output[3:0]
.saxi_bvalid(), // input
.saxi_bready(), // output
.saxi_bid(), // input[5:0]
.saxi_bresp() // input[1:0]
);
4'b0, // 4'b0
tmp_debug[11:8], // 4'b0
tmp_debug[7:4], // 4'b0111 -> 4'bx00x
// dly_addr[1], 0
// dly_addr[0], 0
// clkin_stopped_mmcm, 0
// clkfb_stopped_mmcm, 0
tmp_debug[3:0], // 4'b1100 -> 4'bxx00
// ddr_rst, 1 1 4000609c -> 0 , 40006098 -> 1
// rst_in, 0 0
// dci_rst, 0 1
// dly_rst 0 1
4'h0,
// phy_locked_mmcm, // 1 1
// phy_locked_pll, // 1 1
// phy_dci_ready, // 1 0
// phy_dly_ready, // 1 0
4'h0
// locked_mmcm, // 1 1
// locked_pll, // 1 1
// dci_ready, // 1 0
// dly_ready // 1 0
}:{
waddr_wcount[3:0],
waddr_rcount[3:0],
waddr_num_in_fifo[3:0],
wdata_wcount[3:0],
wdata_rcount[3:0],
wdata_num_in_fifo[3:0],
wresp_wcount[3:0],
wresp_rcount[3:0],
wresp_num_in_fifo[3:0],
wleft[3:0],
wlength[3:0],
wlen_in_dbg[3:0]
},
//ps_out[7:4], // 4'b0 input[7:0] 4'b0
//ps_out[3:0], // 4'b0 input[7:0] 4'b0
1'b0,
waddr_under_r,
wdata_under_r,
wresp_under_r,
1'b0,
waddr_over_r,
wdata_over_r,
wresp_over_r, // ???
1'b0, // run_busy, // input // 0
1'b0, //locked, // input // 1
1'b0, // ps_rdy, // input // 1
axi_arready, // 1
axi_awready, // 1
axi_wready, // 1 - sometimes gets stuck with 0 (axi_awready==1) ? TODO: Add timeout
fifo_rst, // fclk[0], // 0/1
axi_rst_pre //axi_rst // 0
};
*/
axibram_write #(
.ADDRESS_BITS(AXI_WR_ADDR_BITS)
) axibram_write_i ( //SuppressThisWarning ISExst Output port <bram_wstb> of the instance <axibram_write_i> is unconnected or connected to loadless signal.
......
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