Skip to content
Projects
Groups
Snippets
Help
Loading...
Help
Submit feedback
Contribute to GitLab
Sign in
Toggle navigation
X
x393
Project
Project
Details
Activity
Releases
Cycle Analytics
Repository
Repository
Files
Commits
Branches
Tags
Contributors
Graph
Compare
Charts
Members
Members
Collapse sidebar
Close sidebar
Activity
Graph
Charts
Commits
Open sidebar
Elphel
x393
Commits
6ad657e2
Commit
6ad657e2
authored
Apr 27, 2014
by
Andrey Filippov
Browse files
Options
Browse Files
Download
Email Patches
Plain Diff
Added IODELAY_GROUP synthesis attribute
parent
63e3b7c0
Changes
3
Hide whitespace changes
Inline
Side-by-side
Showing
3 changed files
with
22 additions
and
13 deletions
+22
-13
idelay_ctrl.v
phy/wrap/idelay_ctrl.v
+5
-1
idelay_fine_pipe.v
phy/wrap/idelay_fine_pipe.v
+8
-5
odelay_fine_pipe.v
phy/wrap/odelay_fine_pipe.v
+9
-7
No files found.
phy/wrap/idelay_ctrl.v
View file @
6ad657e2
...
@@ -20,12 +20,16 @@
...
@@ -20,12 +20,16 @@
*******************************************************************************/
*******************************************************************************/
`timescale
1
ns
/
1
ps
`timescale
1
ns
/
1
ps
module
idelay_ctrl
(
module
idelay_ctrl
//SuppressWarnings VEditor - IODELAY_GRP used in (* *) construnt
#
(
parameter
IODELAY_GRP
=
"IODELAY_MEMORY"
)
(
input
refclk
,
input
refclk
,
input
rst
,
input
rst
,
output
rdy
output
rdy
)
;
)
;
(
*
IODELAY_GROUP
=
IODELAY_GRP
*
)
IDELAYCTRL
idelay_ctrl_i
(
IDELAYCTRL
idelay_ctrl_i
(
.
RDY
(
rdy
)
,
.
RDY
(
rdy
)
,
.
REFCLK
(
refclk
)
,
.
REFCLK
(
refclk
)
,
...
...
phy/wrap/idelay_fine_pipe.v
View file @
6ad657e2
...
@@ -20,7 +20,13 @@
...
@@ -20,7 +20,13 @@
*******************************************************************************/
*******************************************************************************/
`timescale
1
ns
/
1
ps
`timescale
1
ns
/
1
ps
module
idelay_fine_pipe
(
module
idelay_fine_pipe
//SuppressWarnings VEditor - IODELAY_GRP used in (* *) construnt
#
(
parameter
IODELAY_GRP
=
"IODELAY_MEMORY"
,
parameter
integer
DELAY_VALUE
=
0
,
parameter
real
REFCLK_FREQUENCY
=
200.0
,
parameter
HIGH_PERFORMANCE_MODE
=
"FALSE"
)
(
input
clk
,
input
clk
,
input
rst
,
input
rst
,
input
set
,
input
set
,
...
@@ -29,9 +35,6 @@ module idelay_fine_pipe(
...
@@ -29,9 +35,6 @@ module idelay_fine_pipe(
input
data_in
,
input
data_in
,
output
data_out
output
data_out
)
;
)
;
parameter
integer
DELAY_VALUE
=
0
;
parameter
real
REFCLK_FREQUENCY
=
200.0
;
parameter
HIGH_PERFORMANCE_MODE
=
"FALSE"
;
reg
[
2
:
0
]
fdly_pre
=
DELAY_VALUE
[
2
:
0
]
,
fdly
=
DELAY_VALUE
[
2
:
0
]
;
reg
[
2
:
0
]
fdly_pre
=
DELAY_VALUE
[
2
:
0
]
,
fdly
=
DELAY_VALUE
[
2
:
0
]
;
always
@
(
posedge
clk
or
posedge
rst
)
begin
always
@
(
posedge
clk
or
posedge
rst
)
begin
...
@@ -40,7 +43,7 @@ module idelay_fine_pipe(
...
@@ -40,7 +43,7 @@ module idelay_fine_pipe(
if
(
rst
)
fdly
<=
DELAY_VALUE
[
2
:
0
]
;
if
(
rst
)
fdly
<=
DELAY_VALUE
[
2
:
0
]
;
else
if
(
set
)
fdly
<=
fdly_pre
;
else
if
(
set
)
fdly
<=
fdly_pre
;
end
end
IDELAYE2_FINEDELAY
(
*
IODELAY_GROUP
=
IODELAY_GRP
*
)
IDELAYE2_FINEDELAY
#(
#(
.
CINVCTRL_SEL
(
"FALSE"
)
,
.
CINVCTRL_SEL
(
"FALSE"
)
,
.
DELAY_SRC
(
"IDATAIN"
)
,
.
DELAY_SRC
(
"IDATAIN"
)
,
...
...
phy/wrap/odelay_fine_pipe.v
View file @
6ad657e2
...
@@ -10,7 +10,7 @@
...
@@ -10,7 +10,7 @@
* the Free Software Foundation, either version 3 of the License, or
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
* (at your option) any later version.
*
*
*
i
delay_fine_pipe.v is distributed in the hope that it will be useful,
*
o
delay_fine_pipe.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
* GNU General Public License for more details.
...
@@ -20,7 +20,13 @@
...
@@ -20,7 +20,13 @@
*******************************************************************************/
*******************************************************************************/
`timescale
1
ns
/
1
ps
`timescale
1
ns
/
1
ps
module
odelay_fine_pipe
(
module
odelay_fine_pipe
//SuppressWarnings VEditor - IODELAY_GRP used in (* *) construnt
#
(
parameter
IODELAY_GRP
=
"IODELAY_MEMORY"
,
parameter
integer
DELAY_VALUE
=
0
,
parameter
real
REFCLK_FREQUENCY
=
200.0
,
parameter
HIGH_PERFORMANCE_MODE
=
"FALSE"
)
(
input
clk
,
input
clk
,
input
rst
,
input
rst
,
input
set
,
input
set
,
...
@@ -29,10 +35,6 @@ module odelay_fine_pipe(
...
@@ -29,10 +35,6 @@ module odelay_fine_pipe(
input
data_in
,
input
data_in
,
output
data_out
output
data_out
)
;
)
;
parameter
integer
DELAY_VALUE
=
0
;
parameter
real
REFCLK_FREQUENCY
=
200.0
;
parameter
HIGH_PERFORMANCE_MODE
=
"FALSE"
;
reg
[
2
:
0
]
fdly_pre
=
DELAY_VALUE
[
2
:
0
]
,
fdly
=
DELAY_VALUE
[
2
:
0
]
;
reg
[
2
:
0
]
fdly_pre
=
DELAY_VALUE
[
2
:
0
]
,
fdly
=
DELAY_VALUE
[
2
:
0
]
;
always
@
(
posedge
clk
or
posedge
rst
)
begin
always
@
(
posedge
clk
or
posedge
rst
)
begin
if
(
rst
)
fdly_pre
<=
DELAY_VALUE
[
2
:
0
]
;
if
(
rst
)
fdly_pre
<=
DELAY_VALUE
[
2
:
0
]
;
...
@@ -41,7 +43,7 @@ module odelay_fine_pipe(
...
@@ -41,7 +43,7 @@ module odelay_fine_pipe(
else
if
(
set
)
fdly
<=
fdly_pre
;
else
if
(
set
)
fdly
<=
fdly_pre
;
end
end
ODELAYE2_FINEDELAY
(
*
IODELAY_GROUP
=
IODELAY_GRP
*
)
ODELAYE2_FINEDELAY
#(
#(
.
CINVCTRL_SEL
(
"FALSE"
)
,
.
CINVCTRL_SEL
(
"FALSE"
)
,
.
DELAY_SRC
(
"ODATAIN"
)
,
.
DELAY_SRC
(
"ODATAIN"
)
,
...
...
Write
Preview
Markdown
is supported
0%
Try again
or
attach a new file
Attach a file
Cancel
You are about to add
0
people
to the discussion. Proceed with caution.
Finish editing this message first!
Cancel
Please
register
or
sign in
to comment