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Commit 6a297fff authored by Andrey Filippov's avatar Andrey Filippov
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working on the logger

parent 707d6aec
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logger/event_logger.v
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...@@ -20,42 +20,66 @@ ...@@ -20,42 +20,66 @@
*******************************************************************************/ *******************************************************************************/
`timescale 1ns/1ps `timescale 1ns/1ps
module event_logger( clk, // system clock, negedge module event_logger#(
xclk, // half frequency (80 MHz nominal) parameter LOGGER_ADDR = 'h1a0, //TODO: assign valid address
we, // write enable (lower 16 bits, high - next cycle) parameter LOGGER_STATUS = 'h1a2, //TODO: assign valid address (just 1 location)
wa, // write address(1)/data(0) parameter LOGGER_STATUS_REG_ADDR = 'h0b, //TODO: assign valid address (just 1 location)
di, // 16-bit data in (32 multiplexed) parameter LOGGER_MASK = 'h3fe,
usec, // un-latched timestamp microseconds parameter LOGGER_STATUS_MASK = 'h3ff,
sec, // un-latched timestamp seconds
ext_di, parameter LOGGER_PAGE_IMU = 0, // 'h00..'h1f - overlaps with period/duration/halfperiod/config?
ext_do, parameter LOGGER_PAGE_GPS = 1, // 'h20..'h3f
ext_en, parameter LOGGER_PAGE_MSG = 2, // 'h40..'h5f
ts_rcv_sec, // [31:0] timestamp seconds received over the sync line
ts_rcv_usec, // [19:0] timestamp microseconds received over the sync line parameter LOGGER_PERIOD = 0,
ts_stb, // strobe when received timestamp is valid - single negedge sclk cycle parameter LOGGER_BIT_DURATION = 1,
data_out, // 16-bit data out to DMA1 (@negedge clk) parameter LOGGER_BIT_HALF_PERIOD = 2, //rs232 half bit period
data_out_stb,// data out valid (@negedge clk) parameter LOGGER_CONFIG = 3,
sample_counter, // could be DMA latency, safe to use sample_counter-1
debug_state parameter LOGGER_CONF_IMU = 2,
); parameter LOGGER_CONF_IMU_BITS = 2,
parameter LOGGER_CONF_GPS = 7,
parameter LOGGER_CONF_GPS_BITS = 4,
parameter LOGGER_CONF_MSG = 13,
parameter LOGGER_CONF_MSG_BITS = 5,
parameter LOGGER_CONF_SYN = 15,
parameter LOGGER_CONF_SYN_BITS = 1,
parameter LOGGER_CONF_EN = 17,
parameter LOGGER_CONF_EN_BITS = 1,
parameter LOGGER_CONF_DBG = 22,
parameter LOGGER_CONF_DBG_BITS = 4,
parameter GPIO_N = 10 // number of GPIO bits to control
)(
input rst,
input mclk, // system clock, negedge TODO:COnvert to posedge!
input xclk, // half frequency (80 MHz nominal)
// programming interface
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
input cmd_stb, // strobe (with first byte) for the command a/d
output [7:0] status_ad, // status address/data - up to 5 bytes: A - {seq,status[1:0]} - status[2:9] - status[10:17] - status[18:25]
output status_rq, // input request to send status downstream
input status_start, // Acknowledge of the first status packet byte (address)
// input we, // write enable (lower 16 bits, high - next cycle)
// input wa, // write address(1)/data(0)
// input [15:0] di, // 16-bit data in (32 multiplexed)
input [19:0] usec, // un-latched timestamp microseconds
input [31:0] sec, // un-latched timestamp seconds
input [GPIO_N-1:0] ext_di,
output [GPIO_N-1:0] ext_do,
output [GPIO_N-1:0] ext_en,
input [31:0] ts_rcv_sec, // [31:0] timestamp seconds received over the sync line
input [19:0] ts_rcv_usec, // [19:0] timestamp microseconds received over the sync line
input ts_stb, // strobe when received timestamp is valid - single negedge sclk cycle
// TODO: Convert to 32-bit?
output [15:0] data_out, // 16-bit data out to DMA1 (@negedge mclk)
output data_out_stb,// data out valid (@negedge mclk)
// sample_counter, // could be DMA latency, safe to use sample_counter-1
output [31:0] debug_state);
wire [23:0] sample_counter; // TODO: read with status! could be DMA latency, safe to use sample_counter-1
input clk; // system clock, negedge
input xclk; // half frequency (80 MHz nominal)
input we; // write enable (lower 16 bits, high - next cycle)
input wa; // write address(1)/data(0)
input [15:0] di; // 16-bit data in (32 multiplexed)
input [19:0] usec; // latched timestamp microseconds
input [31:0] sec; // latched timestamp seconds
input [11:0] ext_di; // external GPIO in
output [11:0] ext_do; // external GPIO out
output [11:0] ext_en; // external GPIO enable out
input [31:0] ts_rcv_sec; // [31:0] timestamp seconds received over the sync line
input [19:0] ts_rcv_usec; // [19:0] timestamp microseconds received over the sync line
input ts_stb; // strobe when received timestamp is valid - single negedge sclk cycle
output [15:0] data_out; // 16-bit data out to DMA1 (@negedge clk)
output data_out_stb;// data out valid (@negedge clk)
output [23:0] sample_counter; // could be DMA latency, safe to use sample_counter-1
output [31:0] debug_state;
wire ser_di; // gps serial data in wire ser_di; // gps serial data in
wire gps_pulse1sec; wire gps_pulse1sec;
...@@ -78,7 +102,7 @@ module event_logger( clk, // system clock, negedge ...@@ -78,7 +102,7 @@ module event_logger( clk, // system clock, negedge
// reg we_config_rst; // bit 16, 17 - enable - reset modules // reg we_config_rst; // bit 16, 17 - enable - reset modules
// reg we_config_debug; // bits 21:18, 22 - enable // reg we_config_debug; // bits 21:18, 22 - enable
reg [15:0] di_d; // reg [15:0] di_d;
// reg di_d2; // reg di_d2;
reg [1:0] config_imu; reg [1:0] config_imu;
...@@ -112,8 +136,10 @@ module event_logger( clk, // system clock, negedge ...@@ -112,8 +136,10 @@ module event_logger( clk, // system clock, negedge
reg enable_timestamps; reg enable_timestamps;
wire message_trig; wire message_trig;
reg ts_stb_rq; // reg ts_stb_rq;
reg [1:0] ext_ts_stb; // reg [1:0] ext_ts_stb;
wire ts_stb_xclk; // re-clocked to posedge xclk
wire gps_ts_stb, ser_do,ser_do_stb; wire gps_ts_stb, ser_do,ser_do_stb;
wire [15:0] imu_data; wire [15:0] imu_data;
...@@ -127,43 +153,82 @@ module event_logger( clk, // system clock, negedge ...@@ -127,43 +153,82 @@ module event_logger( clk, // system clock, negedge
reg [1:0] gps_pulse1sec_denoise; reg [1:0] gps_pulse1sec_denoise;
reg [7:0] gps_pulse1sec_denoise_count; reg [7:0] gps_pulse1sec_denoise_count;
reg gps_pulse1sec_single; reg gps_pulse1sec_single;
// wire gps_ts; // single cycle @posedge xclk
wire [3:0] timestamp_request; // 0 - imu, 1 - gps, 2 - ext, 3 - msg wire [3:0] timestamp_request; // 0 - imu, 1 - gps, 2 - ext, 3 - msg
wire [3:0] timestamp_ackn; wire [3:0] timestamp_ackn;
wire [23:0] sample_counter;// could be DMA latency, safe to use sample_counter-1
wire [3:0] timestamp_request_long; //from sub-module ts request until reset by arbiter, to allow timestamp_ackn wire [3:0] timestamp_request_long; //from sub-module ts request until reset by arbiter, to allow timestamp_ackn
wire [3:0] channel_ready; // 0 - imu, 1 - gps, 2 - ext, 3 - msg wire [3:0] channel_ready; // 0 - imu, 1 - gps, 2 - ext, 3 - msg
wire [3:0] channel_next; // 0 - imu, 1 - gps, 2 - ext, 3 - msg wire [3:0] channel_next; // 0 - imu, 1 - gps, 2 - ext, 3 - msg
wire [1:0] channel; // currently logged channel number wire [1:0] channel; // currently logged channel number
wire [1:0] timestamp_sel; // selected word in timestamp (0..3) wire [1:0] timestamp_sel; // selected word in timestamp (0..3)
wire ts_en; // log timestamp (when false - data) wire ts_en; // log timestamp (when false - data)
wire mux_data_valid; // data valid from multiplexer (to xclk->clk converter fifo) wire mux_data_valid; // data valid from multiplexer (to xclk->mclk converter fifo)
reg [15:0] mux_data_source;// data multiplexed from 1 of the 4 channels reg [15:0] mux_data_source;// data multiplexed from 1 of the 4 channels
reg mux_rdy_source; // data ready multiplexed from 1of the 4 channels (to fill rest with zeros) reg mux_rdy_source; // data ready multiplexed from 1of the 4 channels (to fill rest with zeros)
reg [15:0] mux_data_final; // data multiplexed between timestamps and channel data (or 0 if ~ready) reg [15:0] mux_data_final; // data multiplexed between timestamps and channel data (or 0 if ~ready)
wire [15:0] data_out; // 16-bit data out to DMA1 (@negedge clk)
wire data_out_stb;// data out valid (@posegedge clk)
wire rs232_wait_pause;// may be used as reset for decoder wire rs232_wait_pause;// may be used as reset for decoder
wire rs232_start; // serial character start (single pulse) wire rs232_start; // serial character start (single pulse)
wire nmea_sent_start; // serial character start (single pulse) wire nmea_sent_start; // serial character start (single pulse)
reg pre_message_trig;
// reg [1:0] debug_reg; // reg [1:0] debug_reg;
reg [7:0] dbg_cntr; reg [7:0] dbg_cntr;
wire pre_message_trig;
wire [15:0] ext_di16 ={{(16-GPIO_N){1'b0}},ext_di};
wire cmd_a; // single bit
wire [31:0] cmd_data;
reg [31:0] cmd_data_r; // valid next after cmd_we;
wire cmd_we;
wire cmd_status;
assign ext_en[11:0]= {5'b0,(config_imu[1:0]==2'h3)?1'b1:1'b0,1'b0,(config_imu[1:0]==2'h2)?1'b1:1'b0,1'b0,(config_imu[1:0]==2'h1)?1'b1:1'b0,(config_imu[1:0]!=2'h0)?{sda_en,scl_en}:2'h0};
assign ext_do[11:0]= {5'b0,(config_imu[1:0]==2'h3)?mosi:1'b0,1'b0,(config_imu[1:0]==2'h2)?mosi:1'b0,1'b0,(config_imu[1:0]==2'h1)?mosi:1'b0,(config_imu[1:0]!=2'h0)?{sda,scl}:2'h0};
assign miso= config_imu[1]?(config_imu[0]?ext_di[7] :ext_di[5]):(config_imu[0]?ext_di[3]:1'b0);
assign ser_di= config_gps[1]?(config_gps[0]?ext_di[6] :ext_di[4]):(config_gps[0]?ext_di[2]:1'b0);
assign gps_pulse1sec=config_gps[2]^(config_gps[1]?(config_gps[0]?ext_di[7] :ext_di[5]):(config_gps[0]?ext_di[3]:1'b0));
//sngl_wire
always @(config_msg[3:0] or ext_di[11:0]) begin /*
assign ext_en[11:0]= {5'b0,
(config_imu[1:0]==2'h3)?1'b1:1'b0,
1'b0,
(config_imu[1:0]==2'h2)?1'b1:1'b0,
1'b0,
(config_imu[1:0]==2'h1)?1'b1:1'b0,
(config_imu[1:0]!=2'h0)?{sda_en,scl_en}:2'h0};
assign ext_do[11:0]= {5'b0,
(config_imu[1:0]==2'h3)?mosi:1'b0,
1'b0,
(config_imu[1:0]==2'h2)?mosi:1'b0,
1'b0,
(config_imu[1:0]==2'h1)?mosi:1'b0,
(config_imu[1:0]!=2'h0)?{sda,scl}:2'h0};
*/
assign ext_en = {{(GPIO_N-5){1'b0}},
(config_imu[1:0]==2'h2)?1'b1:1'b0,
1'b0,
(config_imu[1:0]==2'h1)?1'b1:1'b0,
(config_imu[1:0]!=2'h0)?{sda_en,scl_en}:2'h0};
assign ext_do= {{(GPIO_N-5){1'b0}},
(config_imu[1:0]==2'h2)?mosi:1'b0,
1'b0,
(config_imu[1:0]==2'h1)?mosi:1'b0,
(config_imu[1:0]!=2'h0)?{sda,scl}:2'h0};
assign miso= config_imu[1]?
(config_imu[0]?1'b0 :ext_di[5]):
(config_imu[0]?ext_di[3]:1'b0);
assign ser_di= config_gps[1]?
(config_gps[0]?1'b0 :ext_di[4]):
(config_gps[0]?ext_di[2]:1'b0);
// if (we_config_gps) config_gps_mclk[3:0] <= di_d[ 6:3]; // bits 6:3, 7 - enable - {ext,inver, slot[1:0]} slot==0 - disable
assign gps_pulse1sec=config_gps[2]^(config_gps[1]?
(config_gps[0]?1'b0 :ext_di[5]):
(config_gps[0]?ext_di[3]:1'b0));
//sngl_wire
/*
// always @(config_msg[3:0] or ext_di[11:0]) begin
always @* begin
case (config_msg[3:0]) case (config_msg[3:0])
4'h0: pre_message_trig = ext_di[0]; 4'h0: pre_message_trig = ext_di[0];
4'h1: pre_message_trig = ext_di[1]; 4'h1: pre_message_trig = ext_di[1];
...@@ -180,6 +245,9 @@ module event_logger( clk, // system clock, negedge ...@@ -180,6 +245,9 @@ module event_logger( clk, // system clock, negedge
default:pre_message_trig = 1'b0; default:pre_message_trig = 1'b0;
endcase endcase
end end
*/
assign pre_message_trig = ext_di16[config_msg[3:0]];
assign message_trig= config_msg[4]^pre_message_trig; assign message_trig= config_msg[4]^pre_message_trig;
assign timestamp_request[1]=config_gps[3]? (config_gps[2]?nmea_sent_start:gps_ts_stb):gps_pulse1sec_single; assign timestamp_request[1]=config_gps[3]? (config_gps[2]?nmea_sent_start:gps_ts_stb):gps_pulse1sec_single;
...@@ -202,7 +270,8 @@ module event_logger( clk, // system clock, negedge ...@@ -202,7 +270,8 @@ module event_logger( clk, // system clock, negedge
// re-sync single pulse @ negedge sclk - ts_stb to @posedge xclk // re-sync single pulse @ negedge sclk - ts_stb to @posedge xclk
always @ (posedge ext_ts_stb[1] or negedge clk) begin /*
always @ (posedge ext_ts_stb[1] or negedge mclk) begin
if (ext_ts_stb[1]) ts_stb_rq <= 1'b0; if (ext_ts_stb[1]) ts_stb_rq <= 1'b0;
else if (config_rst_mclk) ts_stb_rq <= 1'b0; else if (config_rst_mclk) ts_stb_rq <= 1'b0;
else if (ts_stb) ts_stb_rq <= 1'b1; else if (ts_stb) ts_stb_rq <= 1'b1;
...@@ -210,38 +279,36 @@ module event_logger( clk, // system clock, negedge ...@@ -210,38 +279,36 @@ module event_logger( clk, // system clock, negedge
always @ (posedge xclk) begin always @ (posedge xclk) begin
ext_ts_stb[1:0] <= {ext_ts_stb[0] & ~ext_ts_stb[1],ts_stb_rq}; ext_ts_stb[1:0] <= {ext_ts_stb[0] & ~ext_ts_stb[1],ts_stb_rq};
end end
*/
always @ (negedge clk) begin always @ (posedge mclk) begin // was negedge
if (we) di_d[15:0] <= di[15:0]; if (cmd_we) cmd_data_r <= cmd_data; // valid next after cmd_we;
// di_d2 <=di_d[0]; // if (we) di_d[15:0] <= di[15:0];
// we_d <= we && !wa; we_d <= cmd_we && !cmd_a;
we_d <= we && !wa; we_imu <= cmd_we && !cmd_a && (ctrl_addr[6:5] == LOGGER_PAGE_IMU);
we_imu <= we && !wa && (ctrl_addr[6:5] == 2'h0); we_gps <= cmd_we && !cmd_a && (ctrl_addr[6:5] == LOGGER_PAGE_GPS);
we_gps <= we && !wa && (ctrl_addr[6:5] == 2'h1); we_message <= cmd_we && !cmd_a && (ctrl_addr[6:5] == LOGGER_PAGE_MSG);
we_message <= we && !wa && (ctrl_addr[6:5] == 2'h2); we_period <= cmd_we && !cmd_a && (ctrl_addr[6:0] == LOGGER_PERIOD);
// we_timer[4:0] <= {we_timer[3:0], we && !wa && (ctrl_addr[5:0]==6'h0)} ; we_bit_duration <= cmd_we && !cmd_a && (ctrl_addr[6:0] == LOGGER_BIT_DURATION);
we_period <= we && !wa && (ctrl_addr[6:0]==7'h0); we_bitHalfPeriod<= cmd_we && !cmd_a && (ctrl_addr[6:0] == LOGGER_BIT_HALF_PERIOD);
we_bit_duration <= we && !wa && (ctrl_addr[6:0]==7'h1); we_config <= cmd_we && !cmd_a && (ctrl_addr[6:0] == LOGGER_CONFIG);
we_bitHalfPeriod<= we && !wa && (ctrl_addr[6:0]==7'h2); we_config_imu <= cmd_we && !cmd_a && (ctrl_addr[6:0] == LOGGER_CONFIG) && cmd_data[LOGGER_CONF_IMU];
we_config <= we && !wa && (ctrl_addr[6:0]==7'h3); we_config_gps <= cmd_we && !cmd_a && (ctrl_addr[6:0] == LOGGER_CONFIG) && cmd_data[LOGGER_CONF_GPS];
we_config_imu <= we && !wa && (ctrl_addr[6:0]==7'h3) && di[ 2]; we_config_msg <= cmd_we && !cmd_a && (ctrl_addr[6:0] == LOGGER_CONFIG) && cmd_data[LOGGER_CONF_MSG];
we_config_gps <= we && !wa && (ctrl_addr[6:0]==7'h3) && di[ 7]; we_config_syn <= cmd_we && !cmd_a && (ctrl_addr[6:0] == LOGGER_CONFIG) && cmd_data[LOGGER_CONF_SYN];
we_config_msg <= we && !wa && (ctrl_addr[6:0]==7'h3) && di[13];
we_config_syn <= we && !wa && (ctrl_addr[6:0]==7'h3) && di[15]; if (we_config_imu) config_imu_mclk[1:0] <= cmd_data_r[LOGGER_CONF_IMU - 1 -: LOGGER_CONF_IMU_BITS]; // bits 1:0, 2 - enable slot[1:0]
// we_config_rst <= we_config && di[1]; if (we_config_gps) config_gps_mclk[3:0] <= cmd_data_r[LOGGER_CONF_GPS - 1 -: LOGGER_CONF_GPS_BITS]; // bits 6:3, 7 - enable - {ext,inver, slot[1:0]} slot==0 - disable
if (we_config_msg) config_msg_mclk[4:0] <= cmd_data_r[LOGGER_CONF_MSG - 1 -: LOGGER_CONF_MSG_BITS]; // bits 12:8,13 - enable - {invert,extinp[3:0]} extinp[3:0]=='hf' - disable
if (we_config_imu) config_imu_mclk[1:0] <= di_d[ 1:0]; // bits 1:0, 2 - enable slot[1:0] if (we_config_syn) config_syn_mclk <= cmd_data_r[LOGGER_CONF_SYN - 1 -: LOGGER_CONF_SYN_BITS]; // bit 14, 15 - enable
if (we_config_gps) config_gps_mclk[3:0] <= di_d[ 6:3]; // bits 6:3, 7 - enable - {ext,inver, slot[1:0]} slot==0 - disable if (we_config && cmd_data_r[LOGGER_CONF_EN]) config_rst_mclk <= cmd_data_r[LOGGER_CONF_EN -1 -: LOGGER_CONF_EN_BITS]; // bit 16, 17 - enable
if (we_config_msg) config_msg_mclk[4:0] <= di_d[12:8]; // bits 12:8,13 - enable - {invert,extinp[3:0]} extinp[3:0]=='hf' - disable
if (we_config_syn) config_syn_mclk <= di_d[ 14]; // bit 14, 15 - enable if (we_config && cmd_data_r[LOGGER_CONF_DBG]) config_debug_mclk[3:0] <= cmd_data_r[LOGGER_CONF_DBG - 1 -: LOGGER_CONF_DBG_BITS]; // bit 21:18, 22 - enable
if (we_config && di[1]) config_rst_mclk <= di[0]; // bit 16, 17 - enable
if (we_bitHalfPeriod) bitHalfPeriod_mclk[15:0] <= cmd_data_r[15:0];
if (we_config && di[6]) config_debug_mclk[3:0] <= di[5:2]; // bit 21:18, 22 - enable
if (cmd_we && cmd_a) ctrl_addr[6:5] <= cmd_data[6:5];
if (we_bitHalfPeriod) bitHalfPeriod_mclk[15:0]<=di_d[15:0]; if (cmd_we && cmd_a) ctrl_addr[4:0] <= cmd_data[4:0];
if (we && wa) ctrl_addr[6:5] <= di[6:5];
if (we && wa) ctrl_addr[4:0] <= di[4:0];
else if (we_d && (ctrl_addr[4:0]!=5'h1f)) ctrl_addr[4:0] <=ctrl_addr[4:0]+1; // no roll over, else if (we_d && (ctrl_addr[4:0]!=5'h1f)) ctrl_addr[4:0] <=ctrl_addr[4:0]+1; // no roll over,
end end
...@@ -262,25 +329,70 @@ module event_logger( clk, // system clock, negedge ...@@ -262,25 +329,70 @@ module event_logger( clk, // system clock, negedge
config_rst <= config_rst_pre; config_rst <= config_rst_pre;
config_debug[3:0] <= config_debug_pre[3:0]; config_debug[3:0] <= config_debug_pre[3:0];
enable_gps <= (config_gps[1:0] != 2'h0) && !config_rst; // enable_gps <= (config_gps[1:0] != 2'h0) && !config_rst;
enable_gps <= (^config_gps[1:0]) && !config_rst; // both 00 and 11 - disable
enable_msg <= (config_gps[3:0] != 4'hf) && !config_rst; enable_msg <= (config_gps[3:0] != 4'hf) && !config_rst;
enable_syn <= config_syn && !config_rst; enable_syn <= config_syn && !config_rst;
enable_timestamps <= !config_rst; enable_timestamps <= !config_rst;
end end
always @ (posedge xclk) begin always @ (posedge xclk) begin
mux_data_source[15:0] <= channel[1]?(channel[0]?msg_data[15:0]:extts_data[15:0]):(channel[0]?nmea_data[15:0]:imu_data[15:0]); mux_data_source[15:0] <= channel[1]?
mux_rdy_source <= channel[1]?(channel[0]?channel_ready[3]:channel_ready[2]):(channel[0]?channel_ready[1]:channel_ready[0]); (channel[0]?msg_data[15:0]:extts_data[15:0]):
mux_data_final[15:0] <= ts_en? timestamps_rdata[15:0]:(mux_rdy_source?mux_data_source[15:0]:16'h0); // replace 16'h0 with some pattern to debug output (channel[0]?nmea_data[15:0]:imu_data[15:0]);
mux_rdy_source <= channel[1]?
(channel[0]?channel_ready[3]:channel_ready[2]):
(channel[0]?channel_ready[1]:channel_ready[0]);
mux_data_final[15:0] <= ts_en?
timestamps_rdata[15:0]:
(mux_rdy_source?
mux_data_source[15:0]:
16'h0); // replace 16'h0 with some pattern to debug output
end end
imu_spi393 i_imu_spi ( .sclk(clk), // system clock, negedge pulse_cross_clock i_ts_stb_xclk (.rst(1'b0), .src_clk(mclk), .dst_clk(xclk), .in_pulse(ts_stb), .out_pulse(ts_stb_xclk),.busy());
cmd_deser #(
.ADDR (LOGGER_ADDR),
.ADDR_MASK (LOGGER_MASK),
.NUM_CYCLES (6),
.ADDR_WIDTH (1),
.DATA_WIDTH (32),
.ADDR1 (LOGGER_STATUS),
.ADDR_MASK1 (LOGGER_STATUS_MASK)
) cmd_deser_32bit_i (
.rst (rst), // input
.clk (mclk), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (cmd_a), // output[3:0]
.data (cmd_data), // output[31:0]
.we ({cmd_status,cmd_we}) // output
);
status_generate #(
.STATUS_REG_ADDR (LOGGER_STATUS_REG_ADDR),
.PAYLOAD_BITS (26),
.REGISTER_STATUS (1)
) status_generate_i (
.rst (), // input
.clk (mclk), // input
.we (cmd_status), // input
.wd (cmd_data[7:0]), // input[7:0]
.status ({sample_counter,2'b0}), // input[25:0] // 2 LSBs - may add "real" status
.ad (status_ad), // output[7:0]
.rq (status_rq), // output
.start (status_start) // input
);
imu_spi393 i_imu_spi ( .sclk(mclk), // system clock, negedge
.xclk(xclk), // half frequency (80 MHz nominal) .xclk(xclk), // half frequency (80 MHz nominal)
.we_ra(we_imu), // write enable for registers to log (@negedge clk) .we_ra(we_imu), // write enable for registers to log (@negedge mclk)
.we_div(we_bit_duration),// write enable for clock dividing(@negedge clk) .we_div(we_bit_duration),// write enable for clock dividing(@negedge mclk)
.we_period(we_period),// write enable for IMU cycle period(@negedge clk) 0 - disable, 1 - single, >1 - half bit periods .we_period(we_period),// write enable for IMU cycle period(@negedge mclk) 0 - disable, 1 - single, >1 - half bit periods
.wa(ctrl_addr[4:0]), // write address for register (5 bits, @negedge clk) .wa(ctrl_addr[4:0]), // write address for register (5 bits, @negedge mclk)
.di(di[15:0]), // 16?-bit data in (di, not di_d) .di(cmd_data_r[15:0]), // 16?-bit data in (di, not di_d)
.mosi(mosi), // to IMU, bit 2 in J9 .mosi(mosi), // to IMU, bit 2 in J9
.miso(miso), // from IMU, bit 3 on J9 .miso(miso), // from IMU, bit 3 on J9
.config_debug(config_debug[3:0]), .config_debug(config_debug[3:0]),
...@@ -300,11 +412,11 @@ So it is possible to assert trig input (will request timestamp), write message b ...@@ -300,11 +412,11 @@ So it is possible to assert trig input (will request timestamp), write message b
de-assert the trig input - message with the timestamp will be logged de-assert the trig input - message with the timestamp will be logged
fixed-length de-noise circuitry with latency 256*T(xclk) (~3usec) fixed-length de-noise circuitry with latency 256*T(xclk) (~3usec)
*/ */
imu_message393 i_imu_message(.sclk(clk), // system clock, negedge imu_message393 i_imu_message(.sclk(mclk), // system clock, negedge
.xclk(xclk), // half frequency (80 MHz nominal) .xclk(xclk), // half frequency (80 MHz nominal)
.we(we_message), // write enable for registers to log (@negedge sclk), with lower data half .we(we_message), // write enable for registers to log (@negedge sclk), with lower data half
.wa(ctrl_addr[3:0]), // write address for register (4 bits, @negedge sclk) .wa(ctrl_addr[3:0]), // write address for register (4 bits, @negedge sclk)
.di(di[15:0]), // 16-bit data in multiplexed .di(cmd_data_r[15:0]), // 16-bit data in multiplexed
.en(enable_msg), // enable module operation, if 0 - reset .en(enable_msg), // enable module operation, if 0 - reset
.trig(message_trig), // leading edge - sample time, trailing set rdy .trig(message_trig), // leading edge - sample time, trailing set rdy
.ts(timestamp_request[3]), // timestamop request .ts(timestamp_request[3]), // timestamop request
...@@ -315,7 +427,7 @@ imu_message393 i_imu_message(.sclk(clk), // system clock, negedge ...@@ -315,7 +427,7 @@ imu_message393 i_imu_message(.sclk(clk), // system clock, negedge
// ts_stb (mclk) -> trig) // ts_stb (mclk) -> trig)
imu_exttime393 i_imu_exttime(.xclk(xclk), // half frequency (80 MHz nominal) imu_exttime393 i_imu_exttime(.xclk(xclk), // half frequency (80 MHz nominal)
.en(enable_syn), // enable module operation, if 0 - reset .en(enable_syn), // enable module operation, if 0 - reset
.trig(ext_ts_stb[1]), // external time stamp updated, single pulse @posedge xclk .trig(ts_stb_xclk), // ext_ts_stb[1]), // external time stamp updated, single pulse @posedge xclk
.usec(ts_rcv_usec[19:0]), // microseconds from external timestamp (should not chnage after trig for 10 xclk) .usec(ts_rcv_usec[19:0]), // microseconds from external timestamp (should not chnage after trig for 10 xclk)
.sec(ts_rcv_sec[31:0]), // seconds from external timestamp .sec(ts_rcv_sec[31:0]), // seconds from external timestamp
.ts(timestamp_request[2]), // timestamop request .ts(timestamp_request[2]), // timestamop request
...@@ -324,7 +436,7 @@ imu_exttime393 i_imu_exttime(.xclk(xclk), // half frequency (80 MHz nominal) ...@@ -324,7 +436,7 @@ imu_exttime393 i_imu_exttime(.xclk(xclk), // half frequency (80 MHz nominal)
.rdata(extts_data[15:0])); // data out (16 bits) .rdata(extts_data[15:0])); // data out (16 bits)
imu_timestamps393 i_imu_timestamps ( imu_timestamps393 i_imu_timestamps (
.sclk(clk), // 160MHz, negedge .sclk(mclk), // 160MHz, negedge
.xclk(xclk), // 80 MHz, posedge .xclk(xclk), // 80 MHz, posedge
.rst(!enable_timestamps), // reset (@posedge xclk) .rst(!enable_timestamps), // reset (@posedge xclk)
.sec(sec[31:0]), // running seconds (@negedge sclk) .sec(sec[31:0]), // running seconds (@negedge sclk)
...@@ -333,6 +445,8 @@ imu_timestamps393 i_imu_timestamps ( ...@@ -333,6 +445,8 @@ imu_timestamps393 i_imu_timestamps (
.ts_ackn(timestamp_ackn[3:0]), // timestamp for this channel is stored .ts_ackn(timestamp_ackn[3:0]), // timestamp for this channel is stored
.ra({channel[1:0],timestamp_sel[1:0]}), // read address (2 MSBs - channel number, 2 LSBs - usec_low, (usec_high ORed with channel <<24), sec_low, sec_high .ra({channel[1:0],timestamp_sel[1:0]}), // read address (2 MSBs - channel number, 2 LSBs - usec_low, (usec_high ORed with channel <<24), sec_low, sec_high
.dout(timestamps_rdata[15:0]));// output data .dout(timestamps_rdata[15:0]));// output data
wire debug_unused_a; // SuppressThisWarning Veditor (unused)
rs232_rcv393 i_rs232_rcv (.xclk(xclk), // half frequency (80 MHz nominal) rs232_rcv393 i_rs232_rcv (.xclk(xclk), // half frequency (80 MHz nominal)
.bitHalfPeriod(bitHalfPeriod[15:0]), // half of the serial bit duration, in xclk cycles .bitHalfPeriod(bitHalfPeriod[15:0]), // half of the serial bit duration, in xclk cycles
.ser_di(ser_di), // rs232 (ttl) serial data in .ser_di(ser_di), // rs232 (ttl) serial data in
...@@ -344,7 +458,7 @@ rs232_rcv393 i_rs232_rcv (.xclk(xclk), // half frequency (80 MHz nomin ...@@ -344,7 +458,7 @@ rs232_rcv393 i_rs232_rcv (.xclk(xclk), // half frequency (80 MHz nomin
.ser_do(ser_do), // serial data out(@posedge xclk) LSB first! .ser_do(ser_do), // serial data out(@posedge xclk) LSB first!
.ser_do_stb(ser_do_stb), // output data strobe (@posedge xclk), first cycle after ser_do becomes valid .ser_do_stb(ser_do_stb), // output data strobe (@posedge xclk), first cycle after ser_do becomes valid
// .debug(debug_state[4:0]), // .debug(debug_state[4:0]),
.debug(debug_state[15:12]), .debug({debug_unused_a, debug_state[15:12]}),
.bit_dur_cntr(debug_state[31:16]), .bit_dur_cntr(debug_state[31:16]),
.bit_cntr(debug_state[11:7]) .bit_cntr(debug_state[11:7])
); );
...@@ -358,10 +472,10 @@ rs232_rcv393 i_rs232_rcv (.xclk(xclk), // half frequency (80 MHz nomin ...@@ -358,10 +472,10 @@ rs232_rcv393 i_rs232_rcv (.xclk(xclk), // half frequency (80 MHz nomin
// else if (ser_do_stb) dbg_cntr[7:0] <= dbg_cntr[7:0]+1; // else if (ser_do_stb) dbg_cntr[7:0] <= dbg_cntr[7:0]+1;
else if (rs232_start) dbg_cntr[7:0] <= dbg_cntr[7:0]+1; else if (rs232_start) dbg_cntr[7:0] <= dbg_cntr[7:0]+1;
end end
nmea_decoder393 i_nmea_decoder (.sclk(clk), // system clock, @negedge nmea_decoder393 i_nmea_decoder (.sclk(mclk), // system clock, @negedge
.we(we_gps), // registers write enable (@negedge sclk) .we(we_gps), // registers write enable (@negedge sclk)
.wa(ctrl_addr[4:0]), // registers write address .wa(ctrl_addr[4:0]), // registers write address
.wd(di_d[7:0]), // write data .wd(cmd_data_r[7:0]), // write data
.xclk(xclk), // 80MHz, posedge .xclk(xclk), // 80MHz, posedge
.start(gps_ts_stb), // start of the serial message .start(gps_ts_stb), // start of the serial message
.rs232_wait_pause(rs232_wait_pause),// may be used as reset for decoder .rs232_wait_pause(rs232_wait_pause),// may be used as reset for decoder
...@@ -373,8 +487,6 @@ nmea_decoder393 i_nmea_decoder (.sclk(clk), // system clock, @negedge ...@@ -373,8 +487,6 @@ nmea_decoder393 i_nmea_decoder (.sclk(clk), // system clock, @negedge
.rd_stb(channel_next[1]), // encoded nmea data read strobe (increment address) .rd_stb(channel_next[1]), // encoded nmea data read strobe (increment address)
.rdata(nmea_data[15:0]), // encoded data (16 bits) .rdata(nmea_data[15:0]), // encoded data (16 bits)
.ser_rst(!enable_gps), // reset (now only debug register) .ser_rst(!enable_gps), // reset (now only debug register)
// .debug(debug_state[31:8])
// .debug(debug_state[15:8])
.debug() .debug()
); );
...@@ -393,7 +505,7 @@ logger_arbiter393 i_logger_arbiter(.xclk(xclk), // 80 MHz, posedge ...@@ -393,7 +505,7 @@ logger_arbiter393 i_logger_arbiter(.xclk(xclk), // 80 MHz, posedge
.sample_counter(sample_counter));// number of 64-byte samples logged .sample_counter(sample_counter));// number of 64-byte samples logged
buf_xclk_mclk16_393 i_buf_xclk_mclk16(.xclk(xclk), // posedge buf_xclk_mclk16_393 i_buf_xclk_mclk16(.xclk(xclk), // posedge
.mclk(clk), // posedge! .mclk(mclk), // posedge!
.rst(config_rst), // @posedge xclk .rst(config_rst), // @posedge xclk
.din(mux_data_final[15:0]), .din(mux_data_final[15:0]),
.din_stb(mux_data_valid), .din_stb(mux_data_valid),
......
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