changed order of the function defines (69eeb5d7) · Commits · Elphel / x393

includes/x393_mcontr_encode_cmd.vh

+34 −33

Original line number	Diff line number	Diff line
		@@ -36,10 +36,10 @@
		* with at least one of the Free Software programs.
		*/

		function [31:0] func_encode_skip;
		input [CMD_PAUSE_BITS-1:0] skip; // number of extra cycles to skip (and keep all the other outputs)
		input done; // end of sequence
		function [31:0] func_encode_cmd;
		input [14:0] addr; // 15-bit row/column address
		input [2:0] bank; // bank (here OK to be any)
		input [2:0] rcw; // RAS/CAS/WE, positive logic
		input odt_en; // enable ODT
		input cke; // disable CKE
		input sel; // first/second half-cycle, other will be nop (cke+odt applicable to both)
		@@ -49,30 +49,32 @@
		input dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
		input buf_wr; // connect to external buffer (but only if not paused)
		input buf_rd; // connect to external buffer (but only if not paused)
		input nop; // add NOP after the current command, keep other data
		input buf_rst; // connect to external buffer (but only if not paused)
		begin
		func_encode_skip= func_encode_cmd (
		{{14-CMD_DONE_BIT{1'b0}}, done, skip[CMD_PAUSE_BITS-1:0]}, // 15-bit row/column address
		bank[2:0], // bank (here OK to be any)
		3'b0, // RAS/CAS/WE, positive logic
		func_encode_cmd={
		addr[14:0], // 15-bit row/column address
		bank [2:0], // bank
		rcw[2:0], // RAS/CAS/WE
		odt_en, // enable ODT
		cke, // disable CKE
		cke, // may be optimized (removed from here)?
		sel, // first/second half-cycle, other will be nop (cke+odt applicable to both)
		dq_en, // enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0)
		dqs_en, // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0)
		dqs_toggle, // enable toggle DQS according to the pattern
		dci, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
		buf_wr, // connect to external buffer (but only if not paused)
		buf_rd, // connect to external buffer (but only if not paused)
		1'b0, // nop
		buf_rst);
		buf_wr, // phy_buf_wr, // connect to external buffer (but only if not paused)
		buf_rd, // phy_buf_rd, // connect to external buffer (but only if not paused)
		nop, // add NOP after the current command, keep other data
		buf_rst // Reserved for future use
		};
		end
		endfunction

		function [31:0] func_encode_cmd;
		input [14:0] addr; // 15-bit row/column address
		function [31:0] func_encode_skip;
		input [CMD_PAUSE_BITS-1:0] skip; // number of extra cycles to skip (and keep all the other outputs)
		input done; // end of sequence
		input [2:0] bank; // bank (here OK to be any)
		input [2:0] rcw; // RAS/CAS/WE, positive logic
		input odt_en; // enable ODT
		input cke; // disable CKE
		input sel; // first/second half-cycle, other will be nop (cke+odt applicable to both)
		@@ -82,25 +84,24 @@
		input dci; // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
		input buf_wr; // connect to external buffer (but only if not paused)
		input buf_rd; // connect to external buffer (but only if not paused)
		input nop; // add NOP after the current command, keep other data
		input buf_rst; // connect to external buffer (but only if not paused)
		begin
		func_encode_cmd={
		addr[14:0], // 15-bit row/column address
		bank [2:0], // bank
		rcw[2:0], // RAS/CAS/WE
		func_encode_skip= func_encode_cmd (
		{{14-CMD_DONE_BIT{1'b0}}, done, skip[CMD_PAUSE_BITS-1:0]}, // 15-bit row/column address
		bank[2:0], // bank (here OK to be any)
		3'b0, // RAS/CAS/WE, positive logic
		odt_en, // enable ODT
		cke, // may be optimized (removed from here)?
		cke, // disable CKE
		sel, // first/second half-cycle, other will be nop (cke+odt applicable to both)
		dq_en, // enable (not tristate) DQ lines (internal timing sequencer for 0->1 and 1->0)
		dqs_en, // enable (not tristate) DQS lines (internal timing sequencer for 0->1 and 1->0)
		dqs_toggle, // enable toggle DQS according to the pattern
		dci, // DCI disable, both DQ and DQS lines (internal logic and timing sequencer for 0->1 and 1->0)
		buf_wr, // phy_buf_wr, // connect to external buffer (but only if not paused)
		buf_rd, // phy_buf_rd, // connect to external buffer (but only if not paused)
		nop, // add NOP after the current command, keep other data
		buf_rst // Reserved for future use
		};
		buf_wr, // connect to external buffer (but only if not paused)
		buf_rd, // connect to external buffer (but only if not paused)
		1'b0, // nop
		buf_rst);
		end
		endfunction


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