Skip to content

X
x393
Commit 69b1d30b authored by Andrey Filippov's avatar Andrey Filippov
Browse files
Options

Ready to start with the real serial sensor, all done so far can be used with parallel ones too

parents 0a729a6a 9c457ded
Expand all Hide whitespace changes
Inline Side-by-side
Showing with 83472 additions and 70487 deletions
.gitignore
View file @ 69b1d30b
......@@ -10,9 +10,11 @@ x393.prj
*DEBUG_VDT*
*.kate-swp
*.old
*.new
*.bad
*.pyc
*.pickle
py393/dbg
py393/dbg*
includes/x393_cur_params_sim.vh
includes/x393_cur_params_target_*.vh
......
.project
View file @ 69b1d30b
......@@ -62,42 +62,42 @@
<link>
<name>vivado_logs/VivadoBitstream.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151009231737365.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151103114104932.log</location>
</link>
<link>
<name>vivado_logs/VivadoOpt.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151009231737365.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151103114104932.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151009231737365.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151103114104932.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPower.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151009231737365.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151103114104932.log</location>
</link>
<link>
<name>vivado_logs/VivadoPlace.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151009231737365.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151103114104932.log</location>
</link>
<link>
<name>vivado_logs/VivadoRoute.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151009231737365.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151103114104932.log</location>
</link>
<link>
<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151009231255456.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151103114104932.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151009231737365.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151103114104932.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
......@@ -107,7 +107,7 @@
<link>
<name>vivado_logs/VivadoTimingReportImplemented.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150904164653967.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20151101221627109.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
......
.settings/com.elphel.vdt.VivadoRoute.prefs
View file @ 69b1d30b
VivadoRoute_122_SkipSnapshotRoute=true
VivadoRoute_123_SkipSnapshotRoute=true
com.elphel.store.context.VivadoRoute=VivadoRoute_122_SkipSnapshotRoute<-@\#\#@->VivadoRoute_123_SkipSnapshotRoute<-@\#\#@->
VivadoRoute_125_directive_route=MoreGlobalIterations
com.elphel.store.context.VivadoRoute=VivadoRoute_122_SkipSnapshotRoute<-@\#\#@->VivadoRoute_123_SkipSnapshotRoute<-@\#\#@->VivadoRoute_125_directive_route<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoSynthesis.prefs
View file @ 69b1d30b
......@@ -2,7 +2,7 @@ VivadoSynthesis_101_MaxMsg=10000
VivadoSynthesis_102_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@->
VivadoSynthesis_115_flatten_hierarchy=none
VivadoSynthesis_121_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@->
VivadoSynthesis_122_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@->
VivadoSynthesis_122_ConstraintsFiles=x393.xdc<-@\#\#@->x393_nox2_timing.xdc<-@\#\#@->
VivadoSynthesis_122_SkipSnapshotSynth=true
VivadoSynthesis_123_ResetProject=true
VivadoSynthesis_123_SkipSnapshotSynth=true
......
compressor_jp/bit_stuffer_27_32.v 0 → 100644
View file @ 69b1d30b
/*******************************************************************************
* Module: bit_stuffer_27_32
* Date:2015-10-23
* Author: andrey
* Description: Aggregate MSB aligned variable-length (1..27) data to 32-bit words
*
* Copyright (c) 2015 Elphel, Inc .
* bit_stuffer_27_32.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* bit_stuffer_27_32.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module bit_stuffer_27_32#(
parameter DIN_LEN = 27
)(
input xclk, // pixel clock, sync to incoming data
input rst, // @xclk
input [DIN_LEN-1:0] din, // input data, MSB aligned
input [4:0] dlen, // input data width
input ds, // input data valid
input flush_in, // flush remaining data - should be after last ds. Also prepares for the next block
output [31:0] d_out, // outpt 32-bit data
output reg [1:0] bytes_out, // (0 means 4) valid with dv
output reg dv, // output data valid
output reg flush_out // delayed flush in matching the data latency
);
localparam DATA1_LEN = DIN_LEN + 32 - 8;
localparam DATA2_LEN = DIN_LEN + 32 - 2;
localparam DATA3_LEN = DIN_LEN + 32 - 1;
reg [DATA1_LEN-1:0] data1; // first stage of the barrel shifter
reg [DATA2_LEN-1:0] data2; // second stage of the barrel shifter
reg [DATA3_LEN-1:0] data3; // second stage of the barrel shifter/ output register
reg [5:0] early_length; // number of bits in the last word (mod 32)
reg [5:0] dlen1; // use for the stage 2, MSB - carry out
reg [5:0] dlen2; // use for the stege 3
reg [31:0] dmask2_rom; // data mask (sync with data2) - 1 use new data, 0 - use old data. Use small ROM?
reg [1:0] stage; // delayed ds or flush
reg [1:0] ds_stage;
reg [2:0] flush_stage;
wire [4:0] pre_bits_out_w = dlen2[4:0] + 5'h7;
assign d_out = data3[DATA3_LEN-1 -: 32];
always @ (posedge xclk) begin
if (rst) stage <= 0;
else stage <= {stage[0], ds | flush_in};
if (rst) ds_stage <= 0;
else ds_stage <= {ds_stage[0], ds};
if (rst) flush_stage <= 0;
else flush_stage <= {flush_stage[1:0], flush_in};
if (rst || flush_in) early_length <= 0;
else if (ds) early_length <= early_length[4:0] + dlen; // early_length[5] is not used in calculations, it is just carry out
if (rst) dlen1 <= 0;
else if (ds) dlen1 <= early_length; // previous value
if (rst) dlen2 <= 0;
else if (stage[0]) dlen2 <= dlen1; // previous value (position)
// barrel shifter stage 1 (0/8/16/24)
if (rst) data1 <= 'bx;
else if (ds) case (early_length[4:3])
2'h0: data1 <= { din, 24'b0};
2'h1: data1 <= { 8'b0,din, 16'b0};
2'h2: data1 <= {16'b0,din, 8'b0};
2'h3: data1 <= {24'b0,din };
endcase
// barrel shifter stage 2 (0/2/4/6)
if (rst) data2 <= 'bx;
else if (stage[0]) case (dlen1[2:1])
2'h0: data2 <= { data1, 6'b0};
2'h1: data2 <= { 2'b0,data1, 4'b0};
2'h2: data2 <= { 4'b0,data1, 2'b0};
2'h3: data2 <= { 6'b0,data1 };
endcase
if (rst) dmask2_rom <= 'bx;
else if (stage[0]) case (dlen1[4:0])
5'h00: dmask2_rom <= 32'hffffffff;
5'h01: dmask2_rom <= 32'h7fffffff;
5'h02: dmask2_rom <= 32'h3fffffff;
5'h03: dmask2_rom <= 32'h1fffffff;
5'h04: dmask2_rom <= 32'h0fffffff;
5'h05: dmask2_rom <= 32'h07ffffff;
5'h06: dmask2_rom <= 32'h03ffffff;
5'h07: dmask2_rom <= 32'h01ffffff;
5'h08: dmask2_rom <= 32'h00ffffff;
5'h09: dmask2_rom <= 32'h007fffff;
5'h0a: dmask2_rom <= 32'h003fffff;
5'h0b: dmask2_rom <= 32'h001fffff;
5'h0c: dmask2_rom <= 32'h000fffff;
5'h0d: dmask2_rom <= 32'h0007ffff;
5'h0e: dmask2_rom <= 32'h0003ffff;
5'h0f: dmask2_rom <= 32'h0001ffff;
5'h10: dmask2_rom <= 32'h0000ffff;
5'h11: dmask2_rom <= 32'h00007fff;
5'h12: dmask2_rom <= 32'h00003fff;
5'h13: dmask2_rom <= 32'h00001fff;
5'h14: dmask2_rom <= 32'h00000fff;
5'h15: dmask2_rom <= 32'h000007ff;
5'h16: dmask2_rom <= 32'h000003ff;
5'h17: dmask2_rom <= 32'h000001ff;
5'h18: dmask2_rom <= 32'h000000ff;
5'h19: dmask2_rom <= 32'h0000007f;
5'h1a: dmask2_rom <= 32'h0000003f;
5'h1b: dmask2_rom <= 32'h0000001f;
5'h1c: dmask2_rom <= 32'h0000000f;
5'h1d: dmask2_rom <= 32'h00000007;
5'h1e: dmask2_rom <= 32'h00000003;
5'h1f: dmask2_rom <= 32'h00000001;
endcase
// barrel shifter stage 3 (0/1), combined with output/hold register
if (rst) data3 <= 'bx;
else if (ds_stage[1]) begin
data3[DATA3_LEN-1 -: 32] <= (~dmask2_rom & (dlen2[5] ? {data3[DATA3_LEN-1-32 : 0],6'b0}: data3[DATA3_LEN-1 -: 32])) |
( dmask2_rom & (dlen2[0] ? {1'b0,data2[DATA2_LEN-1 -: 31]} : data2[DATA2_LEN-1 -: 32]));
data3[DATA3_LEN-1-32: 0] <= dlen2[0] ? data2[DATA2_LEN-31-1 : 0] : {data2[DATA2_LEN-32-1 : 0], 1'b0};
end
// dv <= (ds_stage[1] && dlen2[5]) || (flush_stage[1] && !(|data3[DATA3_LEN-1 -: 32]));
// dv <= (ds_stage[1] && dlen1[5]) || (flush_stage[1] && !(|data3[DATA3_LEN-1 -: 32]));
// dv <= (ds_stage[0] && dlen1[5]) || (flush_stage[1] && !(|data3[DATA3_LEN-1 -: 32]));
dv <= (ds_stage[0] && dlen1[5]) || (flush_stage[1] && (|data3[DATA3_LEN-1 -: 32]));
// no difference in number of cells
// if (rst ) bytes_out <= 0; // if the dv was caused by 32 bits full - output 4 bytes
// else if (ds_stage[1]) bytes_out <= 0; // if the dv was caused by 32 bits full - output 4 bytes
if (rst || ds_stage[1]) bytes_out <= 0; // if the dv was caused by 32 bits full - output 4 bytes
else if (flush_stage[1]) bytes_out <= pre_bits_out_w[4:3];
flush_out <= flush_stage[2];
end
endmodule
compressor_jp/bit_stuffer_escape.v 0 → 100644
View file @ 69b1d30b
This diff is collapsed.
compressor_jp/bit_stuffer_metadata.v 0 → 100644
View file @ 69b1d30b
/*******************************************************************************
* Module: bit_stuffer_metadata
* Date:2015-10-25
* Author: andrey
* Description:
*
* Copyright (c) 2015 Elphel, Inc .
* bit_stuffer_metadata.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* bit_stuffer_metadata.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module bit_stuffer_metadata(
input mclk,
input mrst, // @posedge mclk, sync reset
input xclk,
input xrst, // @posedge xclk, sync reset
input last_block, // use it to copy timestamp from fifo
// time stamping - will copy time at the end of color_first (later than the first hact after vact in the current frame, but before the next one
// and before the data is needed for output
input ts_pre_stb, // @mclk - 1 cycle before receiving 8 bytes of timestamp data
input [7:0] ts_data, // timestamp data (s0,s1,s2,s3,us0,us1,us2,us3==0)
input color_first, // @fradv_clk only used for timestamp
input [31:0] din, // input data, MSB aligned
input [1:0] bytes_in, // number of bytes, valid @ ds (0 means 4)
input in_stb, // input data/bytes_in strobe
input flush, // end of input data
input abort, // @ any, extracts 0->1 and flushes
// outputs @ negedge clk
output reg [31:0] data_out, // [31:0] output data
output reg data_out_valid,// output data valid
output reg done, // reset by !en, goes high after some delay after flushing
output reg running // from registering timestamp until done
`ifdef DEBUG_RING
, output reg [3:0] dbg_etrax_dma
,output dbg_ts_rstb
,output [7:0] dbg_ts_dout
`endif
);
reg [7:0] time_ram0[0:3]; // 0 - seconds, 1 - microseconds MSB in the output 32-bit word, byt LSB of the sec/usec
reg [7:0] time_ram1[0:3];
reg [7:0] time_ram2[0:3];
reg [7:0] time_ram3[0:3];
reg [3:0] ts_in=8;
reg last_block_d; // last_block delayed by one clock
reg color_first_r;
reg [2:0] abort_r;
reg force_flush;
// reg color_first_r; // registered with the same clock as color_first to extract leading edge
// stb_time[2] - single-cycle pulse after color_first goes low
// reg [19:0] imgsz32; // current image size in multiples of 32-bytes
reg [21:0] imgsz4; // current image size in multiples of 4-bytes
reg last_stb_4; // last stb_in was 4 bytes
reg trailer;
reg meta_out;
reg [1:0] meta_word;
reg zeros_out; // output of 32 bytes (8 words) of zeros
wire trailer_done = (imgsz4[2:0] == 7) && zeros_out;
wire meta_last = (imgsz4[2:0] == 7) && meta_out;
// re-clock enable to this clock
wire ts_rstb= last_block && !last_block_d; // enough time to have timestamp data; // one cycle before getting timestamp data from FIFO
wire [7:0] ts_dout; // timestamp data, byte at a time
wire write_size = (in_stb && (bytes_in != 0)) || (flush && last_stb_4);
wire stb_start = !color_first && color_first_r;
wire stb = in_stb & !trailer && !force_flush;
always @ (posedge xclk) begin
if (xrst ||trailer_done) imgsz4 <= 0;
else if (stb || trailer) imgsz4 <= imgsz4 + 1;
if (stb) last_stb_4 <= (bytes_in == 0);
last_block_d <= last_block;
color_first_r <= color_first;
if (xrst) ts_in <= 8;
else if (ts_rstb) ts_in <= 0;
else if (!ts_in[3]) ts_in <= ts_in + 1;
if ((!ts_in[3] && (ts_in[1:0] == 0)) || write_size) time_ram0[ts_in[3:2]] <= ts_in[3]? ({imgsz4[5:0],flush?2'b0:bytes_in}):ts_dout; //ts_in[3:2] == 2'b10 when write_size
if ((!ts_in[3] && (ts_in[1:0] == 1)) || write_size) time_ram1[ts_in[3:2]] <= ts_in[3]? (imgsz4[13:6]):ts_dout;
if ((!ts_in[3] && (ts_in[1:0] == 2)) || write_size) time_ram2[ts_in[3:2]] <= ts_in[3]? (imgsz4[21:14]):ts_dout;
if ((!ts_in[3] && (ts_in[1:0] == 3)) || write_size) time_ram3[ts_in[3:2]] <= ts_in[3]? (8'hff):ts_dout;
if (xrst) trailer <= 0;
else if (flush || force_flush) trailer <= 1;
else if (trailer_done) trailer <= 0;
if (xrst) meta_out <= 0;
else if (trailer && (imgsz4[2:0] == 4) &&!zeros_out) meta_out <= 1;
else if (meta_last) meta_out <= 0;
if (!meta_out) meta_word <= 0;
else meta_word <= meta_word + 1;
if (xrst) zeros_out <= 0;
else if (meta_last) zeros_out <= 1;
else if (trailer_done) zeros_out <= 0;
data_out <= ({32{stb}} & din) | ({32{meta_out}} & {time_ram0[meta_word],time_ram1[meta_word],time_ram2[meta_word],time_ram3[meta_word]});
data_out_valid <= stb || trailer;
if (xrst || trailer) running <= 0;
else if (stb_start) running <= 1;
done <= trailer_done;
// re-clock abort, extract leading edge
abort_r <= {abort_r[0] & ~abort_r[1], abort_r[0], abort & ~trailer};
if (xrst || trailer) force_flush <= 0;
else if (abort_r) force_flush <= 1;
end
// just for testing
`ifdef DEBUG_RING
assign dbg_ = ts_rstb;
assign dbg_ts_dout = ts_dout;
always @ (posedge xclk) begin
dbg_etrax_dma <= imgsz4[3:0];
end
`endif
//color_first && color_first_r
timestamp_fifo timestamp_fifo_i (
.sclk (mclk), // input
.srst (mrst), // input
.pre_stb (ts_pre_stb), // input
.din (ts_data), // input[7:0]
.aclk (xclk), //fradv_clk), // input
.arst (xrst), //fradv_clk), // input
.advance (stb_start), // triggers at the 0->1
.rclk (xclk), // input
.rrst (xrst), //fradv_clk), // input
.rstb (ts_rstb), // input
.dout (ts_dout) // output[7:0] reg
);
endmodule
compressor_jp/cmprs_out_fifo32.v 0 → 100644
View file @ 69b1d30b
/*******************************************************************************
* Module: cmprs_out_fifo32
* Date:2015-06-25
* Author: Andrey Filippov
* Description: Compressor output FIFO, modified to use 32-bit input and xclk
*
* Copyright (c) 2015 Elphel, Inc.
* cmprs_out_fifo32.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* cmprs_out_fifo32.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module cmprs_out_fifo32(
// input rst, // mostly for simulation
// wclk domain
input wclk, // source clock (1x pixel clock)
input wrst, // @posedge wclk, sync reset
input we,
input [31:0] wdata,
input wa_rst, // reset low address bits when stuffer is disabled (to make sure it is multiple of 32 bytes
input wlast, // written last 32 bytes of a frame (flush FIFO) - stuffer_done (has to be later than we)
output eof_written_wclk, // eof_written - reclocked to wclk
// rclk domain
input rclk,
input rrst, // @posedge rclk, sync reset
input rst_fifo, // reset FIFO (set read address to write, reset count)
input ren,
output [63:0] rdata,
output eof, // single rclk pulse signalling EOF
input eof_written, // confirm frame written ofer AFI to the system memory (single rclk pulse)
output flush_fifo, // EOF, need to output all what is in FIFO (Stays active until enough data chunks are read)
output [7:0] fifo_count // number of 32-byte chunks in FIFO
);
reg regen;
reg [ 8:0] raddr;
reg [ 7:0] count32;
reg [ 7:0] lcount32; // counting chunks left in the same frame
reg [ 9:0] waddr;
wire written32b; // written 32 bytes, re-clocked to read clock domain (single-cycle)
wire wlast_rclk;
reg flush_fifo_r;
assign flush_fifo = flush_fifo_r;
assign fifo_count = count32;
assign eof = wlast_rclk;
always @ (posedge wclk) begin
if (wrst) waddr <= 0;
else if (wa_rst) waddr <= waddr & 10'h3f8; // reset 3 LSBs only
else if (we) waddr <= waddr + 1;
end
always @ (posedge rclk) begin
regen <= ren;
if (rst_fifo) raddr <= {waddr[9:3],2'b0};
else if (ren) raddr <= raddr + 1;
if (rst_fifo) count32 <= 0;
else if ( written32b && !(ren && (&raddr[1:0]))) count32 <= count32 + 1;
else if (!written32b && (ren && (&raddr[1:0]))) count32 <= count32 - 1;
if (rst_fifo) lcount32 <= 0;
else if (wlast_rclk) lcount32 <= count32;
else if ((lcount32 !=0) && ren && (&raddr[1:0])) lcount32 <= lcount32 - 1;
if (rst_fifo) flush_fifo_r <= 0;
else if (wlast_rclk) flush_fifo_r <= 1;
else if ((count32[7:1] == 0) && ( !count32[0] || ren)) flush_fifo_r <= 0;
end
// wclk -> rclk
pulse_cross_clock written32b_i (.rst(wrst), .src_clk(wclk), .dst_clk(rclk), .in_pulse(we && (&waddr[2:0])), .out_pulse(written32b),.busy());
pulse_cross_clock wlast_rclk_i (.rst(wrst), .src_clk(wclk), .dst_clk(rclk), .in_pulse(wlast), .out_pulse(wlast_rclk),.busy());
// rclk -> wclk
pulse_cross_clock eof_written_wclk_i (.rst(rrst), .src_clk(rclk), .dst_clk(wclk), .in_pulse(eof_written), .out_pulse(eof_written_wclk),.busy());
ram_var_w_var_r #(
.REGISTERS(1),
.LOG2WIDTH_WR(5),
.LOG2WIDTH_RD(6)
) fifo_i (
.rclk (rclk), // input
.raddr (raddr), // input[8:0]
.ren (ren), // input
.regen (regen), // input
.data_out (rdata), // output[63:0]
.wclk (wclk), // input - OK, negedge mclk
.waddr (waddr), // input[10:0]
.we (we), // input
.web (8'hff), // input[7:0]
.data_in (wdata) // input[15:0]
);
endmodule
compressor_jp/compressor393.v
View file @ 69b1d30b
......@@ -119,9 +119,10 @@ module compressor393 # (
`endif
)(
// input rst, // global reset
input xclk, // global clock input, compressor single clock rate
`ifdef USE_XCLK2X
input xclk2x, // global clock input, compressor double clock rate, nominally rising edge aligned
`endif
input mrst, // @posedge mclk, sync reset
input xrst, // @posedge xclk, sync reset
input hrst, // @posedge hclk, sync reset
......@@ -388,7 +389,9 @@ module compressor393 # (
) jp_channel_i (
// .rst (rst), // input
.xclk (xclk), // input
`ifdef USE_XCLK2X
.xclk2x (xclk2x), // input
`endif
.mrst (mrst), // input
.xrst (xrst), // input
.hrst (hrst), // input
......
compressor_jp/csconvert18a.v
View file @ 69b1d30b
......@@ -249,7 +249,7 @@ module csconvert18a(
wire ystrt,nxtline;
reg [7:0] yaddr_r; // address for the external buffer memory to write 16x16x8bit Y data
reg ywe_r; // wrire enable of Y data
reg ywe_r; // write enable of Y data
reg [6:0] caddr_r; // address for the external buffer memory 2x8x8x8bit Cb+Cr data (MSB=0 - Cb, 1 - Cr)
reg cwe_r; // write enable for CbCr data
reg odd_pix; // odd pixel (assumes even number of pixels in a line
......@@ -267,10 +267,10 @@ module csconvert18a(
assign n000 = n000_r;
assign n255 = n255_r;
assign signed_y = signed_y_r; // - now signed char, -128(black) to +127 (white)
assign yaddr = yaddr_r;
assign ywe = ywe_r;
assign caddr = caddr_r;
assign cwe = cwe_r;
assign yaddr = yaddr_r2;
assign ywe = ywe_r2;
assign caddr = caddr_r2;
assign cwe = cwe_r2;
dly_16 #(.WIDTH(1)) i_strt_dly0 (.clk(CLK),.rst(1'b0), .dly(4'd15), .din(pre_first_in), .dout(strt_dly[0]));
dly_16 #(.WIDTH(1)) i_strt_dly1 (.clk(CLK),.rst(1'b0), .dly(4'd15), .din(strt_dly[0]), .dout(strt_dly[1]));
......@@ -532,20 +532,29 @@ Y[1,1]=(0x96*P[1,1]+ 0x1d*((P[1,0]+P[1,2])/2 + 0x4d*((P[0,1] +
reg [7:0] y;
// reg [7:0] y0; // bypass in monochrome mode
wire [7:0] y0 = pdc;
// wire [7:0] y0 = pdc;
reg [7:0] y0_r;
// wire [7:0] y0; // bypass in monochrome mode
reg [15:0] y1,y2,y3;
wire [15:0] y_sum =y1+y2+y3;
reg [15:0] y1,y2,y3;
// TODO: insert register to ease mm1..3 -> y (OK to delay all outputs).
// TODO: reduce width of y1,y2,y3 and correctly round
// wire [15:0] y_sum =y1+y2+y3;
reg [15:0] y_sum_r;
// always @ (posedge CLK) y0 <= pd1_dly; // m1; // equivalent
always @ (posedge CLK) y1 <= mm1;
always @ (posedge CLK) y2 <= mm2;
always @ (posedge CLK) y3 <= mm3;
// wire [7:0] pre_y= mono ? y0 : (y_sum[15:8]+y_sum[7]);
wire [7:0] pre_y= mono ? y0_r : (y_sum_r[15:8]+y_sum_r[7]);
// making y output signed -128..+127
wire [7:0] pre_y= mono ? y0 : (y_sum[15:8]+y_sum[7]);
always @ (posedge CLK) y[7:0] <= pre_y[7:0];
always @ (posedge CLK) signed_y_r[7:0] <= {~pre_y[7], pre_y[6:0]};
always @ (posedge CLK) begin
y1 <= mm1;
y2 <= mm2;
y3 <= mm3;
y0_r <= pdc;
y_sum_r <= y1+y2+y3;
y[7:0] <= pre_y[7:0];
signed_y_r[7:0] <= {~pre_y[7], pre_y[6:0]};
end
// Try easier and hope better algorithm of color extractions that should perform better on gradients.
......@@ -574,19 +583,31 @@ reg use_cr; // in this line cr is calculated. Valid during ywe_r
reg sub_y; // output accumulator/subtractor. 0 - load new data, 1 - subtract. Walid 2 cycles after ywe_r
wire cwe0; // preliminary cwe_r (to be modulated by odd/even pixels)
reg cstrt; //ystrt dealyed by 1
reg cnxt; // nxtline delayed by 1
reg cnxt; // nxtline delayed by 1
reg pre_sel_cbcrmult1;
// delaying, for now uing "old" ywe,cwe, yaddr,caddr - registering them on the output
always @ (posedge CLK) begin
if (~(ywe_r || ystrt || nxtline)) sel_cbcrmult1 <= ~(bayer_phase[1] ^ bayer_phase[0] ^ odd_line);
else sel_cbcrmult1 <= ~sel_cbcrmult1;
// if (~(ywe_r || ystrt || nxtline)) sel_cbcrmult1 <= ~(bayer_phase[1] ^ bayer_phase[0] ^ odd_line);
// else sel_cbcrmult1 <= ~sel_cbcrmult1;
if (~(ywe_r || ystrt || nxtline)) pre_sel_cbcrmult1 <= ~(bayer_phase[1] ^ bayer_phase[0] ^ odd_line);
else pre_sel_cbcrmult1 <= ~pre_sel_cbcrmult1;
sel_cbcrmult1 <=pre_sel_cbcrmult1;
sub_y <= ~sel_cbcrmult1;
cbcrmult1 <= sel_cbcrmult1?y[7:0]:pdc[7:0];
cbcrmult1 <= sel_cbcrmult1?y[7:0]:pdc[7:0];
// cbcrmult1 <= sel_cbcrmult1?y[7:0]:pdc[7:0];
cbcrmult1 <= sel_cbcrmult1?y[7:0]:y0_r[7:0]; // delayed by 1 clock
if (~ywe_r) use_cr <= ~(bayer_phase[1] ^ odd_line);
end
assign cbcrmult2=use_cr?m_cr:m_cb; // maybe will need a register? (use_cr will still be good as it is valid early)
assign cbcrmulto=cbcrmult1*cbcrmult2;
assign cbcrmult2 = use_cr?m_cr:m_cb; // maybe will need a register? (use_cr will still be good as it is valid early)
//assign cbcrmulto = cbcrmult1*cbcrmult2;
assign cbcrmulto = cbcrmult1*cbcrmult2_r;
reg [9:0] cbcrmult2_r; // will be one cycle later than cbcrmult2, but is still OK. Will be absorbed into the DSP block
// will preserve extra bit, but do not need to add half of the truncated MSB - on average there will be no shift after subtraction
always @ (posedge CLK) begin
cbcrmult2_r <= cbcrmult2;
cbcrmultr[10:0] <= cbcrmulto[17:7];
cbcr[10:0] <= sub_y? (cbcr[10:0]-cbcrmultr[10:0]+ 1'b1):cbcrmultr[10:0];
end
......@@ -598,23 +619,38 @@ end
dly_16 #(.WIDTH(1)) i_cwe0 (.clk(CLK),.rst(1'b0), .dly(4'd1), .din(ywe_r), .dout(cwe0));
//SRL16 i_cwe0 (.D(ywe_r ), .Q(cwe0), .A0(1'b1), .A1(1'b0), .A2(1'b0), .A3(1'b0), .CLK(CLK)); // dly=2=1+1
always @ (posedge CLK) begin
cstrt <= ystrt;
cnxt <= nxtline;
cwe_r <= cwe0 && sub_y;
caddr_r[2:0]<= cwe0?(caddr_r[2:0]+cwe_r):3'b0;
if (cstrt) caddr_r[6] <= ~bayer_phase[1];
else if (cnxt) caddr_r[6] <= ~caddr_r[6];
if (cstrt) caddr_r[5:3] <=3'b0;
else if (cnxt) caddr_r[5:3] <=(bayer_phase[1]^caddr_r[6])? caddr_r[5:3]:(caddr_r[5:3]+1);
end
always @ (posedge CLK) begin
cstrt <= ystrt;
cnxt <= nxtline;
// cwe_r <= cwe0 && sub_y;
cwe_r <= cwe0 && !sel_cbcrmult1;
caddr_r[2:0]<= cwe0?(caddr_r[2:0]+cwe_r):3'b0;
if (cstrt) caddr_r[6] <= ~bayer_phase[1];
else if (cnxt) caddr_r[6] <= ~caddr_r[6];
if (cstrt) caddr_r[5:3] <=3'b0;
else if (cnxt) caddr_r[5:3] <=(bayer_phase[1]^caddr_r[6])? caddr_r[5:3]:(caddr_r[5:3]+1);
end
// extra signals delayed by 1 clock
reg ywe_r2, cwe_r2;
reg [6:0] caddr_r2;
reg [7:0] yaddr_r2;
always @ (posedge CLK) begin
ywe_r2 <= ywe_r;
cwe_r2 <= cwe_r;
yaddr_r2 <= yaddr_r;
caddr_r2 <= caddr_r;
end
always @ (posedge CLK) begin
y_eq_0 <= (y0[7:0] == 8'h0);
y_eq_255 <= (y0[7:0] == 8'hff);
y_eq_0 <= (y0_r[7:0] == 8'h0);
y_eq_255 <= (y0_r[7:0] == 8'hff);
if (strt) n000_r[7:0] <= 8'h0;
else if ((n000_r[7:0]!=8'hff) && y_eq_0 && ywe_r) n000_r[7:0] <= n000_r[7:0]+1;
else if ((n000_r[7:0]!=8'hff) && y_eq_0 && ywe_r2) n000_r[7:0] <= n000_r[7:0]+1;
if (strt) n255_r[7:0] <= 8'h0;
else if ((n255_r[7:0]!=8'hff) && y_eq_255 && ywe_r) n255_r[7:0] <= n255_r[7:0]+1;
else if ((n255_r[7:0]!=8'hff) && y_eq_255 && ywe_r2) n255_r[7:0] <= n255_r[7:0]+1;
end
......
compressor_jp/focus_sharp393.v
View file @ 69b1d30b
......@@ -27,7 +27,8 @@
*/
`include "system_defines.vh"
`timescale 1ns/1ps
//TODO: Modify to work with other modes (now only on color)
// TODO: Modify to work with other modes (now only on color)
// NOTE: when removing clk2x, temporarily use clk here, just keep mode ==0 (disabled)
module focus_sharp393(
input clk, // pixel clock, posedge
input clk2x, // 2x pixel clock
......
compressor_jp/huffman393.v
View file @ 69b1d30b
......@@ -2,9 +2,9 @@
** -----------------------------------------------------------------------------**
** huffman333.v
**
** Huffman encoder for JPEG compressorrdy
** Huffman encoder for JPEG compressor
**
** Copyright (C) 2002-20015 Elphelk, Inc
** Copyright (C) 2002-20015 Elphel, Inc
**
** -----------------------------------------------------------------------------**
** huffman393 is free software - hardware description language (HDL) code.
......
compressor_jp/huffman_merge_code_literal.v 0 → 100644
View file @ 69b1d30b
/*******************************************************************************
* Module: huffman_merge_code_literal
* Date:2015-10-22
* Author: andrey
* Description: Merge 1-16 bits of Huffman code with 0..11 bits of literal data,
* align result to MSB : {huffman,literal, {n{1'b0}}
*
* Copyright (c) 2015 Elphel, Inc .
* huffman_merge_code_literal.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* huffman_merge_code_literal.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module huffman_merge_code_literal(
input clk,
input in_valid,
input [15:0] huff_code,
input [ 3:0] huff_code_len, // 0 means 16
input [10:0] literal,
input [ 3:0] literal_len,
output reg out_valid, // latency 5 from input
output reg [26:0] out_bits, // latency 5 from input
output reg [ 4:0] out_len // latency 5 from input
);
reg [10:0] lit0;
reg [10:0] lit1;
reg [10:0] lit2;
reg [15:0] huff0; // SR-s will be extracted?
reg [15:0] huff1;
reg [15:0] huff2;
reg [26:0] data3;
reg [3:0] llen0;
reg [3:0] llen1;
reg [3:0] llen2;
reg [4:0] olen3;
reg [3:0] hlen0;
reg [3:0] hlen1;
reg [4:0] hlen2;
reg [3:0] hlen2m1;
reg [1:0] hlen3m1;
reg [3:0] valid;
always @ (posedge clk) begin
// input layer 0
lit0 <= literal;
llen0 <= literal_len;
huff0 <= huff_code;
hlen0 <= huff_code_len;
valid[0] <= in_valid;
// layer 1
casex (llen0[3:2])
2'b1x: lit1 <= lit0;
2'b01: lit1 <= {lit0[6:0],4'b0};
2'b00: lit1 <= {lit0[2:0],8'b0};
endcase
llen1 <= llen0;
huff1 <= huff0;
hlen1 <= hlen0;
valid[1] <= valid[0];
// layer 2
case (llen1[1:0])
2'b11: lit2 <= lit1;
2'b10: lit2 <= {lit1[9:0], 1'b0};
2'b01: lit2 <= {lit1[8:0], 2'b0};
2'b00: lit2 <= {lit1[7:0], 3'b0};
endcase
llen2 <= llen1;
huff2 <= huff1;
hlen2 <= {~(|hlen1),hlen1};
hlen2m1 <= hlen1 - 1; // s0
valid[2] <= valid[1];
// layer 3
olen3 <= hlen2 + llen2;
case (hlen2m1[3:2])
2'b11: data3 <= {huff2[15:0],lit2[10:0]};
2'b10: data3 <= {huff2[11:0],lit2[10:0], 4'b0};
2'b01: data3 <= {huff2[ 7:0],lit2[10:0], 8'b0};
2'b00: data3 <= {huff2[ 3:0],lit2[10:0],12'b0};
endcase
hlen3m1 <= hlen2m1[1:0];
valid[3] <= valid[2];
//layer4
out_len <= olen3;
case (hlen3m1[1:0])
2'b11: out_bits <= data3;
2'b10: out_bits <= {data3[25:0], 1'b0};
2'b01: out_bits <= {data3[24:0], 2'b0};
2'b00: out_bits <= {data3[23:0], 3'b0};
endcase
out_valid <= valid[3];
end
endmodule
compressor_jp/huffman_snglclk.v 0 → 100644
View file @ 69b1d30b
This diff is collapsed.
compressor_jp/huffman_stuffer_meta.v 0 → 100644
View file @ 69b1d30b
/*******************************************************************************
* Module: huffman_stuffer_meta
* Date:2015-10-26
* Author: andrey
* Description: Huffman encoder, bit stuffer, inser meta-data
* "New" part of the JPEG/JP4 comressor that used double frequency clock
*
* Copyright (c) 2015 Elphel, Inc .
* huffman_stuffer_meta.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* huffman_stuffer_meta.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module huffman_stuffer_meta(
input mclk, // system clock to write tables
input mrst,
input xclk, // pixel clock, sync to incoming data
input en_huffman, // @xclk
input en_stuffer, // @xclk
input abort_stuffer, // @ any
// Interface to program Huffman tables
input tser_we, // enable write to a table
input tser_a_not_d, // address/not data distributed to submodules
input [ 7:0] tser_d, // byte-wide serialized tables address/data to submodules
// Input data
input [15:0] di, // [15:0] specially RLL prepared 16-bit data (to FIFO) (sync to xclk)
input ds, // di valid strobe (sync to xclk)
// time stamping - will copy time at the end of color_first (later than the first hact after vact in the current frame, but before the next one
// and before the data is needed for output
input ts_pre_stb, // @mclk - 1 cycle before receiving 8 bytes of timestamp data
input [7:0] ts_data, // timestamp data (s0,s1,s2,s3,us0,us1,us2,us3==0)
input color_first, // @fradv_clk only used for timestamp
// outputs @ negedge clk
output [31:0] data_out, // [31:0] output data
output data_out_valid,// output data valid
output done, // reset by !en, goes high after some delay after flushing
output running, // from registering timestamp until done
input clk_flush, // other clock to generate synchronized 1-cycle flush_clk output
output flush_clk // 1-cycle flush output @ clk_flush
`ifdef DEBUG_RING
,output test_lbw,
output gotLastBlock, // last block done - flush the rest bits
output [3:0] dbg_etrax_dma
,output dbg_ts_rstb
,output [7:0] dbg_ts_dout
`endif
);
wire [26:0] huffman_do27;
wire [4:0] huffman_dl;
wire huffman_dv;
wire huffman_flush;
wire huffman_last_block;
wire [31:0] stuffer_do32;
wire [1:0] stuffer_bytes;
wire stuffer_dv;
wire stuffer_flush_out;
wire [31:0] escape_do32;
wire [1:0] escape_bytes;
wire escape_dv;
wire escape_flush_out;
huffman_snglclk huffman_snglclk_i (
.xclk (xclk), // input
.rst (~en_huffman), // input
.mclk (mclk), // input
.tser_we (tser_we), // input
.tser_a_not_d (tser_a_not_d), // input
.tser_d (tser_d), // input[7:0]
.di (di), // input[15:0]
.ds (ds), // input
.do27 (huffman_do27), // output[26:0]
.dl (huffman_dl), // output[4:0]
.dv (huffman_dv), // output
.flush (huffman_flush), // output
.last_block (huffman_last_block), // output
`ifdef DEBUG_RING
.test_lbw (test_lbw),
.gotLastBlock (gotLastBlock), // last block done - flush the rest bits
`else
.test_lbw (),
.gotLastBlock (), // last block done - flush the rest bits
`endif
.clk_flush (clk_flush), // input
.flush_clk (flush_clk), // output
.fifo_or_full() // output
);
bit_stuffer_27_32 #(
.DIN_LEN(27)
) bit_stuffer_27_32_i (
.xclk (xclk), // input
.rst (~en_huffman), // input
.din (huffman_do27), // input[26:0]
.dlen (huffman_dl), // input[4:0]
.ds (huffman_dv), // input
.flush_in (huffman_flush), // input
.d_out (stuffer_do32), // output[31:0]
.bytes_out (stuffer_bytes), // output[1:0] reg
.dv (stuffer_dv), // output reg
.flush_out (stuffer_flush_out) // output reg
);
bit_stuffer_escape bit_stuffer_escape_i (
.xclk (xclk), // input
.rst (~en_huffman), // input
.din (stuffer_do32), // input[31:0]
.bytes_in (stuffer_bytes), // input[1:0]
.in_stb (stuffer_dv), // input
.flush_in (stuffer_flush_out), // input
.d_out (escape_do32), // output[31:0] reg
.bytes_out (escape_bytes), // output[1:0] reg
.dv (escape_dv), // output reg
.flush_out (escape_flush_out) // output reg
);
bit_stuffer_metadata bit_stuffer_metadata_i (
.mclk (mclk), // input
.mrst (mrst), // input
.xclk (xclk), // input
.xrst (~en_stuffer), // input
.last_block (huffman_last_block), // input
.ts_pre_stb (ts_pre_stb), // input
.ts_data (ts_data), // input[7:0]
.color_first (color_first), // input
.din (escape_do32), // input[31:0]
.bytes_in (escape_bytes), // input[1:0]
.in_stb (escape_dv), // input
.flush (escape_flush_out), // input
.abort (abort_stuffer), // input
.data_out (data_out), // output[31:0] reg
.data_out_valid (data_out_valid), // output reg
.done (done), // output reg
.running (running) // output reg
);
endmodule
compressor_jp/jp_channel.v
View file @ 69b1d30b
This diff is collapsed.
compressor_jp/varlen_encode393.v
View file @ 69b1d30b
......@@ -39,15 +39,7 @@ module varlen_encode393 (
output reg [3:0] l, // [3:0] code length
output reg [3:0] l_late,// delayed l (sync to q)
output reg [10:0] q); // [10:0]code
/*
varlen_encode393 i_varlen_encode(.clk(clk),
.en(stuffer_was_rdy), //will enable registers. 0 - freeze
.start(steps[0]),
.d(sval[11:0]), // 12-bit signed
.l(var_dl[ 3:0]), // [3:0] code length
.l_late(var_dl_late[3:0]),
.q(var_do[10:0])); // [10:0]code
*/
reg [11:0] d1;
reg [10:0] q0;
reg [2:0] cycles;
......
compressor_jp/varlen_encode_snglclk.v 0 → 100644
View file @ 69b1d30b
/*
** -----------------------------------------------------------------------------**
** varlen_encode_snglclk.v
**
** Part of the Huffman encoder for JPEG compressor - variable length encoder
**
** Copyright (C) 2002-2015 Elphel, Inc
**
** -----------------------------------------------------------------------------**
** varlen_encode_snglclk.v is free software - hardware description language (HDL) code.
**
** This program is free software: you can redistribute it and/or modify
** it under the terms of the GNU General Public License as published by
** the Free Software Foundation, either version 3 of the License, or
** (at your option) any later version.
**
** This program is distributed in the hope that it will be useful,
** but WITHOUT ANY WARRANTY; without even the implied warranty of
** MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
** GNU General Public License for more details.
**
** You should have received a copy of the GNU General Public License
** along with this program. If not, see <http://www.gnu.org/licenses/>.
** -----------------------------------------------------------------------------**
**
*/
module varlen_encode_snglclk (
input clk, // posedge
input [11:0] d, // 12-bit 2-s complement
output reg [3:0] l, // [3:0] code length, latency 2 clocks
output reg [10:0] q); // [10:0] literal, latency = 2 clocks
reg [11:0] d1;
wire this0 = |d1[ 3:0];
wire this1 = |d1[ 7:4];
wire this2 = |d1[10:8];
wire [1:0] codel0 = {|d1[ 3: 2],d1[ 3] || (d1[ 1] & ~d1[ 2])};
wire [1:0] codel1 = {|d1[ 7: 6],d1[ 7] || (d1[ 5] & ~d1[ 6])};
wire [1:0] codel2 = {|d1[ 10], (d1[ 9] & ~d1[10])};
wire [3:0] codel = this2? {2'b10,codel2[1:0]} :
(this1? {2'b01, codel1[1:0]} :
(this0 ? {2'b00,codel0[1:0]} : 4'b1111)); // after +1 will be 0;
always @(posedge clk) begin
d1[ 11] <= d[11];
d1[10:0] <= d[11] ? -d[10:0] : d[10:0];
q[10:0] <= d1[11] ? ~d1[10:0] : d1[10:0];
l <= codel[3:0]+1; // needed only ASAP, valid only 2 cycles after start
end
endmodule
compressor_jp/xdct393r.v 0 → 100644
View file @ 69b1d30b
This diff is collapsed.
ddr3/ddr3.v
View file @ 69b1d30b
......@@ -85,7 +85,7 @@
* 1.69 SPH 03/19/13 Update tZQCS, tZQinit, tZQoper timing parameters
* 1.70 SPH 04/08/14 Update tRFC to PRECARGE check
*****************************************************************************************/
`define den4096Mb 1
`include "system_defines.vh"
// DO NOT CHANGE THE TIMESCALE
// MAKE SURE YOUR SIMULATOR USES "PS" RESOLUTION
`timescale 1ps / 1ps
......@@ -121,6 +121,19 @@ module ddr3 (
// to select the correct component density before continuing
ERROR: You must specify component density with +define+den____Mb.
`endif
initial begin
$display ("TCK_MIN = %d", TCK_MIN);
`ifdef sg15E
$display ("sg15E = `sg15E");
`endif
`ifdef sg093 // sg093 is equivalent to the JEDEC DDR3-2133 (14-14-14) speed bin
$display ("sg093");
`elsif sg15E
$display ("sg15E");
`endif
end
parameter check_strict_mrbits = 1;
parameter check_strict_timing = 1;
parameter feature_pasr = 1;
......
fpga_version.vh
View file @ 69b1d30b
parameter FPGA_VERSION = 32'h03930042;
\ No newline at end of file
parameter FPGA_VERSION = 32'h03930065; // (same rev) all met, using "old" (non-inverted) phase - OK (full phase range)
// parameter FPGA_VERSION = 32'h03930065; // switch phy_top.v (all met) - OK with inverted phase control (reduced phase range)
// parameter FPGA_VERSION = 32'h03930064; // switch mcomtr_sequencer.v (xclk not met) - wrong!
// parameter FPGA_VERSION = 32'h03930063; // switch mcntrl_linear_rw.v (met) good, worse mem valid phases
// parameter FPGA_VERSION = 32'h03930062; // (met)debugging - what was broken (using older versions of some files) - mostly OK (some glitches)
// parameter FPGA_VERSION = 32'h03930061; // restored bufr instead of bufio for memory high speed clock
// parameter FPGA_VERSION = 32'h03930060; // moving CLK1..3 in memory controller MMCM, keeping CLK0 and FB. Stuck at memory calib
// parameter FPGA_VERSION = 32'h0393005f; // restored mclk back to 200KHz, registers added to csconvert18a
// parameter FPGA_VERSION = 32'h0393005e; // trying mclk = 225 MHz (was 200MHz) define MCLK_VCO_MULT 18
// parameter FPGA_VERSION = 32'h0393005d; // trying mclk = 250 MHz (was 200MHz) define MCLK_VCO_MULT 20
// parameter FPGA_VERSION = 32'h0393005c; // 250MHz OK, no timing violations
// parameter FPGA_VERSION = 32'h0393005b; // 250MHz Not tested, timing violation in bit_stuffer_escape: xclk -0.808 -142.047 515
// parameter FPGA_VERSION = 32'h0393005a; // Trying xclk = 250MHz - timing viloations in xdct393, but particular hardware works
// parameter FPGA_VERSION = 32'h03930059; // 'new' (no pclk2x, no xclk2x clocks) sensor/converter w/o debug - OK
// parameter FPGA_VERSION = 32'h03930058; // 'new' (no pclk2x, no xclk2x clocks) sensor/converter w/o debug - broken end of frame
// parameter FPGA_VERSION = 32'h03930057; // 'new' (no pclk2x, yes xclk2x clocks) sensor/converter w/o debug - OK
// parameter FPGA_VERSION = 32'h03930056; // 'new' (no 2x clocks) sensor/converter w/o debug - broken
// parameter FPGA_VERSION = 32'h03930055; // 'old' sensor/converter w/o debug, fixed bug with irst - OK
// parameter FPGA_VERSION = 32'h03930054; // 'old' sensor/converter with debug
// parameter FPGA_VERSION = 32'h03930053; // trying if(reset ) reg <- 'bx
\ No newline at end of file
includes/x393_parameters.vh
View file @ 69b1d30b
......@@ -138,7 +138,11 @@
parameter real REFCLK_FREQUENCY = 200.0, // 300.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter CLKIN_PERIOD = 20, // 10, //ns >1.25, 600<Fvco<1200 // Hardware 150MHz , change to | 6.667
`ifdef MCLK_VCO_MULT
parameter CLKFBOUT_MULT = `MCLK_VCO_MULT ,
`else
parameter CLKFBOUT_MULT = 16, // 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE | 16
`endif
parameter CLKFBOUT_MULT_REF = 16, // 18, // 9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE | 6
parameter CLKFBOUT_DIV_REF = 4, // 200Mhz 3, // To get 300MHz for the reference clock
`else
......@@ -150,11 +154,12 @@
parameter CLKFBOUT_DIV_REF = 3, // To get 300MHz for the reference clock
`endif
parameter DIVCLK_DIVIDE= 1,
parameter CLKFBOUT_USE_FINE_PS= 0, //1, // 0 - old, 1 - new
parameter CLKFBOUT_PHASE = 0.000,
parameter SDCLK_PHASE = 0.000,
parameter CLK_PHASE = 0.000,
parameter CLK_PHASE = 0.000, //11.25, /// 0.000,
parameter CLK_DIV_PHASE = 0.000,
parameter MCLK_PHASE = 90.000,
parameter MCLK_PHASE = 90.000, //78.75, // 90.000,
parameter REF_JITTER1 = 0.010,
parameter SS_EN = "FALSE",
parameter SS_MODE = "CENTER_HIGH",
......@@ -273,6 +278,7 @@
parameter MCONTR_LINTILE_SINGLE = 9, // read/write a single page
parameter MCONTR_LINTILE_REPEAT = 10, // read/write pages until disabled
parameter MCONTR_LINTILE_DIS_NEED = 11, // disable 'need' request
parameter MCONTR_LINTILE_SKIP_LATE = 12, // skip actual R/W operation when it is too late, advance pointers
// Channel test module parameters
parameter MCNTRL_TEST01_ADDR= 'h0f0,
......@@ -429,11 +435,20 @@
parameter SENS_CTRL_ARST = 2, // 3: 2
parameter SENS_CTRL_ARO = 4, // 5: 4
parameter SENS_CTRL_RST_MMCM = 6, // 7: 6
//`ifdef HISPI
parameter SENS_CTRL_IGNORE_EMBED =8, // 9: 8
//`else
parameter SENS_CTRL_EXT_CLK = 8, // 9: 8
//`endif
parameter SENS_CTRL_LD_DLY = 10, // 10
//`ifdef HISPI
parameter SENS_CTRL_GP0= 12, // 13:12
parameter SENS_CTRL_GP1= 14, // 15:14
//`else
parameter SENS_CTRL_QUADRANTS = 12, // 17:12, enable - 20
parameter SENS_CTRL_QUADRANTS_WIDTH = 6,
parameter SENS_CTRL_QUADRANTS_EN = 20, // 17:12, enable - 20 (2 bits reserved)
//`endif
parameter SENSIO_STATUS = 'h1,
parameter SENSIO_JTAG = 'h2,
// SENSIO_JTAG register bits
......@@ -442,7 +457,9 @@
parameter SENS_JTAG_TCK = 4,
parameter SENS_JTAG_TMS = 2,
parameter SENS_JTAG_TDI = 0,
//`ifndef HISPI
parameter SENSIO_WIDTH = 'h3, // 1.. 2^16, 0 - use HACT
//`endif
parameter SENSIO_DELAYS = 'h4, // 'h4..'h7
// 4 of 8-bit delays per register
// sensor_i2c_io command/data write registers s (relative to SENSOR_GROUP_ADDR)
......@@ -466,10 +483,13 @@
parameter SENSI2C_IOSTANDARD = "LVCMOS25",
parameter SENSI2C_SLEW = "SLOW",
//`ifndef HISPI
//sensor_fifo parameters
parameter SENSOR_DATA_WIDTH = 12,
parameter SENSOR_FIFO_2DEPTH = 4,
parameter SENSOR_FIFO_DELAY = 4'd5, // 7,
parameter SENSOR_DATA_WIDTH = 12,
parameter SENSOR_FIFO_2DEPTH = 4,
parameter [3:0] SENSOR_FIFO_DELAY = 5, // 7,
//`endif
// other parameters for histogram_saxi module
parameter HIST_SAXI_ADDR_MASK = 'h7f0,
parameter HIST_SAXI_MODE_WIDTH = 8,
......@@ -504,16 +524,31 @@
parameter real SENS_REFCLK_FREQUENCY = 200.0,
`endif
parameter SENS_HIGH_PERFORMANCE_MODE = "FALSE",
//`ifdef HISPI
parameter PXD_CAPACITANCE = "DONT_CARE",
parameter PXD_CLK_DIV = 10, // 220MHz -> 22MHz
parameter PXD_CLK_DIV_BITS = 4,
//`endif
parameter SENS_PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
parameter SENS_PCLK_PERIOD = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
// parameter SENS_PCLK_PERIOD = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"
parameter CLKFBOUT_MULT_SENSOR = 8, // 100 MHz --> 800 MHz
// parameters for the sensor-synchronous clock PLL
`ifdef HISPI
parameter CLKIN_PERIOD_SENSOR = 3.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 3, // 330 MHz --> 990 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
`else
parameter CLKIN_PERIOD_SENSOR = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter CLKFBOUT_MULT_SENSOR = 8, // 100 MHz --> 800 MHz
parameter CLKFBOUT_PHASE_SENSOR = 0.000, // CLOCK FEEDBACK phase in degrees (3 significant digits, -360.000...+360.000)
parameter IPCLK_PHASE = 0.000,
parameter IPCLK2X_PHASE = 0.000,
`endif
// parameter BUF_IPCLK = "BUFMR", //G", // "BUFR", // BUFR fails for both clocks for sensors1 and 3
// parameter BUF_IPCLK2X = "BUFMR", //G", // "BUFR",
......@@ -530,11 +565,23 @@
parameter BUF_IPCLK2X_SENS3 = "BUFG", // "BUFR",
parameter SENS_DIVCLK_DIVIDE = 1, // Integer 1..106. Divides all outputs with respect to CLKIN
parameter SENS_REF_JITTER1 = 0.010, // Expectet jitter on CLKIN1 (0.000..0.999)
parameter SENS_REF_JITTER1 = 0.010, // Expected jitter on CLKIN1 (0.000..0.999)
parameter SENS_REF_JITTER2 = 0.010,
parameter SENS_SS_EN = "FALSE", // Enables Spread Spectrum mode
parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
parameter SENS_SS_MOD_PERIOD = 10000, // integer 4000-40000 - SS modulation period in ns
//`ifdef HISPI
parameter HISPI_MSB_FIRST = 0,
parameter HISPI_NUMLANES = 4,
parameter HISPI_CAPACITANCE = "DONT_CARE",
parameter HISPI_DIFF_TERM = "TRUE",
parameter HISPI_DQS_BIAS = "TRUE",
parameter HISPI_IBUF_DELAY_VALUE = "0",
parameter HISPI_IBUF_LOW_PWR = "TRUE",
parameter HISPI_IFD_DELAY_VALUE = "AUTO",
parameter HISPI_IOSTANDARD = "DEFAULT",
//`endif
parameter CMPRS_NUM_AFI_CHN = 1, // 2, // 1 - multiplex all 4 compressors to a single AXI_HP, 2 - split between to AXI_HP
parameter CMPRS_GROUP_ADDR = 'h600, // total of 'h60
......@@ -760,12 +807,19 @@
parameter CLKFBOUT_MULT_AXIHP = 18, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKOUT_DIV_AXIHP = 6, // To get 150MHz for the reference clock
parameter BUF_CLK1X_AXIHP = "BUFG", // "BUFG", "BUFH", "BUFR", "NONE"
`ifdef HISPI
parameter CLKIN_PERIOD_PCLK = 42, // 24MHz (actually needed is 24.4444
parameter DIVCLK_DIVIDE_PCLK = 1,
parameter CLKFBOUT_MULT_PCLK = 36, // 880 MHz
parameter CLKOUT_DIV_PCLK = 4, // 220 MHz
parameter CLKOUT_DIV_PCLK2X = 2, // 440 MHz
`else
parameter CLKIN_PERIOD_PCLK = 42, // 24MHz
parameter DIVCLK_DIVIDE_PCLK = 1,
parameter CLKFBOUT_MULT_PCLK = 40, // 960 MHz
parameter CLKOUT_DIV_PCLK = 10, // 96MHz
parameter CLKOUT_DIV_PCLK2X = 5, // 192 MHz
`endif
parameter PHASE_CLK2X_PCLK = 0.000,
parameter BUF_CLK1X_PCLK = "BUFG",
parameter BUF_CLK1X_PCLK2X = "BUFG",
......@@ -773,7 +827,11 @@
parameter CLKIN_PERIOD_XCLK = 20, // 50MHz
parameter DIVCLK_DIVIDE_XCLK = 1,
parameter CLKFBOUT_MULT_XCLK = 20, // 50*20=1000 MHz
`ifdef USE_XCLK2X
parameter CLKOUT_DIV_XCLK = 10, // 100 MHz
`else
parameter CLKOUT_DIV_XCLK = 4, // 250 MHz
`endif
parameter CLKOUT_DIV_XCLK2X = 5, // 200 MHz
parameter PHASE_CLK2X_XCLK = 0.000,
parameter BUF_CLK1X_XCLK = "BUFG",
......
includes/x393_simulation_parameters.vh
View file @ 69b1d30b
......@@ -38,6 +38,10 @@
// parameter SENSOR12BITS_NROWA = 1, // number of "blank rows" from last hact to end of vact
// parameter nAV = 24, //240; // clocks from ARO to VACT (actually from en_dclkd)
// parameter SENSOR12BITS_NBPF = 20, //16; // bpf length
parameter SENSOR_IMAGE_TYPE0 = "NORM", // "RUN1",
parameter SENSOR_IMAGE_TYPE1 = "RUN1",
parameter SENSOR_IMAGE_TYPE2 = "NORM", // "RUN1",
parameter SENSOR_IMAGE_TYPE3 = "RUN1",
parameter SENSOR12BITS_NGPL = 8, // bpf to hact
parameter SENSOR12BITS_NVLO = 1, // VACT=0 in video mode (clocks)
//parameter tMD = 14; //
......
includes/x393_tasks_mcntrl_timing.vh
View file @ 69b1d30b
......@@ -193,11 +193,19 @@
task axi_set_phase;
input [PHASE_WIDTH-1:0] phase;
reg [PHASE_WIDTH-1:0] inverted_phase;
begin
$display("SET CLOCK PHASE to 0x%x @ %t",phase,$time);
write_contol_register(LD_DLY_PHASE, {{(32-PHASE_WIDTH){1'b0}},phase}); // control regiter address
if (CLKFBOUT_USE_FINE_PS) begin
inverted_phase = -phase;
$display("SET CLOCK INVERTED PHASE (0x%x) to 0x%x @ %t",phase,inverted_phase,$time);
write_contol_register(LD_DLY_PHASE, {{(32-PHASE_WIDTH){1'b0}},inverted_phase}); // control regiter address
target_phase <= inverted_phase;
end else begin
$display("SET CLOCK PHASE to 0x%x @ %t",phase,$time);
write_contol_register(LD_DLY_PHASE, {{(32-PHASE_WIDTH){1'b0}},phase}); // control regiter address
target_phase <= phase;
end
write_contol_register(DLY_SET,0);
target_phase <= phase;
end
endtask
......
input_data/sensor_run1.dat 0 → 100644
View file @ 69b1d30b
This diff is collapsed.
memctrl/cmd_encod_tiled_32_rd.v
View file @ 69b1d30b
......@@ -224,7 +224,7 @@ module cmd_encod_tiled_32_rd #(
// ROM-based (registered output) encoded sequence
always @ (posedge clk) begin
if (mrst) rom_r <= 0;
if (mrst) rom_r <= 0; // TODO: make mrst cause gen_addr = 4'hf?
else case (gen_addr)
4'h0: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT) | (1 << ENC_NOP) | (1 << ENC_PAUSE_SHIFT); // here does not matter, just to work with masked ACTIVATE
4'h1: rom_r <= (ENC_CMD_ACTIVATE << ENC_CMD_SHIFT);
......
memctrl/mcntrl393.v
View file @ 69b1d30b
This diff is collapsed.
memctrl/mcntrl_linear_rw.v
View file @ 69b1d30b
This diff is collapsed.
memctrl/memctrl16.v
View file @ 69b1d30b
This diff is collapsed.
memctrl/phy/byte_lane.v
View file @ 69b1d30b
......@@ -78,7 +78,27 @@ reg set_r=0;
reg dci_disable_dqs_r, dci_disable_dq_r;
reg [7:0] ld_odly=8'b0, ld_idly=8'b0;
reg ld_odly_dqs,ld_idly_dqs,ld_odly_dm;
BUFR iclk_i (.O(iclk),.I(dqs_read), .CLR(1'b0),.CE(1'b1)); // OK, works with constraint? Seems now work w/o
BUFR iclk_i (.O(iclk),.I(dqs_read), .CLR(1'b0),.CE(1'b1)); // OK, works with constraint? Seems now work w/o
/*
wire iclk_int;
//BUFR iclk_int_i (.O(iclk_int), .I(dqs_read), .CLR(1'b0),.CE(1'b1));
assign iclk_int = dqs_read && !rst;
BUFIO iclk_i (.O(iclk), .I(iclk_int));
CRITICAL WARNING: [Vivado 12-1411] Cannot set LOC property of ports, Could not legally place instance
mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dqs_i/iobufs_dqs_i/IBUFDS/IBUFDS_M at N7 (IOB_X1Y120
since it belongs to a shape containing instance mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/iclk_i.
The shape requires relative placement between
mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/dqs_i/iobufs_dqs_i/IBUFDS/IBUFDS_M and
mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/iclk_i that cannnot be honored because it would result in
an invalid location for mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/iclk_i. [x393.xdc:193]
----------
ERROR: [DRC 23-20] Rule violation (RTSTAT-1) Unrouted net - 2 net(s) are unrouted. The problem bus(es) and/or net(s) are
mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane1_i/iclk_int,
mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/byte_lane0_i/iclk_int.
*/
wire [9:0] decode_sel={
(dly_addr[3:0]==9)?1'b1:1'b0,
(dly_addr[3:0]==8)?1'b1:1'b0,
......
memctrl/phy/mcontr_sequencer.v
View file @ 69b1d30b
......@@ -80,6 +80,7 @@ module mcontr_sequencer #(
parameter CLKFBOUT_MULT_REF = 9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_DIV_REF = 3, // To get 300MHz for the reference clock
parameter DIVCLK_DIVIDE= 1,
parameter CLKFBOUT_USE_FINE_PS= 1, // 0 - old, 1 - new
parameter CLKFBOUT_PHASE = 0.000,
parameter SDCLK_PHASE = 0.000,
parameter CLK_PHASE = 0.000,
......@@ -505,6 +506,7 @@ module mcontr_sequencer #(
.rclk (mclk), // input
.raddr (cmd_addr), // input[9:0]
.ren (ren0), // input TODO: verify cmd_busy[0] is correct (was cmd_busy ). TODO: make cleaner ren/regen
// .ren (ren0 && !sequence_done), // input TODO: verify cmd_busy[0] is correct (was cmd_busy ). TODO: make cleaner ren/regen
.regen (ren0), // input
.data_out (phy_cmd0_word), // output[31:0]
.wclk (cmd0_clk), // input
......@@ -513,14 +515,19 @@ module mcontr_sequencer #(
.web (4'hf), // input[3:0]
.data_in (cmd0_data) // input[31:0]
);
// NOTE: Simulation sometimes may show:
// Memory Collision Error on RAMB36E1 : x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd1_buf_i.RAMB36E1_i.genblk1.INT_RAMB_TDP.chk_for_col_msg
// It is OK, as the sequencer reads 2 extra (unused) locations before it stops at the end of block (stop depends on the read memory that has latency)
// Command sequence memory 0 ("manual"):
// Command sequence memory 1
ram_1kx32_1kx32 #(
.REGISTERS (1) // (0) // register output
) cmd1_buf_i (
.rclk (mclk), // input
.raddr (cmd_addr), // input[9:0]
.ren ( ren1), // input ??? TODO: make cleaner ren/regen
// .ren ( ren1 && !sequence_done), // input ??? TODO: make cleaner ren/regen
.regen ( ren1), // input ???
.data_out (phy_cmd1_word), // output[31:0]
.wclk (cmd1_clk), // input
......@@ -545,9 +552,9 @@ module mcontr_sequencer #(
.CLKFBOUT_MULT_REF (CLKFBOUT_MULT_REF),
.CLKFBOUT_DIV_REF (CLKFBOUT_DIV_REF),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKFBOUT_USE_FINE_PS (CLKFBOUT_USE_FINE_PS),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE),
.SDCLK_PHASE (SDCLK_PHASE), /// debugging
.CLK_PHASE (CLK_PHASE),
.CLK_DIV_PHASE (CLK_DIV_PHASE),
.MCLK_PHASE (MCLK_PHASE),
......
memctrl/phy/phy_cmd.v
View file @ 69b1d30b
......@@ -36,8 +36,9 @@ module phy_cmd#(
parameter CLKFBOUT_MULT_REF = 9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_DIV_REF = 3, // To get 300MHz for the reference clock
parameter DIVCLK_DIVIDE= 1,
parameter CLKFBOUT_USE_FINE_PS= 1, // 0 - old, 1 - new
parameter CLKFBOUT_PHASE = 0.000,
parameter SDCLK_PHASE = 0.000,
parameter SDCLK_PHASE = 0.000,
parameter CLK_PHASE = 0.000,
parameter CLK_DIV_PHASE = 0.000,
parameter MCLK_PHASE = 90.000,
......@@ -379,6 +380,7 @@ module phy_cmd#(
.CLKFBOUT_MULT_REF(CLKFBOUT_MULT_REF),
.CLKFBOUT_DIV_REF (CLKFBOUT_DIV_REF),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKFBOUT_USE_FINE_PS (CLKFBOUT_USE_FINE_PS),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE),
.SDCLK_PHASE (SDCLK_PHASE),
.CLK_PHASE (CLK_PHASE),
......
memctrl/phy/phy_top.v
View file @ 69b1d30b
......@@ -43,8 +43,9 @@ module phy_top #(
parameter CLKFBOUT_MULT_REF = 9, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE
parameter CLKFBOUT_DIV_REF = 3, // To get 300MHz for the reference clock
parameter DIVCLK_DIVIDE= 1,
parameter CLKFBOUT_USE_FINE_PS =1, // if 1 move CLKFBOUT_PHASE and SDCLK_PHASE, if 0 - other outputs (moved phases should be 0/same)
parameter CLKFBOUT_PHASE = 0.000,
parameter SDCLK_PHASE = 0.000,
parameter SDCLK_PHASE = 0.000,
parameter CLK_PHASE = 0.000,
parameter CLK_DIV_PHASE = 0.000,
parameter MCLK_PHASE = 90.000,
......@@ -312,6 +313,7 @@ wire sdclk; // BUFIO
// So shifting phase dynamically by plus/- 113 moves SDCLK by a full period (2.5ns) forward and backward (113= 0x71)
wire clk_pre, clk_div_pre, sdclk_pre, mclk_pre, clk_fb;
BUFR clk_bufr_i (.O(clk), .CE(), .CLR(), .I(clk_pre));
//BUFIO clk_buf_i (.O(clk), .I(clk_pre));
BUFR clk_div_bufr_i (.O(clk_div), .CE(), .CLR(), .I(clk_div_pre));
BUFIO iclk_bufio_i (.O(sdclk), .I(sdclk_pre) );
//BUFIO clk_ref_i (.O(ref_clk), .I(clk_ref_pre));
......@@ -325,19 +327,21 @@ BUFG mclk_i (.O(mclk),.I(mclk_pre) );
.BANDWIDTH (BANDWIDTH),
.CLKFBOUT_MULT_F (CLKFBOUT_MULT),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.CLKFBOUT_PHASE (CLKFBOUT_PHASE),
.CLKOUT0_PHASE (SDCLK_PHASE),
.CLKOUT1_PHASE (CLK_PHASE),
.CLKOUT2_PHASE (CLK_DIV_PHASE),
.CLKOUT3_PHASE (MCLK_PHASE),
.CLKFBOUT_PHASE (CLKFBOUT_USE_FINE_PS? 0.0 : CLKFBOUT_PHASE),
.CLKOUT0_PHASE (CLKFBOUT_USE_FINE_PS? 0.0 : SDCLK_PHASE),
.CLKOUT1_PHASE (CLKFBOUT_USE_FINE_PS? CLK_PHASE : 0.0),
.CLKOUT2_PHASE (CLKFBOUT_USE_FINE_PS? CLK_DIV_PHASE : 0.0),
.CLKOUT3_PHASE (CLKFBOUT_USE_FINE_PS? MCLK_PHASE : 90.000), // (78.75), // (MCLK_PHASE), // should be multiple of 11.25 (90.000/8)
//ERROR: [DRC 23-20] Rule violation (AVAL-139) Phase shift check - The MMCME2_ADV cell mcntrl393_i/memctrl16_i/mcontr_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i has a fractional CLKOUT3_PHASE value (75.000) with CLKOUT3_USE_FINE_PS set to FALSE. It should be a multiple of [45 / CLKOUT3_DIVIDE] = [45 / 4] = 11.250.
// .CLKOUT4_PHASE (0.000),
// .CLKOUT5_PHASE (0.000),
// .CLKOUT6_PHASE (0.000),
.CLKFBOUT_USE_FINE_PS ("FALSE"),
.CLKOUT0_USE_FINE_PS ("FALSE"),
.CLKOUT1_USE_FINE_PS ("TRUE"),
.CLKOUT2_USE_FINE_PS ("TRUE"),
.CLKOUT3_USE_FINE_PS ("TRUE"),
.CLKFBOUT_USE_FINE_PS (CLKFBOUT_USE_FINE_PS? "TRUE" : "FALSE"),
.CLKOUT0_USE_FINE_PS (CLKFBOUT_USE_FINE_PS? "TRUE" : "FALSE"),
.CLKOUT1_USE_FINE_PS (CLKFBOUT_USE_FINE_PS? "FALSE" : "TRUE"),
.CLKOUT2_USE_FINE_PS (CLKFBOUT_USE_FINE_PS? "FALSE" : "TRUE"),
.CLKOUT3_USE_FINE_PS (CLKFBOUT_USE_FINE_PS? "FALSE" : "TRUE"),
// .CLKOUT4_USE_FINE_PS("FALSE"),
// .CLKOUT5_USE_FINE_PS("FALSE"),
// .CLKOUT6_USE_FINE_PS("FALSE"),
......
py393/dbg/x393_mcntrl.pickle
View file @ 69b1d30b
This diff is collapsed.
py393/import_verilog_parameters.py
View file @ 69b1d30b
......@@ -393,6 +393,11 @@ class ImportVerilogParameters(object):
# Try binary operation
# repeat until end of line or ')'
while True:
try:
opStart=skipWS(operand1[2])
except:
print("line=\n",line)
print("defines=\n",self.defines)
opStart=skipWS(operand1[2])
if (opStart == len(line)) : # or (line[opStart] == ')'): # just primary
return operand1
......@@ -485,7 +490,7 @@ class ImportVerilogParameters(object):
# Macro substitution excluding the very first character
if "`" in line [1:]:
for define in self.defines:
line.replace("`"+define,self.defines[define])
line = line.replace("`"+define,self.defines[define])
if line[0]== "`":
tokens=line[1:].replace("\t"," ").split(" ",1) #second tokens
for i in (1,2):
......
py393/vrlg.py
View file @ 69b1d30b
This diff is collapsed.
py393/x393_cmprs.py
View file @ 69b1d30b
......@@ -295,7 +295,7 @@ class X393Cmprs(object):
@param byte32 - 32-byte columns
@param tile_width tile width,
@param extra_pages extra pages needed (1)
@param disable_need disable need (preference to sesnor channels - they can not wait
@param disable_need disable need (preference to sensor channels - they can not wait
"""
tile_vstep = 16
tile_height= 18
......
py393/x393_cmprs_afi.py
View file @ 69b1d30b
......@@ -102,7 +102,8 @@ class X393CmprsAfi(object):
channel,
cirbuf_start = 0x27a00000,
circbuf_len = 0x1000000,
verbose = 1):
verbose = 1,
num_lines_print = 20):
"""
Returns image metadata (start, length,timestamp) or null
@param port_afi - AFI port (0/1), currently only 0
......@@ -140,13 +141,13 @@ class X393CmprsAfi(object):
if img_start < 0:
img_start += circbuf_len
if verbose >0:
for a in range ( img_start, img_start + 0x10, 4):
for a in range ( img_start, img_start + (0x10 * num_lines_print), 4):
d = self.x393_mem.read_mem(cirbuf_start + a)
if (a % 16) == 0:
print ("\n%08x: "%(a),end ="" )
print("%02x %02x %02x %02x "%(d & 0xff, (d >> 8) & 0xff, (d >> 16) & 0xff, (d >> 24) & 0xff), end = "")
print("\n...",end="")
for a0 in range ( last_image_chunk - 0x10, last_image_chunk + 0x20, 4):
for a0 in range ( last_image_chunk - (0x10 * num_lines_print), last_image_chunk + 0x20, 4):
a = a0
if (a < 0):
a -=circbuf_len
......
py393/x393_jpeg.py
View file @ 69b1d30b
......@@ -820,6 +820,8 @@ ff d9
"""
"""
Camera compressors testing sequence
cd /usr/local/verilog/; test_mcntrl.py @hargs
#or (for debug)
cd /usr/local/verilog/; test_mcntrl.py @hargs -x -v
Next 2 lines needed to use jpeg functionality if the program was started w/o setup_all_sensors True None 0xf
......@@ -830,7 +832,7 @@ specify_window
measure_all "*DI"
# Run 'measure_all' again (but w/o arguments) to perform full calibration (~10 minutes) and save results.
# Needed after new bitstream
# setup_all_sensors , 3-rd argument - bitmask of sesnors to initialize
# setup_all_sensors , 3-rd argument - bitmask of sensors to initialize
setup_all_sensors True None 0xf
#reset all compressors - NOT NEEDED
......@@ -849,7 +851,7 @@ compressor_control all None None None None None 3
#Gamma 0.57
program_gamma all 0 0.57 0.04
program_gamma all 0 1.0 0.04
#colors - outdoor
write_sensor_i2c all 1 0 0x9035000a
write_sensor_i2c all 1 0 0x902c000e
......@@ -886,7 +888,24 @@ axi_write_single_w 0x686 0x079800a3
axi_write_single_w 0x6a6 0x079800a3
axi_write_single_w 0x6b6 0x079800a3
#run copmpressors once (#1 - stop gracefully, 0 - reset, 2 - single, 3 - repetitive with sync to sensors)
#color pattern:
#turn off black shift (normally 0xa8)
write_sensor_i2c all 1 0 0x90490000
write_sensor_i2c all 1 0 0x90a00001
write_sensor_i2c all 1 0 0x90a00009
write_sensor_i2c all 1 0 0x90a00019
#running 1:
write_sensor_i2c all 1 0 0x90a00029
...
write_sensor_i2c all 1 0 0x90a00041
#color pattern off:
write_sensor_i2c all 1 0 0x90a00000
#run compressors once (#1 - stop gracefully, 0 - reset, 2 - single, 3 - repetitive with sync to sensors)
compressor_control all 2
jpeg_write "img.jpeg" all
......@@ -898,6 +917,14 @@ compressor_control all 2
jpeg_write "img.jpeg" all 85
-----
#turn off black shift (normally 0xa8)
write_sensor_i2c all 1 0 0x90490000
program_gamma all 0 1.0 0.00
membridge_start
mem_dump 0x2ba00000 0x100
mem_save "/usr/local/verilog/sensor_dump_01" 0x2ba00000 0x2300000
#scp -p root@192.168.0.8:/mnt/mmc/local/verilog/sensor_dump_01 /home/andrey/git/x393/py393/dbg1
setup_membridge_sensor <write_mem=False> <cache_mode=3> <window_width=2592> <window_height=1944> <window_left=0> <window_top=0> <membridge_start=731906048> <membridge_end=768606208> <verbose=1>
setup_membridge_sensor 0 3 2608 1936
......@@ -905,7 +932,6 @@ setup_membridge_sensor <num_sensor=0> <write_mem=False> <cache_mode=3> <wind
setup_membridge_sensor 0 0 3 2608 1936
setup_membridge_sensor 1 0 3 2608 1936
# Trying quadrants @param quadrants - 90-degree shifts for data [1:0], hact [3:2] and vact [5:4] (6'h01), None - no change
# set_sensor_io_ctl <num_sensor> <mrst=None> <arst=None> <aro=None> <mmcm_rst=None> <clk_sel=None> <set_delays=False> <quadrants=None>
......
py393/x393_mcntrl_adjust.py
View file @ 69b1d30b
......@@ -1361,6 +1361,8 @@ class X393McntrlAdjust(object):
y=a*phase+b
y0=y
#find the lowest approximate solution to consider
if (quiet <2):
print("phase= %d, y=%f, variantStep=%f"%(phase,y,variantStep))
if y0 > (-max_dly_err):
while (y0 >= (variantStep-max_dly_err)):
y0 -= variantStep
......@@ -1369,6 +1371,8 @@ class X393McntrlAdjust(object):
while (y0<(-max_dly_err)):
y0 += variantStep
periods += 1
if (quiet <2):
print("y0=%f"%(y0))
dly_min= max(0,int(y0-4.5))
dly_max= min(max_lin_dly,int(y0+5.5))
dly_to_try=[]
......
py393/x393_mcntrl_timing.py
View file @ 69b1d30b
......@@ -88,9 +88,15 @@ class X393McntrlTiming(object):
if phase is None:
phase= vrlg.get_default("DLY_PHASE")
vrlg.DLY_PHASE=phase & ((1<<vrlg.PHASE_WIDTH)-1)
if quiet<2:
print("SET CLOCK PHASE=0x%x"%(vrlg.DLY_PHASE))
self.x393_axi_tasks.write_control_register(vrlg.LD_DLY_PHASE,vrlg.DLY_PHASE) # {{(32-PHASE_WIDTH){1'b0}},phase}); // control register address
if vrlg.CLKFBOUT_USE_FINE_PS:
phase_value = (-vrlg.DLY_PHASE) & ((1<<vrlg.PHASE_WIDTH)-1)
if quiet<2:
print("SET INVERTED CLOCK PHASE=0x%x (actual value is 0x%x)"%(vrlg.DLY_PHASE, phase_value))
self.x393_axi_tasks.write_control_register(vrlg.LD_DLY_PHASE, phase_value) # {{(32-PHASE_WIDTH){1'b0}},phase}); // control register address
else:
if quiet<2:
print("SET CLOCK PHASE=0x%x"%(vrlg.DLY_PHASE))
self.x393_axi_tasks.write_control_register(vrlg.LD_DLY_PHASE,vrlg.DLY_PHASE) # {{(32-PHASE_WIDTH){1'b0}},phase}); // control register address
self.x393_axi_tasks.write_control_register(vrlg.DLY_SET,0)
# self.target_phase = phase
if wait_phase_en:
......@@ -106,7 +112,10 @@ class X393McntrlTiming(object):
<wait_seq> read and re-send status request to make sure status reflects new data (just for testing, too fast for Python)
Returns 1 if success, 0 if timeout
"""
patt = 0x3000000 | vrlg.DLY_PHASE
if vrlg.CLKFBOUT_USE_FINE_PS:
patt = 0x3000000 | ((-vrlg.DLY_PHASE) & 0xff)
else:
patt = 0x3000000 | vrlg.DLY_PHASE
mask = 0x3000100
if check_phase_value:
mask |= 0xff
......@@ -452,6 +461,9 @@ class X393McntrlTiming(object):
Wait until clock phase shifter is ready
"""
data=self.x393_axi_tasks.read_status(vrlg.MCONTR_PHY_STATUS_REG_ADDR)
expected_phase = vrlg.DLY_PHASE
if (vrlg.CLKFBOUT_USE_FINE_PS):
expected_phase = (-expected_phase) & 0xff;
while (((data & vrlg.STATUS_PSHIFTER_RDY_MASK) == 0) or (((data ^ vrlg.DLY_PHASE) & 0xff) != 0)):
data=self.x393_axi_tasks.read_status(vrlg.MCONTR_PHY_STATUS_REG_ADDR)
if self.DRY_MODE: break
......
py393/x393_sens_cmprs.py
View file @ 69b1d30b
......@@ -470,7 +470,7 @@ class X393SensCmprs(object):
if verbose >0 :
print ("===================== GAMMA_CTL =========================")
self.x393Sensor.set_sensor_gamma_ctl (# doing last to enable sesnor data when everything else is set up
self.x393Sensor.set_sensor_gamma_ctl (# doing last to enable sensor data when everything else is set up
num_sensor = num_sensor, # input [1:0] num_sensor; # sensor channel number (0..3)
bayer = 0,
table_page = 0,
......
py393/x393_sensor.py
View file @ 69b1d30b
......@@ -892,20 +892,25 @@ class X393Sensor(object):
):
"""
@brief Calculate gamma table (as array of 257 unsigned short values)
@param gamma - gamma value (1.0 - linear)
@param gamma - gamma value (1.0 - linear), 0 - linear as a special case
@param black - black level, 1.0 corresponds to 256 for 8bit values
@return array of 257 int elements (for a single color), right-shifted to match original 0..0x3ff range
"""
black256 = max(0.0, min(255, black * 256.0))
k= 1.0 / (256.0 - black256)
gamma =max(0.13, min(gamma, 10.0))
gtable = []
for i in range (257):
x=k * (i - black256)
x = max(x, 0.0)
ig = int (0.5 + 65535.0 * pow(x, gamma))
ig = min(ig, 0xffff)
gtable.append(ig >> rshift)
if gamma <= 0: # special case
for i in range (257):
ig = min(i*256, 0xffff)
gtable.append(ig >> rshift)
else:
black256 = max(0.0, min(255, black * 256.0))
k= 1.0 / (256.0 - black256)
gamma =max(0.13, min(gamma, 10.0))
for i in range (257):
x=k * (i - black256)
x = max(x, 0.0)
ig = int (0.5 + 65535.0 * pow(x, gamma))
ig = min(ig, 0xffff)
gtable.append(ig >> rshift)
return gtable
......
sensor/pxd_single.v
View file @ 69b1d30b
......@@ -38,8 +38,8 @@ module pxd_single#(
output pxd_in, // data output (@posedge ipclk?)
input ipclk, // restored clock from the sensor, phase-shifted
input ipclk2x, // restored clock from the sensor, phase-shifted, twice frequency
input mrst, // reset @ posxedge mclk
input irst, // reset @ posxedge iclk
input mrst, // reset @ posedge mclk
input irst, // reset @ posedge iclk
input mclk, // clock for setting delay values
input [7:0] dly_data, // delay value (3 LSB - fine delay) - @posedge mclk
input set_idelay, // mclk synchronous load idelay value
......
sensor/sens_10398.v 0 → 100644
View file @ 69b1d30b
This diff is collapsed.
sensor/sens_hispi12l4.v 0 → 100644
View file @ 69b1d30b
This diff is collapsed.
sensor/sens_hispi_clock.v 0 → 100644
View file @ 69b1d30b
This diff is collapsed.
sensor/sens_hispi_din.v 0 → 100644
View file @ 69b1d30b
This diff is collapsed.
sensor/sens_hispi_fifo.v 0 → 100644
View file @ 69b1d30b
This diff is collapsed.
sensor/sens_hispi_lane.v 0 → 100644
View file @ 69b1d30b
This diff is collapsed.
sensor/sens_histogram.v
View file @ 69b1d30b
This diff is collapsed.
sensor/sens_histogram_snglclk.v 0 → 100644
View file @ 69b1d30b
This diff is collapsed.
sensor/sens_parallel12.v
View file @ 69b1d30b
This diff is collapsed.
sensor/sensor_channel.v
View file @ 69b1d30b
This diff is collapsed.
sensor/sensor_fifo.v
View file @ 69b1d30b
......@@ -23,7 +23,7 @@
module sensor_fifo #(
parameter SENSOR_DATA_WIDTH = 12,
parameter SENSOR_FIFO_2DEPTH = 4, // 4-bit address
parameter SENSOR_FIFO_DELAY = 5 // 7 // approxiametly half (1 << SENSOR_FIFO_2DEPTH) - how long to wait after getting HACT on FIFO before stering it on output
parameter [3:0] SENSOR_FIFO_DELAY = 5 // 7 // approxiametly half (1 << SENSOR_FIFO_2DEPTH) - how long to wait after getting HACT on FIFO before stering it on output
)(
// input rst,
input iclk, // input -synchronous clock
......
sensor/sensors393.v
View file @ 69b1d30b
This diff is collapsed.
simulation_modules/par12_hispi_psp4l.v 0 → 100644
View file @ 69b1d30b
This diff is collapsed.
simulation_modules/sim_clk_div.v 0 → 100644
View file @ 69b1d30b
This diff is collapsed.
simulation_modules/sim_frac_clk_delay.v 0 → 100644
View file @ 69b1d30b
This diff is collapsed.
simulation_modules/simul_clk_div_mult.v 0 → 100644
View file @ 69b1d30b
This diff is collapsed.
simulation_modules/simul_clk_mult.v 0 → 100644
View file @ 69b1d30b
This diff is collapsed.
simulation_modules/simul_clk_mult_div.v 0 → 100644
View file @ 69b1d30b
This diff is collapsed.
simulation_modules/simul_sensor12bits.v
View file @ 69b1d30b
......@@ -20,6 +20,7 @@
*******************************************************************************/
module simul_sensor12bits # (
parameter SENSOR_IMAGE_TYPE = "NORM", // "RUN1",
parameter lline = 192, // 1664;// line duration in clocks
parameter ncols = 66, //58; //56; // 129; //128; //1288;
parameter nrows = 18, // 16; // 1032;
......@@ -134,6 +135,7 @@ initial begin
//parameter nrows = 16; // 1032;
$display ("sensor parameters");
$display (" -- image type = %s",SENSOR_IMAGE_TYPE);
$display (" -- ramp = %d (0 - random, 1 - ramp)",ramp);
$display (" -- lline = %d (line duration in clocks)",lline);
$display (" -- ncols = %d (numer of clocks in HACT)",ncols);
......@@ -143,7 +145,12 @@ initial begin
$display (" -- new_bayer = %d ",new_bayer);
// reg [15:0] sensor_data[0:4095]; // up to 64 x 64 pixels
$readmemh("input_data/sensor.dat",sensor_data);
if (SENSOR_IMAGE_TYPE == "NORM") $readmemh("input_data/sensor.dat",sensor_data);
else if (SENSOR_IMAGE_TYPE == "RUN1") $readmemh("input_data/sensor_run1.dat",sensor_data);
else begin
$display ("WARNING: Unrecognized sensor image :'%s', using default 'NORM': input_data/sensor.dat",SENSOR_IMAGE_TYPE);
$readmemh("input_data/sensor.dat",sensor_data);
end
c=0;
// {ibpf,ihact,ivact}=0;
stopped=1;
......
system_defines.vh
View file @ 69b1d30b
This diff is collapsed.
timing/camsync393.v
View file @ 69b1d30b
......@@ -570,7 +570,7 @@ module camsync393 #(
end
// Why was it local_got_pclk? Also, it is a multi-bit vector
// rcv_done_rq <= start_en && ((ts_external_pclk && local_got_pclk) || (rcv_done_rq && rcv_run));
// TODO: think of disabling receiving sync if sesnor is not ready yet (not done with a previous frame)
// TODO: think of disabling receiving sync if sensor is not ready yet (not done with a previous frame)
rcv_done_rq <= start_en && ((ts_external_pclk && (rcv_run && !rcv_run_d)) || (rcv_done_rq && rcv_run));
//
rcv_done_rq_d <= rcv_done_rq;
......
util_modules/clocks393.v
View file @ 69b1d30b
This diff is collapsed.
util_modules/fifo_1cycle.v
View file @ 69b1d30b
This diff is collapsed.
util_modules/fifo_cross_clocks.v
View file @ 69b1d30b
This diff is collapsed.
util_modules/fifo_same_clock.v
View file @ 69b1d30b
This diff is collapsed.
util_modules/status_router16.v
View file @ 69b1d30b
This diff is collapsed.
util_modules/status_router2.v
View file @ 69b1d30b
This diff is collapsed.
util_modules/status_router4.v
View file @ 69b1d30b
This diff is collapsed.
util_modules/status_router8.v
View file @ 69b1d30b
This diff is collapsed.
util_modules/sync_resets.v
View file @ 69b1d30b
This diff is collapsed.
wrap/ddr3_wrap.v
View file @ 69b1d30b
This diff is collapsed.
wrap/iserdes_mem.v
View file @ 69b1d30b
This diff is collapsed.
wrap/mmcm_adv.v
View file @ 69b1d30b
This diff is collapsed.
wrap/mmcm_phase_cntr.v
View file @ 69b1d30b
This diff is collapsed.
wrap/obufds.v 0 → 100644
View file @ 69b1d30b
This diff is collapsed.
wrap/ram18t_var_w_var_r.v 0 → 100644
View file @ 69b1d30b
This diff is collapsed.
wrap/ram18tp_var_w_var_r.v 0 → 100644
View file @ 69b1d30b
This diff is collapsed.
x393.v
View file @ 69b1d30b
This diff is collapsed.
x393_no_pclk2x_timing.xdc 0 → 100644
View file @ 69b1d30b
This diff is collapsed.
x393_nox2_timing.xdc 0 → 100644
View file @ 69b1d30b
This diff is collapsed.
x393_testbench02.sav
View file @ 69b1d30b
This diff is collapsed.
x393_testbench02.tf
View file @ 69b1d30b
This diff is collapsed.
x393_testbench03.sav 0 → 100644
View file @ 69b1d30b
This diff is collapsed.
x393_testbench03.tf 0 → 100644
View file @ 69b1d30b
This diff is collapsed.
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment