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Elphel
x393
Commits
691ae8a4
Commit
691ae8a4
authored
Nov 08, 2015
by
Andrey Filippov
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223 changed files
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423 additions
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227 deletions
+423
-227
axibram_read.v
axi/axibram_read.v
+1
-1
axibram_write.v
axi/axibram_write.v
+1
-1
cmprs_afi_mux.v
axi/cmprs_afi_mux.v
+1
-1
cmprs_afi_mux_ptr.v
axi/cmprs_afi_mux_ptr.v
+1
-1
cmprs_afi_mux_ptr_wresp.v
axi/cmprs_afi_mux_ptr_wresp.v
+1
-1
cmprs_afi_mux_status.v
axi/cmprs_afi_mux_status.v
+1
-1
histogram_saxi.v
axi/histogram_saxi.v
+1
-1
membridge.v
axi/membridge.v
+1
-1
mul_saxi_wr_chn.v
axi/mul_saxi_wr_chn.v
+1
-1
mult_saxi_wr.v
axi/mult_saxi_wr.v
+1
-1
mult_saxi_wr_inbuf.v
axi/mult_saxi_wr_inbuf.v
+1
-1
mult_saxi_wr_pointers.v
axi/mult_saxi_wr_pointers.v
+1
-1
cmd_mux.v
cmd_mux.v
+1
-1
cmd_readback.v
cmd_readback.v
+1
-1
bit_stuffer_27_32.v
compressor_jp/bit_stuffer_27_32.v
+1
-1
bit_stuffer_escape.v
compressor_jp/bit_stuffer_escape.v
+1
-1
bit_stuffer_metadata.v
compressor_jp/bit_stuffer_metadata.v
+1
-1
cmprs_buf_average.v
compressor_jp/cmprs_buf_average.v
+1
-1
cmprs_cmd_decode.v
compressor_jp/cmprs_cmd_decode.v
+1
-1
cmprs_frame_sync.v
compressor_jp/cmprs_frame_sync.v
+1
-1
cmprs_macroblock_buf_iface.v
compressor_jp/cmprs_macroblock_buf_iface.v
+1
-1
cmprs_out_fifo.v
compressor_jp/cmprs_out_fifo.v
+1
-1
cmprs_out_fifo32.v
compressor_jp/cmprs_out_fifo32.v
+1
-1
cmprs_pixel_buf_iface.v
compressor_jp/cmprs_pixel_buf_iface.v
+1
-1
cmprs_status.v
compressor_jp/cmprs_status.v
+1
-1
cmprs_tile_mode2_decode.v
compressor_jp/cmprs_tile_mode2_decode.v
+1
-1
cmprs_tile_mode_decode.v
compressor_jp/cmprs_tile_mode_decode.v
+1
-1
compressor393.v
compressor_jp/compressor393.v
+1
-1
csconvert.v
compressor_jp/csconvert.v
+1
-1
csconvert_jp4.v
compressor_jp/csconvert_jp4.v
+1
-1
csconvert_jp4diff.v
compressor_jp/csconvert_jp4diff.v
+1
-1
csconvert_mono.v
compressor_jp/csconvert_mono.v
+1
-1
dcc_sync393.v
compressor_jp/dcc_sync393.v
+1
-1
huffman_merge_code_literal.v
compressor_jp/huffman_merge_code_literal.v
+1
-1
huffman_stuffer_meta.v
compressor_jp/huffman_stuffer_meta.v
+1
-1
jp_channel.v
compressor_jp/jp_channel.v
+1
-1
ddrc_test01.xcf
ddrc_test01.xcf
+13
-0
ddrc_test01.xdc
ddrc_test01.xdc
+13
-0
ddrc_test01_timing.xdc
ddrc_test01_timing.xdc
+13
-0
fpga_version.vh
fpga_version.vh
+49
-16
tasks_tests_memory.vh
includes/tasks_tests_memory.vh
+1
-1
x393_cur_params_target.vh
includes/x393_cur_params_target.vh
+1
-1
x393_localparams.vh
includes/x393_localparams.vh
+1
-1
x393_mcontr_encode_cmd.vh
includes/x393_mcontr_encode_cmd.vh
+1
-1
x393_parameters.vh
includes/x393_parameters.vh
+1
-1
x393_simulation_parameters.vh
includes/x393_simulation_parameters.vh
+1
-1
x393_tasks01.vh
includes/x393_tasks01.vh
+1
-1
x393_tasks_afi.vh
includes/x393_tasks_afi.vh
+1
-1
x393_tasks_mcntrl_buffers.vh
includes/x393_tasks_mcntrl_buffers.vh
+1
-1
x393_tasks_mcntrl_en_dis_priority.vh
includes/x393_tasks_mcntrl_en_dis_priority.vh
+1
-1
x393_tasks_mcntrl_timing.vh
includes/x393_tasks_mcntrl_timing.vh
+1
-1
x393_tasks_pio_sequences.vh
includes/x393_tasks_pio_sequences.vh
+1
-1
x393_tasks_ps_pio.vh
includes/x393_tasks_ps_pio.vh
+1
-1
x393_tasks_status.vh
includes/x393_tasks_status.vh
+1
-1
buf_xclk_mclk16_393.v
logger/buf_xclk_mclk16_393.v
+1
-1
event_logger.v
logger/event_logger.v
+1
-1
imu_exttime393.v
logger/imu_exttime393.v
+1
-1
imu_message393.v
logger/imu_message393.v
+1
-1
imu_spi393.v
logger/imu_spi393.v
+1
-1
imu_timestamps393.v
logger/imu_timestamps393.v
+1
-1
logger_arbiter393.v
logger/logger_arbiter393.v
+1
-1
nmea_decoder393.v
logger/nmea_decoder393.v
+1
-1
rs232_rcv393.v
logger/rs232_rcv393.v
+1
-1
cmd_encod_4mux.v
memctrl/cmd_encod_4mux.v
+1
-1
cmd_encod_linear_mux.v
memctrl/cmd_encod_linear_mux.v
+1
-1
cmd_encod_linear_rd.v
memctrl/cmd_encod_linear_rd.v
+1
-1
cmd_encod_linear_rw.v
memctrl/cmd_encod_linear_rw.v
+1
-1
cmd_encod_linear_wr.v
memctrl/cmd_encod_linear_wr.v
+1
-1
cmd_encod_tiled_32_rd.v
memctrl/cmd_encod_tiled_32_rd.v
+1
-1
cmd_encod_tiled_32_rw.v
memctrl/cmd_encod_tiled_32_rw.v
+1
-1
cmd_encod_tiled_32_wr.v
memctrl/cmd_encod_tiled_32_wr.v
+1
-1
cmd_encod_tiled_mux.v
memctrl/cmd_encod_tiled_mux.v
+1
-1
cmd_encod_tiled_rd.v
memctrl/cmd_encod_tiled_rd.v
+1
-1
cmd_encod_tiled_rw.v
memctrl/cmd_encod_tiled_rw.v
+1
-1
cmd_encod_tiled_wr.v
memctrl/cmd_encod_tiled_wr.v
+1
-1
ddr_refresh.v
memctrl/ddr_refresh.v
+1
-1
mcntrl393.v
memctrl/mcntrl393.v
+1
-1
mcntrl393_test01.v
memctrl/mcntrl393_test01.v
+1
-1
mcntrl_1kx32r.v
memctrl/mcntrl_1kx32r.v
+1
-1
mcntrl_1kx32w.v
memctrl/mcntrl_1kx32w.v
+1
-1
mcntrl_buf_rd.v
memctrl/mcntrl_buf_rd.v
+1
-1
mcntrl_buf_wr.v
memctrl/mcntrl_buf_wr.v
+1
-1
mcntrl_linear_rw.v
memctrl/mcntrl_linear_rw.v
+1
-1
mcntrl_ps_pio.v
memctrl/mcntrl_ps_pio.v
+1
-1
mcntrl_tiled_rw.v
memctrl/mcntrl_tiled_rw.v
+1
-1
memctrl16.v
memctrl/memctrl16.v
+1
-1
byte_lane.v
memctrl/phy/byte_lane.v
+1
-1
cmd_addr.v
memctrl/phy/cmd_addr.v
+1
-1
cmda_single.v
memctrl/phy/cmda_single.v
+1
-1
dm_single.v
memctrl/phy/dm_single.v
+1
-1
dq_single.v
memctrl/phy/dq_single.v
+1
-1
dqs_single.v
memctrl/phy/dqs_single.v
+1
-1
dqs_single_nofine.v
memctrl/phy/dqs_single_nofine.v
+1
-1
mcontr_sequencer.v
memctrl/phy/mcontr_sequencer.v
+1
-1
phy_cmd.v
memctrl/phy/phy_cmd.v
+1
-1
phy_top.v
memctrl/phy/phy_top.v
+1
-1
scheduler16.v
memctrl/scheduler16.v
+1
-1
lens_flat393.v
sensor/lens_flat393.v
+1
-1
pxd_clock.v
sensor/pxd_clock.v
+1
-1
pxd_single.v
sensor/pxd_single.v
+1
-1
sens_10398.v
sensor/sens_10398.v
+1
-1
sens_gamma.v
sensor/sens_gamma.v
+1
-1
sens_hispi12l4.v
sensor/sens_hispi12l4.v
+1
-1
sens_hispi_clock.v
sensor/sens_hispi_clock.v
+1
-1
sens_hispi_din.v
sensor/sens_hispi_din.v
+1
-1
sens_hispi_fifo.v
sensor/sens_hispi_fifo.v
+1
-1
sens_hispi_lane.v
sensor/sens_hispi_lane.v
+1
-1
sens_histogram.v
sensor/sens_histogram.v
+1
-1
sens_histogram_mux.v
sensor/sens_histogram_mux.v
+1
-1
sens_histogram_snglclk.v
sensor/sens_histogram_snglclk.v
+1
-1
sens_parallel12.v
sensor/sens_parallel12.v
+1
-1
sens_sync.v
sensor/sens_sync.v
+1
-1
sensor_channel.v
sensor/sensor_channel.v
+1
-1
sensor_fifo.v
sensor/sensor_fifo.v
+1
-1
sensor_i2c.v
sensor/sensor_i2c.v
+1
-1
sensor_i2c_io.v
sensor/sensor_i2c_io.v
+1
-1
sensor_i2c_prot.v
sensor/sensor_i2c_prot.v
+1
-1
sensor_i2c_scl_sda.v
sensor/sensor_i2c_scl_sda.v
+1
-1
sensor_membuf.v
sensor/sensor_membuf.v
+1
-1
sensors393.v
sensor/sensors393.v
+1
-1
par12_hispi_psp4l.v
simulation_modules/par12_hispi_psp4l.v
+1
-1
sim_clk_div.v
simulation_modules/sim_clk_div.v
+1
-1
sim_frac_clk_delay.v
simulation_modules/sim_frac_clk_delay.v
+1
-1
simul_axi_hp_rd.v
simulation_modules/simul_axi_hp_rd.v
+1
-1
simul_axi_hp_wr.v
simulation_modules/simul_axi_hp_wr.v
+1
-1
simul_axi_master_rdaddr.v
simulation_modules/simul_axi_master_rdaddr.v
+1
-1
simul_axi_master_wdata.v
simulation_modules/simul_axi_master_wdata.v
+1
-1
simul_axi_master_wraddr.v
simulation_modules/simul_axi_master_wraddr.v
+1
-1
simul_axi_read.v
simulation_modules/simul_axi_read.v
+1
-1
simul_axi_slow_ready.v
simulation_modules/simul_axi_slow_ready.v
+1
-1
simul_clk.v
simulation_modules/simul_clk.v
+1
-1
simul_clk_div_mult.v
simulation_modules/simul_clk_div_mult.v
+1
-1
simul_clk_mult.v
simulation_modules/simul_clk_mult.v
+1
-1
simul_clk_mult_div.v
simulation_modules/simul_clk_mult_div.v
+1
-1
simul_fifo.v
simulation_modules/simul_fifo.v
+1
-1
simul_saxi_gp_wr.v
simulation_modules/simul_saxi_gp_wr.v
+1
-1
simul_sensor12bits.v
simulation_modules/simul_sensor12bits.v
+1
-1
status_read.v
status_read.v
+1
-1
system_defines.vh
system_defines.vh
+33
-0
camsync393.v
timing/camsync393.v
+1
-1
rtc393.v
timing/rtc393.v
+1
-1
timestamp_fifo.v
timing/timestamp_fifo.v
+1
-1
timestamp_snapshot.v
timing/timestamp_snapshot.v
+1
-1
timestamp_to_parallel.v
timing/timestamp_to_parallel.v
+1
-1
timestamp_to_serial.v
timing/timestamp_to_serial.v
+1
-1
timing393.v
timing/timing393.v
+1
-1
IBUFG.v
unisims_extra/IBUFG.v
+1
-1
IBUFGDS.v
unisims_extra/IBUFGDS.v
+1
-1
axi_hp_clk.v
util_modules/axi_hp_clk.v
+1
-1
clk_to_clk2x.v
util_modules/clk_to_clk2x.v
+1
-1
clocks393.v
util_modules/clocks393.v
+1
-1
clocks393m.v
util_modules/clocks393m.v
+1
-1
cmd_deser.v
util_modules/cmd_deser.v
+1
-1
cmd_frame_sequencer.v
util_modules/cmd_frame_sequencer.v
+1
-1
cmd_seq_mux.v
util_modules/cmd_seq_mux.v
+1
-1
debug_master.v
util_modules/debug_master.v
+1
-1
debug_slave.v
util_modules/debug_slave.v
+1
-1
dly01_16.v
util_modules/dly01_16.v
+1
-1
dly_16.v
util_modules/dly_16.v
+1
-1
dual_clock_source.v
util_modules/dual_clock_source.v
+1
-1
elastic_cross_clock.v
util_modules/elastic_cross_clock.v
+1
-1
fifo_1cycle.v
util_modules/fifo_1cycle.v
+1
-1
fifo_2regs.v
util_modules/fifo_2regs.v
+1
-1
fifo_cross_clocks.v
util_modules/fifo_cross_clocks.v
+1
-1
fifo_same_clock.v
util_modules/fifo_same_clock.v
+1
-1
fifo_same_clock_fill.v
util_modules/fifo_same_clock_fill.v
+1
-1
gpio393.v
util_modules/gpio393.v
+1
-1
index_max_16.v
util_modules/index_max_16.v
+1
-1
level_cross_clocks.v
util_modules/level_cross_clocks.v
+1
-1
masked_max_reg.v
util_modules/masked_max_reg.v
+1
-1
mcont_common_chnbuf_reg.v
util_modules/mcont_common_chnbuf_reg.v
+1
-1
mcont_from_chnbuf_reg.v
util_modules/mcont_from_chnbuf_reg.v
+1
-1
mcont_to_chnbuf_reg.v
util_modules/mcont_to_chnbuf_reg.v
+1
-1
multipulse_cross_clock.v
util_modules/multipulse_cross_clock.v
+1
-1
pri1hot16.v
util_modules/pri1hot16.v
+1
-1
pulse_cross_clock.v
util_modules/pulse_cross_clock.v
+1
-1
round_robin.v
util_modules/round_robin.v
+1
-1
status_generate.v
util_modules/status_generate.v
+1
-1
status_router16.v
util_modules/status_router16.v
+1
-1
status_router2.v
util_modules/status_router2.v
+1
-1
status_router4.v
util_modules/status_router4.v
+1
-1
status_router8.v
util_modules/status_router8.v
+1
-1
sync_resets.v
util_modules/sync_resets.v
+1
-1
table_ad_receive.v
util_modules/table_ad_receive.v
+1
-1
table_ad_transmit.v
util_modules/table_ad_transmit.v
+1
-1
dci_reset.v
wrap/dci_reset.v
+1
-1
ddr3_wrap.v
wrap/ddr3_wrap.v
+1
-1
ibuf_ibufg.v
wrap/ibuf_ibufg.v
+1
-1
ibufds_ibufgds.v
wrap/ibufds_ibufgds.v
+1
-1
ibufg.v
wrap/ibufg.v
+1
-1
ibufgds.v
wrap/ibufgds.v
+1
-1
idelay_ctrl.v
wrap/idelay_ctrl.v
+1
-1
idelay_fine_pipe.v
wrap/idelay_fine_pipe.v
+1
-1
idelay_nofine.v
wrap/idelay_nofine.v
+1
-1
iobuf.v
wrap/iobuf.v
+1
-1
iserdes_mem.v
wrap/iserdes_mem.v
+1
-1
latch_g_ce.v
wrap/latch_g_ce.v
+1
-1
mmcm_adv.v
wrap/mmcm_adv.v
+1
-1
mmcm_phase_cntr.v
wrap/mmcm_phase_cntr.v
+1
-1
mpullup.v
wrap/mpullup.v
+1
-1
obuf.v
wrap/obuf.v
+1
-1
obufds.v
wrap/obufds.v
+1
-1
oddr.v
wrap/oddr.v
+1
-1
oddr_ds.v
wrap/oddr_ds.v
+1
-1
oddr_ss.v
wrap/oddr_ss.v
+1
-1
odelay_fine_pipe.v
wrap/odelay_fine_pipe.v
+1
-1
odelay_pipe.v
wrap/odelay_pipe.v
+1
-1
oserdes_mem.v
wrap/oserdes_mem.v
+1
-1
pll_base.v
wrap/pll_base.v
+1
-1
ram18_var_w_var_r.v
wrap/ram18_var_w_var_r.v
+1
-1
ram18t_var_w_var_r.v
wrap/ram18t_var_w_var_r.v
+1
-1
ram18tp_var_w_var_r.v
wrap/ram18tp_var_w_var_r.v
+1
-1
ramt_var_w_var_r.v
wrap/ramt_var_w_var_r.v
+1
-1
ramtp_var_w_var_r.v
wrap/ramtp_var_w_var_r.v
+1
-1
select_clk_buf.v
wrap/select_clk_buf.v
+1
-1
x393.v
x393.v
+1
-1
x393.xcf
x393.xcf
+13
-0
x393.xdc
x393.xdc
+13
-0
x393_hispi.xdc
x393_hispi.xdc
+13
-0
x393_hispi_timing.xdc
x393_hispi_timing.xdc
+13
-0
x393_no_pclk2x_timing.xdc
x393_no_pclk2x_timing.xdc
+13
-0
x393_nox2_timing.xdc
x393_nox2_timing.xdc
+13
-0
x393_timing.xdc
x393_timing.xdc
+13
-0
No files found.
axi/axibram_read.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
axi/axibram_write.v
View file @
691ae8a4
...
...
@@ -24,7 +24,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
axi/cmprs_afi_mux.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
axi/cmprs_afi_mux_ptr.v
View file @
691ae8a4
...
...
@@ -24,7 +24,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
axi/cmprs_afi_mux_ptr_wresp.v
View file @
691ae8a4
...
...
@@ -24,7 +24,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
axi/cmprs_afi_mux_status.v
View file @
691ae8a4
...
...
@@ -27,7 +27,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
axi/histogram_saxi.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
axi/membridge.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
axi/mul_saxi_wr_chn.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
axi/mult_saxi_wr.v
View file @
691ae8a4
...
...
@@ -26,7 +26,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
axi/mult_saxi_wr_inbuf.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
axi/mult_saxi_wr_pointers.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
cmd_mux.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
cmd_readback.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
compressor_jp/bit_stuffer_27_32.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
compressor_jp/bit_stuffer_escape.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
compressor_jp/bit_stuffer_metadata.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
compressor_jp/cmprs_buf_average.v
View file @
691ae8a4
...
...
@@ -25,7 +25,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
compressor_jp/cmprs_cmd_decode.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
compressor_jp/cmprs_frame_sync.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
compressor_jp/cmprs_macroblock_buf_iface.v
View file @
691ae8a4
...
...
@@ -25,7 +25,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
compressor_jp/cmprs_out_fifo.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
compressor_jp/cmprs_out_fifo32.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
compressor_jp/cmprs_pixel_buf_iface.v
View file @
691ae8a4
...
...
@@ -25,7 +25,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
compressor_jp/cmprs_status.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
compressor_jp/cmprs_tile_mode2_decode.v
View file @
691ae8a4
...
...
@@ -24,7 +24,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
compressor_jp/cmprs_tile_mode_decode.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
compressor_jp/compressor393.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
compressor_jp/csconvert.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
compressor_jp/csconvert_jp4.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
compressor_jp/csconvert_jp4diff.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
compressor_jp/csconvert_mono.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
compressor_jp/dcc_sync393.v
View file @
691ae8a4
...
...
@@ -25,7 +25,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
compressor_jp/huffman_merge_code_literal.v
View file @
691ae8a4
...
...
@@ -24,7 +24,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
compressor_jp/huffman_stuffer_meta.v
View file @
691ae8a4
...
...
@@ -24,7 +24,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
compressor_jp/jp_channel.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
ddrc_test01.xcf
View file @
691ae8a4
...
...
@@ -17,6 +17,19 @@
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/> .
#
# Additional permission under GNU GPL version 3 section 7:
# If you modify this Program, or any covered work, by linking or combining it
# with independent modules provided by the FPGA vendor only (this permission
# does not extend to any 3-rd party modules, "soft cores" or macros) under
# different license terms solely for the purpose of generating binary "bitstream"
# files and/or simulating the code, the copyright holders of this Program give
# you the right to distribute the covered work without those independent modules
# as long as the source code for them is available from the FPGA vendor free of
# charge, and there is no dependence on any ecrypted modules for simulating of
# the combined code. This permission applies to you if the distributed code
# contains all the components and scripts required to completely simulate it
# with at least one of the Free Software programs.
#################################################################################
# output SDRST, // output SDRST, active low
...
...
ddrc_test01.xdc
View file @
691ae8a4
...
...
@@ -17,6 +17,19 @@
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/> .
#
# Additional permission under GNU GPL version 3 section 7:
# If you modify this Program, or any covered work, by linking or combining it
# with independent modules provided by the FPGA vendor only (this permission
# does not extend to any 3-rd party modules, "soft cores" or macros) under
# different license terms solely for the purpose of generating binary "bitstream"
# files and/or simulating the code, the copyright holders of this Program give
# you the right to distribute the covered work without those independent modules
# as long as the source code for them is available from the FPGA vendor free of
# charge, and there is no dependence on any ecrypted modules for simulating of
# the combined code. This permission applies to you if the distributed code
# contains all the components and scripts required to completely simulate it
# with at least one of the Free Software programs.
#################################################################################
# output SDRST, // output SDRST, active low
...
...
ddrc_test01_timing.xdc
View file @
691ae8a4
...
...
@@ -17,6 +17,19 @@
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/> .
#
# Additional permission under GNU GPL version 3 section 7:
# If you modify this Program, or any covered work, by linking or combining it
# with independent modules provided by the FPGA vendor only (this permission
# does not extend to any 3-rd party modules, "soft cores" or macros) under
# different license terms solely for the purpose of generating binary "bitstream"
# files and/or simulating the code, the copyright holders of this Program give
# you the right to distribute the covered work without those independent modules
# as long as the source code for them is available from the FPGA vendor free of
# charge, and there is no dependence on any ecrypted modules for simulating of
# the combined code. This permission applies to you if the distributed code
# contains all the components and scripts required to completely simulate it
# with at least one of the Free Software programs.
#################################################################################
create_clock -name axi_aclk -period 20 [get_nets -hierarchical *axi_aclk]
...
...
fpga_version.vh
View file @
691ae8a4
/*******************************************************************************
* File: fpga_version.vh
* Date:2015-08-26
* Author: Andrey Filippov
* Description: Defining run-time readable FPGA code version
*
* Copyright (c) 2015 Elphel, Inc.
* fpga_version.vh is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* fpga_version.vh is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
parameter FPGA_VERSION = 32'h0393006a; // modified clock generation, trying with HiSPi - 72.77% utilization
// parameter FPGA_VERSION = 32'h03930069; // modified clock generation, rebuilding for parallel sensors - all met, 71.8% utilization
// parameter FPGA_VERSION = 32'h03930068; // trying BUFR/FUFIO on all sensors ipclk/ipclk2x
...
...
includes/tasks_tests_memory.vh
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
includes/x393_cur_params_target.vh
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
includes/x393_localparams.vh
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
includes/x393_mcontr_encode_cmd.vh
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
includes/x393_parameters.vh
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
includes/x393_simulation_parameters.vh
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
includes/x393_tasks01.vh
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
includes/x393_tasks_afi.vh
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
includes/x393_tasks_mcntrl_buffers.vh
View file @
691ae8a4
...
...
@@ -24,7 +24,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
includes/x393_tasks_mcntrl_en_dis_priority.vh
View file @
691ae8a4
...
...
@@ -24,7 +24,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
includes/x393_tasks_mcntrl_timing.vh
View file @
691ae8a4
...
...
@@ -24,7 +24,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
includes/x393_tasks_pio_sequences.vh
View file @
691ae8a4
...
...
@@ -24,7 +24,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
includes/x393_tasks_ps_pio.vh
View file @
691ae8a4
...
...
@@ -24,7 +24,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
includes/x393_tasks_status.vh
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
logger/buf_xclk_mclk16_393.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
logger/event_logger.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
logger/imu_exttime393.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
logger/imu_message393.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
logger/imu_spi393.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
logger/imu_timestamps393.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
logger/logger_arbiter393.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
logger/nmea_decoder393.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
logger/rs232_rcv393.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
memctrl/cmd_encod_4mux.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
memctrl/cmd_encod_linear_mux.v
View file @
691ae8a4
...
...
@@ -25,7 +25,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
memctrl/cmd_encod_linear_rd.v
View file @
691ae8a4
...
...
@@ -24,7 +24,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
memctrl/cmd_encod_linear_rw.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
memctrl/cmd_encod_linear_wr.v
View file @
691ae8a4
...
...
@@ -24,7 +24,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
memctrl/cmd_encod_tiled_32_rd.v
View file @
691ae8a4
...
...
@@ -29,7 +29,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
memctrl/cmd_encod_tiled_32_rw.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
memctrl/cmd_encod_tiled_32_wr.v
View file @
691ae8a4
...
...
@@ -29,7 +29,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
memctrl/cmd_encod_tiled_mux.v
View file @
691ae8a4
...
...
@@ -25,7 +25,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
memctrl/cmd_encod_tiled_rd.v
View file @
691ae8a4
...
...
@@ -31,7 +31,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
memctrl/cmd_encod_tiled_rw.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
memctrl/cmd_encod_tiled_wr.v
View file @
691ae8a4
...
...
@@ -31,7 +31,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
memctrl/ddr_refresh.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
memctrl/mcntrl393.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
memctrl/mcntrl393_test01.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
memctrl/mcntrl_1kx32r.v
View file @
691ae8a4
...
...
@@ -24,7 +24,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
memctrl/mcntrl_1kx32w.v
View file @
691ae8a4
...
...
@@ -24,7 +24,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
memctrl/mcntrl_buf_rd.v
View file @
691ae8a4
...
...
@@ -24,7 +24,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
memctrl/mcntrl_buf_wr.v
View file @
691ae8a4
...
...
@@ -24,7 +24,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
memctrl/mcntrl_linear_rw.v
View file @
691ae8a4
...
...
@@ -24,7 +24,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
memctrl/mcntrl_ps_pio.v
View file @
691ae8a4
...
...
@@ -24,7 +24,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
memctrl/mcntrl_tiled_rw.v
View file @
691ae8a4
...
...
@@ -26,7 +26,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
memctrl/memctrl16.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
memctrl/phy/byte_lane.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
memctrl/phy/cmd_addr.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
memctrl/phy/cmda_single.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
memctrl/phy/dm_single.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
memctrl/phy/dq_single.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
memctrl/phy/dqs_single.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
memctrl/phy/dqs_single_nofine.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
memctrl/phy/mcontr_sequencer.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
memctrl/phy/phy_cmd.v
View file @
691ae8a4
...
...
@@ -24,7 +24,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
memctrl/phy/phy_top.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
memctrl/scheduler16.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
sensor/lens_flat393.v
View file @
691ae8a4
...
...
@@ -29,7 +29,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
sensor/pxd_clock.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
sensor/pxd_single.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
sensor/sens_10398.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
sensor/sens_gamma.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
sensor/sens_hispi12l4.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
sensor/sens_hispi_clock.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
sensor/sens_hispi_din.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
sensor/sens_hispi_fifo.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
sensor/sens_hispi_lane.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
sensor/sens_histogram.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
sensor/sens_histogram_mux.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
sensor/sens_histogram_snglclk.v
View file @
691ae8a4
...
...
@@ -25,7 +25,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
sensor/sens_parallel12.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
sensor/sens_sync.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
sensor/sensor_channel.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
sensor/sensor_fifo.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
sensor/sensor_i2c.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
sensor/sensor_i2c_io.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
sensor/sensor_i2c_prot.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
sensor/sensor_i2c_scl_sda.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
sensor/sensor_membuf.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
sensor/sensors393.v
View file @
691ae8a4
...
...
@@ -24,7 +24,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
simulation_modules/par12_hispi_psp4l.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
simulation_modules/sim_clk_div.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
simulation_modules/sim_frac_clk_delay.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
simulation_modules/simul_axi_hp_rd.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
simulation_modules/simul_axi_hp_wr.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
simulation_modules/simul_axi_master_rdaddr.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
simulation_modules/simul_axi_master_wdata.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
simulation_modules/simul_axi_master_wraddr.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
simulation_modules/simul_axi_read.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
simulation_modules/simul_axi_slow_ready.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
simulation_modules/simul_clk.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
simulation_modules/simul_clk_div_mult.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
simulation_modules/simul_clk_mult.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
simulation_modules/simul_clk_mult_div.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
simulation_modules/simul_fifo.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
simulation_modules/simul_saxi_gp_wr.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
simulation_modules/simul_sensor12bits.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
status_read.v
View file @
691ae8a4
...
...
@@ -31,7 +31,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
system_defines.vh
View file @
691ae8a4
/*******************************************************************************
* File: system_defines.vh
* Date:2015-02-28
* Author: Andrey Filippov
* Description: Preprocessor macros definitions to be included in the project
*
* Copyright (c) 2015 Elphel, Inc.
* system_defines.vh is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* system_defines.vh is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*******************************************************************************/
// This file may be used to define same pre-processor macros to be included into each parsed file
`ifndef SYSTEM_DEFINES
`define SYSTEM_DEFINES
...
...
timing/camsync393.v
View file @
691ae8a4
...
...
@@ -28,7 +28,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
timing/rtc393.v
View file @
691ae8a4
...
...
@@ -25,7 +25,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
timing/timestamp_fifo.v
View file @
691ae8a4
...
...
@@ -27,7 +27,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
timing/timestamp_snapshot.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
timing/timestamp_to_parallel.v
View file @
691ae8a4
...
...
@@ -24,7 +24,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
timing/timestamp_to_serial.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
timing/timing393.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
unisims_extra/IBUFG.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
unisims_extra/IBUFGDS.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
util_modules/axi_hp_clk.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
util_modules/clk_to_clk2x.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
util_modules/clocks393.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
util_modules/clocks393m.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
util_modules/cmd_deser.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
util_modules/cmd_frame_sequencer.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
util_modules/cmd_seq_mux.v
View file @
691ae8a4
...
...
@@ -24,7 +24,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
util_modules/debug_master.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
util_modules/debug_slave.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
util_modules/dly01_16.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
util_modules/dly_16.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
util_modules/dual_clock_source.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
util_modules/elastic_cross_clock.v
View file @
691ae8a4
...
...
@@ -28,7 +28,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
util_modules/fifo_1cycle.v
View file @
691ae8a4
...
...
@@ -24,7 +24,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
util_modules/fifo_2regs.v
View file @
691ae8a4
...
...
@@ -24,7 +24,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
util_modules/fifo_cross_clocks.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
util_modules/fifo_same_clock.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
util_modules/fifo_same_clock_fill.v
View file @
691ae8a4
...
...
@@ -24,7 +24,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
util_modules/gpio393.v
View file @
691ae8a4
...
...
@@ -24,7 +24,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
util_modules/index_max_16.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
util_modules/level_cross_clocks.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
util_modules/masked_max_reg.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
util_modules/mcont_common_chnbuf_reg.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
util_modules/mcont_from_chnbuf_reg.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
util_modules/mcont_to_chnbuf_reg.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
util_modules/multipulse_cross_clock.v
View file @
691ae8a4
...
...
@@ -27,7 +27,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
util_modules/pri1hot16.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
util_modules/pulse_cross_clock.v
View file @
691ae8a4
...
...
@@ -25,7 +25,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
util_modules/round_robin.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
util_modules/status_generate.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
util_modules/status_router16.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
util_modules/status_router2.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
util_modules/status_router4.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
util_modules/status_router8.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
util_modules/sync_resets.v
View file @
691ae8a4
...
...
@@ -24,7 +24,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
util_modules/table_ad_receive.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
util_modules/table_ad_transmit.v
View file @
691ae8a4
...
...
@@ -25,7 +25,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
wrap/dci_reset.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
wrap/ddr3_wrap.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
wrap/ibuf_ibufg.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
wrap/ibufds_ibufgds.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
wrap/ibufg.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
wrap/ibufgds.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
wrap/idelay_ctrl.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
wrap/idelay_fine_pipe.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
wrap/idelay_nofine.v
View file @
691ae8a4
...
...
@@ -22,7 +22,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
wrap/iobuf.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
wrap/iserdes_mem.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
wrap/latch_g_ce.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
wrap/mmcm_adv.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
wrap/mmcm_phase_cntr.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
wrap/mpullup.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
wrap/obuf.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
wrap/obufds.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
wrap/oddr.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
wrap/oddr_ds.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
wrap/oddr_ss.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
wrap/odelay_fine_pipe.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
wrap/odelay_pipe.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
wrap/oserdes_mem.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
wrap/pll_base.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
wrap/ram18_var_w_var_r.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
wrap/ram18t_var_w_var_r.v
View file @
691ae8a4
...
...
@@ -25,7 +25,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
wrap/ram18tp_var_w_var_r.v
View file @
691ae8a4
...
...
@@ -25,7 +25,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
wrap/ramt_var_w_var_r.v
View file @
691ae8a4
...
...
@@ -25,7 +25,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
wrap/ramtp_var_w_var_r.v
View file @
691ae8a4
...
...
@@ -25,7 +25,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
wrap/select_clk_buf.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
x393.v
View file @
691ae8a4
...
...
@@ -23,7 +23,7 @@
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files
*
and/or simulating the code, the copyright holders of this Program give
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any ecrypted modules for simulating of
...
...
x393.xcf
View file @
691ae8a4
...
...
@@ -17,6 +17,19 @@
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/> .
#
# Additional permission under GNU GPL version 3 section 7:
# If you modify this Program, or any covered work, by linking or combining it
# with independent modules provided by the FPGA vendor only (this permission
# does not extend to any 3-rd party modules, "soft cores" or macros) under
# different license terms solely for the purpose of generating binary "bitstream"
# files and/or simulating the code, the copyright holders of this Program give
# you the right to distribute the covered work without those independent modules
# as long as the source code for them is available from the FPGA vendor free of
# charge, and there is no dependence on any ecrypted modules for simulating of
# the combined code. This permission applies to you if the distributed code
# contains all the components and scripts required to completely simulate it
# with at least one of the Free Software programs.
#################################################################################
# output SDRST, // output SDRST, active low
...
...
x393.xdc
View file @
691ae8a4
...
...
@@ -17,6 +17,19 @@
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/> .
#
# Additional permission under GNU GPL version 3 section 7:
# If you modify this Program, or any covered work, by linking or combining it
# with independent modules provided by the FPGA vendor only (this permission
# does not extend to any 3-rd party modules, "soft cores" or macros) under
# different license terms solely for the purpose of generating binary "bitstream"
# files and/or simulating the code, the copyright holders of this Program give
# you the right to distribute the covered work without those independent modules
# as long as the source code for them is available from the FPGA vendor free of
# charge, and there is no dependence on any ecrypted modules for simulating of
# the combined code. This permission applies to you if the distributed code
# contains all the components and scripts required to completely simulate it
# with at least one of the Free Software programs.
#################################################################################
# Global constraints
...
...
x393_hispi.xdc
View file @
691ae8a4
...
...
@@ -17,6 +17,19 @@
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/> .
#
# Additional permission under GNU GPL version 3 section 7:
# If you modify this Program, or any covered work, by linking or combining it
# with independent modules provided by the FPGA vendor only (this permission
# does not extend to any 3-rd party modules, "soft cores" or macros) under
# different license terms solely for the purpose of generating binary "bitstream"
# files and/or simulating the code, the copyright holders of this Program give
# you the right to distribute the covered work without those independent modules
# as long as the source code for them is available from the FPGA vendor free of
# charge, and there is no dependence on any ecrypted modules for simulating of
# the combined code. This permission applies to you if the distributed code
# contains all the components and scripts required to completely simulate it
# with at least one of the Free Software programs.
#################################################################################
# Global constraints
...
...
x393_hispi_timing.xdc
View file @
691ae8a4
...
...
@@ -17,6 +17,19 @@
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/> .
#
# Additional permission under GNU GPL version 3 section 7:
# If you modify this Program, or any covered work, by linking or combining it
# with independent modules provided by the FPGA vendor only (this permission
# does not extend to any 3-rd party modules, "soft cores" or macros) under
# different license terms solely for the purpose of generating binary "bitstream"
# files and/or simulating the code, the copyright holders of this Program give
# you the right to distribute the covered work without those independent modules
# as long as the source code for them is available from the FPGA vendor free of
# charge, and there is no dependence on any ecrypted modules for simulating of
# the combined code. This permission applies to you if the distributed code
# contains all the components and scripts required to completely simulate it
# with at least one of the Free Software programs.
#################################################################################
create_clock -name axi_aclk -period 20 [get_nets -hierarchical *axi_aclk]
...
...
x393_no_pclk2x_timing.xdc
View file @
691ae8a4
...
...
@@ -17,6 +17,19 @@
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/> .
#
# Additional permission under GNU GPL version 3 section 7:
# If you modify this Program, or any covered work, by linking or combining it
# with independent modules provided by the FPGA vendor only (this permission
# does not extend to any 3-rd party modules, "soft cores" or macros) under
# different license terms solely for the purpose of generating binary "bitstream"
# files and/or simulating the code, the copyright holders of this Program give
# you the right to distribute the covered work without those independent modules
# as long as the source code for them is available from the FPGA vendor free of
# charge, and there is no dependence on any ecrypted modules for simulating of
# the combined code. This permission applies to you if the distributed code
# contains all the components and scripts required to completely simulate it
# with at least one of the Free Software programs.
#################################################################################
create_clock -name axi_aclk -period 20 [get_nets -hierarchical *axi_aclk]
...
...
x393_nox2_timing.xdc
View file @
691ae8a4
...
...
@@ -17,6 +17,19 @@
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/> .
#
# Additional permission under GNU GPL version 3 section 7:
# If you modify this Program, or any covered work, by linking or combining it
# with independent modules provided by the FPGA vendor only (this permission
# does not extend to any 3-rd party modules, "soft cores" or macros) under
# different license terms solely for the purpose of generating binary "bitstream"
# files and/or simulating the code, the copyright holders of this Program give
# you the right to distribute the covered work without those independent modules
# as long as the source code for them is available from the FPGA vendor free of
# charge, and there is no dependence on any ecrypted modules for simulating of
# the combined code. This permission applies to you if the distributed code
# contains all the components and scripts required to completely simulate it
# with at least one of the Free Software programs.
#################################################################################
create_clock -name axi_aclk -period 20 [get_nets -hierarchical *axi_aclk]
...
...
x393_timing.xdc
View file @
691ae8a4
...
...
@@ -17,6 +17,19 @@
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/> .
#
# Additional permission under GNU GPL version 3 section 7:
# If you modify this Program, or any covered work, by linking or combining it
# with independent modules provided by the FPGA vendor only (this permission
# does not extend to any 3-rd party modules, "soft cores" or macros) under
# different license terms solely for the purpose of generating binary "bitstream"
# files and/or simulating the code, the copyright holders of this Program give
# you the right to distribute the covered work without those independent modules
# as long as the source code for them is available from the FPGA vendor free of
# charge, and there is no dependence on any ecrypted modules for simulating of
# the combined code. This permission applies to you if the distributed code
# contains all the components and scripts required to completely simulate it
# with at least one of the Free Software programs.
#################################################################################
create_clock -name axi_aclk -period 20 [get_nets -hierarchical *axi_aclk]
...
...
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