More file headers editing

axi/axibram_read.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

axi/axibram_write.v

@@ -24,7 +24,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

axi/cmprs_afi_mux.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

axi/cmprs_afi_mux_ptr.v

@@ -24,7 +24,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

axi/cmprs_afi_mux_ptr_wresp.v

@@ -24,7 +24,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

axi/cmprs_afi_mux_status.v

@@ -27,7 +27,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

axi/histogram_saxi.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

axi/membridge.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

axi/mul_saxi_wr_chn.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

axi/mult_saxi_wr.v

@@ -26,7 +26,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

axi/mult_saxi_wr_inbuf.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

axi/mult_saxi_wr_pointers.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

cmd_mux.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

cmd_readback.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

compressor_jp/bit_stuffer_27_32.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

compressor_jp/bit_stuffer_escape.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

compressor_jp/bit_stuffer_metadata.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

compressor_jp/cmprs_buf_average.v

@@ -25,7 +25,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

compressor_jp/cmprs_cmd_decode.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

compressor_jp/cmprs_frame_sync.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

compressor_jp/cmprs_macroblock_buf_iface.v

@@ -25,7 +25,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

compressor_jp/cmprs_out_fifo.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

compressor_jp/cmprs_out_fifo32.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

compressor_jp/cmprs_pixel_buf_iface.v

@@ -25,7 +25,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

compressor_jp/cmprs_status.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

compressor_jp/cmprs_tile_mode2_decode.v

@@ -24,7 +24,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

compressor_jp/cmprs_tile_mode_decode.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

compressor_jp/compressor393.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

compressor_jp/csconvert.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

compressor_jp/csconvert_jp4.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

compressor_jp/csconvert_jp4diff.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

compressor_jp/csconvert_mono.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

compressor_jp/dcc_sync393.v

@@ -25,7 +25,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

compressor_jp/huffman_merge_code_literal.v

@@ -24,7 +24,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

compressor_jp/huffman_stuffer_meta.v

@@ -24,7 +24,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

compressor_jp/jp_channel.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

ddrc_test01.xcf

@@ -17,6 +17,19 @@
 #
 # You should have received a copy of the GNU General Public License
 # along with this program.  If not, see <http://www.gnu.org/licenses/> .
+#
+# Additional permission under GNU GPL version 3 section 7:
+# If you modify this Program, or any covered work, by linking or combining it
+# with independent modules provided by the FPGA vendor only (this permission
+# does not extend to any 3-rd party modules, "soft cores" or macros) under
+# different license terms solely for the purpose of generating binary "bitstream"
+# files and/or simulating the code, the copyright holders of this Program give
+# you the right to distribute the covered work without those independent modules
+# as long as the source code for them is available from the FPGA vendor free of
+# charge, and there is no dependence on any ecrypted modules for simulating of
+# the combined code. This permission applies to you if the distributed code
+# contains all the components and scripts required to completely simulate it
+# with at least one of the Free Software programs.
 #################################################################################
 
 #    output                       SDRST, // output SDRST, active low

ddrc_test01.xdc

@@ -17,6 +17,19 @@
 #
 # You should have received a copy of the GNU General Public License
 # along with this program.  If not, see <http://www.gnu.org/licenses/> .
+#
+# Additional permission under GNU GPL version 3 section 7:
+# If you modify this Program, or any covered work, by linking or combining it
+# with independent modules provided by the FPGA vendor only (this permission
+# does not extend to any 3-rd party modules, "soft cores" or macros) under
+# different license terms solely for the purpose of generating binary "bitstream"
+# files and/or simulating the code, the copyright holders of this Program give
+# you the right to distribute the covered work without those independent modules
+# as long as the source code for them is available from the FPGA vendor free of
+# charge, and there is no dependence on any ecrypted modules for simulating of
+# the combined code. This permission applies to you if the distributed code
+# contains all the components and scripts required to completely simulate it
+# with at least one of the Free Software programs.
 #################################################################################
 
 #    output                       SDRST, // output SDRST, active low

ddrc_test01_timing.xdc

@@ -17,6 +17,19 @@
 #
 # You should have received a copy of the GNU General Public License
 # along with this program.  If not, see <http://www.gnu.org/licenses/> .
+#
+# Additional permission under GNU GPL version 3 section 7:
+# If you modify this Program, or any covered work, by linking or combining it
+# with independent modules provided by the FPGA vendor only (this permission
+# does not extend to any 3-rd party modules, "soft cores" or macros) under
+# different license terms solely for the purpose of generating binary "bitstream"
+# files and/or simulating the code, the copyright holders of this Program give
+# you the right to distribute the covered work without those independent modules
+# as long as the source code for them is available from the FPGA vendor free of
+# charge, and there is no dependence on any ecrypted modules for simulating of
+# the combined code. This permission applies to you if the distributed code
+# contains all the components and scripts required to completely simulate it
+# with at least one of the Free Software programs.
 #################################################################################
 
 create_clock -name axi_aclk -period 20 [get_nets -hierarchical *axi_aclk]

fpga_version.vh

-      parameter FPGA_VERSION =          32'h0393006a; // modified clock generation, trying with HiSPi - 72.77% utilization
-//      parameter FPGA_VERSION =          32'h03930069; // modified clock generation, rebuilding for parallel sensors - all met, 71.8% utilization
-//      parameter FPGA_VERSION =          32'h03930068; // trying BUFR/FUFIO on all sensors ipclk/ipclk2x
-//      parameter FPGA_VERSION =          32'h03930067; // removing DUMMY_TO_KEEP, moving IOSTANDARD to HDL code
-//      parameter FPGA_VERSION =          32'h03930066; // trying just one histogram to watch utilization - with 4 was: Slice 15913 (80.98%), now Slice = 14318 (72.87%)
-//      parameter FPGA_VERSION =          32'h03930065; // (same rev) all met,  using "old" (non-inverted) phase - OK (full phase range)
-//      parameter FPGA_VERSION =          32'h03930065; // switch phy_top.v (all met) - OK with inverted phase control (reduced phase range)
-//      parameter FPGA_VERSION =          32'h03930064; // switch mcomtr_sequencer.v  (xclk not met) - wrong!
-//      parameter FPGA_VERSION =          32'h03930063; // switch mcntrl_linear_rw.v (met) good, worse mem valid phases 
-//      parameter FPGA_VERSION =          32'h03930062; // (met)debugging - what was broken (using older versions of some files) - mostly OK (some glitches)
-//      parameter FPGA_VERSION =          32'h03930061; // restored bufr instead of bufio for memory high speed clock
-//      parameter FPGA_VERSION =          32'h03930060; // moving CLK1..3 in memory controller MMCM, keeping CLK0 and FB. Stuck at memory calib 
-//      parameter FPGA_VERSION =          32'h0393005f; // restored mclk back to 200KHz, registers added to csconvert18a
-//      parameter FPGA_VERSION =          32'h0393005e; // trying mclk = 225 MHz (was 200MHz) define MCLK_VCO_MULT 18
-//      parameter FPGA_VERSION =          32'h0393005d; // trying mclk = 250 MHz (was 200MHz) define MCLK_VCO_MULT 20
-//      parameter FPGA_VERSION =          32'h0393005c; // 250MHz OK, no timing violations
+ /*******************************************************************************
+ * File: fpga_version.vh
+ * Date:2015-08-26  
+ * Author: Andrey Filippov     
+ * Description: Defining run-time readable FPGA code version
+ *
+ * Copyright (c) 2015 Elphel, Inc.
+ * fpga_version.vh is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * fpga_version.vh is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *
+ * Additional permission under GNU GPL version 3 section 7:
+ * If you modify this Program, or any covered work, by linking or combining it
+ * with independent modules provided by the FPGA vendor only (this permission
+ * does not extend to any 3-rd party modules, "soft cores" or macros) under
+ * different license terms solely for the purpose of generating binary "bitstream"
+ * files and/or simulating the code, the copyright holders of this Program give
+ * you the right to distribute the covered work without those independent modules
+ * as long as the source code for them is available from the FPGA vendor free of
+ * charge, and there is no dependence on any ecrypted modules for simulating of
+ * the combined code. This permission applies to you if the distributed code
+ * contains all the components and scripts required to completely simulate it
+ * with at least one of the Free Software programs.
+ *******************************************************************************/
+    parameter FPGA_VERSION =          32'h0393006a; // modified clock generation, trying with HiSPi - 72.77% utilization
+//    parameter FPGA_VERSION =          32'h03930069; // modified clock generation, rebuilding for parallel sensors - all met, 71.8% utilization
+//    parameter FPGA_VERSION =          32'h03930068; // trying BUFR/FUFIO on all sensors ipclk/ipclk2x
+//    parameter FPGA_VERSION =          32'h03930067; // removing DUMMY_TO_KEEP, moving IOSTANDARD to HDL code
+//    parameter FPGA_VERSION =          32'h03930066; // trying just one histogram to watch utilization - with 4 was: Slice 15913 (80.98%), now Slice = 14318 (72.87%)
+//    parameter FPGA_VERSION =          32'h03930065; // (same rev) all met,  using "old" (non-inverted) phase - OK (full phase range)
+//    parameter FPGA_VERSION =          32'h03930065; // switch phy_top.v (all met) - OK with inverted phase control (reduced phase range)
+//    parameter FPGA_VERSION =          32'h03930064; // switch mcomtr_sequencer.v  (xclk not met) - wrong!
+//    parameter FPGA_VERSION =          32'h03930063; // switch mcntrl_linear_rw.v (met) good, worse mem valid phases 
+//    parameter FPGA_VERSION =          32'h03930062; // (met)debugging - what was broken (using older versions of some files) - mostly OK (some glitches)
+//    parameter FPGA_VERSION =          32'h03930061; // restored bufr instead of bufio for memory high speed clock
+//    parameter FPGA_VERSION =          32'h03930060; // moving CLK1..3 in memory controller MMCM, keeping CLK0 and FB. Stuck at memory calib 
+//    parameter FPGA_VERSION =          32'h0393005f; // restored mclk back to 200KHz, registers added to csconvert18a
+//    parameter FPGA_VERSION =          32'h0393005e; // trying mclk = 225 MHz (was 200MHz) define MCLK_VCO_MULT 18
+//    parameter FPGA_VERSION =          32'h0393005d; // trying mclk = 250 MHz (was 200MHz) define MCLK_VCO_MULT 20
+//    parameter FPGA_VERSION =          32'h0393005c; // 250MHz OK, no timing violations
 //    parameter FPGA_VERSION =          32'h0393005b; // 250MHz Not tested, timing violation in bit_stuffer_escape: xclk -0.808 -142.047 515
 //    parameter FPGA_VERSION =          32'h0393005a; // Trying xclk = 250MHz - timing viloations in xdct393, but particular hardware works
 //    parameter FPGA_VERSION =          32'h03930059; // 'new' (no pclk2x, no xclk2x  clocks) sensor/converter w/o debug - OK

includes/tasks_tests_memory.vh

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

includes/x393_cur_params_target.vh

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

includes/x393_localparams.vh

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

includes/x393_mcontr_encode_cmd.vh

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

includes/x393_parameters.vh

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

includes/x393_simulation_parameters.vh

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

includes/x393_tasks01.vh

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

includes/x393_tasks_afi.vh

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

includes/x393_tasks_mcntrl_buffers.vh

@@ -24,7 +24,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

includes/x393_tasks_mcntrl_en_dis_priority.vh

@@ -24,7 +24,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

includes/x393_tasks_mcntrl_timing.vh

@@ -24,7 +24,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

includes/x393_tasks_pio_sequences.vh

@@ -24,7 +24,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

includes/x393_tasks_ps_pio.vh

@@ -24,7 +24,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

includes/x393_tasks_status.vh

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

logger/buf_xclk_mclk16_393.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

logger/event_logger.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

logger/imu_exttime393.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

logger/imu_message393.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

logger/imu_spi393.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

logger/imu_timestamps393.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

logger/logger_arbiter393.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

logger/nmea_decoder393.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

logger/rs232_rcv393.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

memctrl/cmd_encod_4mux.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

memctrl/cmd_encod_linear_mux.v

@@ -25,7 +25,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

memctrl/cmd_encod_linear_rd.v

@@ -24,7 +24,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

memctrl/cmd_encod_linear_rw.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

memctrl/cmd_encod_linear_wr.v

@@ -24,7 +24,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

memctrl/cmd_encod_tiled_32_rd.v

@@ -29,7 +29,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

memctrl/cmd_encod_tiled_32_rw.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

memctrl/cmd_encod_tiled_32_wr.v

@@ -29,7 +29,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

memctrl/cmd_encod_tiled_mux.v

@@ -25,7 +25,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

memctrl/cmd_encod_tiled_rd.v

@@ -31,7 +31,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

memctrl/cmd_encod_tiled_rw.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

memctrl/cmd_encod_tiled_wr.v

@@ -31,7 +31,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

memctrl/ddr_refresh.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

memctrl/mcntrl393.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

memctrl/mcntrl393_test01.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

memctrl/mcntrl_1kx32r.v

@@ -24,7 +24,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

memctrl/mcntrl_1kx32w.v

@@ -24,7 +24,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

memctrl/mcntrl_buf_rd.v

@@ -24,7 +24,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

memctrl/mcntrl_buf_wr.v

@@ -24,7 +24,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

memctrl/mcntrl_linear_rw.v

@@ -24,7 +24,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

memctrl/mcntrl_ps_pio.v

@@ -24,7 +24,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

memctrl/mcntrl_tiled_rw.v

@@ -26,7 +26,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

memctrl/memctrl16.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

memctrl/phy/byte_lane.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

memctrl/phy/cmd_addr.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

memctrl/phy/cmda_single.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

memctrl/phy/dm_single.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

memctrl/phy/dq_single.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

memctrl/phy/dqs_single.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

memctrl/phy/dqs_single_nofine.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

memctrl/phy/mcontr_sequencer.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

memctrl/phy/phy_cmd.v

@@ -24,7 +24,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

memctrl/phy/phy_top.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

memctrl/scheduler16.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

sensor/lens_flat393.v

@@ -29,7 +29,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

sensor/pxd_clock.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

sensor/pxd_single.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

sensor/sens_10398.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

sensor/sens_gamma.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

sensor/sens_hispi12l4.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

sensor/sens_hispi_clock.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

sensor/sens_hispi_din.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

sensor/sens_hispi_fifo.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

sensor/sens_hispi_lane.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

sensor/sens_histogram.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

sensor/sens_histogram_mux.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

sensor/sens_histogram_snglclk.v

@@ -25,7 +25,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

sensor/sens_parallel12.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

sensor/sens_sync.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

sensor/sensor_channel.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

sensor/sensor_fifo.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

sensor/sensor_i2c.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

sensor/sensor_i2c_io.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

sensor/sensor_i2c_prot.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

sensor/sensor_i2c_scl_sda.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

sensor/sensor_membuf.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

sensor/sensors393.v

@@ -24,7 +24,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

simulation_modules/par12_hispi_psp4l.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

simulation_modules/sim_clk_div.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

simulation_modules/sim_frac_clk_delay.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

simulation_modules/simul_axi_hp_rd.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

simulation_modules/simul_axi_hp_wr.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

simulation_modules/simul_axi_master_rdaddr.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

simulation_modules/simul_axi_master_wdata.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

simulation_modules/simul_axi_master_wraddr.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

simulation_modules/simul_axi_read.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

simulation_modules/simul_axi_slow_ready.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

simulation_modules/simul_clk.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

simulation_modules/simul_clk_div_mult.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

simulation_modules/simul_clk_mult.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

simulation_modules/simul_clk_mult_div.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

simulation_modules/simul_fifo.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

simulation_modules/simul_saxi_gp_wr.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

simulation_modules/simul_sensor12bits.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

status_read.v

@@ -31,7 +31,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

system_defines.vh

+ /*******************************************************************************
+ * File: system_defines.vh
+ * Date:2015-02-28  
+ * Author: Andrey Filippov     
+ * Description: Preprocessor macros definitions to be included in the project
+ *
+ * Copyright (c) 2015 Elphel, Inc.
+ * system_defines.vh is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ * system_defines.vh is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *
+ * Additional permission under GNU GPL version 3 section 7:
+ * If you modify this Program, or any covered work, by linking or combining it
+ * with independent modules provided by the FPGA vendor only (this permission
+ * does not extend to any 3-rd party modules, "soft cores" or macros) under
+ * different license terms solely for the purpose of generating binary "bitstream"
+ * files and/or simulating the code, the copyright holders of this Program give
+ * you the right to distribute the covered work without those independent modules
+ * as long as the source code for them is available from the FPGA vendor free of
+ * charge, and there is no dependence on any ecrypted modules for simulating of
+ * the combined code. This permission applies to you if the distributed code
+ * contains all the components and scripts required to completely simulate it
+ * with at least one of the Free Software programs.
+ *******************************************************************************/
   // This file may be used to define same pre-processor macros to be included into each parsed file
 `ifndef SYSTEM_DEFINES
   `define SYSTEM_DEFINES

timing/camsync393.v

@@ -28,7 +28,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

timing/rtc393.v

@@ -25,7 +25,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

timing/timestamp_fifo.v

@@ -27,7 +27,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

timing/timestamp_snapshot.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

timing/timestamp_to_parallel.v

@@ -24,7 +24,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

timing/timestamp_to_serial.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

timing/timing393.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

unisims_extra/IBUFG.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

unisims_extra/IBUFGDS.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

util_modules/axi_hp_clk.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

util_modules/clk_to_clk2x.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

util_modules/clocks393.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

util_modules/clocks393m.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

util_modules/cmd_deser.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

util_modules/cmd_frame_sequencer.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

util_modules/cmd_seq_mux.v

@@ -24,7 +24,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

util_modules/debug_master.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

util_modules/debug_slave.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

util_modules/dly01_16.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

util_modules/dly_16.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

util_modules/dual_clock_source.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

util_modules/elastic_cross_clock.v

@@ -28,7 +28,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

util_modules/fifo_1cycle.v

@@ -24,7 +24,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

util_modules/fifo_2regs.v

@@ -24,7 +24,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

util_modules/fifo_cross_clocks.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

util_modules/fifo_same_clock.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

util_modules/fifo_same_clock_fill.v

@@ -24,7 +24,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

util_modules/gpio393.v

@@ -24,7 +24,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

util_modules/index_max_16.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

util_modules/level_cross_clocks.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

util_modules/masked_max_reg.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

util_modules/mcont_common_chnbuf_reg.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

util_modules/mcont_from_chnbuf_reg.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

util_modules/mcont_to_chnbuf_reg.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

util_modules/multipulse_cross_clock.v

@@ -27,7 +27,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

util_modules/pri1hot16.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

util_modules/pulse_cross_clock.v

@@ -25,7 +25,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

util_modules/round_robin.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

util_modules/status_generate.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

util_modules/status_router16.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

util_modules/status_router2.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

util_modules/status_router4.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

util_modules/status_router8.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

util_modules/sync_resets.v

@@ -24,7 +24,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

util_modules/table_ad_receive.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

util_modules/table_ad_transmit.v

@@ -25,7 +25,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

wrap/dci_reset.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

wrap/ddr3_wrap.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

wrap/ibuf_ibufg.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

wrap/ibufds_ibufgds.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

wrap/ibufg.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

wrap/ibufgds.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

wrap/idelay_ctrl.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

wrap/idelay_fine_pipe.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

wrap/idelay_nofine.v

@@ -22,7 +22,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

wrap/iobuf.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

wrap/iserdes_mem.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

wrap/latch_g_ce.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

wrap/mmcm_adv.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

wrap/mmcm_phase_cntr.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

wrap/mpullup.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

wrap/obuf.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

wrap/obufds.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

wrap/oddr.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

wrap/oddr_ds.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

wrap/oddr_ss.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

wrap/odelay_fine_pipe.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

wrap/odelay_pipe.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

wrap/oserdes_mem.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

wrap/pll_base.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

wrap/ram18_var_w_var_r.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

wrap/ram18t_var_w_var_r.v

@@ -25,7 +25,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

wrap/ram18tp_var_w_var_r.v

@@ -25,7 +25,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

wrap/ramt_var_w_var_r.v

@@ -25,7 +25,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

wrap/ramtp_var_w_var_r.v

@@ -25,7 +25,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

wrap/select_clk_buf.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

x393.v

@@ -23,7 +23,7 @@
  * with independent modules provided by the FPGA vendor only (this permission
  * does not extend to any 3-rd party modules, "soft cores" or macros) under
  * different license terms solely for the purpose of generating binary "bitstream"
- * files * and/or simulating the code, the copyright holders of this Program give
+ * files and/or simulating the code, the copyright holders of this Program give
  * you the right to distribute the covered work without those independent modules
  * as long as the source code for them is available from the FPGA vendor free of
  * charge, and there is no dependence on any ecrypted modules for simulating of

x393.xcf

@@ -17,6 +17,19 @@
 #
 # You should have received a copy of the GNU General Public License
 # along with this program.  If not, see <http://www.gnu.org/licenses/> .
+#
+# Additional permission under GNU GPL version 3 section 7:
+# If you modify this Program, or any covered work, by linking or combining it
+# with independent modules provided by the FPGA vendor only (this permission
+# does not extend to any 3-rd party modules, "soft cores" or macros) under
+# different license terms solely for the purpose of generating binary "bitstream"
+# files and/or simulating the code, the copyright holders of this Program give
+# you the right to distribute the covered work without those independent modules
+# as long as the source code for them is available from the FPGA vendor free of
+# charge, and there is no dependence on any ecrypted modules for simulating of
+# the combined code. This permission applies to you if the distributed code
+# contains all the components and scripts required to completely simulate it
+# with at least one of the Free Software programs.
 #################################################################################
 
 #    output                       SDRST, // output SDRST, active low

x393.xdc

@@ -17,6 +17,19 @@
 #
 # You should have received a copy of the GNU General Public License
 # along with this program.  If not, see <http://www.gnu.org/licenses/> .
+#
+# Additional permission under GNU GPL version 3 section 7:
+# If you modify this Program, or any covered work, by linking or combining it
+# with independent modules provided by the FPGA vendor only (this permission
+# does not extend to any 3-rd party modules, "soft cores" or macros) under
+# different license terms solely for the purpose of generating binary "bitstream"
+# files and/or simulating the code, the copyright holders of this Program give
+# you the right to distribute the covered work without those independent modules
+# as long as the source code for them is available from the FPGA vendor free of
+# charge, and there is no dependence on any ecrypted modules for simulating of
+# the combined code. This permission applies to you if the distributed code
+# contains all the components and scripts required to completely simulate it
+# with at least one of the Free Software programs.
 #################################################################################
 
 # Global constraints

x393_hispi.xdc

@@ -17,6 +17,19 @@
 #
 # You should have received a copy of the GNU General Public License
 # along with this program.  If not, see <http://www.gnu.org/licenses/> .
+#
+# Additional permission under GNU GPL version 3 section 7:
+# If you modify this Program, or any covered work, by linking or combining it
+# with independent modules provided by the FPGA vendor only (this permission
+# does not extend to any 3-rd party modules, "soft cores" or macros) under
+# different license terms solely for the purpose of generating binary "bitstream"
+# files and/or simulating the code, the copyright holders of this Program give
+# you the right to distribute the covered work without those independent modules
+# as long as the source code for them is available from the FPGA vendor free of
+# charge, and there is no dependence on any ecrypted modules for simulating of
+# the combined code. This permission applies to you if the distributed code
+# contains all the components and scripts required to completely simulate it
+# with at least one of the Free Software programs.
 #################################################################################
 
 # Global constraints

x393_hispi_timing.xdc

@@ -17,6 +17,19 @@
 #
 # You should have received a copy of the GNU General Public License
 # along with this program.  If not, see <http://www.gnu.org/licenses/> .
+#
+# Additional permission under GNU GPL version 3 section 7:
+# If you modify this Program, or any covered work, by linking or combining it
+# with independent modules provided by the FPGA vendor only (this permission
+# does not extend to any 3-rd party modules, "soft cores" or macros) under
+# different license terms solely for the purpose of generating binary "bitstream"
+# files and/or simulating the code, the copyright holders of this Program give
+# you the right to distribute the covered work without those independent modules
+# as long as the source code for them is available from the FPGA vendor free of
+# charge, and there is no dependence on any ecrypted modules for simulating of
+# the combined code. This permission applies to you if the distributed code
+# contains all the components and scripts required to completely simulate it
+# with at least one of the Free Software programs.
 #################################################################################
 
 create_clock -name axi_aclk -period 20 [get_nets -hierarchical *axi_aclk]

x393_no_pclk2x_timing.xdc

@@ -17,6 +17,19 @@
 #
 # You should have received a copy of the GNU General Public License
 # along with this program.  If not, see <http://www.gnu.org/licenses/> .
+#
+# Additional permission under GNU GPL version 3 section 7:
+# If you modify this Program, or any covered work, by linking or combining it
+# with independent modules provided by the FPGA vendor only (this permission
+# does not extend to any 3-rd party modules, "soft cores" or macros) under
+# different license terms solely for the purpose of generating binary "bitstream"
+# files and/or simulating the code, the copyright holders of this Program give
+# you the right to distribute the covered work without those independent modules
+# as long as the source code for them is available from the FPGA vendor free of
+# charge, and there is no dependence on any ecrypted modules for simulating of
+# the combined code. This permission applies to you if the distributed code
+# contains all the components and scripts required to completely simulate it
+# with at least one of the Free Software programs.
 #################################################################################
 
 create_clock -name axi_aclk -period 20 [get_nets -hierarchical *axi_aclk]

x393_nox2_timing.xdc

@@ -17,6 +17,19 @@
 #
 # You should have received a copy of the GNU General Public License
 # along with this program.  If not, see <http://www.gnu.org/licenses/> .
+#
+# Additional permission under GNU GPL version 3 section 7:
+# If you modify this Program, or any covered work, by linking or combining it
+# with independent modules provided by the FPGA vendor only (this permission
+# does not extend to any 3-rd party modules, "soft cores" or macros) under
+# different license terms solely for the purpose of generating binary "bitstream"
+# files and/or simulating the code, the copyright holders of this Program give
+# you the right to distribute the covered work without those independent modules
+# as long as the source code for them is available from the FPGA vendor free of
+# charge, and there is no dependence on any ecrypted modules for simulating of
+# the combined code. This permission applies to you if the distributed code
+# contains all the components and scripts required to completely simulate it
+# with at least one of the Free Software programs.
 #################################################################################
 
 create_clock -name axi_aclk -period 20 [get_nets -hierarchical *axi_aclk]

x393_timing.xdc

@@ -17,6 +17,19 @@
 #
 # You should have received a copy of the GNU General Public License
 # along with this program.  If not, see <http://www.gnu.org/licenses/> .
+#
+# Additional permission under GNU GPL version 3 section 7:
+# If you modify this Program, or any covered work, by linking or combining it
+# with independent modules provided by the FPGA vendor only (this permission
+# does not extend to any 3-rd party modules, "soft cores" or macros) under
+# different license terms solely for the purpose of generating binary "bitstream"
+# files and/or simulating the code, the copyright holders of this Program give
+# you the right to distribute the covered work without those independent modules
+# as long as the source code for them is available from the FPGA vendor free of
+# charge, and there is no dependence on any ecrypted modules for simulating of
+# the combined code. This permission applies to you if the distributed code
+# contains all the components and scripts required to completely simulate it
+# with at least one of the Free Software programs.
 #################################################################################
 
 create_clock -name axi_aclk -period 20 [get_nets -hierarchical *axi_aclk]