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Commit 691579c0 authored by Andrey Filippov's avatar Andrey Filippov
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commands and status for LWIR/VOSPI, exported to C

parent c49619fd
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includes/x393_parameters.vh
View file @ 691579c0
......@@ -35,6 +35,9 @@
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
// All paremeters should be defined for all defines values - needed to export to C
parameter MCONTR_WR_MASK = 'h3c00, // AXI write address mask for the 1Kx32 buffers command sequence memory
parameter MCONTR_RD_MASK = 'h3c00, // AXI read address mask to generate busy
......@@ -155,11 +158,11 @@
parameter real REFCLK_FREQUENCY = 200.0, // 300.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE",
parameter CLKIN_PERIOD = 20, // 10, //ns >1.25, 600<Fvco<1200 // Hardware 150MHz , change to | 6.667
`ifdef MCLK_VCO_MULT
`ifdef MCLK_VCO_MULT
parameter CLKFBOUT_MULT = `MCLK_VCO_MULT ,
`else
`else
parameter CLKFBOUT_MULT = 16, // 8, // Fvco=Fclkin*CLKFBOUT_MULT_F/DIVCLK_DIVIDE, Fout=Fvco/CLKOUT#_DIVIDE | 16
`endif
`endif
`else
parameter real REFCLK_FREQUENCY = 300.0,
parameter HIGH_PERFORMANCE_MODE = "FALSE",
......@@ -533,7 +536,40 @@
parameter SENSI2C_IBUF_LOW_PWR= "TRUE",
parameter SENSI2C_SLEW = "SLOW",
//`ifndef HISPI
//`ifdef HISPI
//`elsif LWIR
parameter VOSPI_EN = 0,
parameter VOSPI_EN_BITS = 2,
parameter VOSPI_SEGM0_OK = 2,
parameter VOSPI_SEGM0_OK_BITS = 2,
parameter VOSPI_OUT_EN = 4,
parameter VOSPI_OUT_EN_BITS = 2,
parameter VOSPI_OUT_EN_SINGL = 6,
parameter VOSPI_RESET_CRC = 7,
parameter VOSPI_MRST = 8,
parameter VOSPI_MRST_BITS = 2,
parameter VOSPI_PWDN = 10,
parameter VOSPI_PWDN_BITS = 2,
parameter VOSPI_MCLK = 12,
parameter VOSPI_MCLK_BITS = 2,
parameter VOSPI_SPI_CLK = 14,
parameter VOSPI_SPI_CLK_BITS = 2,
parameter VOSPI_GPIO = 16,
parameter VOSPI_GPIO_BITS = 8,
parameter VOSPI_FAKE_OUT = 24, // to keep hardware
parameter VOSPI_MOSI = 25, // not used
parameter VOSPI_PACKET_WORDS = 80,
parameter VOSPI_NO_INVALID = 1, // do not output invalid packets data
parameter VOSPI_PACKETS_PER_LINE = 2,
parameter VOSPI_SEGMENT_FIRST = 1,
parameter VOSPI_SEGMENT_LAST = 4,
parameter VOSPI_PACKET_FIRST = 0,
parameter VOSPI_PACKET_LAST = 60,
parameter VOSPI_PACKET_TTT = 20, // line number where segment number is provided
parameter VOSPI_SOF_TO_HACT = 2, // clock cycles from SOF to HACT
parameter VOSPI_HACT_TO_HACT_EOF = 2, // minimal clock cycles from HACT to HACT or to EOF
//`else
//sensor_fifo parameters
parameter SENSOR_DATA_WIDTH = 12,
parameter SENSOR_FIFO_2DEPTH = 4,
......@@ -927,6 +963,7 @@
parameter MULTICLK_DIV_XCLK2X = 6, // 200 MHz for compressor (when MULTICLK_DIV_XCLK uses 100 MHz)
`else
parameter MULTICLK_DIV_XCLK = 5, // 240 MHz for compressor (12 for 100 MHz)
parameter MULTICLK_DIV_XCLK2X = 6, // unused value
`endif
parameter MULTICLK_DIV_SYNC = 12, // 100 MHz for inter-camera synchronization and time keeping
// Additional parameters for multi-clock PLL (phases and buffer types)
......
py393/vrlg.py
View file @ 691579c0
......@@ -131,24 +131,29 @@ HIST_SAXI_ADDR_MASK = int
CONTROL_RBACK_ADDR_MASK = int
SENSOR_CHN_EN_BIT_SET__RAW = str
CMPRS_CBIT_QBANK__TYPE = str
LWIR_TELEMETRY_AGC_HIGH = int
CLKOUT_DIV_PCLK__RAW = str
SENS_GAMMA_CTRL__RAW = str
DFLT_INV_CLK_DIV__RAW = str
SENS_LENS_SCALES_MASK__TYPE = str
CONTROL_RBACK_DEPTH = int
DLY_LANE0_DQS_WLV_IDELAY__TYPE = str
LOGGER_ADDR__RAW = str
DFLT_DQ_TRI_OFF_PATTERN = int
LWIR_MS_PERIOD = int
NUM_CYCLES_30__RAW = str
DLY_DQ_IDELAY__TYPE = str
VOSPI_SOF_TO_HACT = int
MCNTRL_TEST01_STATUS_REG_CHN4_ADDR__TYPE = str
MCONTR_LINTILE_RST_FRAME = int
CMPRS_CBIT_CMODE_MONO6__RAW = str
MCONTR_PHY_0BIT_DCI_RST = int
SENSOR_FIFO_2DEPTH = int
HIGH_PERFORMANCE_MODE__TYPE = str
VOSPI_MCLK = int
PXD_CAPACITANCE__RAW = str
AFI_LO_ADDR64__TYPE = str
CAMSYNC_TRIG_DELAY2 = int
VOSPI_MRST_BITS = int
MCNTRL_SCANLINE_STATUS_CNTRL__RAW = str
VOSPI_EN = int
AFI_SIZE64 = int
LOGGER_CONF_IMU_BITS = int
SENS_JTAG_TCK__RAW = str
......@@ -162,8 +167,10 @@ DQSTRI_LAST = int
MCNTRL_TEST01_CHN2_STATUS_CNTRL__TYPE = str
STATUS_2LSB_SHFT__TYPE = str
MEMBRIDGE_LEN64__TYPE = str
TABLE_QUANTIZATION_INDEX__TYPE = str
SENSOR_TIMING_STATUS_REG_INC = int
HISTOGRAM_ADDR_MASK__RAW = str
LOGGER_CONF_EN__RAW = str
LWIR_TELEMETRY_AGC_LOW__TYPE = str
HIST_CONFIRM_WRITE = int
CMPRS_GROUP_ADDR__TYPE = str
CMDFRAMESEQ_ADDR_INC = int
......@@ -179,6 +186,7 @@ CLKFBOUT_PHASE_SENSOR = float
DFLT_REFRESH_PERIOD = int
MCONTR_TOP_0BIT_REFRESH_EN__TYPE = str
NUM_CYCLES_20__TYPE = str
SENSI2C_TBL_NBRD__TYPE = str
SENS_JTAG_PGMEN = int
NUM_CYCLES_03__TYPE = str
CMPRS_CBIT_RUN_BITS__TYPE = str
......@@ -193,10 +201,13 @@ SENSIO_WIDTH__TYPE = str
MCNTRL_TEST01_CHN3_STATUS_CNTRL__TYPE = str
CONTROL_RBACK_ADDR__RAW = str
CMPRS_AFIMUX_CYCBITS = int
VOSPI_OUT_EN__RAW = str
RTC_MHZ = int
VOSPI_PACKET_WORDS = int
SENS_LENS_C_MASK = int
MCONTR_PHY_16BIT_EXTRA = int
HIST_SAXI_EN__TYPE = str
VOSPI_SEGMENT_FIRST = int
DEBUG_READ_REG_ADDR__TYPE = str
DEBUG_LOAD__RAW = str
WINDOW_Y0__RAW = str
......@@ -209,6 +220,7 @@ MEMBRIDGE_WIDTH64__RAW = str
LOGGER_CONF_MSG_BITS__RAW = str
SENS_GAMMA_MODE_REPET = int
SENSI2C_TBL_DLY__RAW = str
SENSOR_TIMING_LANE = int
CMPRS_CBIT_BAYER_BITS__TYPE = str
MCONTR_CMPRS_STATUS_INC = int
MCONTR_PHY_0BIT_CMDA_EN__TYPE = str
......@@ -247,6 +259,8 @@ HIST_SAXI_EN__RAW = str
SENSOR_16BIT_BIT__RAW = str
HIST_SAXI_AWCACHE__TYPE = str
SENSI2C_CMD_RUN_PBITS__TYPE = str
VOSPI_PACKET_LAST__TYPE = str
LWIR_TELEMETRY_TEMP_KELVIN__RAW = str
LOGGER_CONF_SYN_BITS__TYPE = str
MULTICLK_DIVCLK__RAW = str
GPIO_ADDR__TYPE = str
......@@ -258,6 +272,7 @@ MEMCLK_IOSTANDARD__RAW = str
MAX_TILE_HEIGHT__RAW = str
BUF_IPCLK2X_SENS3__TYPE = str
IBUF_LOW_PWR = str
MCONTR_LINTILE_LINEAR = int
DEBUG_CMD_LATENCY = int
CMD_DONE_BIT = int
NUM_CYCLES_31 = int
......@@ -267,11 +282,12 @@ CMPRS_CBIT_QBANK__RAW = str
SENS_SYNC_MASK__TYPE = str
MEMCLK_PERIOD__TYPE = str
MCONTR_BUF0_RD_ADDR__RAW = str
HISPI_MMCM1 = str
LWIR_TELEMETRY_SREV__RAW = str
SENS_PHASE_WIDTH = int
HIST_SAXI_MODE_ADDR_MASK__TYPE = str
MCONTR_CMPRS_STATUS_BASE__RAW = str
SENS_LENS_RADDR__TYPE = str
LWIR_TELEMETRY_AGC_HIGH__RAW = str
SENSI2C_CMD_SOFT_SCL = int
CAMSYNC_PRE_MAGIC__TYPE = str
MCNTRL_TEST01_CHN3_STATUS_CNTRL__RAW = str
......@@ -286,6 +302,8 @@ MCNTRL_TILED_FRAME_PAGE_RESET = int
MCONTR_SENS_STATUS_BASE__TYPE = str
CMPRS_FORMAT__TYPE = str
DLY_LANE1_DQS_WLV_IDELAY__RAW = str
VOSPI_NO_INVALID__RAW = str
VOSPI_FAKE_OUT__TYPE = str
SENS_LENS_RADDR = int
SENSI2C_CMD_TABLE__TYPE = str
PXD_IOSTANDARD = str
......@@ -295,10 +313,11 @@ BUF_CLK1X_PCLK = str
LOGGER_CONF_DBG_BITS = int
SENS_CTRL_ARO__TYPE = str
SENS_LENS_SCALES_MASK__RAW = str
LWIR_WINDOW_HEIGHT__TYPE = str
MCNTRL_TILED_STATUS_REG_CHN2_ADDR__TYPE = str
MCONTR_LINTILE_BYTE32__RAW = str
HISTOGRAM_WIDTH_HEIGHT = int
SENSOR_HIST_NRST_BITS__RAW = str
LWIR_TELEMETRY_AGC_ROI_BOTTOM = int
MCONTR_RD_MASK__TYPE = str
MULT_SAXI_CNTRL_MASK = int
NUM_CYCLES_23__RAW = str
......@@ -309,7 +328,7 @@ MCONTR_LINTILE_EXTRAPG_BITS__TYPE = str
MCONTR_BUF3_RD_ADDR__TYPE = str
LOGGER_CONF_EN_BITS__TYPE = str
CLKIN_PERIOD_PCLK__RAW = str
MAX_TILE_WIDTH__TYPE = str
HISPI_DQS_BIAS__TYPE = str
MULTICLK_DIV_DLYREF__TYPE = str
MULTICLK_MULT = int
SENS_LENS_POST_SCALE_MASK = int
......@@ -327,6 +346,7 @@ MCONTR_SENS_INC = int
CAMSYNC_TRIG_PERIOD__TYPE = str
SENSIO_STATUS = int
DFLT_DQS_PATTERN = int
MCONTR_BUF3_RD_ADDR__RAW = str
SENS_GAMMA_ADDR_DATA__RAW = str
DLY_LANE1_IDELAY__RAW = str
SLEW_CLK = str
......@@ -334,7 +354,9 @@ CMPRS_JP4DIFF = int
RTC_STATUS_REG_ADDR = int
SENS_LENS_BY_MASK__TYPE = str
CMPRS_CBIT_CMODE__RAW = str
SENS_GAMMA_BUFFER = int
TILED_EXTRA_PAGES__TYPE = str
FRAME_START_ADDRESS__TYPE = str
AXI_RDADDR_LATENCY = int
AFI_MUX_BUF_LATENCY = int
WINDOW_WIDTH = int
......@@ -355,11 +377,14 @@ DFLT_WBUF_DELAY__RAW = str
CAMSYNC_POST_MAGIC__RAW = str
NUM_CYCLES_07__RAW = str
NUM_CYCLES_24__RAW = str
VOSPI_SEGM0_OK__RAW = str
NUM_INTERRUPTS = int
NUM_CYCLES_13__RAW = str
LOGGER_CONF_MSG__RAW = str
MCNTRL_TILED_STATUS_REG_CHN2_ADDR__RAW = str
VOSPI_PACKETS_PER_LINE = int
LAST_FRAME_BITS__RAW = str
VOSPI_MCLK__RAW = str
SENS_DIVCLK_DIVIDE = int
SENSI2C_CMD_SOFT_SDA__TYPE = str
SENS_LENS_COEFF__RAW = str
......@@ -369,7 +394,7 @@ AXI_TASK_HOLD__RAW = str
MCNTRL_SCANLINE_WINDOW_WH__TYPE = str
CMPRS_AFIMUX_RADDR0__TYPE = str
MCNTRL_TILED_WINDOW_WH__RAW = str
DLY_DM_ODELAY__RAW = str
CMDFRAMESEQ_DEPTH__TYPE = str
CMPRS_FRMT_MBRM1_BITS = int
CAMSYNC_EXTERNAL_BIT = int
CMPRS_STATUS_REG_BASE__TYPE = str
......@@ -391,17 +416,21 @@ SENS_CTRL_QUADRANTS__TYPE = str
SENS_LENS_BY_MASK__RAW = str
SENS_CTRL_GP0__TYPE = str
DFLT_REFRESH_ADDR = int
HISPI_FIFO_START__TYPE = str
DLY_DQS_ODELAY__TYPE = str
TEST01_SUSPEND__RAW = str
SENS_GAMMA_HEIGHT01__TYPE = str
LWIR_TELEMETRY_AGC_LOW__RAW = str
LWIR_TELEMETRY_TEMP_KELVIN__TYPE = str
CMPRS_HIFREQ_REG_INC = int
STATUS_ADDR_MASK__TYPE = str
MCONTR_TOP_0BIT_ADDR_MASK__RAW = str
TEST01_START_FRAME = int
LWIR_DATA_FILE3 = str
RTC_SET_USEC__RAW = str
LOGGER_CONF_SYN_BITS__RAW = str
CAMSYNC_ADDR__TYPE = str
CMPRS_CBIT_CMODE_JP4DIFFDIV2__TYPE = str
LWIR_TELEMETRY_AGC_LOW = int
MULT_SAXI_BSLOG1__TYPE = str
LOGGER_CONF_MSG_BITS__TYPE = str
LOGGER_ADDR = int
......@@ -423,7 +452,7 @@ NUM_CYCLES_20 = int
NUM_CYCLES_21 = int
FRAME_FULL_WIDTH__TYPE = str
CAMSYNC_TRIG_DELAY2__TYPE = str
MULTICLK_BUF_DLYREF__RAW = str
SENS_CTRL_QUADRANTS_WIDTH__RAW = str
FCLK0_PERIOD = float
CMDFRAMESEQ_REL__TYPE = str
HISPI_DELAY_CLK0 = str
......@@ -441,18 +470,20 @@ MULT_SAXI_CNTRL_STATUS__TYPE = str
CMPRS_FRMT_MBRM1_BITS__RAW = str
SCANLINE_EXTRA_PAGES = int
LD_DLY_LANE1_ODELAY__RAW = str
SENSOR_CHN_EN_BIT_SET__TYPE = str
LOGGER_CONF_EN_BITS__RAW = str
SENS_CTRL_IGNORE_EMBED__TYPE = str
MAX_TILE_WIDTH__TYPE = str
SENS_LENS_FAT0_IN_MASK__TYPE = str
RSEL = int
CMPRS_CBIT_DCSUB_BITS__TYPE = str
LWIR_TELEMETRY_AGC_ROI_TOP__TYPE = str
TABLE_CORING_INDEX__TYPE = str
AXI_RD_ADDR_BITS__TYPE = str
CAMSYNC_CHN_EN_BIT__TYPE = str
CMDFRAMESEQ_ADDR_BASE__RAW = str
MCONTR_LINTILE_SKIP_LATE__TYPE = str
DEBUG_ADDR__RAW = str
CONTROL_ADDR__RAW = str
SENSI2C_CMD_RESET = int
TILED_STARTY__RAW = str
RTC_BITC_PREDIV = int
CMPRS_FRMT_MBCM1_BITS__TYPE = str
SENS_CTRL_QUADRANTS_EN__RAW = str
......@@ -468,10 +499,11 @@ MCONTR_SENS_STATUS_BASE = int
AXI_WR_ADDR_BITS__RAW = str
SENSI2C_CMD_RUN__TYPE = str
MULTICLK_DIV_SYNC__RAW = str
VOSPI_EN__RAW = str
CMPRS_CORING_MODE = int
LOGGER_STATUS__TYPE = str
DFLT_REFRESH_PERIOD__TYPE = str
FFCLK1_IOSTANDARD = str
SENS_JTAG_TMS__TYPE = str
MCNTRL_TILED_MASK = int
MULTICLK_DIV_AXIHP = int
SENSIO_JTAG__RAW = str
......@@ -487,15 +519,17 @@ SENS_SYNC_LATE__RAW = str
SENSI2C_TBL_NBRD_BITS__RAW = str
DLY_CMDA_ODELAY = long
GPIO_PORTEN__RAW = str
LOGGER_BIT_DURATION__RAW = str
MCONTR_ARBIT_ADDR_MASK = int
MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR = int
MCNTRL_SCANLINE_WINDOW_WH = int
WBUF_DLY_WLV__RAW = str
SIMULATE_CMPRS_CMODE3__RAW = str
TABLE_HUFFMAN_INDEX = int
VOSPI_HACT_TO_HACT_EOF__RAW = str
MCNTRL_TILED_FRAME_LAST = int
MCNTRL_TEST01_CHN2_MODE__RAW = str
CMPRS_AFIMUX_REG_ADDR0__TYPE = str
CMPRS_RAW__TYPE = str
HISPI_DELAY_CLK1__RAW = str
SENSI2C_TBL_RNWREG__RAW = str
RTC_SEC_USEC_ADDR = int
......@@ -505,12 +539,14 @@ LD_DLY_LANE0_IDELAY = int
NUM_CYCLES_01__TYPE = str
NUM_CYCLES_24__TYPE = str
FCLK0_PERIOD__RAW = str
VOSPI_SEGM0_OK_BITS__RAW = str
MCLK_PHASE__TYPE = str
SENSI2C_DRIVE__TYPE = str
SENS_CTRL_RST_MMCM__RAW = str
MCONTR_BUF2_WR_ADDR__TYPE = str
GPIO_SLEW__TYPE = str
SENS_LENS_BX__RAW = str
DQTRI_LAST__TYPE = str
TEST_INITIAL_BURST = int
SENS_REF_JITTER1__RAW = str
MCNTRL_TILED_FRAME_FULL_WIDTH = int
......@@ -518,6 +554,7 @@ CMDFRAMESEQ_DEPTH = int
SENS_LENS_POST_SCALE__TYPE = str
RTC_MHZ__RAW = str
MCONTR_LINTILE_COPY_FRAME = int
CMPRS_CBIT_BE16 = int
SENSOR_PRIORITY__RAW = str
HIST_SAXI_ADDR_MASK__TYPE = str
SENS_CTRL_LD_DLY = int
......@@ -527,7 +564,7 @@ SENSOR_IMAGE_TYPE1__TYPE = str
MCONTR_TOP_16BIT_REFRESH_ADDRESS__TYPE = str
MCONTR_LINTILE_DIS_NEED__TYPE = str
DFLT_DQS_PATTERN__RAW = str
CMPRS_TABLES__TYPE = str
SIMULATE_CMPRS_CMODE1__TYPE = str
MCNTRL_PS_STATUS_CNTRL__TYPE = str
MCONTR_PHY_16BIT_ADDR = int
REF_JITTER1__TYPE = str
......@@ -544,6 +581,7 @@ SENS_GAMMA_CTRL = int
HISPI_WAIT_ALL_LANES__TYPE = str
SENSIO_RADDR = int
BUF_CLK1X_PCLK__RAW = str
LWIR_FRAME_DELAY = int
GPIO_N__TYPE = str
MCONTR_BUF4_RD_ADDR__TYPE = str
NUM_CYCLES_16__RAW = str
......@@ -559,9 +597,12 @@ HISTOGRAM_RADDR0__TYPE = str
HISPI_FIFO_DEPTH__TYPE = str
LOGGER_CONF_SYN_BITS = int
NUM_CYCLES_19 = int
MULTICLK_DIV_XCLK2X = int
SENS_CTRL_GP1__TYPE = str
MCNTRL_TEST01_MASK__TYPE = str
SENS_CTRL_QUADRANTS_WIDTH__RAW = str
SENSOR_16BIT_BIT_SET__RAW = str
LWIR_TELEMETRY__TYPE = str
MULTICLK_BUF_DLYREF__RAW = str
SENSOR_FIFO_DELAY__RAW = str
DLY_SET = int
CMDFRAMESEQ_CTRL__TYPE = str
......@@ -578,12 +619,13 @@ HISTOGRAM_HEIGHT__TYPE = str
CMPRS_HIFREQ_REG_BASE__TYPE = str
FCLK0_PERIOD__TYPE = str
MCNTRL_SCANLINE_FRAME_PAGE_RESET__RAW = str
DQTRI_LAST__TYPE = str
LWIR_WINDOW_WIDTH__TYPE = str
MULTICLK_DIVCLK__TYPE = str
DLY_DQ_ODELAY = long
BUF_IPCLK_SENS1__TYPE = str
MCONTR_TOP_16BIT_ADDR = int
CMPRS_TIMEOUT = int
LWIR_TELEMETRY_TEMP_COUTS__TYPE = str
HISPI_IOSTANDARD__TYPE = str
CMPRS_AFIMUX_RST = int
NUM_CYCLES_18 = int
......@@ -597,7 +639,6 @@ NUM_CYCLES_16 = int
NUM_CYCLES_15 = int
NUM_CYCLES_21__TYPE = str
CMPRS_CBIT_BAYER = int
LOGGER_CONF_EN_BITS__RAW = str
SLEW_CLK__TYPE = str
MCONTR_PHY_0BIT_DLY_SET = int
HISPI_DIFF_TERM__TYPE = str
......@@ -626,10 +667,11 @@ SIMULATE_CMPRS_CMODE2 = int
SIMULATE_CMPRS_CMODE3 = int
SIMULATE_CMPRS_CMODE0 = int
SIMULATE_CMPRS_CMODE1 = int
MULT_SAXI_CNTRL_ADDR = int
MULT_SAXI_BSLOG3__RAW = str
MULTICLK_BUF_SYNC__TYPE = str
HIST_SAXI_ADDR_REL__RAW = str
SENS_GAMMA_MODE_PAGE_SET__RAW = str
LWIR_DATA_FILE1__RAW = str
CMPRS_CBIT_CMODE_MONO4__TYPE = str
HIST_SAXI_MODE_WIDTH__RAW = str
SENS_LENS_AX = int
......@@ -640,9 +682,9 @@ RTC_ADDR = int
MCLK_PHASE__RAW = str
SENSIO_RADDR__TYPE = str
CLKFBOUT_MULT_PCLK__TYPE = str
VERBOSE__TYPE = str
CLK_ADDR__TYPE = str
CMPRS_FORMAT = int
VOSPI_SEGM0_OK_BITS = int
SENSIO_STATUS_REG_REL = int
FFCLK1_CAPACITANCE = str
CMPRS_CBIT_CMODE_BITS__RAW = str
......@@ -652,14 +694,16 @@ CMPRS_AFIMUX_RADDR0__RAW = str
CAMSYNC_EN_BIT = int
MCONTR_PHY_16BIT_PATTERNS__RAW = str
HISTOGRAM_RAM_MODE = str
VOSPI_GPIO_BITS = int
SENS_REFCLK_FREQUENCY__TYPE = str
HISTOGRAM_TOP__TYPE = str
SENS_GAMMA_MODE_EN__RAW = str
SENS_CTRL_ODD__TYPE = str
SENSI2C_TBL_SA_BITS__TYPE = str
DEBUG_ADDR = int
MCNTRL_SCANLINE_START_DELAY__RAW = str
SIMULATE_CMPRS_CMODE2__TYPE = str
MULT_SAXI_ADV_WR__RAW = str
MCONTR_LINTILE_LINEAR__RAW = str
LOGGER_PAGE_GPS = int
HIST_SAXI_MODE_ADDR_MASK = int
CMPRS_AFIMUX_SA_LEN__RAW = str
......@@ -668,6 +712,7 @@ CMPRS_CSAT_CR__RAW = str
CMPRS_CBIT_RUN = int
SENS_LENS_ADDR_MASK__RAW = str
SENS_CTRL_QUADRANTS__RAW = str
SENSOR_TIMING_BITS__TYPE = str
RTC_MASK__RAW = str
SENS_LENS_ADDR_MASK__TYPE = str
SENS_LENS_AX__TYPE = str
......@@ -679,8 +724,10 @@ SENSI2C_TBL_SA__RAW = str
CMPRS_CBIT_CMODE_JP4__RAW = str
MULTICLK_BUF_AXIHP__RAW = str
CLK_STATUS__TYPE = str
VOSPI_OUT_EN_BITS = int
GPIO_SET_STATUS__RAW = str
SENS_JTAG_TCK = int
SENS_CTRL_ODD__RAW = str
XOR_HIST_BAYER__RAW = str
DEBUG_STATUS_REG_ADDR__TYPE = str
REFRESH_OFFSET__TYPE = str
......@@ -699,12 +746,14 @@ SDCLK_PHASE__RAW = str
SENS_SYNC_RADDR__TYPE = str
BUF_IPCLK_SENS0__TYPE = str
SENSI2C_CMD_RUN__RAW = str
VOSPI_SEGM0_OK = int
MCNTRL_TILED_STARTADDR__TYPE = str
DLY_LD_MASK = int
MCONTR_LINTILE_BYTE32 = int
VOSPI_MRST_BITS__TYPE = str
CAMSYNC_TRIG_DELAY3__RAW = str
NUM_CYCLES_09__RAW = str
SENS_SYNC_LBITS__RAW = str
LOGGER_STATUS_MASK__TYPE = str
MEMBRIDGE_SIZE64__TYPE = str
SENS_GAMMA_HEIGHT2 = int
DLY_LD_MASK__TYPE = str
STATUS_MSB_RSHFT__TYPE = str
......@@ -724,12 +773,15 @@ CMPRS_CBIT_CMODE_JP46DC__TYPE = str
LOGGER_MASK__RAW = str
IBUF_LOW_PWR__RAW = str
DLY_CMDA_ODELAY__TYPE = str
VOSPI_SPI_CLK_BITS = int
SENS_LENS_FAT0_OUT_MASK__TYPE = str
LWIR_GPIO_IN__TYPE = str
SENSI2C_ABS_RADDR__TYPE = str
MCONTR_PHY_STATUS_REG_ADDR__TYPE = str
WBUF_DLY_WLV__TYPE = str
HISPI_MSB_FIRST__TYPE = str
MCONTR_TOP_16BIT_CHN_EN = int
LWIR_WINDOW_WIDTH__RAW = str
BUF_IPCLK2X_SENS1__TYPE = str
DEFAULT_STATUS_MODE = int
CMPRS_CBIT_CMODE_JPEG18__TYPE = str
......@@ -737,6 +789,7 @@ MULT_SAXI_AWCACHE = int
MCNTRL_SCANLINE_FRAME_PAGE_RESET = int
MCNTRL_TILED_FRAME_PAGE_RESET__TYPE = str
CMPRS_CBIT_CMODE_JP46DC__RAW = str
VOSPI_EN_BITS = int
SENSI2C_TBL_RAH__RAW = str
CMPRS_CSAT_CR_BITS__TYPE = str
NUM_CYCLES_05 = int
......@@ -767,22 +820,27 @@ REFRESH_OFFSET = int
MCNTRL_PS_EN_RST = int
MCONTR_SENS_BASE__RAW = str
SENS_GAMMA_ADDR_MASK__TYPE = str
VOSPI_PWDN__RAW = str
CMPRS_CSAT_CR = int
CMPRS_CBIT_RUN_ENABLE = int
INITIALIZE_OFFSET = int
MCONTR_TOP_16BIT_CHN_EN__TYPE = str
CMPRS_CSAT_CB = int
VOSPI_SEGMENT_LAST__TYPE = str
VERBOSE = int
DLY_LANE1_ODELAY = long
LOGGER_PERIOD__RAW = str
LWIR_TELEMETRY_STATUS__RAW = str
MCNTRL_SCANLINE_STATUS_CNTRL__TYPE = str
SENS_LENS_AX_MASK = int
AXI_RD_ADDR_BITS__RAW = str
AXI_WRADDR_LATENCY = int
MCONTR_PHY_16BIT_EXTRA__RAW = str
SENS_SS_MOD_PERIOD__TYPE = str
MCONTR_LINTILE_SKIP_LATE__RAW = str
SENS_JTAG_PGMEN__TYPE = str
CMPRS_CBIT_CMODE_RAW__RAW = str
MEMBRIDGE_LEN64__RAW = str
LWIR_DATA_FILE2__TYPE = str
MCONTR_LINTILE_EN = int
DFLT_REFRESH_ADDR__RAW = str
GPIO_N = int
......@@ -792,9 +850,11 @@ HISTOGRAM_RADDR_INC__TYPE = str
SENS_CTRL_GP0 = int
SENS_CTRL_GP1 = int
FFCLK0_IBUF_LOW_PWR__TYPE = str
LWIR_TELEMETRY_REV = int
CMPRS_CBIT_DCSUB_BITS__TYPE = str
SENS_GAMMA_RADDR = int
NUM_CYCLES_14__RAW = str
NUM_CYCLES_28__RAW = str
CMPRS_AFIMUX_MASK__RAW = str
CLKIN_PERIOD_SENSOR__RAW = str
PHASE_WIDTH__TYPE = str
CMPRS_JP4__RAW = str
......@@ -821,13 +881,15 @@ MULT_SAXI_CNTRL_MODE = int
PHASE_WIDTH = int
DFLT_DQ_TRI_OFF_PATTERN__TYPE = str
MCNTRL_SCANLINE_MASK = int
MCONTR_LINTILE_LINEAR__TYPE = str
MULTICLK_DIVCLK = int
MCNTRL_TILED_TILE_WHS__TYPE = str
MULT_SAXI_BSLOG3__TYPE = str
SENSOR12BITS_NGPL__RAW = str
CLKFBOUT_MULT__RAW = str
VOSPI_SEGMENT_FIRST__TYPE = str
CMPRS_STATUS_REG_INC__RAW = str
SIMULATE_CMPRS_CMODE1__TYPE = str
SENSOR_TIMING_STATUS_REG_INC__RAW = str
HISTOGRAM_RADDR0__RAW = str
HISPI_KEEP_IRST = int
STATUS_ADDR_MASK = int
......@@ -860,13 +922,14 @@ CONTROL_RBACK_ADDR_MASK__TYPE = str
MCONTR_BUF4_WR_ADDR = int
SENS_DIVCLK_DIVIDE__RAW = str
SENSOR_BASE_INC__RAW = str
VOSPI_PACKET_FIRST__RAW = str
CMPRS_CBIT_DCSUB_BITS = int
HISTOGRAM_LEFT__RAW = str
MCONTR_TOP_16BIT_ADDR_MASK = int
PXD_IBUF_LOW_PWR__TYPE = str
MCONTR_LINTILE_REPEAT__TYPE = str
HIST_SAXI_MODE_WIDTH__TYPE = str
SENS_LENS_FAT0_OUT__RAW = str
VOSPI_MRST_BITS__RAW = str
HISTOGRAM_RADDR2__RAW = str
SENSI2C_STATUS = int
CMPRS_CBIT_CMODE_JP4DIFF__TYPE = str
......@@ -874,17 +937,18 @@ MULTICLK_DIV_XCLK__TYPE = str
SENS_SYNC_LATE_DFLT = int
SENSI2C_STATUS_REG_BASE__RAW = str
AFI_LO_ADDR64__RAW = str
BUF_IPCLK_SENS1__RAW = str
TILED_STARTX__RAW = str
MCNTRL_SCANLINE_STARTADDR__RAW = str
SENSI2C_STATUS_REG_BASE__TYPE = str
DEBUG_LOAD__TYPE = str
MCONTR_PHY_16BIT_WBUF_DELAY = int
DLY_LANE1_DQS_WLV_IDELAY__TYPE = str
TILE_HEIGHT__RAW = str
VOSPI_EN_BITS__TYPE = str
MULTICLK_PHASE_SYNC = float
SENSI2C_TBL_SA_BITS__RAW = str
HISPI_MMCM3__RAW = str
CMPRS_CBIT_RUN_STANDALONE = int
LWIR_DATA_FILE2__RAW = str
READ_BLOCK_OFFSET__RAW = str
HISTOGRAM_LEFT_TOP__TYPE = str
MCONTR_CMPRS_INC = int
......@@ -904,11 +968,14 @@ SENSIO_CTRL__TYPE = str
SENSIO_WIDTH__RAW = str
CMPRS_MASK__TYPE = str
MEMBRIDGE_SIZE64__RAW = str
CMPRS_CBIT_CMODE_RAW__TYPE = str
HISPI_IFD_DELAY_VALUE__RAW = str
CAMSYNC_GPIO_EXT_OUT__RAW = str
MCNTRL_PS_STATUS_CNTRL = int
SS_MODE__TYPE = str
SENSI2C_STATUS__RAW = str
CMPRS_MASK = int
CMPRS_CBIT_CMODE_RAW = int
SENSI2C_CMD_ACIVE_EARLY0__RAW = str
T_RFC__TYPE = str
HISPI_IBUF_DELAY_VALUE__RAW = str
......@@ -923,7 +990,7 @@ MULTICLK_BUF_AXIHP = str
FRAME_WIDTH_BITS = int
READ_PATTERN_OFFSET__TYPE = str
SENS_CTRL_RST_MMCM = int
HISPI_DQS_BIAS__TYPE = str
VOSPI_PACKET_LAST = int
MCONTR_CMD_WR_ADDR = int
SENSI2C_TBL_DLY_BITS__RAW = str
SENSOR12BITS_TDDO1__RAW = str
......@@ -934,17 +1001,20 @@ DLY_LANE0_ODELAY = long
NUM_XFER_BITS = int
HISPI_NUMLANES__RAW = str
MCNTRL_TEST01_STATUS_REG_CHN2_ADDR = int
DLY_DQS_ODELAY__TYPE = str
LWIR_DATA_FILE4 = str
LWIR_DATA_FILE1 = str
DLY_LANE0_ODELAY__RAW = str
LWIR_DATA_FILE2 = str
MCONTR_BUF3_WR_ADDR__TYPE = str
SCANLINE_STARTX__TYPE = str
CAMSYNC_MASTER_BIT__TYPE = str
SIMUL_AXI_READ_WIDTH = int
WRITE_BLOCK_OFFSET = int
FRAME_FULL_WIDTH__RAW = str
LOGGER_CONF_EN__TYPE = str
LOGGER_PAGE_IMU__RAW = str
SENS_SYNC_MINPER__RAW = str
CMPRS_AFIMUX_MODE__RAW = str
DFLT_DQ_TRI_OFF_PATTERN = int
SENSI2C_TBL_RAH_BITS = int
MULT_SAXI_CNTRL_IRQ__RAW = str
MCNTRL_TEST01_STATUS_REG_CHN2_ADDR__RAW = str
......@@ -955,6 +1025,7 @@ HISPI_MMCM1__RAW = str
MULT_SAXI_CNTRL_STATUS = int
TEST_INITIAL_BURST__TYPE = str
SENSOR12BITS_NVLO = int
LWIR_TELEMETRY_AGC_ROI_LEFT = int
NUM_CYCLES_19__RAW = str
SIMULATE_CMPRS_CMODE2__RAW = str
MCNTRL_PS_MASK__RAW = str
......@@ -962,9 +1033,11 @@ CMPRS_CBIT_CMODE_JPEG20__TYPE = str
HISPI_IBUF_LOW_PWR__TYPE = str
CMPRS_TIMEOUT_BITS__RAW = str
MEMBRIDGE_LO_ADDR64__RAW = str
LWIR_TELEMETRY_VIDEO_FORMAT = int
MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR = int
RTC_SET_USEC__TYPE = str
MULT_SAXI_BSLOG3__RAW = str
MCNTRL_TILED_WINDOW_X0Y0__RAW = str
MULT_SAXI_CNTRL_ADDR = int
CMPRS_TIMEOUT_BITS__TYPE = str
PHASE_CLK2X_PCLK__TYPE = str
FFCLK1_DIFF_TERM__TYPE = str
......@@ -986,11 +1059,13 @@ MULTICLK_MULT__TYPE = str
SS_EN__TYPE = str
CMDSEQMUX_STATUS = int
SENSI2C_TBL_RNWREG__TYPE = str
MULT_SAXI_ADV_WR__RAW = str
LWIR_TELEMETRY_TEMP_LAST_KELVIN__TYPE = str
FRAME_START_ADDRESS_INC = int
TILED_STARTY = int
LOGGER_MASK = int
MCNTRL_SCANLINE_FRAME_FULL_WIDTH = int
WINDOW_Y0 = int
CMPRS_GROUP_ADDR = int
CAMSYNC_PRE_MAGIC__RAW = str
PXD_CLK_DIV_BITS = int
SENSOR_CHN_EN_BIT = int
......@@ -998,6 +1073,8 @@ LD_DLY_LANE0_ODELAY = int
CMPRS_MONO16__TYPE = str
READ_PATTERN_OFFSET__RAW = str
SENSI2C_TBL_DLY__TYPE = str
LWIR_FRAME_DELAY__TYPE = str
MULTICLK_DIV_XCLK2X__TYPE = str
MEMBRIDGE_SIZE64 = int
SENSOR_IMAGE_TYPE1__RAW = str
MCONTR_PHY_0BIT_CKE_EN__TYPE = str
......@@ -1005,23 +1082,26 @@ CMPRS_FRMT_MBCM1_BITS = int
SENS_GAMMA_MODE_REPET_SET__TYPE = str
HISTOGRAM_RAM_MODE__TYPE = str
AFI_LO_ADDR64 = int
NUM_CYCLES_28__TYPE = str
HISTOGRAM_RADDR_INC = int
VOSPI_PACKETS_PER_LINE__TYPE = str
NUM_CYCLES_07__TYPE = str
SENS_LENS_FAT0_IN = int
CMPRS_FRMT_LMARG_BITS__TYPE = str
SENSOR12BITS_NGPL__TYPE = str
HISTOGRAM_RADDR1__TYPE = str
SIMUL_AXI_READ_WIDTH = int
CAMSYNC_MASTER_BIT__TYPE = str
HISTOGRAM_ADDR_MASK = int
MCONTR_BUF2_RD_ADDR__RAW = str
MCONTR_TOP_16BIT_ADDR_MASK__RAW = str
MULTICLK_DIV_DLYREF__RAW = str
MCNTRL_PS_EN_RST__RAW = str
VERBOSE__TYPE = str
BUF_CLK1X_PCLK__TYPE = str
MULT_SAXI_BSLOG1__RAW = str
CLKFBOUT_MULT_PCLK__RAW = str
MCONTR_SENS_STATUS_INC__TYPE = str
LWIR_TELEMETRY_STATUS = int
CAMSYNC_TRIG_DELAY0__TYPE = str
LWIR_DATA_FILE3__RAW = str
SENSI2C_STATUS_REG_INC = int
CLKFBOUT_PHASE__TYPE = str
TABLE_QUANTIZATION_INDEX__RAW = str
......@@ -1032,6 +1112,7 @@ MCNTRL_TILED_WINDOW_X0Y0__TYPE = str
MULTICLK_PHASE_FB = float
NUM_XFER_BITS__RAW = str
MCNTRL_TILED_WINDOW_STARTXY__RAW = str
LWIR_TELEMETRY_AGC_ROI_BOTTOM__TYPE = str
CMPRS_CSAT_CB_BITS__RAW = str
CMPRS_CBIT_RUN__RAW = str
SENS_GAMMA_RADDR__RAW = str
......@@ -1040,12 +1121,13 @@ MULT_SAXI_IRQLEN_ADDR__RAW = str
SENSI2C_CMD_ACIVE_EARLY0__TYPE = str
MCNTRL_SCANLINE_FRAME_LAST = int
MCNTRL_TILED_STATUS_REG_CHN4_ADDR = int
SENS_GAMMA_BUFFER = int
VOSPI_MOSI__RAW = str
GPIO_SET_PINS__RAW = str
SENS_CTRL_RST_MMCM__TYPE = str
AFI_MUX_BUF_LATENCY__RAW = str
CMPRS_CBIT_CMODE_JP46__RAW = str
MULTICLK_DIV_SYNC__TYPE = str
LWIR_WINDOW_HEIGHT__RAW = str
MULTICLK_BUF_DLYREF__TYPE = str
GPIO_DRIVE__RAW = str
GPIO_IBUF_LOW_PWR__TYPE = str
......@@ -1060,7 +1142,9 @@ SENS_LENS_BY = int
SENS_LENS_BX = int
NUM_CYCLES_02__TYPE = str
MCNTRL_TILED_STARTADDR = int
LWIR_TELEMETRY_TIME_LAST_MS__RAW = str
TILE_HEIGHT__TYPE = str
MULTICLK_DIV_XCLK2X__RAW = str
MCNTRL_TILED_CHN4_ADDR__TYPE = str
HISPI_NUMLANES__TYPE = str
HISPI_FIFO_START = int
......@@ -1068,10 +1152,12 @@ TILED_STARTX__TYPE = str
FFCLK0_DIFF_TERM__RAW = str
MCNTRL_PS_STATUS_CNTRL__RAW = str
MCONTR_TOP_STATUS_REG_ADDR = int
SENSI2C_STATUS_REG_INC__RAW = str
SENSOR_TIMING_TO = int
VOSPI_SEGM0_OK__TYPE = str
SDCLK_PHASE = float
SLEW_CMDA = str
SENSOR_IMAGE_TYPE0__RAW = str
DLY_DM_ODELAY__RAW = str
CMPRS_STATUS_REG_BASE__RAW = str
MCNTRL_SCANLINE_MODE__TYPE = str
GPIO_N__RAW = str
......@@ -1083,11 +1169,13 @@ CLKFBOUT_MULT_SENSOR = int
HISPI_MMCM2__RAW = str
CMPRS_AFIMUX_EN = int
COLADDR_NUMBER = int
MCNTRL_TILED_STARTADDR__RAW = str
MCNTRL_PS_CMD = int
VOSPI_OUT_EN_SINGL = int
LWIR_TELEMETRY_SREV__TYPE = str
TABLE_FOCUS_INDEX__TYPE = str
CAMSYNC_DELAY = int
BUF_IPCLK2X_SENS2__TYPE = str
MCNTRL_TEST01_CHN1_MODE__RAW = str
SENSI2C_CMD_USE_EOF__TYPE = str
MULTICLK_PHASE_AXIHP__RAW = str
QUADRANTS_PXD_HACT_VACT = int
FFCLK0_IOSTANDARD__RAW = str
......@@ -1101,6 +1189,7 @@ XOR_HIST_BAYER = int
MULTICLK_BUF_XCLK__TYPE = str
MCONTR_TOP_0BIT_ADDR__TYPE = str
CLKFBOUT_PHASE_SENSOR__RAW = str
CMPRS_AFIMUX_REG_ADDR0 = int
MCONTR_SENS_BASE = int
CMPRS_CBIT_RUN__TYPE = str
SENS_LENS_FAT0_OUT = int
......@@ -1113,7 +1202,8 @@ CAMSYNC_EXTERNAL_BIT__RAW = str
HISTOGRAM_WIDTH = int
MCNTRL_SCANLINE_WINDOW_X0Y0__TYPE = str
HISPI_IBUF_LOW_PWR__RAW = str
SENSI2C_TBL_NBRD__TYPE = str
VOSPI_OUT_EN_SINGL__TYPE = str
SENSOR_TIMING_START__TYPE = str
SENSI2C_CMD_ACIVE_SDA = int
MCONTR_PHY_0BIT_ADDR__TYPE = str
PXD_CLK_DIV_BITS__TYPE = str
......@@ -1131,13 +1221,17 @@ LAST_FRAME_BITS__TYPE = str
CLK_MASK__RAW = str
DLY_DM_ODELAY = long
MEMBRIDGE_STATUS_CNTRL__RAW = str
VOSPI_SPI_CLK__TYPE = str
DEBUG_SHIFT_DATA = int
LWIR_DATA_FILE4__TYPE = str
MEMBRIDGE_STATUS_REG = int
CMPRS_CBIT_CMODE_JPEG18__RAW = str
IPCLK2X_PHASE = float
VOSPI_OUT_EN_BITS__RAW = str
CMPRS_CBIT_FOCUS_BITS = int
LOGGER_CONF_SYN__RAW = str
CMPRS_COLOR20 = int
SENSI2C_CMD_USE_EOF__RAW = str
SENSI2C_CMD_TABLE__RAW = str
SENSIO_DELAYS__TYPE = str
ADDRESS_NUMBER__TYPE = str
......@@ -1156,9 +1250,13 @@ HISPI_WAIT_ALL_LANES__RAW = str
MEMBRIDGE_STATUS_REG__TYPE = str
CLKIN_PERIOD__RAW = str
SENS_SYNC_MULT__RAW = str
SENSOR_TIMING_STATUS_REG_BASE = int
SENSOR_HIST_NRST_BITS__RAW = str
SENS_LENS_BY__TYPE = str
NUM_CYCLES_02__RAW = str
CAMSYNC_GPIO_INT_IN = int
MCNTRL_SCANLINE_STATUS_REG_CHN1_ADDR__RAW = str
VOSPI_MCLK_BITS__RAW = str
MCNTRL_TILED_WINDOW_X0Y0 = int
MCONTR_TOP_16BIT_REFRESH_PERIOD__RAW = str
MULT_SAXI_WLOG__TYPE = str
......@@ -1186,22 +1284,26 @@ MCONTR_SENS_BASE__TYPE = str
LOGGER_BIT_HALF_PERIOD = int
CMPRS_CBIT_CMODE_JP4 = int
CAMSYNC_TRIGGERED_BIT = int
VOSPI_SPI_CLK_BITS__RAW = str
LOGGER_PAGE_IMU__TYPE = str
LOGGER_PAGE_GPS__RAW = str
SENS_PHASE_WIDTH__TYPE = str
CMPRS_COLOR18__TYPE = str
CMPRS_HIFREQ_REG_INC__TYPE = str
VOSPI_OUT_EN = int
PXD_CLK_DIV = int
MCNTRL_TILED_STATUS_CNTRL = int
NUM_CYCLES_29__RAW = str
GPIO_SET_STATUS__TYPE = str
SENSIO_STATUS_REG_REL__RAW = str
CMPRS_RAW__RAW = str
FFCLK0_CAPACITANCE__RAW = str
SENSOR12BITS_TDDO1__TYPE = str
CMDFRAMESEQ_ABS = int
CMPRS_MONO8 = int
MULT_SAXI_ADDR__RAW = str
DEBUG_CMD_LATENCY__TYPE = str
CAMSYNC_GPIO_EXT_OUT__TYPE = str
TILED_KEEP_OPEN = int
MCNTRL_SCANLINE_MASK__RAW = str
MULT_SAXI_STATUS_REG__RAW = str
......@@ -1218,15 +1320,14 @@ MEMBRIDGE_CTRL__TYPE = str
TILED_KEEP_OPEN__TYPE = str
CMPRS_CBIT_RUN_RST__TYPE = str
LOGGER_CONF_GPS_BITS__RAW = str
SENSOR12BITS_TDDO__TYPE = str
MULTICLK_DIV_SYNC = int
CLK_STATUS_REG_ADDR = int
CLK_DIV_PHASE__TYPE = str
MULT_SAXI_BSLOG0__RAW = str
PXD_DRIVE__RAW = str
CLKFBOUT_USE_FINE_PS__RAW = str
CMPRS_FRMT_LMARG__RAW = str
CMDFRAMESEQ_IRQ_BIT__RAW = str
GPIO_SET_PINS = int
FRAME_START_ADDRESS__RAW = str
LOGGER_BIT_DURATION = int
FCLK1_PERIOD__TYPE = str
CAMSYNC_MODE__TYPE = str
......@@ -1241,7 +1342,6 @@ LOGGER_CONF_EN_BITS = int
NUM_CYCLES_22__RAW = str
PXD_CAPACITANCE__TYPE = str
CAMSYNC_POST_MAGIC = int
CMDFRAMESEQ_IRQ_BIT__TYPE = str
PXD_IBUF_LOW_PWR__RAW = str
PXD_DRIVE = int
MULT_SAXI_BSLOG2__RAW = str
......@@ -1249,14 +1349,16 @@ CLK_CNTRL__TYPE = str
GPIO_MASK__RAW = str
DFLT_REFRESH_ADDR__TYPE = str
SENS_GAMMA_MODE_REPET__TYPE = str
SENSOR_TIMING_LANE__TYPE = str
CAMSYNC_TRIG_PERIOD__RAW = str
SENS_BANDWIDTH__RAW = str
CMPRS_CBIT_BE16_BITS__TYPE = str
SENS_SS_EN__TYPE = str
MCNTRL_TEST01_STATUS_REG_CHN4_ADDR = int
LOGGER_PERIOD__TYPE = str
WSEL = int
SENS_REFCLK_FREQUENCY__RAW = str
MEMBRIDGE_SIZE64__TYPE = str
LOGGER_STATUS_MASK__TYPE = str
HISPI_IOSTANDARD = str
LOGGER_CONF_IMU__RAW = str
CMPRS_CBIT_CMODE_JP4DC__RAW = str
......@@ -1265,6 +1367,7 @@ MCNTRL_TEST01_CHN3_MODE__RAW = str
MCNTRL_TEST01_CHN1_MODE__TYPE = str
SENS_SYNC_FBITS__TYPE = str
HISPI_UNTUNED_SPLIT = str
CMPRS_AFIMUX_REG_ADDR0__TYPE = str
MCONTR_TOP_0BIT_ADDR_MASK = int
HISPI_IBUF_DELAY_VALUE__TYPE = str
SENSOR12BITS_NGPL = int
......@@ -1274,11 +1377,13 @@ NUM_CYCLES_29__TYPE = str
RTC_SET_SEC__TYPE = str
CAMSYNC_ADDR = int
FFCLK1_CAPACITANCE__RAW = str
VOSPI_PACKET_LAST__RAW = str
RTC_SET_CORR__TYPE = str
PHASE_WIDTH__RAW = str
SLEW_DQ__RAW = str
CMPRS_CBIT_CMODE_JPEG20__RAW = str
CLK_STATUS = int
SENSI2C_STATUS_REG_INC__RAW = str
GPIO_ADDR__RAW = str
MEMBRIDGE_START64__TYPE = str
CMPRS_CBIT_CMODE_JP46 = int
......@@ -1293,9 +1398,13 @@ CMPRS_AFIMUX_WIDTH__TYPE = str
TILE_VSTEP__RAW = str
CMPRS_CBIT_QBANK = int
SENSI2C_TBL_RAH_BITS__TYPE = str
LWIR_WINDOW_WIDTH = int
CMPRS_AFIMUX_WIDTH = int
HISTOGRAM_ADDR_MASK__TYPE = str
VOSPI_PWDN__TYPE = str
HISTOGRAM_RADDR3__TYPE = str
CMPRS_CBIT_CMODE_MONO1__TYPE = str
SENSOR_TIMING_START = int
SENSOR_NUM_HISTOGRAM = int
HIST_SAXI_NRESET__RAW = str
CMPRS_COLOR18 = int
......@@ -1312,7 +1421,6 @@ SENSIO_JTAG__TYPE = str
SENSOR_GROUP_ADDR__RAW = str
LOGGER_MASK__TYPE = str
T_RFC = int
CAMSYNC_TRIG_DELAY3__RAW = str
FFCLK1_IOSTANDARD__RAW = str
CMD_DONE_BIT__TYPE = str
SENSOR_DATA_WIDTH__TYPE = str
......@@ -1327,6 +1435,7 @@ SENS_SS_EN__RAW = str
SENS_LENS_ADDR_MASK = int
SENSOR_CTRL_RADDR__TYPE = str
CMPRS_CBIT_FRAMES_SINGLE__RAW = str
VOSPI_PACKETS_PER_LINE__RAW = str
CLKOUT_DIV_PCLK = int
MCNTRL_SCANLINE_MASK__TYPE = str
MCONTR_PHY_0BIT_DLY_SET__TYPE = str
......@@ -1339,12 +1448,17 @@ MCNTRL_TILED_FRAME_SIZE__RAW = str
MULT_SAXI_HALF_BRAM__RAW = str
SIMUL_AXI_READ_WIDTH__TYPE = str
DFLT_DQS_TRI_ON_PATTERN__RAW = str
LWIR_MS_PERIOD__RAW = str
SLEW_DQ = str
CAMSYNC_GPIO_INT_OUT__TYPE = str
SENS_GAMMA_MODE_REPET__RAW = str
SENSOR_DATA_WIDTH = int
MCONTR_PHY_16BIT_PATTERNS_TRI__TYPE = str
SENSOR_TIMING_LANE__RAW = str
SLEW_DQS__TYPE = str
LWIR_TELEMETRY_AGC_ROI_RIGHT = int
VOSPI_SEGMENT_LAST__RAW = str
SENSIO_ADDR_MASK = int
TILE_HEIGHT__RAW = str
SCANLINE_STARTY = int
SCANLINE_STARTX = int
SIMULATE_CMPRS_CMODE1__RAW = str
......@@ -1356,18 +1470,21 @@ CMPRS_CBIT_RUN_RST = int
IPCLK2X_PHASE__RAW = str
SENS_SYNC_MINBITS__TYPE = str
SENSI2C_IOSTANDARD__TYPE = str
SENSOR_TIMING_STATUS_REG_BASE__RAW = str
REFCLK_FREQUENCY__TYPE = str
CLKOUT_DIV_PCLK2X__TYPE = str
MEMBRIDGE_CTRL = int
SENSOR_IMAGE_TYPE3__TYPE = str
HISTOGRAM_LEFT = int
MULT_SAXI_HALF_BRAM__TYPE = str
VOSPI_EN_BITS__RAW = str
MCONTR_PHY_STATUS_CNTRL = int
SENSOR_GROUP_ADDR = int
NUM_CYCLES_14 = int
CMPRS_CBIT_RUN_STANDALONE__TYPE = str
TILED_STARTX__RAW = str
BUF_IPCLK_SENS1__RAW = str
WRITE_BLOCK_OFFSET__TYPE = str
VOSPI_NO_INVALID__TYPE = str
SENS_SYNC_LATE_DFLT__TYPE = str
CAMSYNC_MODE = int
CLK_MASK__TYPE = str
......@@ -1378,12 +1495,17 @@ MULT_SAXI_HALF_BRAM_IN__TYPE = str
DEBUG_SET_STATUS = int
MCNTRL_SCANLINE_WINDOW_X0Y0 = int
STATUS_ADDR = int
LWIR_DATA_FILE1__TYPE = str
MCNTRL_TILED_STARTADDR__RAW = str
WINDOW_X0__RAW = str
VOSPI_EN__TYPE = str
LWIR_FRAME_PERIOD__RAW = str
CMDFRAMESEQ_IRQ_BIT = int
CONTROL_ADDR__TYPE = str
CLKFBOUT_MULT_PCLK = int
CMPRS_GROUP_ADDR = int
WINDOW_Y0 = int
LOGGER_CONF_GPS_BITS__TYPE = str
CAMSYNC_GPIO_EXT_IN__TYPE = str
SENS_LENS_AX_MASK__TYPE = str
HISTOGRAM_RADDR0 = int
HISTOGRAM_RADDR1 = int
......@@ -1392,6 +1514,8 @@ HISTOGRAM_RADDR3 = int
MCNTRL_SCANLINE_STATUS_REG_CHN3_ADDR__RAW = str
HISTOGRAM_LEFT__TYPE = str
SENS_LENS_AY_MASK__TYPE = str
VOSPI_PACKET_TTT__RAW = str
VOSPI_MRST__RAW = str
SENS_CTRL_IGNORE_EMBED__RAW = str
READ_BLOCK_OFFSET__TYPE = str
CONTROL_ADDR_MASK__RAW = str
......@@ -1404,6 +1528,7 @@ SS_MOD_PERIOD__RAW = str
CMPRS_NUM_AFI_CHN__RAW = str
SENSOR_IMAGE_TYPE3 = str
MULTICLK_DIV_AXIHP__TYPE = str
LWIR_FRAME_PERIOD__TYPE = str
HISPI_DELAY_CLK2__TYPE = str
MULT_SAXI_ADV_RD = int
WSEL__RAW = str
......@@ -1415,7 +1540,7 @@ BUF_IPCLK_SENS2 = str
BUF_IPCLK_SENS3 = str
BUF_IPCLK_SENS0 = str
BUF_IPCLK_SENS1 = str
SENSI2C_TBL_NABRD = int
MCNTRL_TEST01_CHN1_MODE__RAW = str
SLEW_CMDA__TYPE = str
MULT_SAXI_CNTRL_MODE__TYPE = str
NUM_CYCLES_19__TYPE = str
......@@ -1441,11 +1566,13 @@ DEBUG_MASK__RAW = str
NUM_INTERRUPTS__RAW = str
MCNTRL_TEST01_CHN2_MODE__TYPE = str
MEMBRIDGE_ADDR__RAW = str
LWIR_GPIO_IN = int
CMPRS_COLOR_SATURATION__RAW = str
AXI_RD_ADDR_BITS = int
MULTICLK_IN_PERIOD__TYPE = str
LD_DLY_LANE1_ODELAY__TYPE = str
CMPRS_STATUS_CNTRL__RAW = str
VOSPI_GPIO__TYPE = str
MCONTR_LINTILE_SKIP_LATE = int
SENS_CTRL_ARO = int
LOGGER_CONF_DBG_BITS__TYPE = str
......@@ -1482,12 +1609,14 @@ SIMULATE_CMPRS_CMODE3__TYPE = str
DFLT_DQM_PATTERN = int
HISPI_NUMLANES = int
SENSI2C_CMD_RUN = int
CMPRS_CBIT_BE16_BITS = int
AXI_WRDATA_LATENCY__RAW = str
CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2__TYPE = str
LWIR_FRAME_PERIOD = int
NUM_CYCLES_04 = int
SENS_LENS_C__TYPE = str
MCONTR_PHY_16BIT_EXTRA__TYPE = str
CAMSYNC_TRIGGERED_BIT__RAW = str
VOSPI_NO_INVALID = int
SENSI2C_CMD_SOFT_SCL__RAW = str
CMPRS_CSAT_CR__TYPE = str
SENS_LENS_POST_SCALE__RAW = str
......@@ -1505,6 +1634,7 @@ MCONTR_PHY_0BIT_CKE_EN = int
CMPRS_AFIMUX_STATUS_CNTRL = int
CMPRS_CBIT_FRAMES__RAW = str
SLEW_DQS = str
VOSPI_MOSI__TYPE = str
MCONTR_WR_MASK = int
MCONTR_LINTILE_ABORT_LATE = int
CMPRS_FRMT_MBCM1 = int
......@@ -1530,19 +1660,25 @@ GPIO_PORTEN__TYPE = str
CMDSEQMUX_ADDR__RAW = str
DLY_DM_ODELAY__TYPE = str
SENSIO_CTRL = int
LWIR_TELEMETRY_TEMP_COUTS = int
MULT_SAXI_MASK__TYPE = str
SENSI2C_CMD_ACIVE_SDA__TYPE = str
SCANLINE_STARTY__RAW = str
GPIO_ADDR = int
SENS_SYNC_MINBITS__RAW = str
SENS_SS_MOD_PERIOD__RAW = str
SENSOR_TIMING_TO__RAW = str
COLADDR_NUMBER__TYPE = str
SENSOR_TIMING_FROM = int
CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2__TYPE = str
CAMSYNC_CHN_EN_BIT__RAW = str
LOGGER_PAGE_MSG = int
SENS_HIGH_PERFORMANCE_MODE = str
WINDOW_X0 = int
INITIALIZE_OFFSET__TYPE = str
LOGGER_CONF_IMU_BITS__TYPE = str
LWIR_TELEMETRY_AGC_ROI_RIGHT__RAW = str
MCONTR_PHY_16BIT_PATTERNS_TRI__TYPE = str
IDELAY_VALUE__TYPE = str
SENSOR_IMAGE_TYPE2__RAW = str
CMPRS_CBIT_CMODE_JP4DC__TYPE = str
......@@ -1566,6 +1702,8 @@ SENSIO_CTRL__RAW = str
HISTOGRAM_WIDTH__TYPE = str
MCNTRL_TILED_TILE_WHS = int
MCONTR_LINTILE_COPY_FRAME__TYPE = str
VOSPI_GPIO = int
CMPRS_CBIT_BE16__TYPE = str
NUM_CYCLES_03__RAW = str
MULT_SAXI_HALF_BRAM = int
DLY_LANE1_DQS_WLV_IDELAY = long
......@@ -1587,10 +1725,14 @@ CMPRS_CBIT_CMODE_JP4DIFFHDR = int
TABLE_CORING_INDEX__RAW = str
MCONTR_LINTILE_ABORT_LATE__TYPE = str
SENSI2C_CMD_RESET__TYPE = str
LWIR_DATA_FILE4__RAW = str
MCONTR_ARBIT_ADDR__TYPE = str
CAMSYNC_TRIG_DELAY1__RAW = str
LWIR_TELEMETRY_TEMP_LAST_KELVIN = int
AXI_TASK_HOLD = float
ADDRESS_NUMBER = int
CAMSYNC_GPIO_EXT_OUT = int
SENSOR_TIMING_FROM__RAW = str
SENS_SYNC_LATE__TYPE = str
MCNTRL_TILED_STATUS_REG_CHN4_ADDR__TYPE = str
GPIO_STATUS_REG_ADDR__TYPE = str
......@@ -1598,7 +1740,7 @@ HIST_SAXI_AWCACHE = int
SENSI2C_CMD_RUN_PBITS = int
CMPRS_MONO8__RAW = str
CMPRS_AFIMUX_REG_ADDR1 = int
CMPRS_AFIMUX_REG_ADDR0 = int
SENS_LENS_FAT0_OUT__TYPE = str
SENS_BANDWIDTH__TYPE = str
LD_DLY_LANE0_IDELAY__TYPE = str
CLKFBOUT_PHASE__RAW = str
......@@ -1606,7 +1748,8 @@ NUM_CYCLES_08__RAW = str
GPIO_IBUF_LOW_PWR__RAW = str
HISTOGRAM_RADDR3__RAW = str
NUM_XFER_BITS__TYPE = str
HISTOGRAM_ADDR_MASK__RAW = str
LWIR_GPIO_IN__RAW = str
TABLE_QUANTIZATION_INDEX__TYPE = str
BUF_IPCLK2X_SENS2__RAW = str
MCNTRL_TEST01_CHN4_MODE__TYPE = str
MULT_SAXI_ADDR__TYPE = str
......@@ -1619,8 +1762,10 @@ STATUS_ADDR_MASK__RAW = str
CMPRS_AFIMUX_MODE = int
DLY_CMDA__RAW = str
BUFFER_DEPTH32__RAW = str
LWIR_TELEMETRY_REV__RAW = str
DIVCLK_DIVIDE__RAW = str
MCNTRL_PS_CMD__RAW = str
VOSPI_PACKET_WORDS__RAW = str
CAMSYNC_ADDR__RAW = str
MCONTR_BUF3_WR_ADDR = int
SENS_NUM_SUBCHN__TYPE = str
......@@ -1631,11 +1776,13 @@ HISPI_MMCM2 = str
MULT_SAXI_CNTRL_ADDR__TYPE = str
HISPI_KEEP_IRST__TYPE = str
MULT_SAXI_STATUS_REG__TYPE = str
CAMSYNC_GPIO_EXT_IN = int
MEMCLK_IOSTANDARD__TYPE = str
NUM_CYCLES_27__TYPE = str
SENSI2C_TBL_NBRD = int
CMPRS_CBIT_BAYER_BITS = int
PXD_SLEW__RAW = str
CAMSYNC_GPIO_INT_OUT = int
MULT_SAXI_STATUS_REG = int
CLKIN_PERIOD_SENSOR__TYPE = str
QUADRANTS_PXD_HACT_VACT__TYPE = str
......@@ -1664,15 +1811,18 @@ MULTICLK_DIV_DLYREF = int
TABLE_HUFFMAN_INDEX__RAW = str
LD_DLY_PHASE__RAW = str
TEST_INITIAL_BURST__RAW = str
SENSOR_TIMING_FROM__TYPE = str
CMPRS_CBIT_FRAMES_BITS__TYPE = str
CMPRS_FRMT_MBCM1__RAW = str
FFCLK0_DIFF_TERM = str
DIVCLK_DIVIDE_PCLK__TYPE = str
HISPI_FIFO_START__TYPE = str
SENSOR_HIST_EN_BITS = int
DFLT_DQS_TRI_OFF_PATTERN__RAW = str
CMPRS_FRMT_MBRM1 = int
CAMSYNC_SNDEN_BIT__RAW = str
MCONTR_ARBIT_ADDR_MASK__RAW = str
VOSPI_SEGMENT_LAST = int
WINDOW_WIDTH__TYPE = str
MCONTR_CMPRS_STATUS_INC__TYPE = str
DFLT_INV_CLK_DIV = int
......@@ -1685,30 +1835,33 @@ TEST01_START_FRAME__RAW = str
CMDFRAMESEQ_ABS__RAW = str
FRAME_WIDTH_ROUND_BITS__TYPE = str
BUF_IPCLK2X_SENS0__RAW = str
VOSPI_SPI_CLK_BITS__TYPE = str
MCONTR_BUF4_WR_ADDR__RAW = str
DFLT_DQM_PATTERN__RAW = str
CMPRS_CSAT_CB__TYPE = str
T_REFI__TYPE = str
MCONTR_CMD_WR_ADDR__TYPE = str
RTC_MASK = int
SENSI2C_CMD_SOFT_SCL__TYPE = str
CLKFBOUT_MULT_SENSOR__RAW = str
CMPRS_CSAT_CR_BITS = int
MCONTR_LINTILE_RST_FRAME__RAW = str
LOGGER_CONFIG__TYPE = str
MCNTRL_SCANLINE_DLY_DEFAULT = int
LWIR_TELEMETRY_AGC_ROI_TOP = int
TEST01_NEXT_PAGE__RAW = str
HIST_SAXI_MODE_ADDR_MASK__RAW = str
FFCLK1_IBUF_LOW_PWR__TYPE = str
LWIR_TELEMETRY_AGC_ROI_TOP__RAW = str
SENSOR12BITS_NVLO__TYPE = str
MCONTR_LINTILE_EXTRAPG__TYPE = str
CAMSYNC_SNDEN_BIT__TYPE = str
SENSOR_16BIT_BIT_SET__TYPE = str
NUM_CYCLES_06__TYPE = str
SCANLINE_STARTX__RAW = str
SLEW_DQS__RAW = str
FRAME_HEIGHT_BITS__TYPE = str
CMPRS_CBIT_BAYER__TYPE = str
MCONTR_PHY_0BIT_ADDR = int
MCONTR_PHY_16BIT_EXTRA__RAW = str
AXI_WRADDR_LATENCY = int
MCNTRL_TEST01_STATUS_REG_CHN2_ADDR__TYPE = str
MAX_TILE_HEIGHT__TYPE = str
MCONTR_TOP_16BIT_CHN_EN__RAW = str
......@@ -1733,30 +1886,33 @@ SENS_JTAG_TDI__TYPE = str
SENS_GAMMA_MODE_PAGE = int
MCNTRL_TILED_STATUS_REG_CHN4_ADDR__RAW = str
MCONTR_TOP_16BIT_STATUS_CNTRL__RAW = str
LWIR_TELEMETRY__RAW = str
MCONTR_PHY_0BIT_ADDR_MASK__RAW = str
CAMSYNC_MASTER_BIT = int
DLY_LD_MASK__RAW = str
CMDFRAMESEQ_RST_BIT__TYPE = str
LD_DLY_LANE1_ODELAY = int
CMPRS_AFIMUX_MASK__RAW = str
MCNTRL_TILED_WINDOW_X0Y0__RAW = str
NUM_CYCLES_28__RAW = str
LWIR_TELEMETRY_STATUS__TYPE = str
SENS_GAMMA_MODE_PAGE__TYPE = str
CMPRS_COLOR_SATURATION__TYPE = str
SENSI2C_CMD_SOFT_SDA = int
SENSI2C_CMD_TAND = int
CMPRS_AFIMUX_SA_LEN = int
SENS_CTRL_QUADRANTS_EN__TYPE = str
SENSOR_16BIT_BIT_SET__RAW = str
MCNTRL_PS_EN_RST__RAW = str
HISPI_IFD_DELAY_VALUE__TYPE = str
CMPRS_CBIT_BAYER_BITS__RAW = str
MULTICLK_BUF_AXIHP__TYPE = str
GPIO_IOSTANDARD__RAW = str
MEMBRIDGE_MASK__RAW = str
CAMSYNC_GPIO_EXT_IN__RAW = str
CMPRS_CBIT_CMODE_JP4DIFFDIV2 = int
RTC_SET_CORR__RAW = str
SENSI2C_TBL_RAH_BITS__RAW = str
TILED_STARTY__TYPE = str
HIGH_PERFORMANCE_MODE__RAW = str
SENSOR_TIMING_BITS__RAW = str
DFLT_DQM_PATTERN__TYPE = str
STATUS_ADDR__TYPE = str
MCONTR_PHY_0BIT_CMDA_EN = int
......@@ -1772,6 +1928,9 @@ DFLT_DQ_TRI_OFF_PATTERN__RAW = str
CMPRS_CBIT_DCSUB = int
CMPRS_CBIT_CMODE_JP4DIFF = int
MULT_SAXI_CNTRL_MASK__TYPE = str
LWIR_DATA_FILE3__TYPE = str
LWIR_TELEMETRY_TEMP_KELVIN = int
VOSPI_GPIO__RAW = str
INITIALIZE_OFFSET__RAW = str
CMD_DONE_BIT__RAW = str
DEBUG_STATUS_REG_ADDR__RAW = str
......@@ -1780,9 +1939,10 @@ SENSOR12BITS_TDDO__RAW = str
CAMSYNC_TRIG_DST__RAW = str
MCONTR_TOP_16BIT_REFRESH_PERIOD__TYPE = str
CAMSYNC_TRIG_DELAY3__TYPE = str
FRAME_START_ADDRESS__RAW = str
CMDFRAMESEQ_IRQ_BIT__RAW = str
IPCLK_PHASE = float
SENSI2C_CTRL_RADDR = int
SENSOR_TIMING_TO__TYPE = str
HIST_SAXI_MODE_ADDR_REL__RAW = str
AXI_WRDATA_LATENCY = int
MCNTRL_SCANLINE_START_DELAY = int
......@@ -1824,6 +1984,7 @@ DEBUG_MASK__TYPE = str
DFLT_DQ_TRI_ON_PATTERN = int
SENSI2C_CMD_ACIVE = int
CMPRS_FRMT_LMARG__TYPE = str
LWIR_TELEMETRY_TIME_LAST_MS__TYPE = str
SENSI2C_TBL_NBRD_BITS = int
SENSIO_JTAG = int
DLY_LD = int
......@@ -1842,9 +2003,12 @@ MULTICLK_MULT__RAW = str
MCONTR_PHY_16BIT_ADDR__RAW = str
SENS_CTRL_MRST__RAW = str
SENS_GAMMA_HEIGHT2__TYPE = str
VOSPI_GPIO_BITS__TYPE = str
IPCLK2X_PHASE__TYPE = str
SENSOR_HIST_BITS_SET = int
MCNTRL_SCANLINE_CHN1_ADDR = int
VOSPI_PWDN_BITS__TYPE = str
VOSPI_MCLK__TYPE = str
MULT_SAXI_HALF_BRAM_IN = int
CMDFRAMESEQ_ADDR_INC__RAW = str
IPCLK_PHASE__TYPE = str
......@@ -1860,12 +2024,14 @@ RTC_SET_CORR = int
CMPRS_CBIT_FOCUS__TYPE = str
CMPRS_NUM_AFI_CHN__TYPE = str
CMPRS_GROUP_ADDR__RAW = str
CAMSYNC_GPIO_INT_IN__TYPE = str
SENS_LENS_AX__RAW = str
CMPRS_JP4DIFF__RAW = str
SENS_SS_MODE__RAW = str
SENSOR_16BIT_BIT_SET__TYPE = str
CAMSYNC_SNDEN_BIT__TYPE = str
DEBUG_CMD_LATENCY__RAW = str
CMPRS_CBIT_CMODE__TYPE = str
CAMSYNC_GPIO_INT_OUT__RAW = str
LOGGER_STATUS_MASK = int
MULTICLK_PHASE_XCLK__TYPE = str
DFLT_DQ_TRI_ON_PATTERN__RAW = str
......@@ -1880,10 +2046,12 @@ LOGGER_STATUS_MASK__RAW = str
RTC_ADDR__RAW = str
CMPRS_CBIT_FOCUS_BITS__RAW = str
CMDFRAMESEQ_RUN_BIT__TYPE = str
VOSPI_GPIO_BITS__RAW = str
MCNTRL_TILED_STATUS_CNTRL__TYPE = str
SENSI2C_CTRL__RAW = str
MCONTR_PHY_16BIT_WBUF_DELAY__RAW = str
SENS_CTRL_GP0__RAW = str
SENSI2C_CMD_USE_EOF = int
MCONTR_BUF2_WR_ADDR__RAW = str
MULT_SAXI_BSLOG0 = int
MULT_SAXI_BSLOG1 = int
......@@ -1892,6 +2060,7 @@ MULT_SAXI_BSLOG3 = int
MCONTR_BUF4_RD_ADDR__RAW = str
SENS_SS_MOD_PERIOD = int
DQSTRI_FIRST = int
VOSPI_HACT_TO_HACT_EOF = int
SENS_REF_JITTER2__RAW = str
SCANLINE_EXTRA_PAGES__RAW = str
CMDSEQMUX_STATUS__RAW = str
......@@ -1899,6 +2068,7 @@ MCONTR_PHY_0BIT_SDRST_ACT__RAW = str
SENSOR_IMAGE_TYPE0__TYPE = str
CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2__RAW = str
DIVCLK_DIVIDE_PCLK = int
SENSOR_TIMING_STATUS_REG_INC__TYPE = str
MCNTRL_PS_MASK = int
SENSI2C_STATUS__TYPE = str
CMPRS_CSAT_CB_BITS = int
......@@ -1922,9 +2092,11 @@ CMDFRAMESEQ_RST_BIT = int
CAMSYNC_SNDEN_BIT = int
DQSTRI_FIRST__RAW = str
SENSI2C_CTRL_MASK__TYPE = str
LWIR_TELEMETRY_SREV = int
SENS_LENS_SCALES__TYPE = str
SENS_LENS_COEFF__TYPE = str
LOGGER_STATUS__RAW = str
LWIR_TELEMETRY_TEMP_LAST_KELVIN__RAW = str
SENS_JTAG_TMS__RAW = str
FRAME_WIDTH_ROUND_BITS__RAW = str
FFCLK0_IBUF_LOW_PWR__RAW = str
......@@ -1944,9 +2116,10 @@ SENS_JTAG_TCK__TYPE = str
MCNTRL_TILED_FRAME_SIZE__TYPE = str
CMPRS_AFIMUX_REG_ADDR1__RAW = str
WOI_HEIGHT__RAW = str
VOSPI_MOSI = int
SENS_LENS_COEFF = int
MULTICLK_PHASE_XCLK__RAW = str
LOGGER_BIT_DURATION__RAW = str
SENSOR_CHN_EN_BIT_SET__TYPE = str
MCNTRL_SCANLINE_DLY_WIDTH__TYPE = str
MCONTR_WR_MASK__TYPE = str
SENS_LENS_C__RAW = str
......@@ -1961,6 +2134,7 @@ NUM_CYCLES_26__RAW = str
DEFAULT_STATUS_MODE__RAW = str
MCONTR_LINTILE_KEEP_OPEN__RAW = str
MCONTR_PHY_16BIT_ADDR__TYPE = str
VOSPI_PACKET_TTT__TYPE = str
CMDFRAMESEQ_RST_BIT__RAW = str
SENSIO_RADDR__RAW = str
DFLT_CHN_EN__TYPE = str
......@@ -1972,18 +2146,22 @@ MCONTR_PHY_16BIT_PATTERNS_TRI__RAW = str
CMDSEQMUX_MASK = int
MCNTRL_SCANLINE_PENDING_CNTR_BITS__RAW = str
MEMCLK_CAPACITANCE__RAW = str
VOSPI_PWDN_BITS__RAW = str
DQTRI_FIRST = int
DLY_LANE0_DQS_WLV_IDELAY__TYPE = str
CONTROL_RBACK_DEPTH = int
CAMSYNC_TRIG_DELAY0 = int
CAMSYNC_TRIG_DELAY1 = int
MCNTRL_SCANLINE_STATUS_CNTRL__RAW = str
CAMSYNC_TRIG_DELAY2 = int
CAMSYNC_TRIG_DELAY3 = int
SIMUL_AXI_READ_WIDTH__RAW = str
MCONTR_SENS_STATUS_INC = int
CAMSYNC_GPIO_INT_IN__RAW = str
CMPRS_CBIT_BE16__RAW = str
CAMSYNC_TRIGGERED_BIT__TYPE = str
SENS_GAMMA_MODE_TRIG__TYPE = str
DLY_LANE0_DQS_WLV_IDELAY__RAW = str
CMPRS_FRMT_LMARG_BITS__RAW = str
LWIR_TELEMETRY_TIME_LAST_MS = int
MEMBRIDGE_ADDR__TYPE = str
LAST_FRAME_BITS = int
SENSOR_FIFO_2DEPTH__RAW = str
......@@ -1997,21 +2175,24 @@ CMPRS_CBIT_CMODE_MONO4__RAW = str
MULT_SAXI_MASK = int
SENS_LENS_BX_MASK__TYPE = str
MCNTRL_SCANLINE_WINDOW_STARTXY__TYPE = str
CMDFRAMESEQ_DEPTH__TYPE = str
VOSPI_FAKE_OUT = int
LWIR_TELEMETRY_VIDEO_FORMAT__TYPE = str
DLY_LANE0_IDELAY__RAW = str
TABLE_CORING_INDEX__TYPE = str
HISPI_UNTUNED_SPLIT__RAW = str
HISTOGRAM_RADDR1__RAW = str
SENSI2C_CMD_TAND__TYPE = str
MCONTR_LINTILE_EXTRAPG_BITS__RAW = str
HISTOGRAM_HEIGHT__RAW = str
SENSOR_TIMING_BITS = int
MCNTRL_SCANLINE_MODE__RAW = str
LOGGER_BIT_HALF_PERIOD__TYPE = str
VOSPI_OUT_EN_SINGL__RAW = str
FRAME_START_ADDRESS_INC__RAW = str
MCONTR_BUF3_RD_ADDR__RAW = str
SENSOR12BITS_TDDO__TYPE = str
LWIR_TELEMETRY_AGC_ROI_LEFT__TYPE = str
CLKIN_PERIOD = int
RSEL__TYPE = str
CMDFRAMESEQ_ADDR_INC__TYPE = str
HISPI_UNTUNED_SPLIT__RAW = str
LOGGER_CONF_GPS_BITS = int
HISPI_FIFO_DEPTH = int
CLKFBOUT_PHASE = float
......@@ -2019,6 +2200,7 @@ SENS_GAMMA_ADDR_DATA = int
HISPI_WAIT_ALL_LANES = int
MULT_SAXI_CNTRL_MODE__RAW = str
SENS_GAMMA_ADDR_DATA__TYPE = str
VOSPI_OUT_EN__TYPE = str
CAMSYNC_DELAY__TYPE = str
DFLT_REFRESH_PERIOD__RAW = str
SENS_REF_JITTER1__TYPE = str
......@@ -2031,7 +2213,7 @@ MCONTR_PHY_STATUS_CNTRL__RAW = str
DLY_LANE0_DQS_WLV_IDELAY = long
MCNTRL_SCANLINE_STATUS_CNTRL = int
CMDSEQMUX_MASK__TYPE = str
TILED_STARTY__RAW = str
SENSI2C_CMD_RESET = int
SENSI2C_TBL_NABRD__TYPE = str
NUM_CYCLES_01__RAW = str
WINDOW_HEIGHT__RAW = str
......@@ -2057,6 +2239,7 @@ SENS_REF_JITTER2__TYPE = str
FFCLK0_IBUF_LOW_PWR = str
DFLT_DQ_TRI_ON_PATTERN__TYPE = str
FRAME_WIDTH_ROUND_BITS = int
VOSPI_MCLK_BITS__TYPE = str
LD_DLY_LANE1_IDELAY__TYPE = str
CMPRS_AFIMUX_MODE__TYPE = str
DQTRI_FIRST__TYPE = str
......@@ -2085,6 +2268,7 @@ BUF_CLK1X_PCLK2X__RAW = str
MULT_SAXI_POINTERS_REG = int
MCONTR_TOP_0BIT_REFRESH_EN__RAW = str
SENSI2C_TBL_RAH = int
SENS_LENS_FAT0_OUT__RAW = str
SENSI2C_ADDR_MASK__RAW = str
SENS_HIGH_PERFORMANCE_MODE__TYPE = str
TEST01_SUSPEND__TYPE = str
......@@ -2100,6 +2284,7 @@ BUF_IPCLK2X_SENS3__RAW = str
MCNTRL_SCANLINE_CHN1_ADDR__RAW = str
MEMBRIDGE_LEN64 = int
HISPI_MMCM2__TYPE = str
VOSPI_FAKE_OUT__RAW = str
SENSOR_NUM_HISTOGRAM__TYPE = str
HIST_SAXI_EN = int
RTC_SET_SEC = int
......@@ -2119,7 +2304,8 @@ DLY_DQ_ODELAY__RAW = str
MCNTRL_TILED_PENDING_CNTR_BITS__RAW = str
CMPRS_CORING_BITS = int
CMDFRAMESEQ_MASK__TYPE = str
SENS_JTAG_TMS__TYPE = str
FFCLK1_IOSTANDARD = str
CMPRS_RAW = int
CLK_PHASE__RAW = str
MCONTR_PHY_0BIT_DLY_RST = int
GPIO_MASK__TYPE = str
......@@ -2128,9 +2314,10 @@ TILED_STARTX = int
MEMBRIDGE_MASK__TYPE = str
SENS_GAMMA_MODE_EN = int
MCONTR_BUF3_RD_ADDR = int
HISTOGRAM_RADDR_INC = int
NUM_CYCLES_28__TYPE = str
NUM_CYCLES_31__TYPE = str
HISPI_CAPACITANCE__RAW = str
CMPRS_CBIT_BE16_BITS__RAW = str
CMPRS_CBIT_FRAMES_SINGLE__TYPE = str
HISPI_DIFF_TERM__RAW = str
BUF_IPCLK_SENS2__TYPE = str
......@@ -2142,17 +2329,20 @@ CMPRS_JP4 = int
CAMSYNC_CHN_EN_BIT = int
SENSIO_STATUS_REG_REL__TYPE = str
MULTICLK_BUF_XCLK = str
VOSPI_MRST__TYPE = str
HISTOGRAM_START_PAGE__TYPE = str
MCNTRL_SCANLINE_MODE = int
DLY_LANE0_IDELAY = long
MCNTRL_PS_CMD = int
VOSPI_SEGMENT_FIRST__RAW = str
DEBUG_SHIFT_DATA__TYPE = str
MCNTRL_SCANLINE_CHN3_ADDR__TYPE = str
STATUS_2LSB_SHFT__RAW = str
VOSPI_PACKET_TTT = int
CLK_DIV_PHASE__RAW = str
STATUS_MSB_RSHFT__RAW = str
SLEW_CMDA__RAW = str
HISPI_MMCM0__RAW = str
VOSPI_PWDN_BITS = int
MCONTR_PHY_16BIT_PATTERNS_TRI = int
MCONTR_TOP_STATUS_REG_ADDR__RAW = str
DFLT_DQS_TRI_ON_PATTERN = int
......@@ -2169,11 +2359,15 @@ LOGGER_CONF_IMU__TYPE = str
DEBUG_READ_REG_ADDR__RAW = str
SENS_LENS_AY__RAW = str
SS_EN = str
LWIR_TELEMETRY_AGC_ROI_LEFT__RAW = str
SENSI2C_CMD_TAND__RAW = str
WINDOW_HEIGHT__TYPE = str
SENSOR_IMAGE_TYPE2__TYPE = str
IBUF_LOW_PWR__TYPE = str
VOSPI_PWDN = int
FFCLK1_IBUF_LOW_PWR__TYPE = str
CLK_DIV_PHASE = float
VOSPI_MRST = int
MCNTRL_TEST01_CHN4_STATUS_CNTRL__RAW = str
MCONTR_PHY_16BIT_ADDR_MASK__TYPE = str
SENS_CTRL_ARO__RAW = str
......@@ -2183,8 +2377,10 @@ MCONTR_PHY_0BIT_DLY_SET__RAW = str
NUM_CYCLES_11__RAW = str
SENS_GAMMA_MODE_REPET_SET__RAW = str
SENSI2C_DRIVE__RAW = str
LWIR_WINDOW_HEIGHT = int
SENSOR_HIST_BITS_SET__TYPE = str
CMPRS_CBIT_CMODE_MONO1__TYPE = str
HISPI_MMCM1 = str
LWIR_TELEMETRY_AGC_HIGH__TYPE = str
SENS_LENS_C = int
SENSOR_CTRL_ADDR_MASK__RAW = str
DFLT_CHN_EN__RAW = str
......@@ -2192,11 +2388,15 @@ NUM_CYCLES_LOW_BIT = int
READ_BLOCK_OFFSET = int
RSEL__RAW = str
GPIO_DRIVE__TYPE = str
LWIR_FRAME_DELAY__RAW = str
VOSPI_SEGM0_OK_BITS__TYPE = str
SDCLK_PHASE__TYPE = str
NUM_CYCLES_31__RAW = str
LWIR_TELEMETRY_REV__TYPE = str
SENSI2C_IBUF_LOW_PWR__TYPE = str
SENS_LENS_POST_SCALE_MASK__TYPE = str
SCANLINE_STARTY__TYPE = str
VOSPI_PACKET_WORDS__TYPE = str
SENS_LENS_SCALES_MASK = int
LOGGER_PAGE_MSG__TYPE = str
CAMSYNC_MASK__RAW = str
......@@ -2208,14 +2408,17 @@ CMPRS_BASE_INC__TYPE = str
SENSI2C_CMD_ACIVE__TYPE = str
NUM_FRAME_BITS__TYPE = str
CLKFBOUT_MULT_SENSOR__TYPE = str
MCONTR_LINTILE_BYTE32 = int
SENSI2C_TBL_SA = int
SENSI2C_CTRL_MASK__RAW = str
SENSI2C_TBL_NABRD = int
CLK_CNTRL = int
SENSI2C_TBL_NABRD__RAW = str
MULTICLK_PHASE_XCLK = float
LOGGER_ADDR__TYPE = str
NUM_CYCLES_15__TYPE = str
MCNTRL_TILED_MODE__RAW = str
SENSOR_TIMING_START__RAW = str
NUM_CYCLES_23__TYPE = str
MCNTRL_TILED_MODE__TYPE = str
MULTICLK_IN_PERIOD = int
......@@ -2238,15 +2441,16 @@ SENSOR_HIST_EN_BITS__RAW = str
MULT_SAXI_ADV_WR__TYPE = str
CMPRS_AFIMUX_STATUS_CNTRL__RAW = str
FRAME_FULL_WIDTH = int
VOSPI_SOF_TO_HACT__TYPE = str
CMPRS_AFIMUX_REG_ADDR0__RAW = str
GPIO_SET_PINS = int
CMPRS_FRMT_LMARG__RAW = str
NUM_CYCLES_22__TYPE = str
DLY_PHASE__RAW = str
MCONTR_SENS_INC__RAW = str
MULT_SAXI_WLOG__RAW = str
TILE_WIDTH__RAW = str
CMPRS_FORMAT__RAW = str
RTC_MASK = int
LWIR_TELEMETRY_TEMP_COUTS__RAW = str
CLKIN_PERIOD_SENSOR = float
SENS_GAMMA_CTRL__TYPE = str
HIST_CONFIRM_WRITE__RAW = str
......@@ -2264,15 +2468,20 @@ SENS_GAMMA_BUFFER__TYPE = str
SLEW_DQ__TYPE = str
MCONTR_BUF4_RD_ADDR = int
MCNTRL_PS_MASK__TYPE = str
SENSOR_TIMING_STATUS_REG_BASE__TYPE = str
LWIR_MS_PERIOD__TYPE = str
DIVCLK_DIVIDE_PCLK__RAW = str
LWIR_TELEMETRY_VIDEO_FORMAT__RAW = str
HISPI_DELAY_CLK3__TYPE = str
MCONTR_LINTILE_BYTE32__TYPE = str
VOSPI_HACT_TO_HACT_EOF__TYPE = str
CMPRS_TABLES__RAW = str
SENS_GAMMA_MODE_EN__TYPE = str
FRAME_START_ADDRESS__TYPE = str
CMDFRAMESEQ_IRQ_BIT__TYPE = str
CLK_MASK = int
MCONTR_BUF4_WR_ADDR__TYPE = str
MCNTRL_TILED_CHN2_ADDR = int
LWIR_TELEMETRY_AGC_ROI_BOTTOM__RAW = str
CAMSYNC_MASK = int
COLADDR_NUMBER__RAW = str
STATUS_SEQ_SHFT = int
......@@ -2286,12 +2495,15 @@ FFCLK1_IBUF_LOW_PWR__RAW = str
MCONTR_LINTILE_REPEAT__RAW = str
MCONTR_TOP_16BIT_REFRESH_PERIOD = int
CMPRS_INTERRUPTS__TYPE = str
LWIR_TELEMETRY = int
MCNTRL_TILED_FRAME_FULL_WIDTH__TYPE = str
WOI_HEIGHT__TYPE = str
STATUS_SEQ_SHFT__TYPE = str
MCONTR_CMPRS_BASE = int
DEBUG_SET_STATUS__TYPE = str
LWIR_TELEMETRY_AGC_ROI_RIGHT__TYPE = str
HISTOGRAM_START_PAGE = int
VOSPI_MCLK_BITS = int
RTC_SEC_USEC_ADDR__RAW = str
MCNTRL_PS_ADDR = int
SENS_BANDWIDTH = str
......@@ -2307,10 +2519,15 @@ MCONTR_BUF2_RD_ADDR = int
MCNTRL_TILED_FRAME_SIZE = int
GPIO_SET_STATUS = int
CLKOUT_DIV_PCLK2X = int
VOSPI_PACKET_FIRST = int
MULT_SAXI_ADDR = int
VOSPI_SPI_CLK__RAW = str
MCONTR_TOP_16BIT_ADDR_MASK__TYPE = str
SENS_CTRL_ODD = int
VOSPI_OUT_EN_BITS__TYPE = str
SENSOR_BASE_INC = int
MULT_SAXI_CNTRL_MASK__RAW = str
VOSPI_SOF_TO_HACT__RAW = str
SENSI2C_REL_RADDR__RAW = str
MCONTR_ARBIT_ADDR__RAW = str
MCONTR_LINTILE_EN__TYPE = str
......@@ -2324,6 +2541,7 @@ MCONTR_PHY_STATUS_REG_ADDR__RAW = str
SENSOR_BASE_INC__TYPE = str
MCNTRL_SCANLINE_PENDING_CNTR_BITS = int
SENS_DIVCLK_DIVIDE__TYPE = str
VOSPI_PACKET_FIRST__TYPE = str
LOGGER_CONF_MSG_BITS = int
SENS_GAMMA_RADDR__TYPE = str
MCNTRL_SCANLINE_CHN3_ADDR__RAW = str
......@@ -2338,7 +2556,8 @@ MULT_SAXI_MASK__RAW = str
SENSOR12BITS_TMD = int
MCONTR_CMPRS_STATUS_BASE__TYPE = str
NUM_CYCLES_10__RAW = str
SENS_LENS_FAT0_OUT__TYPE = str
CMPRS_TABLES__TYPE = str
VOSPI_SPI_CLK = int
DEBUG_SHIFT_DATA__RAW = str
SENSOR_16BIT_BIT__TYPE = str
SENS_NUM_SUBCHN = int
......
py393/x393_export_c.py
View file @ 691579c0
......@@ -322,7 +322,9 @@ class X393ExportC(object):
frmt_spcs = frmt_spcs)
stypedefs += self.get_typedef32(comment = "Sensor/multiplexer I/O pins status",
data = [self._enc_status_sens_io(),self._enc_status_sens_io_hispi()],
data = [self._enc_status_sens_io(),
self._enc_status_sens_io_hispi(),
self._enc_status_sens_io_vospi()],
name = "x393_status_sens_io", typ="ro",
frmt_spcs = frmt_spcs)
......@@ -431,7 +433,8 @@ class X393ExportC(object):
stypedefs += self.get_typedef32(comment = "Sensor port I/O control",
data = [self._enc_sensio_ctrl_par12(),
self._enc_sensio_ctrl_hispi()],
self._enc_sensio_ctrl_hispi(),
self._enc_sensio_ctrl_vospi()],
name = "x393_sensio_ctl", typ="wo",
frmt_spcs = frmt_spcs)
stypedefs += self.get_typedef32(comment = "Programming interface for multiplexer FPGA",
......@@ -1853,7 +1856,7 @@ class X393ExportC(object):
dw.append(("hact_ext_alive", 14, 1,0, "HACT signal from the sensor is toggling (N/A for HiSPI)"))
dw.append(("vact_alive", 15, 1,0, "VACT signal from the sensor is toggling (N/A for HiSPI)"))
dw.append(("xfpgatdo_byte", 16, 8,0, "Multiplexer FPGA TDO output"))
dw.append(("senspgmin", 24, 1,0, "senspgm pin state"))
dw.append(("senspgmin", 24, 1,0, "senspgm pin state (0 means non-FPGA SFE is present)"))
dw.append(("xfpgatdo", 25, 1,0, "Multiplexer FPGA TDO output"))
dw.append(("seq_num", 26, 6,0, "Sequence number"))
return dw
......@@ -1876,11 +1879,26 @@ class X393ExportC(object):
# dw.append(("rel_sol", 18, 3,0, "When SOL active on the last lane @ipclk, latches all other lanes SOL"))
# dw.append(("vact_alive", 15, 1,0, "VACT signal from the sensor is toggling (N/A for HiSPI)"))
# dw.append(("xfpgatdo_byte", 16, 8,0, "Multiplexer FPGA TDO output"))
dw.append(("senspgmin", 24, 1,0, "senspgm pin state"))
dw.append(("senspgmin", 24, 1,0, "senspgm pin state (0 means non-FPGA SFE is present)"))
dw.append(("xfpgatdo", 25, 1,0, "Multiplexer FPGA TDO output"))
dw.append(("seq_num", 26, 6,0, "Sequence number"))
return dw
def _enc_status_sens_io_vospi(self):
dw=[]
dw.append(("segment_id", 0, 4,0, "ID of the last received segment: 1-4 for the good frame, 0 - for ITAR-skipped frames"))
dw.append(("gpio_in", 4, 4,0, "Input from GPIO0-GPIO3, only GPIO3 may be used as segment ready"))
dw.append(("in_busy", 8, 1,0, "Frame segments are waited for or received to FIFO"))
dw.append(("out_busy", 9, 1,0, "received frame is being transferred to video memory"))
dw.append(("crc_err", 10, 1,0, "At least 1 CRC error happened since reset by command bit"))
dw.append(("fake in", 11, 1,0, "Just to keep hardware"))
dw.append(("senspgmin", 24, 1,0, "senspgm pin state (0 means non-FPGA SFE is present)"))
dw.append(("busy", 25, 1,0, "in_busy OR out_busy"))
dw.append(("seq_num", 26, 6,0, "Sequence number"))
return dw
def _enc_status_sens_i2c(self):
dw=[]
dw.append(("i2c_fifo_dout", 0, 8,0, "I2c byte read from the device through FIFO"))
......@@ -2107,6 +2125,31 @@ class X393ExportC(object):
dw.append(("gp1_set", vrlg.SENS_CTRL_GP1 + 2, 1, 0, "Set GP1 to 'gp1' value"))
return dw
def _enc_sensio_ctrl_vospi(self):
dw=[]
dw.append(("spi_en", vrlg.VOSPI_EN, 2, 0, "SPI Reset/enable: 0 - NOP, 1 - reset+disable, 2 - noreset, disable, 3 - noreset, enable"))
dw.append(("segm_zero", vrlg.VOSPI_SEGM0_OK, 1, 0, "OK to input segment 0 (invalid, valid are 1,2,3,4)"))
dw.append(("segm_zero_set",vrlg.VOSPI_SEGM0_OK + 1, 1, 0, "Enable setting of segm_zero"))
dw.append(("out_en", vrlg.VOSPI_OUT_EN, 1, 0, "Enable output sensor data to memory"))
dw.append(("out_en_set", vrlg.VOSPI_OUT_EN + 1, 1, 0, "Set enable sensor data to memory"))
dw.append(("out_single", vrlg.VOSPI_OUT_EN_SINGL, 1, 0, "Enable single sensor frame to memory"))
dw.append(("reset_crc", vrlg.VOSPI_RESET_CRC, 1, 0, "Reset CRC error status bit"))
dw.append(("rst", vrlg.VOSPI_MRST, 1, 0, "RESET signal level to the sensor (0 - low(active), 1 - high (inactive)"))
dw.append(("rst_set", vrlg.VOSPI_MRST + 1, 1, 0, "When set to 1, RESET is set to the 'rst' field value"))
dw.append(("pwdn", vrlg.VOSPI_PWDN, 1, 0, "POWER DOWN signal level to the sensor (0 - low(active), 1 - high (inactive)"))
dw.append(("pwdn_set", vrlg.VOSPI_PWDN + 1, 1, 0, "When set to 1, POWER DOWN is set to the 'pwdn' field value"))
dw.append(("mclk", vrlg.VOSPI_MCLK, 1, 0, "Enable master clock (25MHz) to sensor"))
dw.append(("mclk_set", vrlg.VOSPI_MCLK + 1, 1, 0, "When set to 1, MCLK enable is set to the 'mclk' field value"))
dw.append(("spi_clk", vrlg.VOSPI_SPI_CLK, 1, 0, "Enable continuous SPI clock (0 - only when SPI CS is active)"))
dw.append(("spi_clk_set", vrlg.VOSPI_SPI_CLK + 1, 1, 0, "When set to 1, SPI CLK enable is set to the 'spi_clk' field value"))
dw.append(("gpio0", vrlg.VOSPI_GPIO , 2, 0, "Output control for GPIO0: 0 - nop, 1 - set low, 2 - set high, 3 - input"))
dw.append(("gpio1", vrlg.VOSPI_GPIO+2, 2, 0, "Output control for GPIO1: 0 - nop, 1 - set low, 2 - set high, 3 - input"))
dw.append(("gpio2", vrlg.VOSPI_GPIO+4, 2, 0, "Output control for GPIO2: 0 - nop, 1 - set low, 2 - set high, 3 - input"))
dw.append(("gpio3", vrlg.VOSPI_GPIO+6, 2, 0, "Output control for GPIO3: 0 - nop, 1 - set low, 2 - set high, 3 - input"))
dw.append(("fake", vrlg.VOSPI_FAKE_OUT, 1, 0, "Just to keep I/O ports from optimization"))
dw.append(("mosi", vrlg.VOSPI_MOSI, 1, 0, "Just to keep I/O ports from optimization"))
return dw
def _enc_sensio_jtag(self):
dw=[]
dw.append(("tdi", vrlg.SENS_JTAG_TDI, 1, 0, "JTAG TDI level"))
......
sensor/sens_lepton3.v
View file @ 691579c0
......@@ -78,7 +78,6 @@ module sens_lepton3 #(
parameter SENS_HIGH_PERFORMANCE_MODE = "FALSE",
parameter SENS_PHASE_WIDTH= 8, // number of bits for te phase counter (depends on divisors)
// parameter SENS_PCLK_PERIOD = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
parameter SENS_BANDWIDTH = "OPTIMIZED", //"OPTIMIZED", "HIGH","LOW"
parameter CLKIN_PERIOD_SENSOR = 10.000, // input period in ns, 0..100.000 - MANDATORY, resolution down to 1 ps
......@@ -96,7 +95,39 @@ module sens_lepton3 #(
parameter SENS_SS_EN = "FALSE", // Enables Spread Spectrum mode
parameter SENS_SS_MODE = "CENTER_HIGH",//"CENTER_HIGH","CENTER_LOW","DOWN_HIGH","DOWN_LOW"
parameter SENS_SS_MOD_PERIOD = 10000, // integer 4000-40000 - SS modulation period in ns
parameter STATUS_ALIVE_WIDTH = 4
parameter STATUS_ALIVE_WIDTH = 4,
// mode bits
parameter VOSPI_EN = 0,
parameter VOSPI_EN_BITS = 2,
parameter VOSPI_SEGM0_OK = 2,
parameter VOSPI_SEGM0_OK_BITS = 2,
parameter VOSPI_OUT_EN = 4,
parameter VOSPI_OUT_EN_BITS = 2,
parameter VOSPI_OUT_EN_SINGL = 6,
parameter VOSPI_RESET_CRC = 7,
parameter VOSPI_MRST = 8,
parameter VOSPI_MRST_BITS = 2,
parameter VOSPI_PWDN = 10,
parameter VOSPI_PWDN_BITS = 2,
parameter VOSPI_MCLK = 12,
parameter VOSPI_MCLK_BITS = 2,
parameter VOSPI_SPI_CLK = 14,
parameter VOSPI_SPI_CLK_BITS = 2,
parameter VOSPI_GPIO = 16,
parameter VOSPI_GPIO_BITS = 8,
parameter VOSPI_FAKE_OUT = 24, // to keep hardware
parameter VOSPI_MOSI = 25, // pot used
parameter VOSPI_PACKET_WORDS = 80,
parameter VOSPI_NO_INVALID = 1, // do not output invalid packets data
parameter VOSPI_PACKETS_PER_LINE = 2,
parameter VOSPI_SEGMENT_FIRST = 1,
parameter VOSPI_SEGMENT_LAST = 4,
parameter VOSPI_PACKET_FIRST = 0,
parameter VOSPI_PACKET_LAST = 60,
parameter VOSPI_PACKET_TTT = 20, // line number where segment number is provided
parameter VOSPI_SOF_TO_HACT = 2, // clock cycles from SOF to HACT
parameter VOSPI_HACT_TO_HACT_EOF = 2 // minimal clock cycles from HACT to HACT or to EOF
)(
// programming interface
input mrst, // @posedge mclk, sync reset
......@@ -138,34 +169,115 @@ module sens_lepton3 #(
output sof, // @pclk
output eof // @pclk
);
localparam VOSPI_STATUS_BITS = 14;
// Status data (6 bits + 4)
wire [VOSPI_STATUS_BITS-1:0] status;
wire [ 3:0] segment_id;
wire crc_err_w; // single-cycle CRC error
reg crc_err_r; // at least one CRC error happened since reset
wire in_busy;
wire out_busy;
wire [ 3:0] gpio_in; // none currently used
wire fake_in;
assign status = {
fake_in,
crc_err_r,
out_busy,
in_busy,
gpio_in [3:0],
segment_id [3:0],
out_busy | in_busy, senspgm_int
};
/*
xfpgatdo_byte[7:0],
vact_alive, hact_ext_alive, hact_alive, locked_pxd_mmcm,
clkin_pxd_stopped_mmcm, clkfb_pxd_stopped_mmcm, xfpgadone,
ps_rdy, ps_out,
xfpgatdo, senspgmin}; // go to bits 24, 25 when read
*/
// mode register (4 bits + 8 + 1)
/*
bits 0,1: 0: nop
1 - nreset=0 disable
2 - nreset, disable
3 - nreset, enable
2,3: 0,1 - nop
2 - disable invalid segments
3 - enabl;e invalid segments
4,5: 0,1 - nop
2 - disable out_en
3 - enabl;e out_en
6: 0 - nop,
1 - single frame out_en
7: reset CRC error
8,9: 0,1 - nop
2 - lwir_mrst <= 0 (active reset)
3 - lwir_mrst <= 1 (inactive)
10,11: 0,1 - nop
2 - lwir_pwdn <= 0 (active, disable sensor)
3 - lwir_pwdn <= 1 (inactive)
12,13: 0,1 - nop
2 - disable sns_mclk (25 MHz clock to sensor)
3 - enable sns_mclk
14,15: 0,1 - nop
2 - disable spi_clk (stop between CS acvtive)
3 - enabl;e spi_clk (continuously run evenwhen CS is acvtive)
16-23: GPIO[3:0] - use gpio_bit() and generate
24 - fake_out
25 - spi_mosi_int
*/
// then re-sync to pclk (and to sns_mclk)
reg spi_nrst_mclk;
reg spi_en_mclk;
reg segm0_ok_mclk; // from mode register?
reg out_en_mclk; // single paulse - single frame, level - continuous
wire out_en_single_mclk;
wire crc_reset_mclk;
reg lwir_mrst_mclk;
reg lwir_pwdn_mclk;
reg sns_mclk_en_mclk;
reg spi_clk_en_mclk;
wire [ 3:0] gpio_out; // only [3] may be used
wire [ 3:0] gpio_en; // none currently used
// resynced to pclk
reg [ 1:0] spi_nrst_pclk; // reset spi and frame immediately (will need to reset sensor too)
reg [ 1:0] spi_en_pclk; // enable spi communications
reg [ 1:0] segm0_ok_pclk; // allow illegal segments
reg [ 1:0] out_en_pclk;
reg [ 1:0] lwir_mrst_pclk;
reg [ 1:0] lwir_pwdn_pclk;
// reg [ 1:0] sns_mclk_en_pclk;
reg [ 1:0] spi_clk_en_pclk;
wire out_en_single_pclk;
wire crc_reset_pclk;
wire fake_out;
wire fake_in;
wire spi_mosi_int; // not used
reg out_en_r; // single paulse - single frame, level - continuous
wire [25:0] status; // added byte-wide xfpgatdo
wire cmd_we;
wire [2:0] cmd_a;
wire [31:0] cmd_data;
reg [31:0] data_r;
reg set_ctrl_r;
reg set_status_r;
wire spi_clk_en_mclk;
wire sns_mclk_en_mclk;
reg [ 1:0] spi_clk_en_pclk;
reg [ 1:0] sns_mclk_en_lwir_mclk;
wire spi_clken; // from lower module, clock will be combined
wire spi_miso_int;
wire spi_cs_int;
wire spi_mosi_int;
wire [ 3:0] gpio_in; // only [3] may be used
wire [ 3:0] gpio_out; // none currently used
wire [ 3:0] gpio_en = 0; // none currently used
wire lwir_mrst_int;
wire lwir_pwdn_int;
wire senspgm_int;
wire sns_ctl_int;
// not implemented in the sesnor, put dummy input buffer5s
// not implemented in the sensor, put dummy input buffer5s
wire mipi_dp_int;
wire mipi_dn_int;
wire mipi_clkp_int;
......@@ -173,28 +285,87 @@ module sens_lepton3 #(
// temporary?
assign fake_in = senspgm_int ^ sns_ctl_int ^ mipi_dp_int ^ mipi_dn_int ^ mipi_clkp_int ^ mipi_clkn_int;
// assign fake_out = data_r[31];
assign status[25] = fake_in;
assign fake_in = sns_ctl_int ^ mipi_dp_int ^ mipi_dn_int ^ mipi_clkp_int ^ mipi_clkn_int;
// bit assignment will change
assign spi_clk_en_mclk = data_r[2];
assign sns_mclk_en_mclk = data_r[3];
assign out_en_single_mclk = set_ctrl_r && data_r[VOSPI_OUT_EN_SINGL] && !mrst;
assign crc_reset_mclk = set_ctrl_r && data_r[VOSPI_RESET_CRC] && !mrst;
assign fake_out = set_ctrl_r && data_r[VOSPI_FAKE_OUT];
assign spi_mosi_int = set_ctrl_r && data_r[VOSPI_MOSI]; // not used
assign prsts = prst | lwir_mrst_pclk[1];
always @(posedge mclk) begin
if (mrst) data_r <= 0;
else if (cmd_we) data_r <= cmd_data;
if (mrst) set_status_r <=0;
else set_status_r <= cmd_we && (cmd_a== SENSIO_STATUS);
if (mrst) set_ctrl_r <=0;
else set_ctrl_r <= cmd_we && (cmd_a== SENSIO_CTRL);
if (mrst) spi_nrst_mclk <= 0;
else if (set_ctrl_r && |data_r[VOSPI_EN +: VOSPI_EN_BITS]) spi_nrst_mclk <= data_r[VOSPI_EN + 1];
if (mrst) spi_en_mclk <= 0;
else if (set_ctrl_r && |data_r[VOSPI_EN +: VOSPI_EN_BITS]) spi_en_mclk <= &data_r[VOSPI_EN +: 2];
if (mrst) segm0_ok_mclk <= 0;
else if (set_ctrl_r && data_r[VOSPI_SEGM0_OK + VOSPI_SEGM0_OK_BITS - 1]) segm0_ok_mclk <= data_r[VOSPI_SEGM0_OK];
if (mrst) out_en_mclk <= 0;
else if (set_ctrl_r && data_r[VOSPI_OUT_EN + VOSPI_OUT_EN_BITS - 1]) out_en_mclk <= data_r[VOSPI_OUT_EN];
if (mrst) lwir_mrst_mclk <= 0;
else if (set_ctrl_r && data_r[VOSPI_MRST + VOSPI_MRST_BITS - 1]) lwir_mrst_mclk <= data_r[VOSPI_MRST];
if (mrst) lwir_pwdn_mclk <= 0;
else if (set_ctrl_r && data_r[VOSPI_PWDN + VOSPI_PWDN_BITS - 1]) lwir_pwdn_mclk <= data_r[VOSPI_PWDN];
if (mrst) sns_mclk_en_mclk <= 0;
else if (set_ctrl_r && data_r[VOSPI_MCLK + VOSPI_MCLK_BITS - 1]) sns_mclk_en_mclk <= data_r[VOSPI_MCLK];
if (mrst) spi_clk_en_mclk <= 0;
else if (set_ctrl_r && data_r[VOSPI_SPI_CLK + VOSPI_SPI_CLK_BITS - 1]) spi_clk_en_mclk <= data_r[VOSPI_SPI_CLK];
end
// resync to pclk
always @ (posedge pclk) begin
spi_nrst_pclk[1:0] <= {spi_nrst_pclk[0], spi_nrst_mclk};
spi_en_pclk[1:0] <= {spi_en_pclk[0], spi_en_mclk};
segm0_ok_pclk[1:0] <= {segm0_ok_pclk[0], segm0_ok_mclk};
out_en_pclk[1:0] <= {out_en_pclk[0], out_en_mclk};
lwir_mrst_pclk[1:0] <= {lwir_mrst_pclk[0], lwir_mrst_mclk};
lwir_pwdn_pclk[1:0] <= {lwir_pwdn_pclk[0], lwir_pwdn_mclk};
spi_clk_en_pclk[1:0] <= {spi_clk_en_pclk[0], spi_clk_en_mclk};
out_en_r <= out_en_single_pclk | out_en_pclk[1];
if (prst || crc_reset_pclk) crc_err_r <= 0;
else if (crc_err_w) crc_err_r <= 1;
always @(posedge pclk) begin
spi_clk_en_pclk[1:0] <= {spi_clk_en_pclk[0],spi_clk_en_mclk};
end
always @(posedge sns_mclk) begin
sns_mclk_en_lwir_mclk[1:0] <= {sns_mclk_en_lwir_mclk[0],sns_mclk_en_mclk};
end
pulse_cross_clock pulse_cross_clock_out_en_single_i (
.rst (mrst), // input
.src_clk (mclk), // input
.dst_clk (pclk), // input
.in_pulse (out_en_single_mclk), // input
.out_pulse (out_en_single_pclk), // output
.busy() // output
);
pulse_cross_clock pulse_cross_clock_crc_reset_i (
.rst (mrst), // input
.src_clk (mclk), // input
.dst_clk (pclk), // input
.in_pulse (crc_reset_mclk), // input
.out_pulse (crc_reset_pclk), // output
.busy() // output
);
// implement I/O ports, including fake ones, to be able to assign them I/O pads
// generate clocka to sesnor output, controlled by control word bits
......@@ -207,7 +378,7 @@ module sens_lepton3 #(
.SRTYPE ("SYNC")
) spi_clk_i (
.clk (pclk), // input
.ce (spi_clk_en_pclk[1]), // input
.ce (spi_clk_en_pclk[1] | spi_clken), // input
.rst (prst), // input
.set (1'b0), // input
.din (2'b01), // input[1:0]
......@@ -269,7 +440,16 @@ module sens_lepton3 #(
generate // gpio[3:0]
genvar i;
for (i=0; i < 4; i=i+1) begin: gpio_block
for (i=0; i < (VOSPI_GPIO_BITS / 2); i=i+1) begin: gpio_block
gpio_bit gpio_bit_i (
.clk (mclk), // input
.srst (mrst), // input
.we (set_ctrl_r), // input
.d_in (data_r[VOSPI_GPIO + 2*i +: 2]), // input[1:0]
.d_out (gpio_out[i]), // output
.en_out (gpio_en[i]) // output
);
iobuf #(
.DRIVE (PXD_DRIVE),
.IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
......@@ -285,6 +465,7 @@ module sens_lepton3 #(
end
endgenerate
// for debug/test alive
iobuf #( // lwir_mrst
.DRIVE (PXD_DRIVE),
.IBUF_LOW_PWR (PXD_IBUF_LOW_PWR),
......@@ -293,7 +474,7 @@ module sens_lepton3 #(
) lwir_mrst_i (
.O (), // output - currently not used
.IO (lwir_mrst), // inout I/O pad
.I (lwir_mrst_int), // input
.I (lwir_mrst_pclk[0]), // input
.T (1'b0) // input - always on
);
......@@ -305,7 +486,7 @@ module sens_lepton3 #(
) lwir_pwdn_i (
.O (), // output - currently not used
.IO (lwir_pwdn), // inout I/O pad
.I (lwir_pwdn_int), // input
.I (lwir_pwdn_pclk[0]), // input
.T (1'b0) // input - always on
);
......@@ -382,6 +563,68 @@ module sens_lepton3 #(
.T (1'b1) // input - always off
);
wire segment_done;
wire discard_segment;
reg start_segment;
reg [ 3:0] exp_segment;
reg spi_en_d;
// first frame has to be good (only segments only 1..4), next can continue with 0-s
reg segm0_ok_r;
always @(posedge pclk) begin
// spi_en_d <= spi_nrst_pclk[1];
spi_en_d <= spi_en_pclk[1];
if (!spi_en_d) exp_segment <= VOSPI_SEGMENT_FIRST;
else if (segment_done && !discard_segment) exp_segment <= (exp_segment == VOSPI_SEGMENT_LAST) ?
VOSPI_SEGMENT_FIRST :
(exp_segment + 1);
if (!spi_en_d) segm0_ok_r <= 0;
else if (segment_done && !discard_segment && (exp_segment == VOSPI_SEGMENT_LAST)) segm0_ok_r <= segm0_ok_pclk[1];
start_segment <= spi_en_d && !in_busy && !start_segment;
end
vospi_segment_61 #(
.VOSPI_PACKET_WORDS (VOSPI_PACKET_WORDS), // 80
.VOSPI_NO_INVALID (VOSPI_NO_INVALID), // 1
.VOSPI_PACKETS_PER_LINE (VOSPI_PACKETS_PER_LINE), // 2
.VOSPI_SEGMENT_FIRST (VOSPI_SEGMENT_FIRST), // 1
.VOSPI_SEGMENT_LAST (VOSPI_SEGMENT_LAST), // 4
.VOSPI_PACKET_FIRST (VOSPI_PACKET_FIRST), // 0
.VOSPI_PACKET_LAST (VOSPI_PACKET_LAST), // 60
.VOSPI_PACKET_TTT (VOSPI_PACKET_TTT), // 20
.VOSPI_SOF_TO_HACT (VOSPI_SOF_TO_HACT), // 2
.VOSPI_HACT_TO_HACT_EOF (VOSPI_HACT_TO_HACT_EOF) // 2
) vospi_segment_61_i (
.rst (!spi_nrst_pclk[1]), // input
.clk (pclk), // input
.start (start_segment), // input
.exp_segment (exp_segment), // input[3:0]
.segm0_ok (segm0_ok_r), // input
.out_en (out_en_r), // input
.spi_clken (spi_clken), // output
.spi_cs (spi_cs_int), // output
.miso (spi_miso_int), // input
.in_busy (in_busy), // output
.out_busy (out_busy), // output
.segment_done (segment_done), // output reg
.discard_segment (discard_segment), // output
.dout (pxd), // output[15:0]
.hact (hact), // output
.sof (sof), // output
.eof (eof), // output
.crc_err (crc_err_w), // output
.id (segment_id) // output[3:0]
);
cmd_deser #(
.ADDR (SENSIO_ADDR),
.ADDR_MASK (SENSIO_ADDR_MASK),
......@@ -401,7 +644,7 @@ module sens_lepton3 #(
status_generate #(
.STATUS_REG_ADDR(SENSIO_STATUS_REG),
.PAYLOAD_BITS(26) // STATUS_PAYLOAD_BITS)
.PAYLOAD_BITS(VOSPI_STATUS_BITS) // STATUS_PAYLOAD_BITS)
) status_generate_sens_io_i (
.rst (1'b0), // rst), // input
.clk (mclk), // input
......@@ -415,7 +658,8 @@ module sens_lepton3 #(
);
// for debug/test alive
// for debug/test alive kept for debug if it will be needed
/*
pulse_cross_clock pulse_cross_clock_vact_a_mclk_i (
.rst (irst), // input
.src_clk (ipclk), // input
......@@ -442,7 +686,7 @@ module sens_lepton3 #(
.out_pulse (hact_a_mclk), // output
.busy() // output
);
*/
endmodule
sensor/sensor_channel.v
View file @ 691579c0
......@@ -227,13 +227,43 @@ module sensor_channel#(
parameter NUM_FRAME_BITS = 4,
`ifndef HISPI
`ifndef LWIR
`ifdef HISPI
`elsif LWIR
parameter VOSPI_EN = 0,
parameter VOSPI_EN_BITS = 2,
parameter VOSPI_SEGM0_OK = 2,
parameter VOSPI_SEGM0_OK_BITS = 2,
parameter VOSPI_OUT_EN = 4,
parameter VOSPI_OUT_EN_BITS = 2,
parameter VOSPI_OUT_EN_SINGL = 6,
parameter VOSPI_RESET_CRC = 7,
parameter VOSPI_MRST = 8,
parameter VOSPI_MRST_BITS = 2,
parameter VOSPI_PWDN = 10,
parameter VOSPI_PWDN_BITS = 2,
parameter VOSPI_MCLK = 12,
parameter VOSPI_MCLK_BITS = 2,
parameter VOSPI_SPI_CLK = 14,
parameter VOSPI_SPI_CLK_BITS = 2,
parameter VOSPI_GPIO = 16,
parameter VOSPI_GPIO_BITS = 8,
parameter VOSPI_FAKE_OUT = 24, // to keep hardware
parameter VOSPI_MOSI = 25, // not used
parameter VOSPI_PACKET_WORDS = 80,
parameter VOSPI_NO_INVALID = 1, // do not output invalid packets data
parameter VOSPI_PACKETS_PER_LINE = 2,
parameter VOSPI_SEGMENT_FIRST = 1,
parameter VOSPI_SEGMENT_LAST = 4,
parameter VOSPI_PACKET_FIRST = 0,
parameter VOSPI_PACKET_LAST = 60,
parameter VOSPI_PACKET_TTT = 20, // line number where segment number is provided
parameter VOSPI_SOF_TO_HACT = 2, // clock cycles from SOF to HACT
parameter VOSPI_HACT_TO_HACT_EOF = 2, // minimal clock cycles from HACT to HACT or to EOF
`else
//sensor_fifo parameters
parameter SENSOR_DATA_WIDTH = 12,
parameter SENSOR_FIFO_2DEPTH = 4,
parameter [3:0] SENSOR_FIFO_DELAY = 5, // 7,
`endif
`endif
// sens_parallel12 other parameters
......@@ -501,9 +531,12 @@ module sensor_channel#(
reg dav_r;
wire [15:0] dout_w;
wire dav_w;
//`ifndef LWIR
`ifdef LWIR
wire trig; // SuppressThisWarning VEditor - (yet) unused
`else
wire trig;
//`endif
`endif
wire prsts; // @pclk - includes sensor reset and sensor PLL reset
reg sof_out_r;
reg eof_out_r;
......@@ -536,14 +569,24 @@ module sensor_channel#(
`ifdef DEBUG_RING
`ifdef HISPI
`elsif LWIR
`else
reg vact_to_fifo_r;
`endif
`ifdef LWIR
// reg hact_to_fifo_r;
reg [15:0] debug_line_cntr = 0;
reg [15:0] debug_lines = 0;
reg [15:0] hact_cntr = 0;
// reg [15:0] vact_cntr;
`else
reg hact_to_fifo_r;
reg [15:0] debug_line_cntr;
reg [15:0] debug_lines;
reg [15:0] hact_cntr;
reg [15:0] vact_cntr;
`endif
`ifdef HISPI
always @(posedge pclk) begin
// vact_to_fifo_r <= vact_to_fifo;
......@@ -813,7 +856,7 @@ module sensor_channel#(
`endif
`endif
`ifndef LWIR
//`ifndef LWIR
pulse_cross_clock pulse_cross_clock_eof_mclk_i (
.rst (prsts), // input extended to include sensor reset and rst_mmcm
.src_clk (pclk), // input
......@@ -822,7 +865,7 @@ module sensor_channel#(
.out_pulse (eof_mclk), // output
.busy() // output
);
`endif
//`endif
`ifdef HISPI
......@@ -978,7 +1021,37 @@ module sensor_channel#(
.SENS_SS_EN (SENS_SS_EN),
.SENS_SS_MODE (SENS_SS_MODE),
.SENS_SS_MOD_PERIOD (SENS_SS_MOD_PERIOD),
.STATUS_ALIVE_WIDTH (STATUS_ALIVE_WIDTH)
.STATUS_ALIVE_WIDTH (STATUS_ALIVE_WIDTH),
.VOSPI_EN (VOSPI_EN), // 0,
.VOSPI_EN_BITS (VOSPI_EN_BITS), // 2,
.VOSPI_SEGM0_OK (VOSPI_SEGM0_OK), // 2,
.VOSPI_SEGM0_OK_BITS (VOSPI_SEGM0_OK_BITS), // 2,
.VOSPI_OUT_EN (VOSPI_OUT_EN), // 4,
.VOSPI_OUT_EN_BITS (VOSPI_OUT_EN_BITS), // 2,
.VOSPI_OUT_EN_SINGL (VOSPI_OUT_EN_SINGL), // 6,
.VOSPI_RESET_CRC (VOSPI_RESET_CRC), // 7,
.VOSPI_MRST (VOSPI_MRST), // 8,
.VOSPI_MRST_BITS (VOSPI_MRST_BITS), // 2,
.VOSPI_PWDN (VOSPI_PWDN), // 10,
.VOSPI_PWDN_BITS (VOSPI_PWDN_BITS), // 2,
.VOSPI_MCLK (VOSPI_MCLK), // 12,
.VOSPI_MCLK_BITS (VOSPI_MCLK_BITS), // 2,
.VOSPI_SPI_CLK (VOSPI_SPI_CLK), // 14,
.VOSPI_SPI_CLK_BITS (VOSPI_SPI_CLK_BITS), // 2,
.VOSPI_GPIO (VOSPI_GPIO), // 16,
.VOSPI_GPIO_BITS (VOSPI_GPIO_BITS), // 8,
.VOSPI_FAKE_OUT (VOSPI_FAKE_OUT), // 24, // to keep hardware
.VOSPI_MOSI (VOSPI_MOSI), // 25, // pot used
.VOSPI_PACKET_WORDS (VOSPI_PACKET_WORDS),// 80,
.VOSPI_NO_INVALID (VOSPI_NO_INVALID), // 1,
.VOSPI_PACKETS_PER_LINE (VOSPI_PACKETS_PER_LINE), // 2,
.VOSPI_SEGMENT_FIRST (VOSPI_SEGMENT_FIRST), // 1,
.VOSPI_SEGMENT_LAST (VOSPI_SEGMENT_LAST), // 4,
.VOSPI_PACKET_FIRST (VOSPI_PACKET_FIRST), // 0,
.VOSPI_PACKET_LAST (VOSPI_PACKET_LAST), // 60,
.VOSPI_PACKET_TTT (VOSPI_PACKET_TTT), // 20,
.VOSPI_SOF_TO_HACT (VOSPI_SOF_TO_HACT), // 2,
.VOSPI_HACT_TO_HACT_EOF (VOSPI_HACT_TO_HACT_EOF) // 2,
) sens_lepton3_i (
.mrst (mrst), // input
.mclk (mclk), // input
......
sensor/sensors393.v
View file @ 691579c0
......@@ -223,7 +223,39 @@ module sensors393 #(
parameter SENSI2C_IBUF_LOW_PWR= "TRUE",
parameter SENSI2C_SLEW = "SLOW",
`ifndef HISPI
`ifdef HISPI
`elsif LWIR
parameter VOSPI_EN = 0,
parameter VOSPI_EN_BITS = 2,
parameter VOSPI_SEGM0_OK = 2,
parameter VOSPI_SEGM0_OK_BITS = 2,
parameter VOSPI_OUT_EN = 4,
parameter VOSPI_OUT_EN_BITS = 2,
parameter VOSPI_OUT_EN_SINGL = 6,
parameter VOSPI_RESET_CRC = 7,
parameter VOSPI_MRST = 8,
parameter VOSPI_MRST_BITS = 2,
parameter VOSPI_PWDN = 10,
parameter VOSPI_PWDN_BITS = 2,
parameter VOSPI_MCLK = 12,
parameter VOSPI_MCLK_BITS = 2,
parameter VOSPI_SPI_CLK = 14,
parameter VOSPI_SPI_CLK_BITS = 2,
parameter VOSPI_GPIO = 16,
parameter VOSPI_GPIO_BITS = 8,
parameter VOSPI_FAKE_OUT = 24, // to keep hardware
parameter VOSPI_MOSI = 25, // not used
parameter VOSPI_PACKET_WORDS = 80,
parameter VOSPI_NO_INVALID = 1, // do not output invalid packets data
parameter VOSPI_PACKETS_PER_LINE = 2,
parameter VOSPI_SEGMENT_FIRST = 1,
parameter VOSPI_SEGMENT_LAST = 4,
parameter VOSPI_PACKET_FIRST = 0,
parameter VOSPI_PACKET_LAST = 60,
parameter VOSPI_PACKET_TTT = 20, // line number where segment number is provided
parameter VOSPI_SOF_TO_HACT = 2, // clock cycles from SOF to HACT
parameter VOSPI_HACT_TO_HACT_EOF = 2, // minimal clock cycles from HACT to HACT or to EOF
`else
//sensor_fifo parameters
parameter SENSOR_DATA_WIDTH = 12,
parameter SENSOR_FIFO_2DEPTH = 4,
......@@ -644,7 +676,40 @@ module sensors393 #(
.SENSI2C_IOSTANDARD (SENSI2C_IOSTANDARD),
.SENSI2C_SLEW (SENSI2C_SLEW),
.NUM_FRAME_BITS (NUM_FRAME_BITS),
`ifndef HISPI
`ifdef HISPI
`elsif LWIR
.VOSPI_EN (VOSPI_EN), // 0,
.VOSPI_EN_BITS (VOSPI_EN_BITS), // 2,
.VOSPI_SEGM0_OK (VOSPI_SEGM0_OK), // 2,
.VOSPI_SEGM0_OK_BITS (VOSPI_SEGM0_OK_BITS), // 2,
.VOSPI_OUT_EN (VOSPI_OUT_EN), // 4,
.VOSPI_OUT_EN_BITS (VOSPI_OUT_EN_BITS), // 2,
.VOSPI_OUT_EN_SINGL (VOSPI_OUT_EN_SINGL), // 6,
.VOSPI_RESET_CRC (VOSPI_RESET_CRC), // 7,
.VOSPI_MRST (VOSPI_MRST), // 8,
.VOSPI_MRST_BITS (VOSPI_MRST_BITS), // 2,
.VOSPI_PWDN (VOSPI_PWDN), // 10,
.VOSPI_PWDN_BITS (VOSPI_PWDN_BITS), // 2,
.VOSPI_MCLK (VOSPI_MCLK), // 12,
.VOSPI_MCLK_BITS (VOSPI_MCLK_BITS), // 2,
.VOSPI_SPI_CLK (VOSPI_SPI_CLK), // 14,
.VOSPI_SPI_CLK_BITS (VOSPI_SPI_CLK_BITS), // 2,
.VOSPI_GPIO (VOSPI_GPIO), // 16,
.VOSPI_GPIO_BITS (VOSPI_GPIO_BITS), // 8,
.VOSPI_FAKE_OUT (VOSPI_FAKE_OUT), // 24, // to keep hardware
.VOSPI_MOSI (VOSPI_MOSI), // 25, // not used
.VOSPI_PACKET_WORDS (VOSPI_PACKET_WORDS),// 80,
.VOSPI_NO_INVALID (VOSPI_NO_INVALID), // 1,
.VOSPI_PACKETS_PER_LINE (VOSPI_PACKETS_PER_LINE), // 2,
.VOSPI_SEGMENT_FIRST (VOSPI_SEGMENT_FIRST), // 1,
.VOSPI_SEGMENT_LAST (VOSPI_SEGMENT_LAST), // 4,
.VOSPI_PACKET_FIRST (VOSPI_PACKET_FIRST), // 0,
.VOSPI_PACKET_LAST (VOSPI_PACKET_LAST), // 60,
.VOSPI_PACKET_TTT (VOSPI_PACKET_TTT), // 20,
.VOSPI_SOF_TO_HACT (VOSPI_SOF_TO_HACT), // 2,
.VOSPI_HACT_TO_HACT_EOF (VOSPI_HACT_TO_HACT_EOF), // 2,
`else
.SENSOR_DATA_WIDTH (SENSOR_DATA_WIDTH),
.SENSOR_FIFO_2DEPTH (SENSOR_FIFO_2DEPTH),
.SENSOR_FIFO_DELAY (SENSOR_FIFO_DELAY),
......
sensor/vospi_segment_61.v
View file @ 691579c0
......@@ -40,6 +40,7 @@
module vospi_segment_61#(
parameter VOSPI_PACKET_WORDS = 80,
parameter VOSPI_NO_INVALID = 1, // do not output invalid packets data
parameter VOSPI_PACKETS_PER_LINE = 2,
parameter VOSPI_SEGMENT_FIRST = 1,
parameter VOSPI_SEGMENT_LAST = 4,
......@@ -62,13 +63,16 @@ module vospi_segment_61#(
output spi_cs, // active low
input miso, // input from the sensor
output in_busy, // waiting for or receiving a segment
output out_busy,
output reg segment_done, // finished receiving segment (good or bad). next after busy off
output discard_segment, // segment was disc arded
output [15:0] dout, // 16-bit data received
output hact, // data valid
output sof, // start of frame
output eof, // end of frame
output crc_err, // crc error happened for any packet (valid at eos)
output [3:0] id // segment number (valid at eos)
);
localparam VOSPI_PACKETS_FRAME = (VOSPI_SEGMENT_LAST - VOSPI_SEGMENT_FIRST + 1) *
(VOSPI_PACKET_LAST - VOSPI_PACKET_FIRST + 1);
......@@ -86,10 +90,10 @@ module vospi_segment_61#(
reg [ 7:0] full_packet; // current full packet number in a fragment
reg [ 7:0] full_packet_verified; // next packet verified (will not be discarded later)
reg full_packet_frame; // lsb of the input frame // not needed?
reg discard_set; // start discard_segment
reg discard_set; // start discard_segment_r
wire segment_good_w; // recognized expected segment, OK to read FIFO
reg segment_good; // recognized expected segment, OK to read FIFO
reg discard_segment; // read and discard the rest of the current segment
reg discard_segment_r; // read and discard the rest of the current segment
reg running_good; // passed packet 20
wire packet_done; // read full packet
wire packet_busy; // receiving SPI packet (same as spi_clken, !spi_cs)
......@@ -101,12 +105,12 @@ module vospi_segment_61#(
wire is_last_segment_w;
reg start_d;
wire segment_stb;
reg crc_err_r;
// reg crc_err_r;
wire packet_crc_err;
reg packet_start;
wire we; // write data to buffer
wire segment_done;
reg segment_busy;
wire segment_done_w;
reg segment_busy_r;
reg segment_running; // may be discarded
reg [3:0] segment_id_r;
wire frame_in_done;
......@@ -116,11 +120,16 @@ module vospi_segment_61#(
assign is_last_segment_w = (exp_segment == VOSPI_SEGMENT_LAST);
assign segment_good_w = (packet_id[15:12] == exp_segment) || ((packet_id[15:12] == 0) && segm0_ok);
assign segment_stb = id_stb && (packet_id[11:0] == VOSPI_PACKET_TTT);
assign we = segment_running && !discard_segment && packet_dv;
assign crc_err = crc_err_r;
assign segment_done = segment_running && packet_done && (packet_id[11:0] == VOSPI_PACKET_LAST) ;
assign we = segment_running && !discard_segment_r && packet_dv;
assign crc_err = packet_done && packet_crc_err; // crc_err_r;
assign segment_done_w = segment_running && packet_done && (packet_id[11:0] == VOSPI_PACKET_LAST) ;
assign id = segment_id_r;
assign frame_in_done = segment_done && last_segment_in;
assign frame_in_done = segment_done_w && last_segment_in;
assign in_busy= segment_busy_r; // waiting for or receiving a segment
assign discard_segment= discard_segment_r; // segment was disc arded
// To Buffer
always @ (posedge clk) begin
// if (rst) first_segment_in <= 0;
......@@ -131,14 +140,14 @@ module vospi_segment_61#(
start_d <= start;
discard_set <= segment_running && !discard_segment && segment_stb && !segment_good_w;
discard_set <= segment_running && !discard_segment_r && segment_stb && !segment_good_w;
segment_good <= segment_running && !discard_segment && segment_stb && segment_good_w;
segment_good <= segment_running && !discard_segment_r && segment_stb && segment_good_w;
if (segment_running && !discard_segment && segment_stb) segment_id_r <= packet_id[15:12];
if (segment_running && !discard_segment_r && segment_stb) segment_id_r <= packet_id[15:12];
if (start) discard_segment <= 0;
else if (discard_set) discard_segment <= 1;
if (start) discard_segment_r <= 0;
else if (discard_set) discard_segment_r <= 1;
if (start) running_good <= 0;
else if (segment_good) running_good <= 1;
......@@ -152,19 +161,21 @@ module vospi_segment_61#(
if (rst || (start && is_first_segment_w)) full_packet <= 0;
else if (discard_set) full_packet <= segment_start_packet;
else if (!discard_segment && packet_done) full_packet <= full_packet + 1;
else if (!discard_segment_r && packet_done) full_packet <= full_packet + 1;
// if (rst || start) crc_err_r <= 0;
// else if (packet_done && packet_crc_err) crc_err_r <= 0;
if (rst || start) crc_err_r <= 0;
else if (packet_done && packet_crc_err) crc_err_r <= 0;
if (rst) segment_busy_r <= 0;
else if (start) segment_busy_r <= 1'b1;
else if (segment_done_w) segment_busy_r <= 1'b0;
if (rst) segment_busy <= 0;
else if (start) segment_busy <= 1'b1;
else if (segment_done) segment_busy <= 1'b0;
segment_done <= segment_done_w; // module output reg
if (!segment_busy || start) segment_running <= 0;
if (!segment_busy_r || start) segment_running <= 0;
else if (id_stb && (packet_id[11:0] == VOSPI_PACKET_FIRST)) segment_running <= 1;
packet_start <= !rst && !packet_busy && segment_busy;
packet_start <= !rst && !packet_busy && segment_busy_r;
if (rst) waddr <= 0;
else if (discard_set) waddr <= segment_start_waddr;
......@@ -209,6 +220,7 @@ module vospi_segment_61#(
assign hact = hact_r[2];
assign eof = eof_r[2];
assign sof = sof_r;
assign out_busy = out_request | out_frame;
always @ (posedge clk) begin
if (rst) hact_r <= 0;
......@@ -250,8 +262,8 @@ module vospi_segment_61#(
end
vospi_packet_80 #(
.VOSPI_PACKET_WORDS(80),
.VOSPI_NO_INVALID(1)
.VOSPI_PACKET_WORDS (VOSPI_PACKET_WORDS), // 80,
.VOSPI_NO_INVALID (VOSPI_NO_INVALID) // 1
) vospi_packet_80_i (
.rst (rst), // input
.clk (clk), // input
......
util_modules/gpio393.v
View file @ 691579c0
......@@ -221,27 +221,3 @@ module gpio393 #(
endmodule
module gpio_bit (
// input rst, // global reset
input clk, // system clock
input srst, // @posedge clk - sync reset
input we,
input [1:0] d_in, // input bits
output d_out, // output data
output en_out); // enable output
reg d_r = 0;
reg en_r = 0;
assign d_out = d_r;
assign en_out = en_r;
always @ (posedge clk) begin
if (srst) d_r <= 0;
else if (we && (|d_in)) d_r <= !d_in[0];
if (srst) en_r <= 0;
else if (we && (|d_in)) en_r <= !(&d_in);
end
endmodule
x393.v
View file @ 691579c0
......@@ -1834,7 +1834,41 @@ assign axi_grst = axi_rst_pre;
.SENSI2C_IBUF_LOW_PWR (SENSI2C_IBUF_LOW_PWR),
.SENSI2C_IOSTANDARD (SENSI2C_IOSTANDARD),
.SENSI2C_SLEW (SENSI2C_SLEW),
`ifndef HISPI
`ifdef HISPI
`elsif LWIR
.VOSPI_EN (VOSPI_EN), // 0,
.VOSPI_EN_BITS (VOSPI_EN_BITS), // 2,
.VOSPI_SEGM0_OK (VOSPI_SEGM0_OK), // 2,
.VOSPI_SEGM0_OK_BITS (VOSPI_SEGM0_OK_BITS), // 2,
.VOSPI_OUT_EN (VOSPI_OUT_EN), // 4,
.VOSPI_OUT_EN_BITS (VOSPI_OUT_EN_BITS), // 2,
.VOSPI_OUT_EN_SINGL (VOSPI_OUT_EN_SINGL), // 6,
.VOSPI_RESET_CRC (VOSPI_RESET_CRC), // 7,
.VOSPI_MRST (VOSPI_MRST), // 8,
.VOSPI_MRST_BITS (VOSPI_MRST_BITS), // 2,
.VOSPI_PWDN (VOSPI_PWDN), // 10,
.VOSPI_PWDN_BITS (VOSPI_PWDN_BITS), // 2,
.VOSPI_MCLK (VOSPI_MCLK), // 12,
.VOSPI_MCLK_BITS (VOSPI_MCLK_BITS), // 2,
.VOSPI_SPI_CLK (VOSPI_SPI_CLK), // 14,
.VOSPI_SPI_CLK_BITS (VOSPI_SPI_CLK_BITS), // 2,
.VOSPI_GPIO (VOSPI_GPIO), // 16,
.VOSPI_GPIO_BITS (VOSPI_GPIO_BITS), // 8,
.VOSPI_FAKE_OUT (VOSPI_FAKE_OUT), // 24, // to keep hardware
.VOSPI_MOSI (VOSPI_MOSI), // 25, // not used
.VOSPI_PACKET_WORDS (VOSPI_PACKET_WORDS),// 80,
.VOSPI_NO_INVALID (VOSPI_NO_INVALID), // 1,
.VOSPI_PACKETS_PER_LINE (VOSPI_PACKETS_PER_LINE), // 2,
.VOSPI_SEGMENT_FIRST (VOSPI_SEGMENT_FIRST), // 1,
.VOSPI_SEGMENT_LAST (VOSPI_SEGMENT_LAST), // 4,
.VOSPI_PACKET_FIRST (VOSPI_PACKET_FIRST), // 0,
.VOSPI_PACKET_LAST (VOSPI_PACKET_LAST), // 60,
.VOSPI_PACKET_TTT (VOSPI_PACKET_TTT), // 20,
.VOSPI_SOF_TO_HACT (VOSPI_SOF_TO_HACT), // 2,
.VOSPI_HACT_TO_HACT_EOF (VOSPI_HACT_TO_HACT_EOF), // 2,
`else
.SENSOR_DATA_WIDTH (SENSOR_DATA_WIDTH),
.SENSOR_FIFO_2DEPTH (SENSOR_FIFO_2DEPTH),
.SENSOR_FIFO_DELAY (SENSOR_FIFO_DELAY),
......
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