Corrected histograms modules

.settings/org.eclipse.core.resources.prefs

 eclipse.preferences.version=1
+encoding//attic/gen_hist_test.py=utf-8
 encoding//helpers/convert_data_to_params.py=utf-8
 encoding//helpers/convert_pass_init_params.py=utf-8
 encoding//helpers/convert_zigzag_rom.py=utf-8

fpga_version.vh

@@ -35,7 +35,10 @@
  * contains all the components and scripts required to completely simulate it
  * with at least one of the Free Software programs.
  */
-        parameter FPGA_VERSION =          32'h039300b4;      //-a parallel, and more - -0.180/33, 80.68 %
+        parameter FPGA_VERSION =          32'h039300b7;      //parallel, matching histograms Bayer to gamma bayer -0.011/9, 79.92%
+//        parameter FPGA_VERSION =          32'h039300b6;      //parallel, working on histograms odd colors bug -0.207 /58,  79.68%
+//      parameter FPGA_VERSION =          32'h039300b5;      //parallel, moving histograms earlier -0.123/30, 79.47 
+//      parameter FPGA_VERSION =          32'h039300b4;      //-a parallel, and more - -0.180/33, 80.68 %
 //      parameter FPGA_VERSION =          32'h039300b4;      // parallel, and more -0.094/37, 80.18 %
 //      parameter FPGA_VERSION =          32'h039300b3;      // parallel, and more  -0.052/8, 79.56%
 //      parameter FPGA_VERSION =          32'h039300b2;      // parallel, and more -0.163 /47,  79.93%

includes/x393_parameters.vh

@@ -301,7 +301,7 @@
     parameter MCONTR_LINTILE_ABORT_LATE =         14,  // abort frame if not finished by the new frame sync (wait pending memory)
     
     parameter MCNTRL_SCANLINE_DLY_WIDTH =         12,  // delay start pulse by 1..64 mclk
-    parameter MCNTRL_SCANLINE_DLY_DEFAULT =       63,  // initial delay value for start pulse
+    parameter MCNTRL_SCANLINE_DLY_DEFAULT =     1024,  // initial delay value for start pulse
 
 // Channel test module parameters
     parameter MCNTRL_TEST01_ADDR=                 'h0f0,
@@ -513,7 +513,8 @@
       parameter HISTOGRAM_LEFT_TOP =     'h0,
       parameter HISTOGRAM_WIDTH_HEIGHT = 'h1, // 1.. 2^16, 0 - use HACT
 
-    parameter [1:0] XOR_HIST_BAYER =  2'b00,// invert bayer setting    
+//    parameter [1:0] XOR_HIST_BAYER =  2'b00,// invert bayer setting    
+    parameter [1:0] XOR_HIST_BAYER =  2'b01,// invert bayer setting    
     //sensor_i2c_io other parameters
     parameter integer SENSI2C_DRIVE=     12,
     parameter SENSI2C_IBUF_LOW_PWR=      "TRUE",

includes/x393_simulation_parameters.vh

@@ -61,7 +61,7 @@
 //    parameter SENSOR12BITS_NROWA   =     1,   // number of "blank rows" from last hact to end of vact
 //    parameter nAV   =      24,   //240;   // clocks from ARO to VACT (actually from en_dclkd)
 //    parameter SENSOR12BITS_NBPF =       20,   //16; // bpf length
-    parameter SENSOR_IMAGE_TYPE0 =        "RUN1", //"NORM", // "RUN1",
+    parameter SENSOR_IMAGE_TYPE0 =       "RUN1", //"NORM", // "RUN1", "HIST_TEST"
     parameter SENSOR_IMAGE_TYPE1 =       "RUN1",
     parameter SENSOR_IMAGE_TYPE2 =       "RUN1", // "NORM", // "RUN1",
     parameter SENSOR_IMAGE_TYPE3 =       "RUN1",

memctrl/mcntrl393.v

@@ -264,7 +264,7 @@ module  mcntrl393 #(
     parameter MCONTR_LINTILE_COPY_FRAME =     13,  // copy frame number from the master channel (single event, not a persistent mode)
     parameter MCONTR_LINTILE_ABORT_LATE =     14,  // abort frame if not finished by the new frame sync (wait pending memory)
     parameter MCNTRL_SCANLINE_DLY_WIDTH =     12,  // delay start pulse by 1..64 mclk
-    parameter MCNTRL_SCANLINE_DLY_DEFAULT = 63  // initial delay value for start pulse
+    parameter MCNTRL_SCANLINE_DLY_DEFAULT = 1024  // initial delay value for start pulse
     
     ) (
     input                        rst_in,

memctrl/mcntrl_linear_rw.v

@@ -84,7 +84,7 @@ module  mcntrl_linear_rw #(
 // first buffer page, waiting for the request from mcntrl_linear during that first page. And if it will arrive - 
 // just continue.    
     parameter MCNTRL_SCANLINE_DLY_WIDTH =      12,  // delay start pulse by 1..64 mclk
-    parameter MCNTRL_SCANLINE_DLY_DEFAULT =    63  // initial delay value for start pulse
+    parameter MCNTRL_SCANLINE_DLY_DEFAULT =  1024  // initial delay value for start pulse
 )(
     input                          mrst,
     input                          mclk,

py393/x393_export_c.py

@@ -898,8 +898,8 @@ class X393ExportC(object):
         z3z3=(z3,z3)
         sdefines +=[
             (('Windows for histogram subchannels',)),
-            (("X393_HISTOGRAM_LT",                      cs, vrlg.HISTOGRAM_RADDR0 +                         ba, iam, z3z3, "x393_hist_left_top", "rw",          "Specify histograms left/top")),
-            (("X393_HISTOGRAM_WH",                      cs, vrlg.HISTOGRAM_RADDR0 + 1 +                     ba, iam, z3z3, "x393_hist_width_height_m1", "rw",   "Specify histograms width/height")),
+            (("X393_HISTOGRAM_LT",                      cs, vrlg.HISTOGRAM_RADDR0 + vrlg.HISTOGRAM_LEFT_TOP +     ba, iam, z3z3, "x393_hist_left_top", "rw",          "Specify histograms left/top")),
+            (("X393_HISTOGRAM_WH",                      cs, vrlg.HISTOGRAM_RADDR0 + vrlg.HISTOGRAM_WIDTH_HEIGHT + ba, iam, z3z3, "x393_hist_width_height_m1", "rw",   "Specify histograms width/height")),
 ]
         ba = vrlg.SENSOR_GROUP_ADDR
         ia = vrlg.SENSOR_BASE_INC

py393/x393_jpeg.py

@@ -1051,6 +1051,16 @@ setup_all_sensors True None 0x4
 cd /usr/local/verilog/; test_mcntrl.py @hargs-after
 specify_phys_memory
 specify_window
+
+#reset
+write_cmd_frame_sequencer  0  1  2  0x600  0x5    #stop    compressor           `      
+write_cmd_frame_sequencer  0  1  4  0x600  0x4    #reset   reset compressor            (+2)
+write_cmd_frame_sequencer  0  1  4  0x6c0  0x1c48 # reset  reset compressor memory     (+0)
+write_cmd_frame_sequencer  0  1  8  0x6c0  0x3d4b # enable run compressor memory       (+2)
+write_cmd_frame_sequencer  0  1  8  0x600  0x7    # enable run compressor              (+0)
+
+
+
 set_rtc # maybe not needed as it can be set differently
 camsync_setup 0xf # sensor mask - use local timestamps)
 jpeg_write  "img.jpeg" 0 80
@@ -1286,6 +1296,7 @@ killall lighttpd; /usr/sbin/lighttpd -f /etc/lighttpd.conf
 /www/pages/exif.php init=/etc/Exif_template.xml
 
 
+
 setSensorClock 24.0 "2V5_LVDS"
 
 set_rtc # maybe not needed as it can be set differently
@@ -1683,12 +1694,105 @@ write_cmd_frame_sequencer  0  1  1  0x600  0x7    # run compressor
 
 jpeg_sim_multi 12
 
+################## Simulate Parallel 7 ####################
+./py393/test_mcntrl.py @py393/cocoargs  --simulated=localhost:7777
+measure_all "*DI"
+setup_all_sensors True None 0xf
+set_sensor_io_ctl  all None None 1 # Set ARO low - check if it is still needed?
+#just testing
+set_gpio_ports  1 # enable software gpio pins - just for testing. Also needed for legacy i2c!
+set_gpio_pins 0 1 # pin 0 low, pin 1 - high
+
+set_sensor_histogram_window  0  0  4  4  25 21
+set_sensor_histogram_window  1  0  4  4  41 21
+set_sensor_histogram_window  2  0  4  4  25 41
+set_sensor_histogram_window  3  0  4  4  41 41
+r
+read_control_register 0x430
+read_control_register 0x431
+
+#irq coming, image not changing - yes
+write_cmd_frame_sequencer  0  1  1 0x686 0x280005 #save 4 more lines than sensor has                                                                                                                                    
+write_cmd_frame_sequencer  0  1  1 0x680 0x5507 #enable abort
+#write_cmd_frame_sequencer  0  1  1 0x6c6 0x300006 #save 4 more lines that compressor has                                                                                                                                    
+
+write_cmd_frame_sequencer  0  1  2  0x600  0x5    #stop    compressor           `      
+write_cmd_frame_sequencer  0  1  2  0x680  0x5405 # stop  sensor memory         (+0) // sensor memory should be controlled first, (9 commands
+write_cmd_frame_sequencer  0  1  2  0x6c0  0x5c49 # stop compressor memory      (+0)
+
+write_cmd_frame_sequencer  0  1  3 0x686 0x240005 # correct lines                                                                                                   
+write_cmd_frame_sequencer  0  1  3  0x680  0x5507 # run sensor memory           (+1) Can not be 0
+
+write_cmd_frame_sequencer  0  1  4 0x686 0x280005 #save 4 more lines than sensor has                                                                                                                                    
+write_cmd_frame_sequencer  0  1  4 0x6c6 0x300006 #save more lines than compressor needs (sensor provides)                                                                                                                                    
+write_cmd_frame_sequencer  0  1  4  0x6c0  0x7d4b # run compressor memory       (+2)
+write_cmd_frame_sequencer  0  1  4  0x600  0x7    # run compressor              (+0)
+
+read_control_register 0x431
+read_control_register 0x430
+
+#testing histograms
+write_control_register 0x409 0xc0
+
+
+#sequencer test
+#ctrl_cmd_frame_sequencer  <num_sensor>  <reset=False>  <start=False>  <stop=False>
+ctrl_cmd_frame_sequencer   0  0  1  0
+write_cmd_frame_sequencer  0  1  1  0x700  0x6
+write_cmd_frame_sequencer  0  1  1  0x700  0x9
+write_cmd_frame_sequencer  0  1  1  0x700  0xa0
+write_cmd_frame_sequencer  0  1  1  0x700  0x50
+write_cmd_frame_sequencer  0  0  3  0x700  0xa000
+write_cmd_frame_sequencer  0  1  0  0x700  0x90
+write_cmd_frame_sequencer  0  0  2  0x700  0xe00
+write_cmd_frame_sequencer  0  0  3  0x700  0xa
+write_cmd_frame_sequencer  0  0  2  0x700  0x6
+write_cmd_frame_sequencer  0  0  2  0x700  0x9
+write_cmd_frame_sequencer  0  0  2  0x700  0x60
+write_cmd_frame_sequencer  0  0  2  0x700  0x90
+write_cmd_frame_sequencer  0  0  2  0x700  0x600
+write_cmd_frame_sequencer  0  0  2  0x700  0x900
+r
+read_status 0x21
+r
+#set_sensor_io_dly_hispi all 0x48 0x68 0x68 0x68 0x68
+#set_sensor_io_ctl all None None None None None 1 None # load all delays?
+compressor_control  all  None  None  None None None  2
+compressor_interrupt_control all clr
+compressor_interrupt_control all en
+compressor_control  all  3
+r
+read_status 0x21
+r
+jpeg_sim_multi 4
+r
+read_status 0x21
+r
+jpeg_sim_multi 3
+r
+read_status 0x21
+r
+
+
+write_cmd_frame_sequencer  0  1  1 0x686 0x240005 # correct lines                                                                                                   
+write_cmd_frame_sequencer  0  1  1 0x6c6 0x200006 # correct lines                                                                                                                                    
+write_cmd_frame_sequencer  0  1  1  0x680  0x5507 # run sensor memory, update frame#, reset buffers
+write_cmd_frame_sequencer  0  1  1  0x6c0  0x7d4b # run compressor memory
+write_cmd_frame_sequencer  0  1  1  0x600  0x7    # run compressor
+
+jpeg_sim_multi 4
+jpeg_sim_multi 4
+jpeg_sim_multi 4
+
+
 
 
 
 #write_cmd_frame_sequencer  0  1  4  0x6c0  0x1c49 # stop       compressor memory     (+0)
 #write_cmd_frame_sequencer  0  1  6  0x6c0  0x3d4b # enable run compressor memory       (+2)
 
+
+
 ################## Serial ####################
 cd /usr/local/verilog/; test_mcntrl.py @hargs
 bitstream_set_path /usr/local/verilog/x393_hispi.bit

py393/x393_sensor.py

@@ -1858,7 +1858,7 @@ input               mem                 mtd4                ram1
         """
         raddr = (vrlg.HISTOGRAM_RADDR0, vrlg.HISTOGRAM_RADDR1, vrlg.HISTOGRAM_RADDR2, vrlg.HISTOGRAM_RADDR3)
         reg_addr = (vrlg.SENSOR_GROUP_ADDR + num_sensor * vrlg.SENSOR_BASE_INC) + raddr[subchannel & 3]
-        if self.DEBUG_MODE:
+        if self.DEBUG_MODE or True:
             print("set_sensor_histogram_window():")
             print("num_sensor = ", num_sensor)
             print("subchannel = ", subchannel)

sensor/sens_histogram_mux.v

@@ -38,31 +38,39 @@
  */
 `timescale 1ns/1ps
 
-module  sens_histogram_mux(
+module  sens_histogram_mux#(
+    parameter NUM_FRAME_BITS =  4 // number of bits use for frame number 
+)(
     input                       mclk,
     input                       en,
 
     input                       rq0,
+    input  [NUM_FRAME_BITS-1:0] hist_frame0, // frame number matching histogram output
+    
     output                      grant0,
     input                       dav0,
     input                [31:0] din0,
 
     input                       rq1,
+    input  [NUM_FRAME_BITS-1:0] hist_frame1, // frame number matching histogram output
     output                      grant1,
     input                       dav1,
     input                [31:0] din1,
 
     input                       rq2,
+    input  [NUM_FRAME_BITS-1:0] hist_frame2, // frame number matching histogram output
     output                      grant2,
     input                       dav2,
     input                [31:0] din2,
 
     input                       rq3,
+    input  [NUM_FRAME_BITS-1:0] hist_frame3, // frame number matching histogram output
     output                      grant3,
     input                       dav3,
     input                [31:0] din3,
 
     output                      rq,
+    output [NUM_FRAME_BITS-1:0] hist_frame, // frame number matching histogram output
     input                       grant, // grant may stay longer, not masked by rq?
     output                [1:0] chn,
     output                      dv,
@@ -100,6 +108,8 @@ module  sens_histogram_mux(
     assign dav_in =     mux_sel[1] ? (mux_sel[0] ? dav3 :         dav2) :         (mux_sel[0] ? dav1 :         dav0); 
     assign din =        mux_sel[1] ? (mux_sel[0] ? din3 :         din2) :         (mux_sel[0] ? din1 :         din0);
     assign rq_in =      mux_sel[1] ? (mux_sel[0] ? rq3 :          rq2)  :         (mux_sel[0] ? rq1 :          rq0);
+    assign hist_frame = mux_sel[1] ? (mux_sel[0] ? hist_frame3 :  hist_frame2)  : (mux_sel[0] ? hist_frame1 :  hist_frame0);
+     
     assign burst_done_w = dav_out && !dav_in;
     assign chn_start =  {4{start_w}} & {enc_rq[1] & enc_rq[0], enc_rq[1] & ~enc_rq[0], ~enc_rq[1] & enc_rq[0], ~enc_rq[1] & ~enc_rq[0]};
     assign chn_sel =    {mux_sel[1] & mux_sel[0], mux_sel[1] & ~mux_sel[0], ~mux_sel[1] & mux_sel[0], ~mux_sel[1] & ~mux_sel[0]};

sensor/sens_parallel12.v

@@ -144,10 +144,6 @@ module  sens_parallel12 #(
     output  [7:0] status_ad,   // status address/data - up to 5 bytes: A - {seq,status[1:0]} - status[2:9] - status[10:17] - status[18:25]
     output        status_rq,   // input request to send status downstream
     input         status_start // Acknowledge of the first status packet byte (address)
-`ifdef DEBUG_HISTOGRAMS
-    ,input  [7:0] dbg_hist_data
-`endif
-    
 );
 
     // delaying vact and pxd by one clock cycle to match hact register
@@ -251,13 +247,7 @@ module  sens_parallel12 #(
                      xfpgatdo_byte[7:0],
                      vact_alive, hact_ext_alive, hact_alive, locked_pxd_mmcm, 
                      clkin_pxd_stopped_mmcm, clkfb_pxd_stopped_mmcm, xfpgadone,
-                     ps_rdy,
-`ifdef DEBUG_HISTOGRAMS
-                     dbg_hist_data,
-`else
                      ps_out,
-`endif
-                     
                      xfpgatdo, senspgmin};
                         
     assign hact_out = hact_r;

sensor/sensors393.v

@@ -456,6 +456,7 @@ module  sensors393 #(
     wire           [127:0] hist_data;
     
     wire  [4*NUM_FRAME_BITS-1:0] frame_num = {frame_num3, frame_num2, frame_num1, frame_num0};
+    wire  [4*NUM_FRAME_BITS-1:0] hist_frame; // frame numbers of the histogram outputs
      
      
      
@@ -708,6 +709,8 @@ module  sensors393 #(
                 .sof_out_mclk (sof_out_mclk[i]),       // output
                 .sof_late_mclk(sof_late_mclk[i]),      // output
                 .hist_request (hist_request[i]),       // output
+                .hist_frame   (hist_frame[NUM_FRAME_BITS*i +:NUM_FRAME_BITS]), // output[3:0] 
+                
                 .hist_grant   (hist_grant[i]),         // input
                 .hist_chn     (hist_chn[2 * i +: 2]),  // output[1:0] 
                 .hist_dvalid  (hist_dvalid[i]),        // output
@@ -758,35 +761,34 @@ module  sensors393 #(
                 ,.DEBUG_CMD_LATENCY   (DEBUG_CMD_LATENCY) 
 `endif        
     ) histogram_saxi_i (
-//        .rst            (rst),                    // input
         .mclk           (mclk),                                          // input
         .aclk           (aclk),                                          // input
         .mrst           (mrst),                                          // input
         .arst           (arst),                                          // input
-        .frame0         (frame_num0),             // input[3:0] 
+        .frame0         (hist_frame[NUM_FRAME_BITS*0 +:NUM_FRAME_BITS]), // input[3:0] 
         .hist_request0  (hist_request[0]),                               // input
         .hist_grant0    (hist_grant[0]),                                 // output
         .hist_chn0      (hist_chn[0 * 2 +: 2]),                          // input[1:0] 
         .hist_dvalid0   (hist_dvalid[0]),                                // input
-        .hist_data0     (hist_data[0 * 32 +: 32]),// input[31:0] 
-        .frame1         (frame_num1),             // input[3:0] 
+        .hist_data0     (hist_data[0 * 32 +: 32]),                       // input[31:0] 
+        .frame1         (hist_frame[NUM_FRAME_BITS*1 +:NUM_FRAME_BITS]), // input[3:0] 
         .hist_request1  (hist_request[1]),                               // input
         .hist_grant1    (hist_grant[1]),                                 // output
         .hist_chn1      (hist_chn[1 * 2 +: 2]),                          // input[1:0] 
         .hist_dvalid1   (hist_dvalid[1]),                                // input
-        .hist_data1     (hist_data[1 * 32 +: 32]),// input[31:0] 
-        .frame2         (frame_num2),             // input[3:0] 
+        .hist_data1     (hist_data[1 * 32 +: 32]),                       // input[31:0] 
+        .frame2         (hist_frame[NUM_FRAME_BITS*2 +:NUM_FRAME_BITS]), // input[3:0] 
         .hist_request2  (hist_request[2]),                               // input
         .hist_grant2    (hist_grant[2]),                                 // output
         .hist_chn2      (hist_chn[2 * 2 +: 2]),                          // input[1:0]
         .hist_dvalid2   (hist_dvalid[2]),                                // input
-        .hist_data2     (hist_data[2 * 32 +: 32]),// input[31:0] 
-        .frame3         (frame_num3),             // input[3:0] 
+        .hist_data2     (hist_data[2 * 32 +: 32]),                       // input[31:0] 
+        .frame3         (hist_frame[NUM_FRAME_BITS*3 +:NUM_FRAME_BITS]), // input[3:0] 
         .hist_request3  (hist_request[3]),                               // input
         .hist_grant3    (hist_grant[3]),                                 // output
         .hist_chn3      (hist_chn[3 * 2 +: 2]),                          // input[1:0]
         .hist_dvalid3   (hist_dvalid[3]),                                // input
-        .hist_data3     (hist_data[3 * 32 +: 32]),// input[31:0] 
+        .hist_data3     (hist_data[3 * 32 +: 32]),                       // input[31:0] 
         .cmd_ad         (cmd_ad),                                        // input[7:0] 
         .cmd_stb        (cmd_stb),                                       // input
         .saxi_awaddr    (saxi_awaddr),                                   // output[31:0] 

simulation_modules/simul_sensor12bits.v

@@ -172,6 +172,7 @@ initial begin
 //  reg   [15:0]   sensor_data[0:4095]; // up to 64 x 64 pixels
     if      (SENSOR_IMAGE_TYPE == "NORM")      $readmemh({`ROOTPATH,"/input_data/sensor.dat"},sensor_data);
     else if (SENSOR_IMAGE_TYPE == "RUN1")      $readmemh({`ROOTPATH,"/input_data/sensor_run1.dat"},sensor_data);
+    else if (SENSOR_IMAGE_TYPE == "HIST_TEST") $readmemh({`ROOTPATH,"/input_data/sensor_hist_test.dat"},sensor_data);
     else begin
        $display ("WARNING: Unrecognized sensor image :'%s', using default 'NORM': input_data/sensor.dat",SENSOR_IMAGE_TYPE);
        $readmemh({`ROOTPATH,"/input_data/sensor.dat"},sensor_data);