adjusting constraint attributes in the source

.project

@@ -62,77 +62,77 @@
 		<link>
 			<name>vivado_logs/VivadoBitstream.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150722181016920.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20150723175509485.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoOpt.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150722181016920.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20150723175509485.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoOptPhys.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150722181016920.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20150723175509485.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoOptPower.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150722181016920.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20150723175509485.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoPlace.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150722181016920.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20150723175509485.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoRoute.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150722181016920.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20150723175509485.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoSynthesis.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150722180528066.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20150723174740723.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150722181016920.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20150723175509485.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20150722180528066.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportSynthesis-20150723175509485.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimingReportImplemented.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150722181016920.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportImplemented-20150723175509485.log</location>
 		</link>
 		<link>
 			<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150722180528066.log</location>
+			<location>/home/andrey/git/x393/vivado_logs/VivadoTimingReportSynthesis-20150723175509485.log</location>
 		</link>
 		<link>
 			<name>vivado_state/x393-opt-phys.dcp</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_state/x393-opt-phys-20150722181016920.dcp</location>
+			<location>/home/andrey/git/x393/vivado_state/x393-opt-phys-20150723175509485.dcp</location>
 		</link>
 		<link>
 			<name>vivado_state/x393-place.dcp</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_state/x393-place-20150722181016920.dcp</location>
+			<location>/home/andrey/git/x393/vivado_state/x393-place-20150723175509485.dcp</location>
 		</link>
 		<link>
 			<name>vivado_state/x393-route.dcp</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_state/x393-route-20150722181016920.dcp</location>
+			<location>/home/andrey/git/x393/vivado_state/x393-route-20150723175509485.dcp</location>
 		</link>
 		<link>
 			<name>vivado_state/x393-synth.dcp</name>
 			<type>1</type>
-			<location>/home/andrey/git/x393/vivado_state/x393-synth-20150722180528066.dcp</location>
+			<location>/home/andrey/git/x393/vivado_state/x393-synth-20150723174740723.dcp</location>
 		</link>
 	</linkedResources>
 </projectDescription>

.settings/com.elphel.vdt.VivadoSynthesis.prefs

@@ -4,6 +4,6 @@ VivadoSynthesis_115_flatten_hierarchy=none
 VivadoSynthesis_127_verbose=true
 VivadoSynthesis_81_parser_mode=1
 VivadoSynthesis_93_OtherProblems=Netlist 29-345<-@\#\#@->Board 49-26<-@\#\#@->
-VivadoSynthesis_95_ShowInfo=true
+VivadoSynthesis_95_ShowInfo=false
 com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->VivadoSynthesis_115_flatten_hierarchy<-@\#\#@->VivadoSynthesis_101_MaxMsg<-@\#\#@->VivadoSynthesis_127_verbose<-@\#\#@->VivadoSynthesis_93_OtherProblems<-@\#\#@->VivadoSynthesis_81_parser_mode<-@\#\#@->
 eclipse.preferences.version=1

compressor_jp/huffman393.v

@@ -35,12 +35,6 @@ module huffman393    (
     input             tser_a_not_d, // address/not data distributed to submodules
     input      [ 7:0] tser_d,       // byte-wide serialized tables address/data to submodules
     
-//    input             sclk,            // clock to write tables (NOW posgedge) AF2015
-//    input             twe,             // enable write to a table - now the following will be valid ant negedge sclk
-//    input       [8:0] ta,              // [8:0]  table address
-//    input      [15:0] tdi,             // [15:0] table data in
-    
-    
     input      [15:0] di,              // [15:0]    specially RLL prepared 16-bit data (to FIFO) (sync to xclk)
     input             ds,              // di valid strobe  (sync to xclk)
     input             rdy,             // receiver (bit stuffer) is ready to accept data
@@ -50,41 +44,31 @@ module huffman393    (
     output reg        flush,           // last block done - flush the rest bits
     output reg        last_block,
     output reg        test_lbw,
-    output            gotLastBlock);   // last block done - flush the rest bits
-/*
-  huffman i_huffman  (.pclk(clk),      // pixel clock
-                      .clk(clk2x),     // twice frequency - uses negedge inside
-                      .en(cmprs_en),      // enable (0 resets counter) sync to .pclk(clk)
-                      .twe(twhe),      // enable write to a table
-                      .ta(ta[8:0]),      // [8:0]  table address
-                      .tdi(di[15:0]),      // [23:0] table data in (8 LSBs - quantization data, [13:9] zigzag address
-                      .di(enc_do[15:0]),      // [15:0]   specially RLL prepared 16-bit data (to FIFO)
-                      .ds(enc_dv),      // di valid strobe
-                      .rdy(stuffer_rdy),      // receiver (bit stuffer) is ready to accept data
-                      .do(huff_do),      // [15:0]   output data
-                      .dl(huff_dl),      // [3:0]   output width (0==16)
-                      .dv(huff_dv),      // output data bvalid
-                     .flush(flush),
-                     .last_block(last_block),
-                     .test_lbw(),
-                     .gotLastBlock(test_lbw));   // last block done - flush the rest bits
-
-                     
-*/
-
-    wire   [31:0] tables_out; // Only [19:0] are used
+    output            gotLastBlock   // last block done - flush the rest bits
+);
+`ifdef INFER_LATCHES
     reg    [15:0] hcode_latch;    // table output huffman code (1..16 bits)
     reg    [ 3:0] hlen_latch;        // table - code length only 4 LSBs are used
+    reg    [ 7:0] haddr70_latch;
+    reg           haddr8_latch;
+    reg           tables_re_latch;
+    reg           stuffer_was_rdy_early_latch;
+`else
+    wire   [15:0] hcode_latch;    // table output huffman code (1..16 bits)
+    wire   [ 3:0] hlen_latch;        // table - code length only 4 LSBs are used
+    wire   [ 7:0] haddr70_latch;
+    wire          haddr8_latch;
+    wire          tables_re_latch;
+    wire          stuffer_was_rdy_early_latch;
+`endif
+    wire   [31:0] tables_out; // Only [19:0] are used
     reg    [ 7:0] haddr_r;    // index in huffman table    
     wire   [ 7:0] haddr_next;
 
-    reg    [ 7:0] haddr70_latch;
-    reg           haddr8_latch;
     wire   [ 8:0] haddr = {haddr8_latch,haddr70_latch};    // index in huffman table     (after latches)
      
     wire   [15:0] fifo_o;
     reg           stuffer_was_rdy;
-    reg           tables_re_latch;
     wire          read_next;    // assigned depending on steps (each other cycle for normal codes, each for special 00/F0
 
     reg     [5:0] steps;
@@ -148,14 +132,7 @@ module huffman393    (
     assign gotColor= fifo_o[13];
 
     always @(negedge xclk2x) stuffer_was_rdy <= !en2x || rdy; // stuffer ready shoud be on if !en (move to register?)for now]
-    reg           stuffer_was_rdy_early_latch;
     wire          want_read_early;
-/*    
-  LD  i_stuffer_was_rdy_early (.Q(stuffer_was_rdy_early_latch),.G(xclk2x),.D(!en2x || rdy));
-  LD  i_tables_re (.Q(tables_re_latch),.G(xclk2x),.D(en2x && rdy));
-*/  
-    always @* if (xclk2x) stuffer_was_rdy_early_latch <= !en2x || rdy;
-    always @* if (xclk2x) tables_re_latch <= en2x && rdy;
    
 
 
@@ -210,18 +187,18 @@ module huffman393    (
     always @ (negedge xclk2x) if (stuffer_was_rdy && steps[2]) begin    // may be just if (stuffer_was_rdy)
         haddr_r[7:0]    <= haddr_next[7:0];
     end
-/*  
-  LD  i_haddr_8 (.Q(haddr[8]),.G(xclk2x),.D(stuffer_was_rdy?tbsel_YC2:tbsel_YC3));
-  LD  i_haddr_7 (.Q(haddr[7]),.G(xclk2x),.D((stuffer_was_rdy && steps[2])?haddr_next[7]:haddr_r[7]));
-  LD  i_haddr_6 (.Q(haddr[6]),.G(xclk2x),.D((stuffer_was_rdy && steps[2])?haddr_next[6]:haddr_r[6]));
-  LD  i_haddr_5 (.Q(haddr[5]),.G(xclk2x),.D((stuffer_was_rdy && steps[2])?haddr_next[5]:haddr_r[5]));
-  LD  i_haddr_4 (.Q(haddr[4]),.G(xclk2x),.D((stuffer_was_rdy && steps[2])?haddr_next[4]:haddr_r[4]));
-  LD  i_haddr_3 (.Q(haddr[3]),.G(xclk2x),.D((stuffer_was_rdy && steps[2])?haddr_next[3]:haddr_r[3]));
-  LD  i_haddr_2 (.Q(haddr[2]),.G(xclk2x),.D((stuffer_was_rdy && steps[2])?haddr_next[2]:haddr_r[2]));
-  LD  i_haddr_1 (.Q(haddr[1]),.G(xclk2x),.D((stuffer_was_rdy && steps[2])?haddr_next[1]:haddr_r[1]));
-  LD  i_haddr_0 (.Q(haddr[0]),.G(xclk2x),.D((stuffer_was_rdy && steps[2])?haddr_next[0]:haddr_r[0]));
-*/
-//     wire   [ 8:0] haddr = {haddr8_latch,haddr70_latch};    // index in huffman table     (after latches)
+
+
+    assign pre_dv =         steps[4] || (steps[5] && (var_dl_late[3:0]!=4'b0));
+    assign pre_bits[15:0]    = steps[5]?{5'b0,var_do[10:0]}:     hcode_latch[15:0];
+    assign pre_len [ 3:0]    = steps[5]?      var_dl_late[ 3:0]: hlen_latch  [3:0];
+
+`ifdef INFER_LATCHES
+    always @* if (~xclk2x) hlen_latch <=  tables_out[19:16];
+    always @* if (~xclk2x) hcode_latch <= tables_out[15:0];
+    always @* if (xclk2x)  stuffer_was_rdy_early_latch <= !en2x || rdy;
+    always @* if (xclk2x)  tables_re_latch <= en2x && rdy;
+
     always @* if (xclk2x) begin
         if (stuffer_was_rdy) haddr8_latch <= tbsel_YC2;
         else                 haddr8_latch <= tbsel_YC3;
@@ -232,10 +209,86 @@ module huffman393    (
         else                             haddr70_latch <= haddr_r;
     end
 
+`else
+    latch_g_ce #(
+        .WIDTH           (4),
+        .INIT            (0),
+        .IS_CLR_INVERTED (0),
+        .IS_G_INVERTED   (1) // inverted!
+    ) latch_hlen_i (
+        .rst     (1'b0),               // input
+        .g       (xclk2x),             // input
+        .ce      (1'b1),               // input
+        .d_in    (tables_out[19:16]),  // input[0:0] 
+        .q_out   (hlen_latch)          // output[0:0] 
+    );
+
+    latch_g_ce #(
+        .WIDTH           (16),
+        .INIT            (0),
+        .IS_CLR_INVERTED (0),
+        .IS_G_INVERTED   (1) // inverted!
+    ) latch_hcode_i (
+        .rst     (1'b0),               // input
+        .g       (xclk2x),             // input
+        .ce      (1'b1),               // input
+        .d_in    (tables_out[15:0]),   // input[0:0] 
+        .q_out   (hcode_latch)         // output[0:0] 
+    );
+
+    latch_g_ce #(
+        .WIDTH           (1),
+        .INIT            (0),
+        .IS_CLR_INVERTED (0),
+        .IS_G_INVERTED   (0) // non-inverted!
+    ) latch_stuffer_was_rdy_early_i (
+        .rst     (1'b0),                        // input
+        .g       (xclk2x),                      // input
+        .ce      (1'b1),                        // input
+        .d_in    (!en2x || rdy),                // input[0:0] 
+        .q_out   (stuffer_was_rdy_early_latch)  // output[0:0] 
+    );
+
+    latch_g_ce #(
+        .WIDTH           (1),
+        .INIT            (0),
+        .IS_CLR_INVERTED (0),
+        .IS_G_INVERTED   (0) // non-inverted!
+    ) latch_tables_re_i (
+        .rst     (1'b0),                        // input
+        .g       (xclk2x),                      // input
+        .ce      (1'b1),                        // input
+        .d_in    (en2x && rdy),                 // input[0:0] 
+        .q_out   (tables_re_latch)              // output[0:0] 
+    );
+
+    latch_g_ce #(
+        .WIDTH           (1),
+        .INIT            (0),
+        .IS_CLR_INVERTED (0),
+        .IS_G_INVERTED   (0) // non-inverted!
+    ) latch_haddr8_re_i (
+        .rst     (1'b0),                        // input
+        .g       (xclk2x),                      // input
+        .ce      (1'b1),                        // input
+        .d_in    (stuffer_was_rdy ? tbsel_YC2 : tbsel_YC3), // input[0:0] 
+        .q_out   (haddr8_latch)              // output[0:0] 
+    );
+
+    latch_g_ce #(
+        .WIDTH           (8),
+        .INIT            (0),
+        .IS_CLR_INVERTED (0),
+        .IS_G_INVERTED   (0) // non-inverted!
+    ) latch_haddr70_re_i (
+        .rst     (1'b0),                        // input
+        .g       (xclk2x),                      // input
+        .ce      (1'b1),                        // input
+        .d_in    ((stuffer_was_rdy && steps[2]) ? haddr_next : haddr_r), // input[0:0] 
+        .q_out   (haddr70_latch)              // output[0:0] 
+    );
+`endif
 
-    assign pre_dv =         steps[4] || (steps[5] && (var_dl_late[3:0]!=4'b0));
-    assign pre_bits[15:0]    = steps[5]?{5'b0,var_do[10:0]}:     hcode_latch[15:0];
-    assign pre_len [ 3:0]    = steps[5]?      var_dl_late[ 3:0]: hlen_latch  [3:0];
 
     always @ (negedge xclk2x) if (stuffer_was_rdy) begin
         dv0            <= pre_dv;
@@ -263,30 +316,7 @@ module huffman393    (
         tbsel_YC2      <= tbsel_YC1;
         tbsel_YC3      <= tbsel_YC2;
     end
-  /*
-  LD_1 i_hlen3  (.Q( hlen_latch[ 3]),.G(xclk2x),.D(tables_out[19]));  
-  LD_1 i_hlen2  (.Q( hlen_latch[ 2]),.G(xclk2x),.D(tables_out[18]));  
-  LD_1 i_hlen1  (.Q( hlen_latch[ 1]),.G(xclk2x),.D(tables_out[17]));  
-  LD_1 i_hlen0  (.Q( hlen_latch[ 0]),.G(xclk2x),.D(tables_out[16]));  
-  LD_1 i_hcode15(.Q(hcode_latch[15]),.G(xclk2x),.D(tables_out[15]));  
-  LD_1 i_hcode14(.Q(hcode_latch[14]),.G(xclk2x),.D(tables_out[14]));  
-  LD_1 i_hcode13(.Q(hcode_latch[13]),.G(xclk2x),.D(tables_out[13]));  
-  LD_1 i_hcode12(.Q(hcode_latch[12]),.G(xclk2x),.D(tables_out[12]));  
-  LD_1 i_hcode11(.Q(hcode_latch[11]),.G(xclk2x),.D(tables_out[11]));  
-  LD_1 i_hcode10(.Q(hcode_latch[10]),.G(xclk2x),.D(tables_out[10]));  
-  LD_1 i_hcode9 (.Q(hcode_latch[ 9]),.G(xclk2x),.D(tables_out[ 9]));  
-  LD_1 i_hcode8 (.Q(hcode_latch[ 8]),.G(xclk2x),.D(tables_out[ 8]));  
-  LD_1 i_hcode7 (.Q(hcode_latch[ 7]),.G(xclk2x),.D(tables_out[ 7]));  
-  LD_1 i_hcode6 (.Q(hcode_latch[ 6]),.G(xclk2x),.D(tables_out[ 6]));  
-  LD_1 i_hcode5 (.Q(hcode_latch[ 5]),.G(xclk2x),.D(tables_out[ 5]));  
-  LD_1 i_hcode4 (.Q(hcode_latch[ 4]),.G(xclk2x),.D(tables_out[ 4]));  
-  LD_1 i_hcode3 (.Q(hcode_latch[ 3]),.G(xclk2x),.D(tables_out[ 3]));  
-  LD_1 i_hcode2 (.Q(hcode_latch[ 2]),.G(xclk2x),.D(tables_out[ 2]));  
-  LD_1 i_hcode1 (.Q(hcode_latch[ 1]),.G(xclk2x),.D(tables_out[ 1]));  
-  LD_1 i_hcode0 (.Q(hcode_latch[ 0]),.G(xclk2x),.D(tables_out[ 0]));  
-*/  
-    always @* if (~xclk2x) hlen_latch <=  tables_out[19:16];
-    always @* if (~xclk2x) hcode_latch <= tables_out[15:0];
+   
     
     wire          twe;
     wire  [15:0]  tdi;

memctrl/cmd_encod_linear_mux.v

@@ -436,7 +436,7 @@ module  cmd_encod_linear_mux#(
     ;
 
     `ifdef def_scanline_chn0
-        wire start0=0 |
+        wire start0=0
         `ifdef def_read_mem_chn0
             | start0_rd
         `endif
@@ -446,7 +446,7 @@ module  cmd_encod_linear_mux#(
         ;
     `endif
     `ifdef def_scanline_chn1
-        wire start1=0 |
+        wire start1=0
         `ifdef def_read_mem_chn1
             | start1_rd
         `endif
@@ -456,7 +456,7 @@ module  cmd_encod_linear_mux#(
         ;
     `endif
     `ifdef def_scanline_chn2
-        wire start2=0 |
+        wire start2=0
         `ifdef def_read_mem_chn2
             | start2_rd
         `endif
@@ -466,7 +466,7 @@ module  cmd_encod_linear_mux#(
         ;
     `endif
     `ifdef def_scanline_chn3
-        wire start3=0 |
+        wire start3=0
         `ifdef def_read_mem_chn3
             | start3_rd
         `endif
@@ -476,7 +476,7 @@ module  cmd_encod_linear_mux#(
         ;
     `endif
     `ifdef def_scanline_chn4
-        wire start4=0 |
+        wire start4=0
         `ifdef def_read_mem_chn4
             | start4_rd
         `endif
@@ -486,7 +486,7 @@ module  cmd_encod_linear_mux#(
         ;
     `endif
     `ifdef def_scanline_chn5
-        wire start5=0 |
+        wire start5=0
         `ifdef def_read_mem_chn5
             | start5_rd
         `endif
@@ -496,7 +496,7 @@ module  cmd_encod_linear_mux#(
         ;
     `endif
     `ifdef def_scanline_chn6
-        wire start6=0 |
+        wire start6=0
         `ifdef def_read_mem_chn6
             | start6_rd
         `endif
@@ -506,7 +506,7 @@ module  cmd_encod_linear_mux#(
         ;
     `endif
     `ifdef def_scanline_chn7
-        wire start7=0 |
+        wire start7=0
         `ifdef def_read_mem_chn7
             | start7_rd
         `endif
@@ -516,7 +516,7 @@ module  cmd_encod_linear_mux#(
         ;
     `endif
     `ifdef def_scanline_chn8
-        wire start8=0 |
+        wire start8=0
         `ifdef def_read_mem_chn8
             | start8_rd
         `endif
@@ -526,7 +526,7 @@ module  cmd_encod_linear_mux#(
         ;
     `endif
     `ifdef def_scanline_chn9
-        wire start9=0 |
+        wire start9=0
         `ifdef def_read_mem_chn9
             | start9_rd
         `endif
@@ -536,7 +536,7 @@ module  cmd_encod_linear_mux#(
         ;
     `endif
     `ifdef def_scanline_chn10
-        wire start10=0 |
+        wire start10=0
         `ifdef def_read_mem_chn10
             | start10_rd
         `endif
@@ -546,7 +546,7 @@ module  cmd_encod_linear_mux#(
         ;
     `endif
     `ifdef def_scanline_chn11
-        wire start11=0 |
+        wire start11=0
         `ifdef def_read_mem_chn11
             | start11_rd
         `endif
@@ -556,7 +556,7 @@ module  cmd_encod_linear_mux#(
         ;
     `endif
     `ifdef def_scanline_chn12
-        wire start12=0 |
+        wire start12=0
         `ifdef def_read_mem_chn12
             | start12_rd
         `endif
@@ -566,7 +566,7 @@ module  cmd_encod_linear_mux#(
         ;
     `endif
     `ifdef def_scanline_chn13
-        wire start13=0 |
+        wire start13=0
         `ifdef def_read_mem_chn13
             | start13_rd
         `endif
@@ -576,7 +576,7 @@ module  cmd_encod_linear_mux#(
         ;
     `endif
     `ifdef def_scanline_chn14
-        wire start14=0 |
+        wire start14=0
         `ifdef def_read_mem_chn14
             | start14_rd
         `endif
@@ -586,7 +586,7 @@ module  cmd_encod_linear_mux#(
         ;
     `endif
     `ifdef def_scanline_chn15
-        wire start15=0 |
+        wire start15=0
         `ifdef def_read_mem_chn15
             | start15_rd
         `endif

memctrl/cmd_encod_tiled_mux.v

@@ -539,7 +539,7 @@ module  cmd_encod_tiled_mux #(
     ;
 
     `ifdef def_tiled_chn0
-        wire start0=0 |
+        wire start0=0
         `ifdef def_read_mem_chn0
             | start0_rd | start0_rd32
         `endif
@@ -549,7 +549,7 @@ module  cmd_encod_tiled_mux #(
         ;
     `endif
     `ifdef def_tiled_chn1
-        wire start1=0 |
+        wire start1=0
         `ifdef def_read_mem_chn1
             | start1_rd | start1_rd32
         `endif
@@ -559,7 +559,7 @@ module  cmd_encod_tiled_mux #(
         ;
     `endif
     `ifdef def_tiled_chn2
-        wire start2=0 |
+        wire start2=0
         `ifdef def_read_mem_chn2
             | start2_rd | start2_rd32
         `endif
@@ -569,7 +569,7 @@ module  cmd_encod_tiled_mux #(
         ;
     `endif
     `ifdef def_tiled_chn3
-        wire start3=0 |
+        wire start3=0
         `ifdef def_read_mem_chn3
             | start3_rd | start3_rd32
         `endif
@@ -579,7 +579,7 @@ module  cmd_encod_tiled_mux #(
         ;
     `endif
     `ifdef def_tiled_chn4
-        wire start4=0 |
+        wire start4=0
         `ifdef def_read_mem_chn4
             | start4_rd | start4_rd32
         `endif
@@ -589,7 +589,7 @@ module  cmd_encod_tiled_mux #(
         ;
     `endif
     `ifdef def_tiled_chn5
-        wire start5=0 |
+        wire start5=0
         `ifdef def_read_mem_chn5
             | start5_rd | start5_rd32
         `endif
@@ -599,7 +599,7 @@ module  cmd_encod_tiled_mux #(
         ;
     `endif
     `ifdef def_tiled_chn6
-        wire start6=0 |
+        wire start6=0
         `ifdef def_read_mem_chn6
             | start6_rd | start6_rd32
         `endif
@@ -609,7 +609,7 @@ module  cmd_encod_tiled_mux #(
         ;
     `endif
     `ifdef def_tiled_chn7
-        wire start7=0 |
+        wire start7=0
         `ifdef def_read_mem_chn7
             | start7_rd | start7_rd32
         `endif
@@ -619,7 +619,7 @@ module  cmd_encod_tiled_mux #(
         ;
     `endif
     `ifdef def_tiled_chn8
-        wire start8=0 |
+        wire start8=0
         `ifdef def_read_mem_chn8
             | start8_rd | start8_rd32
         `endif
@@ -629,7 +629,7 @@ module  cmd_encod_tiled_mux #(
         ;
     `endif
     `ifdef def_tiled_chn9
-        wire start9=0 |
+        wire start9=0
         `ifdef def_read_mem_chn9
             | start9_rd | start9_rd32
         `endif
@@ -639,7 +639,7 @@ module  cmd_encod_tiled_mux #(
         ;
     `endif
     `ifdef def_tiled_chn10
-        wire start10=0 |
+        wire start10=0
         `ifdef def_read_mem_chn10
             | start10_rd | start10_rd32
         `endif
@@ -649,7 +649,7 @@ module  cmd_encod_tiled_mux #(
         ;
     `endif
     `ifdef def_tiled_chn11
-        wire start11=0 |
+        wire start11=0
         `ifdef def_read_mem_chn11
             | start11_rd | start11_rd32
         `endif
@@ -659,7 +659,7 @@ module  cmd_encod_tiled_mux #(
         ;
     `endif
     `ifdef def_tiled_chn12
-        wire start12=0 |
+        wire start12=0
         `ifdef def_read_mem_chn12
             | start12_rd | start12_rd32
         `endif
@@ -669,7 +669,7 @@ module  cmd_encod_tiled_mux #(
         ;
     `endif
     `ifdef def_tiled_chn13
-        wire start13=0 |
+        wire start13=0
         `ifdef def_read_mem_chn13
             | start13_rd | start13_rd32
         `endif
@@ -679,7 +679,7 @@ module  cmd_encod_tiled_mux #(
         ;
     `endif
     `ifdef def_tiled_chn14
-        wire start14=0 |
+        wire start14=0
         `ifdef def_read_mem_chn14
             | start14_rd | start14_rd32
         `endif
@@ -689,7 +689,7 @@ module  cmd_encod_tiled_mux #(
         ;
     `endif
     `ifdef def_tiled_chn15
-        wire start15=0 |
+        wire start15=0
         `ifdef def_read_mem_chn15
             | start15_rd | start15_rd32
         `endif

memctrl/mcntrl_linear_rw.v

@@ -96,7 +96,10 @@ module  mcntrl_linear_rw #(
 // WARNING: [Synth 8-3936] Found unconnected internal register 'frame_y_reg' and it is trimmed from '16' to '3' bits. [memctrl/mcntrl_linear_rw.v:268]
 // Throblem seems to be that frame_y8_r_reg (load of trimmed bits of the frame_y_reg) is (as intended) absorbed into DSP48. The lower 3 bits are used
 // outside of the DSP 48.  "dont_touch" seems to work here
- (* keep = "true" *) reg   [FRAME_HEIGHT_BITS-1:0] frame_y;     // current line number referenced to the frame top
+`ifndef IGNORE_ATTR
+    (* keep = "true" *)
+`endif    
+    reg   [FRAME_HEIGHT_BITS-1:0] frame_y;     // current line number referenced to the frame top
     reg    [FRAME_WIDTH_BITS-1:0] frame_x;     // current column number referenced to the frame left
     reg   [FRAME_HEIGHT_BITS-4:0] frame_y8_r;  // (13 bits) current row with bank removed, latency2 (to be absorbed when inferred DSP multipler)
     reg      [FRAME_WIDTH_BITS:0] frame_full_width_r;  // (14 bit) register to be absorbed by MPY

memctrl/mcntrl_tiled_rw.v

@@ -110,7 +110,10 @@ module  mcntrl_tiled_rw#(
 //WARNING: [Synth 8-3936] Found unconnected internal register 'frame_y_reg' and it is trimmed from '16' to '3' bits. [memctrl/mcntrl_tiled_rw.v:307]
 // Throblem seems to be that frame_y8_r_reg (load of trimmed bits of the frame_y_reg) is (as intended) absorbed into DSP48. The lower 3 bits are used
 // outside of the DSP 48.  "dont_touch" seems to work here
-(* keep = "true" *) reg   [FRAME_HEIGHT_BITS-1:0] frame_y;     // current line number referenced to the frame top
+`ifndef IGNORE_ATTR
+    (* keep = "true" *)
+`endif    
+    reg   [FRAME_HEIGHT_BITS-1:0] frame_y;     // current line number referenced to the frame top
     reg    [FRAME_WIDTH_BITS-1:0] frame_x;     // current column number referenced to the frame left
     reg   [FRAME_HEIGHT_BITS-4:0] frame_y8_r;  // (13 bits) current row with bank removed, latency2 (to be absorbed when inferred DSP multipler)
     reg      [FRAME_WIDTH_BITS:0] frame_full_width_r;  // (14 bit) register to be absorbed by MPY

memctrl/phy/byte_lane.v

@@ -55,15 +55,26 @@ module  byte_lane #(
     input         set              // clk_div synchronous set all delays from previously loaded values
 );
 
-//(* CLOCK_DEDICATED_ROUTE = "FALSE" *)  // does not seem to work
 wire dqs_read;
 wire  iclk;         // source-synchronous clock (BUFR from DQS)
 reg  [31:0] din_r=0;
 // Preventing register removal of equivalent registers
- (* keep = "true" *) reg  [3:0] din_dm_r=0, din_dqs_r=0, tin_dq_r=4'hf, tin_dqs_r=4'hf;
- (* keep = "true" *) reg  [7:0] dly_data_r=0; 
- (* keep = "true" *) reg        set_r=0;
- (* keep = "true" *) reg  dci_disable_dqs_r, dci_disable_dq_r;
+`ifndef IGNORE_ATTR
+    (* keep = "true" *)
+`endif    
+reg  [3:0] din_dm_r=0, din_dqs_r=0, tin_dq_r=4'hf, tin_dqs_r=4'hf;
+`ifndef IGNORE_ATTR
+    (* keep = "true" *)
+`endif    
+reg  [7:0] dly_data_r=0; 
+`ifndef IGNORE_ATTR
+    (* keep = "true" *)
+`endif    
+reg        set_r=0;
+`ifndef IGNORE_ATTR
+    (* keep = "true" *)
+`endif    
+reg  dci_disable_dqs_r, dci_disable_dq_r;
 reg  [7:0] ld_odly=8'b0, ld_idly=8'b0;
 reg        ld_odly_dqs,ld_idly_dqs,ld_odly_dm;
 BUFR                          iclk_i    (.O(iclk),.I(dqs_read), .CLR(1'b0),.CE(1'b1)); // OK, works with constraint? Seems now work w/o

memctrl/phy/cmd_addr.v

@@ -61,8 +61,14 @@ reg  [1:0] in_we_r=2'h3, in_ras_r=2'h3, in_cas_r=2'h3, in_cke_r=2'h3, in_odt_r=2
 //reg  [1:0] in_tri_r=2'h0; // or tri-state on reset?
 reg  in_tri_r=1'b1; // or tri-state on reset?
 // Preventing register duplication
- (* keep = "true" *) reg  [7:0] dly_data_r=0; 
- (* keep = "true" *) reg        set_r=0;
+ `ifndef IGNORE_ATTR
+    (* keep = "true" *)
+`endif    
+reg  [7:0] dly_data_r=0; 
+`ifndef IGNORE_ATTR
+    (* keep = "true" *)
+`endif    
+reg        set_r=0;
 reg  [7:0] ld_dly_cmd=8'b0;
 reg  [ADDRESS_NUMBER-1:0] ld_dly_addr=0;
 //wire  [ADDRESS_NUMBER-1:0] decode_addr;

memctrl/phy/dq_single.v

@@ -51,7 +51,6 @@ wire dq_tri;
 wire dq_data_dly;
 wire dq_dly;
 // keep IOBUF_DCIEN.O to user as output only (UDM/LDM), so the rest of tyhe read channel will be optimized out, but I/O will stay the same
-//(* keep = "true" *)
 wire dq_di;
 
 

system_defines.vh

@@ -5,6 +5,8 @@
  `define SHREG_SEQUENTIAL_RESET 1
 // synthesis does to recognize global clock as G input of the primitive latch 
  `undef INFER_LATCHES
+ // define when using CDC - it does not support them
+ `undef IGNORE_ATTR
 //`define MEMBRIDGE_DEBUG_READ 1
   `define use200Mhz 1
   `define USE_CMD_ENCOD_TILED_32_RD 1  

util_modules/level_cross_clocks.v

@@ -28,11 +28,77 @@ module  level_cross_clocks#(
     input  [WIDTH-1:0] d_in,
     output [WIDTH-1:0] d_out
 );
+    generate
+        genvar i;
+        for (i = 0; i < WIDTH ; i = i+1) begin: level_cross_clock_block
+            if (REGISTER <= 1)
+                level_cross_clocks_ff_bit    level_cross_clocks_single_i ( // just a single ff (if metastability is not a problem)
+                    .clk   (clk),       // input
+                    .d_in  (d_in[i]),   // input
+                    .d_out (d_out[i])   // output
+                );
+            else if (REGISTER == 2)
+                level_cross_clocks_sync_bit  level_cross_clocks_sync_i ( // classic 2-register synchronizer
+                    .clk   (clk),       // input
+                    .d_in  (d_in[i]),   // input
+                    .d_out (d_out[i])   // output
+                );
+            else
+                level_cross_clocks_single_bit #( // >2 bits (first two only are synchronizer)
+                    .REGISTER(REGISTER)
+                ) level_cross_clocks_single_i (
+                    .clk   (clk),       // input
+                    .d_in  (d_in[i]),   // input
+                    .d_out (d_out[i])   // output
+                );
+        end
+    endgenerate
+endmodule
+
+module  level_cross_clocks_single_bit#(
+    parameter REGISTER = 3 // number of registers (>3)
+)(
+    input   clk,
+    input   d_in,
+    output  d_out
+);
+    reg [REGISTER - 3 : 0] regs;
+    wire                   d_sync; // after a 2-bit synchronizer
+    assign d_out = regs[REGISTER -3];
+    always @ (posedge clk) begin
+        regs <= (regs << 1) + d_sync; // | d_in complains about widths mismatch
+    end
+    level_cross_clocks_sync_bit level_cross_clocks_sync_bit_i (
+        .clk   (clk), // input
+        .d_in  (d_in), // input
+        .d_out (d_sync) // output
+    );
+endmodule
 
-    reg [WIDTH * REGISTER -1 : 0] regs;
-    assign d_out = regs [WIDTH-1:0];
+// Classic 2-bit (exactly) synchronizer
+module  level_cross_clocks_sync_bit(
+    input   clk,
+    input   d_in,
+    output  d_out
+);
+`ifndef IGNORE_ATTR
+    (* ASYNC_REG = "TRUE" *)
+`endif
+    reg  [1:0] sync_zer; 
+    assign d_out = sync_zer [1];
     always @ (posedge clk) begin
-        regs <= {d_in, regs[WIDTH * REGISTER -1 : WIDTH]};
+        sync_zer <= {sync_zer[0],d_in};
     end
 endmodule
 
+module  level_cross_clocks_ff_bit( // just a single FF if REGISTER == 1 (if metastability is not a problem)
+    input       clk,
+    input      d_in,
+    output reg d_out
+);
+    always @ (posedge clk) begin
+        d_out <= d_in;
+    end
+endmodule
+
+

util_modules/pulse_cross_clock.v

@@ -33,8 +33,22 @@ module  pulse_cross_clock#(
     output busy
 );
     localparam EXTRA_DLY_SAFE=EXTRA_DLY ? 1 : 0;
-    reg       in_reg = 0;
+`ifndef IGNORE_ATTR
+    (* KEEP = "TRUE" *)
+`endif    
+    reg       in_reg = 0; // can not be  ASYNC_REG as it can not be put together with out_reg
+//WARNING: [Constraints 18-1079] Register sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_sync_i/pulse_cross_clock_trig_in_pclk_i/in_reg_reg
+// and sensors393_i/sensor_channel_block[0].sensor_channel_i/sens_sync_i/pulse_cross_clock_trig_in_pclk_i/out_reg_reg[0] are
+//from the same synchronizer and have the ASYNC_REG property set, but could not be placed into the same slice due to constraints
+// or mismatched control signals on the registers.
+    
+`ifndef IGNORE_ATTR
+    (* ASYNC_REG = "TRUE" *)
+`endif    
     reg [2:0] out_reg = 0;
+`ifndef IGNORE_ATTR
+    (* ASYNC_REG = "TRUE" *)
+`endif    
     reg       busy_r = 0;
     assign out_pulse=out_reg[2];
     assign busy=busy_r; // in_reg;

wrap/idelay_ctrl.v

@@ -28,8 +28,10 @@ module  idelay_ctrl
     input rst,
     output rdy
 );
+`ifndef IGNORE_ATTR
+    (* IODELAY_GROUP = IODELAY_GRP *)
+`endif    
 
-(* IODELAY_GROUP = IODELAY_GRP *)
 IDELAYCTRL idelay_ctrl_i(
     .RDY(rdy),
     .REFCLK(refclk),

wrap/idelay_fine_pipe.v

@@ -49,7 +49,10 @@ module  idelay_fine_pipe
             if (fdly_pre > 3'h4) $display ("ERROR: fine idelay value should be <5, specified %d @ %t", fdly_pre,$time);  
         end
     `endif
-(* IODELAY_GROUP = IODELAY_GRP *) IDELAYE2_FINEDELAY
+`ifndef IGNORE_ATTR
+    (* IODELAY_GROUP = IODELAY_GRP *)
+`endif    
+ IDELAYE2_FINEDELAY
      #(
         .CINVCTRL_SEL("FALSE"),
         .DELAY_SRC("IDATAIN"),

wrap/idelay_nofine.v

@@ -34,7 +34,10 @@ module  idelay_nofine
     input data_in,
     output data_out
 );
-(* IODELAY_GROUP = IODELAY_GRP *) IDELAYE2
+`ifndef IGNORE_ATTR
+(* IODELAY_GROUP = IODELAY_GRP *)
+`endif    
+ IDELAYE2
      #(
         .CINVCTRL_SEL("FALSE"),
         .DELAY_SRC("IDATAIN"),

wrap/mmcm_phase_cntr.v

@@ -108,11 +108,9 @@ module  mmcm_phase_cntr#(
     reg [PHASE_WIDTH-1:0] ps_target;
     reg ps_busy=0;
 // TODO: find out why it was optimized out!    
-//    (* keep = "true" *)
     reg ps_start0, ps_start; // debugging
     assign ps_ready=!ps_busy && locked && !ps_start0 && !ps_start;
     assign psen=ps_start && (diff != 0);
-//    wire [PHASE_WIDTH:0] diff= ps_target-ps_dout_r;
 // made a difference, so it doesn't seem Vivado extends bits of operands "+", "-"
     wire [PHASE_WIDTH:0] diff= {ps_target[PHASE_WIDTH-1],ps_target}-{ps_dout_r[PHASE_WIDTH-1],ps_dout_r};
     assign  ps_dout = ps_dout_r; 

wrap/odelay_fine_pipe.v

@@ -49,7 +49,10 @@ module  odelay_fine_pipe
         end
     `endif
  
- (* IODELAY_GROUP = IODELAY_GRP *) ODELAYE2_FINEDELAY
+`ifndef IGNORE_ATTR
+    (* IODELAY_GROUP = IODELAY_GRP *)
+`endif    
+ ODELAYE2_FINEDELAY
      #(
         .CINVCTRL_SEL("FALSE"),
         .DELAY_SRC("ODATAIN"),

wrap/odelay_pipe.v

@@ -36,8 +36,10 @@ module  odelay_pipe
     output data_out
 );
  
- (* IODELAY_GROUP = IODELAY_GRP *) ODELAYE2
-     #(
+`ifndef IGNORE_ATTR
+    (* IODELAY_GROUP = IODELAY_GRP *)
+`endif    
+  ODELAYE2 #(
         .CINVCTRL_SEL("FALSE"),
         .DELAY_SRC("ODATAIN"),
 //        .FINEDELAY("ADD_DLY"),

x393.v

@@ -96,15 +96,17 @@ module  x393 #(
 //    localparam ADDRESS_NUMBER=15;
 //    localparam COLADDR_NUMBER=10;
 // Source for reset and clock
-(* keep = "true" *)
+`ifndef IGNORE_ATTR
+    (* KEEP = "TRUE" *)
+`endif    
     wire    [3:0]     fclk;           // PL Clocks [3:0], output
-(* keep = "true" *)   
+`ifndef IGNORE_ATTR
+    (* KEEP = "TRUE" *)
+`endif    
     wire    [3:0]     frst;           // PL Clocks [3:0], output
     
 // AXI write interface signals
-//(* keep = "true" *) 
     wire           axi_aclk;          // clock - should be buffered
-//(* dont_touch = "true" *)
     wire           axi_grst;          // reset, active high, global (try to get rid of) - trying, removed BUFG
 // AXI Write Address
     wire   [31:0]  maxi0_awaddr;      // AWADDR[31:0], input

x393.xdc

@@ -31,6 +31,8 @@ set_property is_enabled false [get_drc_checks REQP-1577]
 #Synchronous clocking for BRAM (mult_saxi_wr_inbuf_i/ram_var_w_var_r_i/ram_i/RAMB36E1_i) in SDP mode ...
 set_property is_enabled false [get_drc_checks REQP-165]
 
+#Useless input. The input pins CE and CLR are not used for BUFR_DIVIDE BYPASS.
+set_property is_enabled false [get_drc_checks REQP-14]
 
 
 #    output                       SDRST, // output SDRST, active low