working on Python code for hardware testing (63ff2819) · Commits · Elphel / x393

.gitignore

+1 −0

Original line number	Original line	Diff line number	Diff line
	@@ -9,3 +9,4 @@ x393.prj
	DEBUG_VDT		DEBUG_VDT
	*.kate-swp		*.kate-swp
	*.old		*.old
			*.pyc
			No newline at end of file

includes/x393_mcontr_encode_cmd.vh

+1 −1

Original line number	Original line	Diff line number	Diff line
	@@ -35,7 +35,7 @@
	input buf_rst; // connect to external buffer (but only if not paused)		input buf_rst; // connect to external buffer (but only if not paused)
	begin		begin
	func_encode_skip= func_encode_cmd (		func_encode_skip= func_encode_cmd (
	{{14-CMD_DONE_BIT{1'b0}}, done, skip[CMD_PAUSE_BITS-1:0]}, // 15-bit row/column adderss		{{14-CMD_DONE_BIT{1'b0}}, done, skip[CMD_PAUSE_BITS-1:0]}, // 15-bit row/column address
	bank[2:0], // bank (here OK to be any)		bank[2:0], // bank (here OK to be any)
	3'b0, // RAS/CAS/WE, positive logic		3'b0, // RAS/CAS/WE, positive logic
	odt_en, // enable ODT		odt_en, // enable ODT

py393/.settings/org.eclipse.core.resources.prefs

+1 −0

Original line number	Original line	Diff line number	Diff line
	eclipse.preferences.version=1		eclipse.preferences.version=1
	encoding/import_verilog_parameters.py=utf-8		encoding/import_verilog_parameters.py=utf-8
	encoding/test1.py=utf-8		encoding/test1.py=utf-8
			encoding/test2.py=utf-8

py393/import_verilog_parameters.py

+35 −7

Original line number	Original line	Diff line number	Diff line
	@@ -30,6 +30,18 @@ __status__ = "Development"
	import re		import re
	import os		import os
	import string		import string
			class VerilogParameters(object): #this is Borg
			__shared_state = {}
			def __init__(self, parameters=None):
			self.__dict__ = self.__shared_state
			if (parameters):
			adict={}
			for parName in parameters:
			adict[parName]= parameters[parName][0]
			adict[parName+"__TYPE"]=parameters[parName][1]
			adict[parName+"__RAW"]= parameters[parName][2]
			self.__dict__.update(adict)

	class ImportVerilogParameters(object):		class ImportVerilogParameters(object):
	'''		'''
	classdocs		classdocs
	@@ -38,6 +50,7 @@ class ImportVerilogParameters(object):
	parameters={}		parameters={}
	conditions=[True]		conditions=[True]
	rootPath=None		rootPath=None
			verbose=1
	'''		'''
	parameters - dictionalry of already known parameters, defines - defined macros		parameters - dictionalry of already known parameters, defines - defined macros
	'''		'''
	@@ -47,6 +60,7 @@ class ImportVerilogParameters(object):
	'''		'''
	if parameters:		if parameters:
	self.parameters=parameters.copy()		self.parameters=parameters.copy()
			self.parseRawParameters()
	if defines:		if defines:
	self.defines=defines.copy()		self.defines=defines.copy()
	if rootPath:		if rootPath:
	@@ -249,6 +263,7 @@ class ImportVerilogParameters(object):
	Adds parsed parameters to the dictionary		Adds parsed parameters to the dictionary
	'''		'''
	def readParameterPortList(self,path,portMode=True):		def readParameterPortList(self,path,portMode=True):
			if (self.verbose>2):
	print ("readParameterPortList:Processing %s"%(path))		print ("readParameterPortList:Processing %s"%(path))
	with open (path, "r") as myfile: #with will close file when done		with open (path, "r") as myfile: #with will close file when done
	text=myfile.read()		text=myfile.read()
	@@ -339,12 +354,13 @@ class ImportVerilogParameters(object):
	for line in preprocessedLines:		for line in preprocessedLines:
	if line[-1] == ";":		if line[-1] == ";":
	portMode=False		portMode=False
			if (self.verbose>2):
	print ("portMode is "+str(portMode))		print ("portMode is "+str(portMode))
	try:		try:
	if portMode and (preprocessedLines[0][0]==","):		if portMode and (preprocessedLines[0][0]==","):
	preprocessedLines.insert(0,preprocessedLines.pop(0)[1:])		preprocessedLines.insert(0,preprocessedLines.pop(0)[1:])
	except:		except:
	pass		if (self.verbose>2):
	print("No preprocessed lines left")		print("No preprocessed lines left")
	while preprocessedLines:		while preprocessedLines:
	# print("A: len(preprocessedLines)=%d, first is %s"%(len(preprocessedLines),preprocessedLines[0]))		# print("A: len(preprocessedLines)=%d, first is %s"%(len(preprocessedLines),preprocessedLines[0]))
	@@ -480,18 +496,30 @@ class ImportVerilogParameters(object):
	# process expression here, for now - just use expression string		# process expression here, for now - just use expression string
	ev= self.parseExpression(expLine)		ev= self.parseExpression(expLine)
	if ev is None:		if ev is None:
	self.parameters[parName]= (expLine,parType)		self.parameters[parName]= (expLine,parType,expLine)
	else:		else:
	if not parType:		if not parType:
	parType=ev[1]		parType=ev[1]
	# self.parameters[parName]= (ev[0],parType)		# self.parameters[parName]= (ev[0],parType)
	self.parameters[parName]= (ev[0],parType+" raw="+expLine)		self.parameters[parName]= (ev[0],parType,expLine)
	# if portMode: # while True:		# if portMode: # while True:
	if portMode or (termChar == ";"): # while True:		if portMode or (termChar == ";"): # while True:
	break;		break;
	# print ("======= Parameters =======")		# print ("======= Parameters =======")
	# for par in self.parameters:		# for par in self.parameters:
	# print (par+": "+self.parameters[par])		# print (par+": "+self.parameters[par])
			def parseRawParameters(self):
			for parName in self.parameters:
			valTyp= self.parameters[parName]
			if (not valTyp[1]) or (valTyp[1]=="RAW"):
			ev= self.parseExpression(valTyp[0])
			# print ("valTyp="+str(valTyp))
			# print ("ev="+str(ev))
			if ev:
			self.parameters[parName]= (ev[0],ev[1],valTyp[0])
			if parName == "VERBOSE":
			self.verbose=ev[0]

	'''		'''
	get parameter dictionary		get parameter dictionary
	'''		'''

py393/import_verilog_parameters.pyc

deleted100644 → 0

−12.3 KiB

File deleted.

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