Commit 632ab621 authored by Andrey Filippov's avatar Andrey Filippov

working more on Bayer version of the MCLT

parent c6bdde56
...@@ -453,11 +453,8 @@ D11 - negate for mode 3 (SS) ...@@ -453,11 +453,8 @@ D11 - negate for mode 3 (SS)
// frequency domain, high address bit - page, 2 next - mode, 6 LSBs - transposed FD data (vertical first) // frequency domain, high address bit - page, 2 next - mode, 6 LSBs - transposed FD data (vertical first)
wire [8:0] dtt_out_ram_wa = {dtt_out_ram_wah,dtt_out_wa16}; wire [8:0] dtt_out_ram_wa = {dtt_out_ram_wah,dtt_out_wa16};
reg [7:0] dtt_dly_cntr; reg [7:0] dtt_dly_cntr;
reg [8:0] dtt_rd_cntr; // counter for dtt readout to rotator reg [8:0] dtt_rd_cntr; // counter for dtt readout to rotator
// wire [8:0] dtt_rd_ra = {dtt_rd_cntr[8],dtt_rd_cntr[1:0],dtt_rd_cntr[7:2]}; // page, mode, frequency
wire [8:0] dtt_rd_ra = {dtt_rd_cntr[8],dtt_rd_cntr[0],dtt_rd_cntr[1],dtt_rd_cntr[7:2]}; // page, mode, frequency wire [8:0] dtt_rd_ra = {dtt_rd_cntr[8],dtt_rd_cntr[0],dtt_rd_cntr[1],dtt_rd_cntr[7:2]}; // page, mode, frequency
reg [2:0] dtt_rd_regen_dv; // dtt output buffer mem read, register enable, data valid reg [2:0] dtt_rd_regen_dv; // dtt output buffer mem read, register enable, data valid
wire [35:0] dtt_rd_data_w; // high bits are not used wire [35:0] dtt_rd_data_w; // high bits are not used
...@@ -466,7 +463,6 @@ D11 - negate for mode 3 (SS) ...@@ -466,7 +463,6 @@ D11 - negate for mode 3 (SS)
wire dtt_first_quad_out = ~dtt_out_ram_cntr[3] & ~dtt_out_ram_cntr[2]; wire dtt_first_quad_out = ~dtt_out_ram_cntr[3] & ~dtt_out_ram_cntr[2];
// reg [9:0] dtt_out_ram_cntr;
always @(posedge clk) begin always @(posedge clk) begin
if (rst) dtt_out_ram_cntr <= 0; if (rst) dtt_out_ram_cntr <= 0;
else if (dtt_inc16) dtt_out_ram_cntr <= dtt_out_ram_cntr + 1; else if (dtt_inc16) dtt_out_ram_cntr <= dtt_out_ram_cntr + 1;
...@@ -507,7 +503,6 @@ D11 - negate for mode 3 (SS) ...@@ -507,7 +503,6 @@ D11 - negate for mode 3 (SS)
.clk (clk), // input .clk (clk), // input
.rst (rst), // input .rst (rst), // input
.start (dtt_start), // input .start (dtt_start), // input
// .mode (dtt_mode), // input[1:0]
.mode ({dtt_mode[0],dtt_mode[1]}), // input[1:0] .mode ({dtt_mode[0],dtt_mode[1]}), // input[1:0]
.xin (dtt_r_data), // input[24:0] signed .xin (dtt_r_data), // input[24:0] signed
.pre_last_in (), // output reg .pre_last_in (), // output reg
...@@ -555,6 +550,7 @@ D11 - negate for mode 3 (SS) ...@@ -555,6 +550,7 @@ D11 - negate for mode 3 (SS)
// are these shift OK? Will need to be valis only @ dtt_start_out // are these shift OK? Will need to be valis only @ dtt_start_out
.shift_h (x_shft_r4), // input[6:0] signed .shift_h (x_shft_r4), // input[6:0] signed
.shift_v (y_shft_r4), // input[6:0] signed .shift_v (y_shft_r4), // input[6:0] signed
.inv_checker (1'b0), // input only used for Bayer mosaic data
.fd_din (dtt_rd_data), // input[24:0] signed. Expected latency = 3 from start .fd_din (dtt_rd_data), // input[24:0] signed. Expected latency = 3 from start
.fd_out (dout), // output[24:0] reg signed .fd_out (dout), // output[24:0] reg signed
.pre_first_out (pre_first_out), // output reg .pre_first_out (pre_first_out), // output reg
......
...@@ -68,9 +68,18 @@ module mclt16x16_bayer#( ...@@ -68,9 +68,18 @@ module mclt16x16_bayer#(
output [PIX_ADDR_WIDTH-1:0] pix_addr, //!< external pixel buffer address output [PIX_ADDR_WIDTH-1:0] pix_addr, //!< external pixel buffer address
output pix_re, //!< pixel read enable (sync with mpixel_a) output pix_re, //!< pixel read enable (sync with mpixel_a)
output pix_page, //!< copy pixel page (should be externally combined with first color) output pix_page, //!< copy pixel page (should be externally combined with first color)
input [PIXEL_WIDTH-1:0] pix_d //!< pixel data, latency = 2 from pixel address input [PIXEL_WIDTH-1:0] pix_d, //!< pixel data, latency = 2 from pixel address
output pre_busy, //!< start should come each 256-th cycle (next after pre_last_in), and not after pre_busy)
output pre_last_in, //!< may increment page
output pre_first_out,//!< next will output first of DCT/DCT coefficients
output pre_last_out, //!< next will be last output of DST/DST coefficients
output [7:0] out_addr, //!< address to save coefficients, 2 MSBs - mode (CC,SC,CS,SS), others - down first
output dv, //!< output data valid
output signed [OUT_WIDTH - 1 : 0] dout0, //!<frequency domain data output (even samples)
output signed [OUT_WIDTH - 1 : 0] dout1 //!<frequency domain data output (odd s amples)
); );
localparam DTT_OUT_DELAY = 99; // 191; // start output to sin/cos rotator, ~=3/4 of 256 localparam DTT_OUT_DELAY = 128; // 191; // start output to sin/cos rotator, with checker - 2*64 +/=?
localparam DTT_IN_DELAY = 62; // 69; // wa -ra min = 1 localparam DTT_IN_DELAY = 62; // 69; // wa -ra min = 1
reg [ 1:0] start_r; reg [ 1:0] start_r;
...@@ -83,6 +92,10 @@ module mclt16x16_bayer#( ...@@ -83,6 +92,10 @@ module mclt16x16_bayer#(
reg [SHIFT_WIDTH-1:0] y_shft_r3; // registered @ start_dtt reg [SHIFT_WIDTH-1:0] y_shft_r3; // registered @ start_dtt
reg [SHIFT_WIDTH-1:0] x_shft_r4; // registered @ dtt_start_first_fill reg [SHIFT_WIDTH-1:0] x_shft_r4; // registered @ dtt_start_first_fill
reg [SHIFT_WIDTH-1:0] y_shft_r4; // registered @ dtt_start_first_fill reg [SHIFT_WIDTH-1:0] y_shft_r4; // registered @ dtt_start_first_fill
reg inv_checker_r;
reg inv_checker_r2;
reg inv_checker_r3;
reg inv_checker_r4;
// wire signed [WND_WIDTH-1:0] window; //!< msb==0, always positive // wire signed [WND_WIDTH-1:0] window; //!< msb==0, always positive
wire [1:0] signs; //!< bit 0: sign to add to dtt-cc input, bit 1: sign to add to dtt-cs input wire [1:0] signs; //!< bit 0: sign to add to dtt-cc input, bit 1: sign to add to dtt-cs input
...@@ -133,7 +146,12 @@ module mclt16x16_bayer#( ...@@ -133,7 +146,12 @@ module mclt16x16_bayer#(
wire signed [35:0] dtt_r_data_w; // high bits are not used wire signed [35:0] dtt_r_data_w; // high bits are not used
wire signed [DTT_IN_WIDTH-1:0] dtt_r_data = dtt_r_data_w[DTT_IN_WIDTH-1:0]; wire signed [DTT_IN_WIDTH-1:0] dtt_r_data = dtt_r_data_w[DTT_IN_WIDTH-1:0];
reg pre_last_out_r;
wire pre_last_in_w;
assign pre_last_out = pre_last_out_r;
assign pre_busy = pre_busy_r || start || (!pre_last_in_w && phases[0]);
assign pre_last_in = pre_last_in_w;
always @ (posedge clk) begin always @ (posedge clk) begin
...@@ -141,23 +159,26 @@ module mclt16x16_bayer#( ...@@ -141,23 +159,26 @@ module mclt16x16_bayer#(
if (start) begin if (start) begin
x_shft_r <= x_shft; x_shft_r <= x_shft;
y_shft_r <= y_shft; y_shft_r <= y_shft;
inv_checker_r <= inv_checker;
end end
start_r <= {start_r[0], start}; start_r <= {start_r[0], start};
if (start_r[1]) begin // same latency as mpix_a_w if (start_r[1]) begin // same latency as mpix_a_w
x_shft_r2 <= x_shft_r; // use for the window x_shft_r2 <= x_shft_r; // use for the window
y_shft_r2 <= y_shft_r; y_shft_r2 <= y_shft_r;
inv_checker_r2 <= inv_checker_r;
end end
if (start_dtt) begin if (start_dtt) begin
x_shft_r3 <= x_shft_r2; x_shft_r3 <= x_shft_r2;
y_shft_r3 <= y_shft_r2; y_shft_r3 <= y_shft_r2;
inv_checker_r3 <= inv_checker_r2;
end end
/*
if (dtt_start_first_fill) begin if (dtt_start_first_fill) begin
x_shft_r4 <= x_shft_r3; x_shft_r4 <= x_shft_r3;
y_shft_r4 <= y_shft_r3; y_shft_r4 <= y_shft_r3;
inv_checker_r4 <= inv_checker_r3;
end end
*/
if (phases[8]) begin if (phases[8]) begin
pix_d_r <= pix_d; pix_d_r <= pix_d;
window_r <= window_w; window_r <= window_w;
...@@ -249,7 +270,8 @@ module mclt16x16_bayer#( ...@@ -249,7 +270,8 @@ module mclt16x16_bayer#(
.window (window_w), // output[17:0] signed .window (window_w), // output[17:0] signed
.signs (signs), // output[1:0] .signs (signs), // output[1:0]
.phases (phases), // output[7:0] .phases (phases), // output[7:0]
.var_first (var_first) // output reg .var_first (var_first), // output reg
.pre_last_in (pre_last_in_w)// output reg
); );
dly_var #( dly_var #(
...@@ -280,10 +302,9 @@ module mclt16x16_bayer#( ...@@ -280,10 +302,9 @@ module mclt16x16_bayer#(
.web (4'hf), // input[3:0] .web (4'hf), // input[3:0]
.data_in ({{(36-DTT_IN_WIDTH){1'b0}}, data_dtt_in}) // input[35:0] .data_in ({{(36-DTT_IN_WIDTH){1'b0}}, data_dtt_in}) // input[35:0]
); );
wire [8:0] dbgt_diff_wara = dtt_in_wa-dtt_r_ra; wire [8:0] dbg_diff_wara_dtt_in = dtt_in_wa-dtt_r_ra; // SuppressThisWarning VEditor : debug only signal
/*
wire signed [OUT_WIDTH-1:0] dtt_out_wd; wire signed [OUT_WIDTH-1:0] dtt_out_wd;
wire [3:0] dtt_out_wa16; wire [3:0] dtt_out_wa16;
wire dtt_out_we; wire dtt_out_we;
...@@ -291,10 +312,218 @@ module mclt16x16_bayer#( ...@@ -291,10 +312,218 @@ module mclt16x16_bayer#(
wire dtt_inc16; wire dtt_inc16;
reg [4:0] dtt_out_ram_cntr; reg [4:0] dtt_out_ram_cntr;
reg [4:0] dtt_out_ram_wah; reg [4:0] dtt_out_ram_wah;
reg [1:0] dtt_out_ram_wpage; // one of 4 pages (128 samples long) being written to
wire dtt_start_fill; // some data available in DTT output buffer, OK to start consecutive readout wire dtt_start_fill; // some data available in DTT output buffer, OK to start consecutive readout
reg dtt_start_first_fill; reg dtt_start_first_fill;
reg dtt_start_out; // start read out to sin/cos rotator reg dtt_start_out; // start read out to sin/cos rotator
*/
// frequency domain, high address bit - page, 2 next - mode, 6 LSBs - transposed FD data (vertical first)
// will change: 2 address bits - page, 1 - mode, 6 LSBs - transposed FD data (vertical first)
// here delay should start after full 2 modes (128 samples) written, as readout to rotators starts from both ends
wire [8:0] dtt_out_ram_wa = {dtt_out_ram_wah,dtt_out_wa16};
reg [7:0] dtt_dly_cntr;
// reg [8:0] dtt_rd_cntr; // counter for dtt readout to rotator
reg [8:0] dtt_rd_cntr_pre; // 1 ahead of the former counter for dtt readout to rotator
// TODO: fix rd addresses
// wire [8:0] dtt_rd_ra = {dtt_rd_cntr[8],dtt_rd_cntr[0],dtt_rd_cntr[1],dtt_rd_cntr[7:2]}; // page, mode, frequency
reg [8:0] dtt_rd_ra0;
reg [8:0] dtt_rd_ra1;
reg [3:0] dtt_rd_regen_dv; // dtt output buffer mem read, register enable, data valid
wire [35:0] dtt_rd_data0_w; // high bits are not used
wire [35:0] dtt_rd_data1_w; // high bits are not used
// data to be input to phase rotator
wire signed [OUT_WIDTH-1:0] dtt_rd_data0 = dtt_rd_data0_w[OUT_WIDTH-1:0]; // valid with dtt_rd_regen_dv[3]
wire signed [OUT_WIDTH-1:0] dtt_rd_data1 = dtt_rd_data1_w[OUT_WIDTH-1:0]; // valid with dtt_rd_regen_dv[3]
// wire dtt_first_quad_out = ~dtt_out_ram_cntr[3] & ~dtt_out_ram_cntr[2];
wire dtt_first_quad_out = ~dtt_out_ram_cntr[2];
always @(posedge clk) begin
if (rst) dtt_out_ram_cntr <= 0;
else if (dtt_inc16) dtt_out_ram_cntr <= dtt_out_ram_cntr + 1;
dtt_out_ram_wah <= dtt_out_ram_cntr - dtt_sub16;
dtt_start_first_fill <= dtt_start_fill & dtt_first_quad_out;
if (dtt_start_first_fill) dtt_out_ram_wpage <= dtt_out_ram_wah[4:3];
if (rst) dtt_dly_cntr <= 0;
else if (dtt_start_first_fill) dtt_dly_cntr <= DTT_OUT_DELAY;
else if (|dtt_dly_cntr) dtt_dly_cntr <= dtt_dly_cntr - 1;
dtt_start_out <= dtt_dly_cntr == 1;
// if (rst) dtt_rd_regen_dv[0] <= 0;
// else if (dtt_start_out) dtt_rd_regen_dv[0] <= 1;
// else if (&dtt_rd_cntr[7:0]) dtt_rd_regen_dv[0] <= 0;
if (rst) dtt_rd_regen_dv[0] <= 0;
else if (dtt_start_out) dtt_rd_regen_dv[0] <= 1;
else if (&dtt_rd_cntr_pre[6:0]) dtt_rd_regen_dv[0] <= 0;
if (rst) dtt_rd_regen_dv[3:1] <= 0;
else dtt_rd_regen_dv[3:1] <= dtt_rd_regen_dv[2:0];
// if (dtt_start_out) dtt_rd_cntr_pre <= {dtt_out_ram_wah[4], 8'b0}; //copy page number
if (dtt_start_out) dtt_rd_cntr_pre <= {dtt_out_ram_wpage, 7'b0}; //copy page number
else if (dtt_rd_regen_dv[0]) dtt_rd_cntr_pre <= dtt_rd_cntr_pre + 1;
//// wire [8:0] dtt_rd_ra = {dtt_rd_cntr[8],dtt_rd_cntr[0],dtt_rd_cntr[1],dtt_rd_cntr[7:2]}; // page, mode, frequency
dtt_rd_ra0 <= {dtt_rd_cntr_pre[8:7],
dtt_rd_cntr_pre[6] ^ dtt_rd_cntr_pre[5],
dtt_rd_cntr_pre[5]? (~dtt_rd_cntr_pre[4:0]) : dtt_rd_cntr_pre[4:0],
dtt_rd_cntr_pre[5]};
dtt_rd_ra1 <= {dtt_rd_cntr_pre[8:7],
dtt_rd_cntr_pre[6] ^ dtt_rd_cntr_pre[5],
dtt_rd_cntr_pre[5]? (~dtt_rd_cntr_pre[4:0]) : dtt_rd_cntr_pre[4:0],
~dtt_rd_cntr_pre[5]};
end
dtt_iv_8x8_ad #(
.INPUT_WIDTH (DTT_IN_WIDTH),
.OUT_WIDTH (OUT_WIDTH),
.OUT_RSHIFT1 (OUT_RSHIFT),
.OUT_RSHIFT2 (OUT_RSHIFT2),
.TRANSPOSE_WIDTH (TRANSPOSE_WIDTH),
.DSP_B_WIDTH (DSP_B_WIDTH),
.DSP_A_WIDTH (DSP_A_WIDTH),
.DSP_P_WIDTH (DSP_P_WIDTH)
) dtt_iv_8x8_ad_i (
.clk (clk), // input
.rst (rst), // input
.start (dtt_start), // input
.mode ({dtt_mode, 1'b0}), // input[1:0] for checker-board: only 2 of 4 modes (CC, SC)
.xin (dtt_r_data), // input[24:0] signed
.pre_last_in (), // output reg
.mode_out (), // dtt_mode_out), // output[1:0] reg
.pre_busy (), // output reg
.out_wd (dtt_out_wd), // output[24:0] reg
.out_wa (dtt_out_wa16), // output[3:0] reg
.out_we (dtt_out_we), // output reg
.sub16 (dtt_sub16), // output reg
.inc16 (dtt_inc16), // output reg
.start_out (dtt_start_fill) // output[24:0] signed
);
// still incorrectly shows difference when filled nto sequentially
reg [8:0] dbg_last_dtt_out_ram_wa; // SuppressThisWarning VEditor : debug only signal
wire [8:0] dbg_diff_wara_dtt_out0 = dbg_last_dtt_out_ram_wa-dtt_rd_ra0; // SuppressThisWarning VEditor : debug only signal
wire [8:0] dbg_diff_wara_dtt_out1 = dbg_last_dtt_out_ram_wa-dtt_rd_ra1; // SuppressThisWarning VEditor : debug only signal
always @ (posedge clk) begin
if (dtt_out_we) dbg_last_dtt_out_ram_wa <= dtt_out_ram_wa;
end
// Two of 2 page buffers after dtt (feeding two phase rotators), address MSB is not needed
ram18p_var_w_var_r #(
.REGISTERS(1),
.LOG2WIDTH_WR(5),
.LOG2WIDTH_RD(5)
) ram18p_var_w_var_r_dtt_out0_i (
.rclk (clk), // input
.raddr (dtt_rd_ra0), // input[8:0]
.ren (dtt_rd_regen_dv[1]), // input
.regen (dtt_rd_regen_dv[2]), // input
.data_out (dtt_rd_data0_w), // output[35:0]
.wclk (clk), // input
.waddr (dtt_out_ram_wa), // input[8:0]
.we (dtt_out_we), // input
.web (4'hf), // input[3:0]
.data_in ({{(36-DTT_IN_WIDTH){1'b0}}, dtt_out_wd}) // input[35:0]
);
ram18p_var_w_var_r #(
.REGISTERS(1),
.LOG2WIDTH_WR(5),
.LOG2WIDTH_RD(5)
) ram18p_var_w_var_r_dtt_out1_i (
.rclk (clk), // input
.raddr (dtt_rd_ra1), // input[8:0]
.ren (dtt_rd_regen_dv[1]), // input
.regen (dtt_rd_regen_dv[2]), // input
.data_out (dtt_rd_data1_w), // output[35:0]
.wclk (clk), // input
.waddr (dtt_out_ram_wa), // input[8:0]
.we (dtt_out_we), // input
.web (4'hf), // input[3:0]
.data_in ({{(36-DTT_IN_WIDTH){1'b0}}, dtt_out_wd}) // input[35:0]
);
// Two rotators in parallel
// TODO: add negating for antisymmetrical (inverted checkerboard)
// Rotate phase (equvalent to pixel domain shift)
phase_rotator #(
.FD_WIDTH(OUT_WIDTH),
.SHIFT_WIDTH(SHIFT_WIDTH), // should be exactly 7
.DSP_B_WIDTH(DSP_B_WIDTH),
.DSP_A_WIDTH(DSP_A_WIDTH),
.DSP_P_WIDTH(DSP_P_WIDTH)
) phase_rotator0_i (
.clk (clk), // input
.rst (rst), // input
.start (dtt_start_out), // input
// are these shift OK? Will need to be valis only @ dtt_start_out
.shift_h (x_shft_r4), // input[6:0] signed
.shift_v (y_shft_r4), // input[6:0] signed
.inv_checker (inv_checker_r4),// input only used for Bayer mosaic data
.fd_din (dtt_rd_data0), // input[24:0] signed. Expected latency = 3 from start
.fd_out (dout0), // output[24:0] reg signed
.pre_first_out (pre_first_out), // output reg
.fd_dv (dv) // output reg
);
phase_rotator #(
.FD_WIDTH(OUT_WIDTH),
.SHIFT_WIDTH(SHIFT_WIDTH), // should be exactly 7
.DSP_B_WIDTH(DSP_B_WIDTH),
.DSP_A_WIDTH(DSP_A_WIDTH),
.DSP_P_WIDTH(DSP_P_WIDTH)
) phase_rotator1_i (
.clk (clk), // input
.rst (rst), // input
.start (dtt_start_out), // input
// are these shift OK? Will need to be valis only @ dtt_start_out
.shift_h (x_shft_r4), // input[6:0] signed
.shift_v (y_shft_r4), // input[6:0] signed
.inv_checker (inv_checker_r4),// input only used for Bayer mosaic data
.fd_din (dtt_rd_data1), // input[24:0] signed. Expected latency = 3 from start
.fd_out (dout1), // output[24:0] reg signed
.pre_first_out (pre_first_out), // output reg
.fd_dv (dv) // output reg
);
reg [7:0] out_addr_r;
reg [3:0] dead_cntr;
reg pre_busy_r;
assign out_addr = {out_addr_r[0],out_addr_r[1],out_addr_r[4:2],out_addr_r[7:5]};
always @ (posedge clk) begin
if (!dv) out_addr_r <= 0;
else out_addr_r <= out_addr_r + 1;
pre_last_out_r <= out_addr_r == 8'hfe;
if (rst) pre_busy_r <= 0;
else if (pre_last_in_w) pre_busy_r <= 1;
else if (dead_cntr == 0) pre_busy_r <= 0;
if (~pre_busy_r) dead_cntr <= DEAD_CYCLES;
else dead_cntr <= dead_cntr - 1;
end
endmodule endmodule
...@@ -72,7 +72,8 @@ module mclt_bayer_fold#( ...@@ -72,7 +72,8 @@ module mclt_bayer_fold#(
output signed [WND_WIDTH-1:0] window, //!< msb==0, always positive output signed [WND_WIDTH-1:0] window, //!< msb==0, always positive
output [1:0] signs, //!< bit 0: sign to add to dtt-cc input, bit 1: sign to add to dtt-cs input output [1:0] signs, //!< bit 0: sign to add to dtt-cc input, bit 1: sign to add to dtt-cs input
output [14:0] phases, //!< other signals output [14:0] phases, //!< other signals
output reg var_first output reg var_first, //!< first of 2 fold variants (4 for monochrome, 2 left for checker)
output reg pre_last_in //!< pre last data in
); );
reg [6:0] in_cntr; // input phase counter reg [6:0] in_cntr; // input phase counter
reg [14:0] run_r; // run phase reg [14:0] run_r; // run phase
...@@ -146,6 +147,10 @@ module mclt_bayer_fold#( ...@@ -146,6 +147,10 @@ module mclt_bayer_fold#(
var_first <= var_first_d; var_first <= var_first_d;
end end
pre_last_in <= in_cntr[7:0] == 8'hfd;
end end
ram18tp_var_w_var_r #( ram18tp_var_w_var_r #(
......
...@@ -51,6 +51,7 @@ module phase_rotator#( ...@@ -51,6 +51,7 @@ module phase_rotator#(
input start, //!< single-cycle start pulse that goes 1 cycle before first data input start, //!< single-cycle start pulse that goes 1 cycle before first data
input signed [SHIFT_WIDTH-1:0] shift_h, //!< subpixel shift horizontal input signed [SHIFT_WIDTH-1:0] shift_h, //!< subpixel shift horizontal
input signed [SHIFT_WIDTH-1:0] shift_v, //!< subpixel shift vertical input signed [SHIFT_WIDTH-1:0] shift_v, //!< subpixel shift vertical
input inv_checker, //!< negate 2-nd and fourth samples (for handling inverted checkerboard)
// input data CC,CS,SC,SS in column scan order (matching DTT) // input data CC,CS,SC,SS in column scan order (matching DTT)
input signed [FD_WIDTH-1:0] fd_din, //!< frequency domain data in, LATENCY=3 from start input signed [FD_WIDTH-1:0] fd_din, //!< frequency domain data in, LATENCY=3 from start
output reg signed [FD_WIDTH-1:0] fd_out, //!< frequency domain data in output reg signed [FD_WIDTH-1:0] fd_out, //!< frequency domain data in
...@@ -90,6 +91,7 @@ module phase_rotator#( ...@@ -90,6 +91,7 @@ module phase_rotator#(
reg [SHIFT_WIDTH-1:0] shift_v0; reg [SHIFT_WIDTH-1:0] shift_v0;
reg [SHIFT_WIDTH-1:0] shift_vr; reg [SHIFT_WIDTH-1:0] shift_vr;
reg [SHIFT_WIDTH-1:0] shift_hv; // combined horizonta and vertical shifts to match cntr_mux; reg [SHIFT_WIDTH-1:0] shift_hv; // combined horizonta and vertical shifts to match cntr_mux;
reg inv_checker_r;
reg [4:0] sign_cs; // sign for cos / sin, feed to DSP reg [4:0] sign_cs; // sign for cos / sin, feed to DSP
wire sign_cs_d; // sign_cs delayed by 3 clocks wire sign_cs_d; // sign_cs delayed by 3 clocks
reg [1:0] sign_cs_r; // sign_cs delayed by 5 clocks reg [1:0] sign_cs_r; // sign_cs delayed by 5 clocks
...@@ -108,6 +110,7 @@ module phase_rotator#( ...@@ -108,6 +110,7 @@ module phase_rotator#(
if (start) shift_hr <= shift_h; if (start) shift_hr <= shift_h;
if (start) shift_v0 <= shift_v; if (start) shift_v0 <= shift_v;
if (start) inv_checker_r <= inv_checker;
if (start_d[3]) shift_vr <= shift_v0; if (start_d[3]) shift_vr <= shift_v0;
if (rst) run_h <= 0; if (rst) run_h <= 0;
......
[*] [*]
[*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI [*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI
[*] Fri Dec 22 06:19:20 2017 [*] Fri Dec 22 22:36:36 2017
[*] [*]
[dumpfile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/simulation/mclt_test_02-20171221231546581.fst" [dumpfile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/simulation/mclt_test_02-20171222152552213.fst"
[dumpfile_mtime] "Fri Dec 22 06:15:49 2017" [dumpfile_mtime] "Fri Dec 22 22:25:57 2017"
[dumpfile_size] 1127723 [dumpfile_size] 1477081
[savefile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/mclt_test_02.sav" [savefile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/mclt_test_02.sav"
[timestart] 0 [timestart] 0
[size] 1920 1171 [size] 1920 1171
[pos] -1920 0 [pos] -1920 0
*-21.434872 1705000 355000 2885000 325000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 *-21.350550 3425000 355000 2885000 325000 7455000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] mclt_test_02. [treeopen] mclt_test_02.
[treeopen] mclt_test_02.mclt16x16_i.dtt_iv_8x8_ad_i.dct_iv8_1d_pass1_0_i. [treeopen] mclt_test_02.mclt16x16_i.dtt_iv_8x8_ad_i.dct_iv8_1d_pass1_0_i.
[treeopen] mclt_test_02.mclt16x16_i.dtt_iv_8x8_ad_i.dct_iv8_1d_pass2_0_i. [treeopen] mclt_test_02.mclt16x16_i.dtt_iv_8x8_ad_i.dct_iv8_1d_pass2_0_i.
...@@ -23,7 +23,7 @@ ...@@ -23,7 +23,7 @@
[treeopen] mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i. [treeopen] mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.
[treeopen] mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i. [treeopen] mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.
[sst_width] 306 [sst_width] 306
[signals_width] 397 [signals_width] 327
[sst_expanded] 1 [sst_expanded] 1
[sst_vpaned_height] 343 [sst_vpaned_height] 343
@c00200 @c00200
...@@ -1272,10 +1272,7 @@ mclt_test_02.mclt_bayer_fold_i.window_w[17:0] ...@@ -1272,10 +1272,7 @@ mclt_test_02.mclt_bayer_fold_i.window_w[17:0]
mclt_test_02.mclt_bayer_fold_i.window_r[17:0] mclt_test_02.mclt_bayer_fold_i.window_r[17:0]
mclt_test_02.mclt_bayer_fold_i.pix_wnd_r[33:0] mclt_test_02.mclt_bayer_fold_i.pix_wnd_r[33:0]
mclt_test_02.mclt_bayer_fold_i.pix_wnd_r2[24:0] mclt_test_02.mclt_bayer_fold_i.pix_wnd_r2[24:0]
@c00200 mclt_test_02.mclt_bayer_fold_i.phases[14:0]
-mclt_test_02.mclt_bayer_fold_i.phases
@1401200
-group_end
@28 @28
mclt_test_02.mclt_bayer_fold_i.var_first mclt_test_02.mclt_bayer_fold_i.var_first
mclt_test_02.mclt_bayer_fold_i.var_last mclt_test_02.mclt_bayer_fold_i.var_last
...@@ -1292,12 +1289,11 @@ mclt_test_02.mclt_bayer_fold_i.data_dtt_in[24:0] ...@@ -1292,12 +1289,11 @@ mclt_test_02.mclt_bayer_fold_i.data_dtt_in[24:0]
mclt_test_02.mclt_bayer_fold_i.dtt_in_cntr[6:0] mclt_test_02.mclt_bayer_fold_i.dtt_in_cntr[6:0]
@28 @28
mclt_test_02.mclt_bayer_fold_i.dtt_in_page mclt_test_02.mclt_bayer_fold_i.dtt_in_page
@29
mclt_test_02.mclt_bayer_fold_i.start_dtt mclt_test_02.mclt_bayer_fold_i.start_dtt
@800200 @c00200
-membuf -membuf
@8022 @8022
mclt_test_02.mclt_bayer_fold_i.dbgt_diff_wara[8:0] mclt_test_02.mclt_bayer_fold_i.dbg_diff_wara_dtt_in[8:0]
@20000 @20000
- -
- -
...@@ -1313,9 +1309,166 @@ mclt_test_02.mclt_bayer_fold_i.ram18p_var_w_var_r_dtt_in_i.waddr[8:0] ...@@ -1313,9 +1309,166 @@ mclt_test_02.mclt_bayer_fold_i.ram18p_var_w_var_r_dtt_in_i.waddr[8:0]
- -
@200 @200
- -
@1000200 @28
mclt_test_02.mclt_bayer_fold_i.dtt_out_we
@8022
mclt_test_02.mclt_bayer_fold_i.dtt_out_ram_wa[8:0]
@20000
-
-
@8022
mclt_test_02.mclt_bayer_fold_i.dbg_last_dtt_out_ram_wa[8:0]
@20000
-
-
-
@8022
mclt_test_02.mclt_bayer_fold_i.dtt_rd_ra0[8:0]
@20000
-
-
@8022
mclt_test_02.mclt_bayer_fold_i.dtt_rd_ra1[8:0]
mclt_test_02.mclt_bayer_fold_i.dbg_diff_wara_dtt_out0[8:0]
@20000
-
-
@8022
mclt_test_02.mclt_bayer_fold_i.dbg_diff_wara_dtt_out1[8:0]
@20000
-
-
@1401200
-membuf -membuf
@22
mclt_test_02.mclt_bayer_fold_i.dtt_r_ra[8:0]
mclt_test_02.mclt_bayer_fold_i.dtt_r_data[24:0]
@8420
mclt_test_02.mclt_bayer_fold_i.dtt_r_data[24:0]
@28
mclt_test_02.mclt_bayer_fold_i.dtt_start
mclt_test_02.mclt_bayer_fold_i.dtt_start_fill
@22
mclt_test_02.mclt_bayer_fold_i.dtt_out_ram_cntr[4:0]
@28
mclt_test_02.mclt_bayer_fold_i.dtt_start_first_fill
@22
mclt_test_02.mclt_bayer_fold_i.dtt_out_wd[24:0]
@28
mclt_test_02.mclt_bayer_fold_i.dtt_out_we
@c00022
mclt_test_02.mclt_bayer_fold_i.dtt_out_ram_wa[8:0]
@28
(0)mclt_test_02.mclt_bayer_fold_i.dtt_out_ram_wa[8:0]
(1)mclt_test_02.mclt_bayer_fold_i.dtt_out_ram_wa[8:0]
(2)mclt_test_02.mclt_bayer_fold_i.dtt_out_ram_wa[8:0]
(3)mclt_test_02.mclt_bayer_fold_i.dtt_out_ram_wa[8:0]
(4)mclt_test_02.mclt_bayer_fold_i.dtt_out_ram_wa[8:0]
(5)mclt_test_02.mclt_bayer_fold_i.dtt_out_ram_wa[8:0]
(6)mclt_test_02.mclt_bayer_fold_i.dtt_out_ram_wa[8:0]
(7)mclt_test_02.mclt_bayer_fold_i.dtt_out_ram_wa[8:0]
(8)mclt_test_02.mclt_bayer_fold_i.dtt_out_ram_wa[8:0]
@1401200
-group_end
@22
mclt_test_02.mclt_bayer_fold_i.dtt_dly_cntr[7:0]
mclt_test_02.mclt_bayer_fold_i.dtt_out_ram_wa[8:0]
mclt_test_02.mclt_bayer_fold_i.dtt_out_ram_wah[4:0]
mclt_test_02.mclt_bayer_fold_i.dtt_out_wa16[3:0]
@28
mclt_test_02.mclt_bayer_fold_i.dtt_start_out
@c00022
mclt_test_02.mclt_bayer_fold_i.dtt_rd_cntr_pre[8:0]
@28
(0)mclt_test_02.mclt_bayer_fold_i.dtt_rd_cntr_pre[8:0]
(1)mclt_test_02.mclt_bayer_fold_i.dtt_rd_cntr_pre[8:0]
(2)mclt_test_02.mclt_bayer_fold_i.dtt_rd_cntr_pre[8:0]
(3)mclt_test_02.mclt_bayer_fold_i.dtt_rd_cntr_pre[8:0]
(4)mclt_test_02.mclt_bayer_fold_i.dtt_rd_cntr_pre[8:0]
(5)mclt_test_02.mclt_bayer_fold_i.dtt_rd_cntr_pre[8:0]
(6)mclt_test_02.mclt_bayer_fold_i.dtt_rd_cntr_pre[8:0]
(7)mclt_test_02.mclt_bayer_fold_i.dtt_rd_cntr_pre[8:0]
(8)mclt_test_02.mclt_bayer_fold_i.dtt_rd_cntr_pre[8:0]
@1401200
-group_end
@28
mclt_test_02.mclt_bayer_fold_i.ram18p_var_w_var_r_dtt_out0_i.we
@c00022
mclt_test_02.mclt_bayer_fold_i.ram18p_var_w_var_r_dtt_out0_i.waddr[8:0]
@28
(0)mclt_test_02.mclt_bayer_fold_i.ram18p_var_w_var_r_dtt_out0_i.waddr[8:0]
(1)mclt_test_02.mclt_bayer_fold_i.ram18p_var_w_var_r_dtt_out0_i.waddr[8:0]
(2)mclt_test_02.mclt_bayer_fold_i.ram18p_var_w_var_r_dtt_out0_i.waddr[8:0]
(3)mclt_test_02.mclt_bayer_fold_i.ram18p_var_w_var_r_dtt_out0_i.waddr[8:0]
(4)mclt_test_02.mclt_bayer_fold_i.ram18p_var_w_var_r_dtt_out0_i.waddr[8:0]
(5)mclt_test_02.mclt_bayer_fold_i.ram18p_var_w_var_r_dtt_out0_i.waddr[8:0]
(6)mclt_test_02.mclt_bayer_fold_i.ram18p_var_w_var_r_dtt_out0_i.waddr[8:0]
(7)mclt_test_02.mclt_bayer_fold_i.ram18p_var_w_var_r_dtt_out0_i.waddr[8:0]
(8)mclt_test_02.mclt_bayer_fold_i.ram18p_var_w_var_r_dtt_out0_i.waddr[8:0]
@1401200
-group_end
@28
mclt_test_02.mclt_bayer_fold_i.ram18p_var_w_var_r_dtt_out0_i.ren
mclt_test_02.mclt_bayer_fold_i.ram18p_var_w_var_r_dtt_out0_i.regen
@c00022
mclt_test_02.mclt_bayer_fold_i.dtt_rd_ra1[8:0]
@28
(0)mclt_test_02.mclt_bayer_fold_i.dtt_rd_ra1[8:0]
(1)mclt_test_02.mclt_bayer_fold_i.dtt_rd_ra1[8:0]
(2)mclt_test_02.mclt_bayer_fold_i.dtt_rd_ra1[8:0]
(3)mclt_test_02.mclt_bayer_fold_i.dtt_rd_ra1[8:0]
(4)mclt_test_02.mclt_bayer_fold_i.dtt_rd_ra1[8:0]
(5)mclt_test_02.mclt_bayer_fold_i.dtt_rd_ra1[8:0]
(6)mclt_test_02.mclt_bayer_fold_i.dtt_rd_ra1[8:0]
(7)mclt_test_02.mclt_bayer_fold_i.dtt_rd_ra1[8:0]
(8)mclt_test_02.mclt_bayer_fold_i.dtt_rd_ra1[8:0]
@1401200
-group_end
@22
mclt_test_02.mclt_bayer_fold_i.x_shft[6:0]
mclt_test_02.mclt_bayer_fold_i.x_shft_r[6:0]
mclt_test_02.mclt_bayer_fold_i.x_shft_r2[6:0]
mclt_test_02.mclt_bayer_fold_i.x_shft_r3[6:0]
mclt_test_02.mclt_bayer_fold_i.x_shft_r4[6:0]
mclt_test_02.mclt_bayer_fold_i.y_shft[6:0]
mclt_test_02.mclt_bayer_fold_i.y_shft_r2[6:0]
mclt_test_02.mclt_bayer_fold_i.y_shft_r3[6:0]
mclt_test_02.mclt_bayer_fold_i.y_shft_r4[6:0]
@28
mclt_test_02.mclt_bayer_fold_i.inv_checker
mclt_test_02.mclt_bayer_fold_i.inv_checker_r
mclt_test_02.mclt_bayer_fold_i.inv_checker_r2
mclt_test_02.mclt_bayer_fold_i.inv_checker_r3
mclt_test_02.mclt_bayer_fold_i.inv_checker_r4
@800023
mclt_test_02.mclt_bayer_fold_i.dtt_rd_ra0[8:0]
@29
(0)mclt_test_02.mclt_bayer_fold_i.dtt_rd_ra0[8:0]
(1)mclt_test_02.mclt_bayer_fold_i.dtt_rd_ra0[8:0]
(2)mclt_test_02.mclt_bayer_fold_i.dtt_rd_ra0[8:0]
(3)mclt_test_02.mclt_bayer_fold_i.dtt_rd_ra0[8:0]
(4)mclt_test_02.mclt_bayer_fold_i.dtt_rd_ra0[8:0]
(5)mclt_test_02.mclt_bayer_fold_i.dtt_rd_ra0[8:0]
(6)mclt_test_02.mclt_bayer_fold_i.dtt_rd_ra0[8:0]
(7)mclt_test_02.mclt_bayer_fold_i.dtt_rd_ra0[8:0]
(8)mclt_test_02.mclt_bayer_fold_i.dtt_rd_ra0[8:0]
@1001201
-group_end
@800200 @800200
-rotator0
@28
mclt_test_02.mclt_bayer_fold_i.phase_rotator0_i.start
@22
mclt_test_02.mclt_bayer_fold_i.phase_rotator0_i.shift_h[6:0]
mclt_test_02.mclt_bayer_fold_i.phase_rotator0_i.shift_v[6:0]
mclt_test_02.mclt_bayer_fold_i.phase_rotator0_i.shift_hr[6:0]
mclt_test_02.mclt_bayer_fold_i.phase_rotator0_i.shift_v0[6:0]
mclt_test_02.mclt_bayer_fold_i.phase_rotator0_i.shift_vr[6:0]
@200
-
@1000200
-rotator0
@c00200
-mclt_bayer_fold -mclt_bayer_fold
@28 @28
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.rst mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.rst
...@@ -1378,8 +1531,8 @@ mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.regrst_a ...@@ -1378,8 +1531,8 @@ mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.regrst_a
mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.regrst_b mclt_test_02.mclt_bayer_fold_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.regrst_b
@1401200 @1401200
-mclt_wnd_mul -mclt_wnd_mul
@1000200
-mclt_bayer_fold -mclt_bayer_fold
@1000200
-mclt_bayer -mclt_bayer
@800200 @800200
-mono -mono
......
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