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Commit 62cf2722 authored by Andrey Filippov's avatar Andrey Filippov
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simulating, starting hardware testing

parent 802a2f02
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.project
View file @ 62cf2722
......@@ -62,42 +62,42 @@
<link>
<name>vivado_logs/VivadoBitstream.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151009231737365.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoBitstream-20151028193641990.log</location>
</link>
<link>
<name>vivado_logs/VivadoOpt.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151009231737365.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOpt-20151028193641990.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151009231737365.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPhys-20151028193641990.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPower.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151009231737365.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoOptPower-20151028193641990.log</location>
</link>
<link>
<name>vivado_logs/VivadoPlace.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151009231737365.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoPlace-20151028193641990.log</location>
</link>
<link>
<name>vivado_logs/VivadoRoute.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151009231737365.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoRoute-20151028193641990.log</location>
</link>
<link>
<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151009231255456.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoSynthesis-20151028193155597.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151009231737365.log</location>
<location>/home/andrey/git/x393/vivado_logs/VivadoTimimgSummaryReportImplemented-20151028193641990.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
......
.settings/com.elphel.vdt.VivadoSynthesis.prefs
View file @ 62cf2722
......@@ -2,7 +2,7 @@ VivadoSynthesis_101_MaxMsg=10000
VivadoSynthesis_102_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@->
VivadoSynthesis_115_flatten_hierarchy=none
VivadoSynthesis_121_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@->
VivadoSynthesis_122_ConstraintsFiles=x393.xdc<-@\#\#@->x393_timing.xdc<-@\#\#@->
VivadoSynthesis_122_ConstraintsFiles=x393.xdc<-@\#\#@->x393_nox2_timing.xdc<-@\#\#@->
VivadoSynthesis_122_SkipSnapshotSynth=true
VivadoSynthesis_123_ResetProject=true
VivadoSynthesis_123_SkipSnapshotSynth=true
......
compressor_jp/bit_stuffer_27_32.v
View file @ 62cf2722
......@@ -76,7 +76,8 @@ module bit_stuffer_27_32#(
// barrel shifter stage 1 (0/8/16/24)
if (ds) case (early_length[4:3])
if (rst) data1 <= 'bx;
else if (ds) case (early_length[4:3])
2'h0: data1 <= { din, 24'b0};
2'h1: data1 <= { 8'b0,din, 16'b0};
2'h2: data1 <= {16'b0,din, 8'b0};
......@@ -84,13 +85,16 @@ module bit_stuffer_27_32#(
endcase
// barrel shifter stage 2 (0/2/4/6)
if (stage[0]) case (dlen1[2:1])
if (rst) data2 <= 'bx;
else if (stage[0]) case (dlen1[2:1])
2'h0: data2 <= { data1, 6'b0};
2'h1: data2 <= { 2'b0,data1, 4'b0};
2'h2: data2 <= { 4'b0,data1, 2'b0};
2'h3: data2 <= { 6'b0,data1 };
endcase
if (stage[0]) case (dlen1[4:0])
if (rst) dmask2_rom <= 'bx;
else if (stage[0]) case (dlen1[4:0])
5'h00: dmask2_rom <= 32'hffffffff;
5'h01: dmask2_rom <= 32'h7fffffff;
5'h02: dmask2_rom <= 32'h3fffffff;
......@@ -125,7 +129,8 @@ module bit_stuffer_27_32#(
5'h1f: dmask2_rom <= 32'h00000001;
endcase
// barrel shifter stage 3 (0/1), combined with output/hold register
if (ds_stage[1]) begin
if (rst) data3 <= 'bx;
else if (ds_stage[1]) begin
data3[DATA3_LEN-1 -: 32] <= (~dmask2_rom & (dlen2[5] ? {data3[DATA3_LEN-1-32 : 0],6'b0}: data3[DATA3_LEN-1 -: 32])) |
( dmask2_rom & (dlen2[0] ? {1'b0,data2[DATA2_LEN-1 -: 31]} : data2[DATA2_LEN-1 -: 32]));
data3[DATA3_LEN-1-32: 0] <= dlen2[0] ? data2[DATA2_LEN-31-1 : 0] : {data2[DATA2_LEN-32-1 : 0], 1'b0};
......@@ -135,7 +140,9 @@ module bit_stuffer_27_32#(
// dv <= (ds_stage[1] && dlen1[5]) || (flush_stage[1] && !(|data3[DATA3_LEN-1 -: 32]));
// dv <= (ds_stage[0] && dlen1[5]) || (flush_stage[1] && !(|data3[DATA3_LEN-1 -: 32]));
dv <= (ds_stage[0] && dlen1[5]) || (flush_stage[1] && (|data3[DATA3_LEN-1 -: 32]));
// no difference in number of cells
// if (rst ) bytes_out <= 0; // if the dv was caused by 32 bits full - output 4 bytes
// else if (ds_stage[1]) bytes_out <= 0; // if the dv was caused by 32 bits full - output 4 bytes
if (rst || ds_stage[1]) bytes_out <= 0; // if the dv was caused by 32 bits full - output 4 bytes
else if (flush_stage[1]) bytes_out <= pre_bits_out_w[4:3];
......
compressor_jp/bit_stuffer_escape.v
View file @ 62cf2722
......@@ -215,7 +215,7 @@ module bit_stuffer_escape(
case (sel0_w)
2'b00 : d_out[ 7: 0] <= fifo_out_barrel_w[ 7: 0];
2'b01 : d_out[ 7: 0] <= fifo_out_barrel_w[15: 8];
2'b01 : d_out[ 7: 0] <= fifo_out_barrel_w[23:16];
2'b10 : d_out[ 7: 0] <= fifo_out_barrel_w[23:16];
2'b11 : d_out[ 7: 0] <= 8'b0;
default : d_out[ 7: 0] <= 'bx;
endcase
......@@ -228,11 +228,14 @@ module bit_stuffer_escape(
if (rst) flush_pend[1] <= 0;
else flush_pend[1] <= flush_pend[0] &&!flush_pend[1] && !rdy_w;
flush_pend[2] <= flush_pend[1];
if (rst) flush_pend[2] <= 0;
else flush_pend[2] <= flush_pend[1];
flush_out <= flush_pend[2];
if (rst) flush_out <= 0;
else flush_out <= flush_pend[2];
if ( rdy_w || flush_pend[1]) casex(bytes_rdy_w[3:0])
if (rst) bytes_out <= 'bx;
else if ( rdy_w || flush_pend[1]) casex(bytes_rdy_w[3:0])
4'b10xx : bytes_out <= 1;
4'b110x : bytes_out <= 2;
4'b1110 : bytes_out <= 3;
......
compressor_jp/bit_stuffer_metadata.v
View file @ 62cf2722
......@@ -119,9 +119,8 @@ module bit_stuffer_metadata(
data_out_valid <= stb || trailer;
if (xrst) running <= 0;
if (xrst || trailer) running <= 0;
else if (stb_start) running <= 1;
else if (trailer) running <= 0;
done <= trailer_done;
// re-clock abort, extract leading edge
......
compressor_jp/cmprs_out_fifo32.v 0 → 100644
View file @ 62cf2722
/*******************************************************************************
* Module: cmprs_out_fifo32
* Date:2015-06-25
* Author: Andrey Filippov
* Description: Compressor output FIFO, modified to use 32-bit input and xclk
*
* Copyright (c) 2015 Elphel, Inc.
* cmprs_out_fifo32.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* cmprs_out_fifo32.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/
`timescale 1ns/1ps
module cmprs_out_fifo32(
// input rst, // mostly for simulation
// wclk domain
input wclk, // source clock (1x pixel clock)
input wrst, // @posedge wclk, sync reset
input we,
input [31:0] wdata,
input wa_rst, // reset low address bits when stuffer is disabled (to make sure it is multiple of 32 bytes
input wlast, // written last 32 bytes of a frame (flush FIFO) - stuffer_done (has to be later than we)
output eof_written_wclk, // eof_written - reclocked to wclk
// rclk domain
input rclk,
input rrst, // @posedge rclk, sync reset
input rst_fifo, // reset FIFO (set read address to write, reset count)
input ren,
output [63:0] rdata,
output eof, // single rclk pulse signalling EOF
input eof_written, // confirm frame written ofer AFI to the system memory (single rclk pulse)
output flush_fifo, // EOF, need to output all what is in FIFO (Stays active until enough data chunks are read)
output [7:0] fifo_count // number of 32-byte chunks in FIFO
);
reg regen;
reg [ 8:0] raddr;
reg [ 7:0] count32;
reg [ 7:0] lcount32; // counting chunks left in the same frame
reg [ 9:0] waddr;
wire written32b; // written 32 bytes, re-clocked to read clock domain (single-cycle)
wire wlast_rclk;
reg flush_fifo_r;
assign flush_fifo = flush_fifo_r;
assign fifo_count = count32;
assign eof = wlast_rclk;
always @ (posedge wclk) begin
if (wrst) waddr <= 0;
else if (wa_rst) waddr <= waddr & 10'h3f8; // reset 3 LSBs only
else if (we) waddr <= waddr + 1;
end
always @ (posedge rclk) begin
regen <= ren;
if (rst_fifo) raddr <= {waddr[9:3],2'b0};
else if (ren) raddr <= raddr + 1;
if (rst_fifo) count32 <= 0;
else if ( written32b && !(ren && (&raddr[1:0]))) count32 <= count32 + 1;
else if (!written32b && (ren && (&raddr[1:0]))) count32 <= count32 - 1;
if (rst_fifo) lcount32 <= 0;
else if (wlast_rclk) lcount32 <= count32;
else if ((lcount32 !=0) && ren && (&raddr[1:0])) lcount32 <= lcount32 - 1;
if (rst_fifo) flush_fifo_r <= 0;
else if (wlast_rclk) flush_fifo_r <= 1;
else if ((count32[7:1] == 0) && ( !count32[0] || ren)) flush_fifo_r <= 0;
end
// wclk -> rclk
pulse_cross_clock written32b_i (.rst(wrst), .src_clk(wclk), .dst_clk(rclk), .in_pulse(we && (&waddr[2:0])), .out_pulse(written32b),.busy());
pulse_cross_clock wlast_rclk_i (.rst(wrst), .src_clk(wclk), .dst_clk(rclk), .in_pulse(wlast), .out_pulse(wlast_rclk),.busy());
// rclk -> wclk
pulse_cross_clock eof_written_wclk_i (.rst(rrst), .src_clk(rclk), .dst_clk(wclk), .in_pulse(eof_written), .out_pulse(eof_written_wclk),.busy());
ram_var_w_var_r #(
.REGISTERS(1),
.LOG2WIDTH_WR(5),
.LOG2WIDTH_RD(6)
) fifo_i (
.rclk (rclk), // input
.raddr (raddr), // input[8:0]
.ren (ren), // input
.regen (regen), // input
.data_out (rdata), // output[63:0]
.wclk (wclk), // input - OK, negedge mclk
.waddr (waddr), // input[10:0]
.we (we), // input
.web (8'hff), // input[7:0]
.data_in (wdata) // input[15:0]
);
endmodule
compressor_jp/compressor393.v
View file @ 62cf2722
......@@ -119,9 +119,10 @@ module compressor393 # (
`endif
)(
// input rst, // global reset
input xclk, // global clock input, compressor single clock rate
`ifdef USE_XCLK2X
input xclk2x, // global clock input, compressor double clock rate, nominally rising edge aligned
`endif
input mrst, // @posedge mclk, sync reset
input xrst, // @posedge xclk, sync reset
input hrst, // @posedge hclk, sync reset
......@@ -388,7 +389,9 @@ module compressor393 # (
) jp_channel_i (
// .rst (rst), // input
.xclk (xclk), // input
`ifdef USE_XCLK2X
.xclk2x (xclk2x), // input
`endif
.mrst (mrst), // input
.xrst (xrst), // input
.hrst (hrst), // input
......
compressor_jp/huffman_snglclk.v
View file @ 62cf2722
......@@ -46,8 +46,8 @@ module huffman_snglclk (
output last_block,
output reg test_lbw,
output gotLastBlock, // last block done - flush the rest bits
// input clk_flush, // other clock to generate synchronized 1-cycle flush_clk output
// output flush_clk, // 1-cycle flush output @ clk_flush
input clk_flush, // other clock to generate synchronized 1-cycle flush_clk output
output flush_clk, // 1-cycle flush output @ clk_flush
output fifo_or_full // FIFO output register full - just for debuging
);
......@@ -256,7 +256,6 @@ module huffman_snglclk (
.out_bits (do27), // output[26:0] reg
.out_len (dl) // output[4:0] reg
);
/*
pulse_cross_clock flush_clk_i (
.rst (rst),
.src_clk (xclk),
......@@ -264,7 +263,5 @@ module huffman_snglclk (
.in_pulse (flush),
.out_pulse (flush_clk),
.busy ());
*/
endmodule
compressor_jp/huffman_stuffer_meta.v
View file @ 62cf2722
......@@ -47,7 +47,10 @@ module huffman_stuffer_meta(
output [31:0] data_out, // [31:0] output data
output data_out_valid,// output data valid
output done, // reset by !en, goes high after some delay after flushing
output running // from registering timestamp until done
output running, // from registering timestamp until done
input clk_flush, // other clock to generate synchronized 1-cycle flush_clk output
output flush_clk // 1-cycle flush output @ clk_flush
`ifdef DEBUG_RING
,output test_lbw,
output gotLastBlock, // last block done - flush the rest bits
......@@ -93,8 +96,8 @@ module huffman_stuffer_meta(
.test_lbw (),
.gotLastBlock (), // last block done - flush the rest bits
`endif
// .clk_flush(), // input
// .flush_clk(), // output
.clk_flush (clk_flush), // input
.flush_clk (flush_clk), // output
.fifo_or_full() // output
);
......
compressor_jp/jp_channel.v
View file @ 62cf2722
......@@ -105,7 +105,9 @@ module jp_channel#(
)(
// input rst, // global reset
input xclk, // global clock input, compressor single clock rate
`ifdef USE_XCLK2X
input xclk2x, // global clock input, compressor double clock rate, nominally rising edge aligned
`endif
input mrst, // @posedge mclk, sync reset
input xrst, // @posedge xclk, sync reset
input hrst, // @posedge xclk, sync reset
......@@ -306,12 +308,15 @@ module jp_channel#(
/// wire test_lbw;
wire stuffer_rdy; // receiver (bit stuffer) is ready to accept data;
`ifdef USE_XCLK2X
wire [15:0] huff_do; // output[15:0] reg
wire [3:0] huff_dl; // output[3:0] reg
wire huff_dv; // output reg
wire flush; // output reg @ negedge xclk2x
wire last_block; // @negedge xxlk2x - used to copy timestamp in stuffer
wire stuffer_rdy; // receiver (bit stuffer) is ready to accept data;
`endif
wire [31:0] cmd_data; // 32-bit data to write to tables and registers(LSB first) - from cmd_deser
......@@ -344,10 +349,24 @@ module jp_channel#(
assign set_coring_w = cmd_we && (cmd_a== CMPRS_CORING_MODE);
assign set_tables_w = cmd_we && ((cmd_a & 6)== CMPRS_TABLES);
// assign buf_ren = buf_rd[0];
// assign buf_regen = buf_rd[1];
`ifdef USE_XCLK2X
// re-sync to posedge xclk2x
reg xrst2xn;
always @ (negedge xclk2x) xrst2xn <= xrst;
`endif
`ifdef DEBUG_RING
`ifndef USE_XCLK2X
// wire [15:0] huff_do; // output[15:0] reg
// wire [3:0] huff_dl; // output[3:0] reg
// wire huff_dv; // output reg
// wire flush; // output reg @ negedge xclk2x
wire last_block = 0; // @negedge xxlk2x - used to copy timestamp in stuffer
wire stuffer_rdy = 1; // receiver (bit stuffer) is ready to accept data;
`endif
reg [31:0] debug_fifo_in;
reg [31:0] debug_fifo_out;
reg [15:0] pre_start_cntr;
......@@ -388,7 +407,11 @@ module jp_channel#(
wire [2:0] dbg_block_mem_wa_save;
timestamp_to_parallel dbg_timestamp_to_parallel_i (
`ifdef USE_XCLK2X
.clk (~xclk2x), // input
`else
.clk (xclk), // input
`endif
.pre_stb (dbg_ts_rstb), // input
.tdata (dbg_ts_dout), // input[7:0]
.sec (dbg_sec), // output[31:0] reg
......@@ -398,7 +421,11 @@ module jp_channel#(
// cmprs_standalone - use to reset flush
`ifdef USE_XCLK2X
always @ (posedge ~xclk2x) begin
`else
always @ (posedge xclk) begin
`endif
dbg_reset_fifo <= fifo_rst;
if (xrst2xn || dbg_reset_fifo) debug_fifo_in <= 0;
else if (stuffer_dv) debug_fifo_in <= debug_fifo_in + 1;
......@@ -968,7 +995,11 @@ module jp_channel#(
// TODO: Verify focus_sharp393: quantizer output (with strobes) is now 2 cycles later than in 353 (relative to xdct out). Seems to be OK.
focus_sharp393 focus_sharp393_i (
.clk (xclk), // input - pixel clock
`ifdef USE_XCLK2X
.clk2x (xclk2x), // input 2x pixel clock
`else
.clk2x (xclk), // FIXME: fix the module not to use xclk2x
`endif
.en (frame_en), // input
.mclk (mclk), // input system clock to write tables
......@@ -991,21 +1022,28 @@ module jp_channel#(
.hifreq (hifreq[31:0]) // output[31:0] reg accumulated high frequency components in a frame sub-window
);
// Format DC components to be output as a mini-frame. Was not used in the late NC353 as the dma1 channel was use3d for IMU instead of dcc
// Format DC components to be output as a mini-frame. Was not used in the late NC353 as the dma1 channel was used for IMU instead of dcc
wire finish_dcc;
`ifdef USE_XCLK2X
wire [15:0] stuffer_do;
`else
wire [31:0] stuffer_do;
`endif
wire stuffer_dv;
wire stuffer_done;
wire eof_written_xclk2xn;
// re-sync to posedge xclk2x
reg xrst2xn;
always @ (negedge xclk2x) xrst2xn <= xrst;
`ifdef USE_XCLK2X
pulse_cross_clock finish_dcc_i (.rst(xrst2xn), .src_clk(~xclk2x), .dst_clk(xclk2x), .in_pulse(stuffer_done), .out_pulse(finish_dcc),.busy());
`else
assign finish_dcc = stuffer_done;
`endif
dcc_sync393 dcc_sync393_i (
`ifdef USE_XCLK2X
.sclk (xclk2x), // input
`else
.sclk (xclk), // input
`endif
.dcc_en (dcc_en), // input xclk rising, sync with start of the frame
.finish_dcc (finish_dcc), // input @ sclk rising
.dcc_vld (dccvld), // input xclk rising
......@@ -1053,6 +1091,7 @@ module jp_channel#(
// wire [2:0] dbg_block_mem_wa;
// wire [2:0] dbg_block_mem_wa_save;
`ifdef USE_XCLK2X
huffman393 i_huffman (
.xclk (xclk), // input
.xclk2x (xclk2x), // input
......@@ -1126,7 +1165,33 @@ module jp_channel#(
,.test_cntr1(test_cntr1[7:0])
`endif
);
`ifdef DISPLAY_COMPRESSED_DATA
//cat x393_testbench03-latest.log | grep "COMPRESSOR[32 ]*CHN" > compressors_out32.log
wire eof_written_xclk2xn;
pulse_cross_clock stuffer_done_mclk_i (.rst(xrst2xn), .src_clk(~xclk2x), .dst_clk(mclk), .in_pulse(stuffer_done), .out_pulse(stuffer_done_mclk),.busy());
cmprs_out_fifo cmprs_out_fifo_i (
// source (stuffer) clock domain
.wclk (~xclk2x), // input source clock (2x pixel clock, inverted) - same as stuffer out
.wrst (xrst2xn), // input mostly for simulation
.we (stuffer_dv), // @ posedge(~xclk2x) input write data from stuffer
.wdata ({stuffer_do[7:0],stuffer_do[15:8]}), // input[15:0] data from stuffer module;
.wa_rst (!stuffer_en), // input reset low address bits when stuffer is disabled (to make sure it is multiple of 32 bytes
.wlast (stuffer_done), // input - written last 32 bytes of a frame (flush FIFO) - stuffer_done (has to be later than we)
.eof_written_wclk (eof_written_xclk2xn), // output - AFI had transferred frame data to the system memory
// AFI clock domain
.rclk (hclk), // @posedge(hclk) input - AFI clock
.rrst (hrst), // input - AFI clock
.rst_fifo (fifo_rst), // input - reset FIFO (set read address to write, reset count)
.ren (fifo_ren), // input - fifo read from AFI channel mux
.rdata (fifo_rdata), // output[63:0] - data to AFI channel mux (latency == 2 from fifo_ren)
.eof (fifo_eof), // output single hclk pulse signalling EOF
.eof_written (eof_written), // input single hclk pulse confirming frame data is written to the system memory
.flush_fifo (fifo_flush), // output level signalling that FIFO has data from the current frame (use short AXI burst if needed)
.fifo_count (fifo_count) // output[7:0] - number of 32-byte chunks available in FIFO
);
pulse_cross_clock eof_written_mclk_i (.rst(xrst2xn), .src_clk(~xclk2x), .dst_clk(mclk), .in_pulse(eof_written_xclk2xn), .out_pulse(eof_written_mclk),.busy());
`ifdef DISPLAY_COMPRESSED_DATA
integer dbg_stuffer_word_number;
reg dbg_odd_stuffer_dv;
reg [15:0] dbg_even_stuffer_do;
......@@ -1150,15 +1215,9 @@ module jp_channel#(
else if (stuffer_dv) dbg_odd_stuffer_dv = ~dbg_odd_stuffer_dv;
end
`endif
// Debugging - attaching new compressor module in parallel to the existing one
wire [31:0] alt_stuffer_do; // SuppressThisWarning VEditor Unused
wire alt_stuffer_dv; // SuppressThisWarning VEditor Unused
wire alt_stuffer_done; // SuppressThisWarning VEditor Unused
wire alt_stuffer_running; // SuppressThisWarning VEditor Unused
`endif
`else
huffman_stuffer_meta huffman_stuffer_meta_i (
.mclk (mclk), // input
.mrst (mrst), // input
......@@ -1174,53 +1233,33 @@ module jp_channel#(
.ts_pre_stb (ts_pre_stb), // input
.ts_data (ts_data), // input[7:0]
.color_first (color_first), // input valid @xclk - only for sec/usec
.data_out (alt_stuffer_do), // output[31:0]
.data_out_valid (alt_stuffer_dv), // output
.done (alt_stuffer_done), // output
.running (alt_stuffer_running) // output
`ifdef DEBUG_RING
,.test_lbw (), // output
.gotLastBlock (), // output // last block done - flush the rest bits
.dbg_etrax_dma (), // output[3:0]
.dbg_ts_rstb (), // output
.dbg_ts_dout () //output[7:0]
`endif
);
`ifdef DISPLAY_COMPRESSED_DATA
integer alt_stuffer_word_number;
always @ (posedge xclk) begin
if (alt_stuffer_dv) begin
$display ("COMPRESSOR32 CHN%d 0x%x -> 0x%x", CMPRS_NUMBER, alt_stuffer_word_number, alt_stuffer_do);
end
if (alt_stuffer_done) begin
$display ("COMPRESSOR32 CHN%d ***** DONE *****",CMPRS_NUMBER);
end
if (!stuffer_en || alt_stuffer_done) alt_stuffer_word_number = 0;
else if (alt_stuffer_dv) alt_stuffer_word_number = alt_stuffer_word_number + 1;
end
//CMPRS_NUMBER
`endif
//cat x393_testbench03-latest.log | grep "COMPRESSOR[32 ]*CHN" > compressors_out32.log
/*
,output dbg_ts_rstb
,output [7:0] dbg_ts_dout
.data_out (stuffer_do), // output[31:0]
.data_out_valid (stuffer_dv), // output
.done (stuffer_done), // output
.running (stuffer_running), // output
.clk_flush (hclk), // input
.flush_clk (flush_hclk) // output
*/
pulse_cross_clock stuffer_done_mclk_i (.rst(xrst2xn), .src_clk(~xclk2x), .dst_clk(mclk), .in_pulse(stuffer_done), .out_pulse(stuffer_done_mclk),.busy());
cmprs_out_fifo cmprs_out_fifo_i (
// .rst (rst), // input mostly for simulation
`ifdef DEBUG_RING
,.test_lbw (dbg_test_lbw), // output reg ??
.gotLastBlock (dbg_gotLastBlock), // output ?? - unused (was for debug)
.dbg_etrax_dma (etrax_dma), // output[3:0]
.dbg_ts_rstb (dbg_ts_rstb), // output
.dbg_ts_dout (dbg_ts_dout) //output[7:0]
`endif
);
wire eof_written_xclk;
pulse_cross_clock stuffer_done_mclk_i (.rst(xrst), .src_clk(xclk), .dst_clk(mclk), .in_pulse(stuffer_done), .out_pulse(stuffer_done_mclk),.busy());
cmprs_out_fifo32 cmprs_out_fifo_i (
// source (stuffer) clock domain
.wclk (~xclk2x), // input source clock (2x pixel clock, inverted) - same as stuffer out
.wrst (xrst2xn), // input mostly for simulation
.wclk (xclk), // input source clock (1x pixel clock, inverted) - same as stuffer out
.wrst (xrst), // input mostly for simulation
.we (stuffer_dv), // @ posedge(~xclk2x) input write data from stuffer
.wdata ({stuffer_do[7:0],stuffer_do[15:8]}), // input[15:0] data from stuffer module;
.wdata ({stuffer_do[7:0],stuffer_do[15:8],stuffer_do[23:16],stuffer_do[31:24]}), // input[15:0] data from stuffer module;
.wa_rst (!stuffer_en), // input reset low address bits when stuffer is disabled (to make sure it is multiple of 32 bytes
.wlast (stuffer_done), // input - written last 32 bytes of a frame (flush FIFO) - stuffer_done (has to be later than we)
.eof_written_wclk (eof_written_xclk2xn), // output - AFI had transferred frame data to the system memory
.eof_written_wclk (eof_written_xclk), // output - AFI had transferred frame data to the system memory
// AFI clock domain
.rclk (hclk), // @posedge(hclk) input - AFI clock
.rrst (hrst), // input - AFI clock
......@@ -1232,7 +1271,23 @@ module jp_channel#(
.flush_fifo (fifo_flush), // output level signalling that FIFO has data from the current frame (use short AXI burst if needed)
.fifo_count (fifo_count) // output[7:0] - number of 32-byte chunks available in FIFO
);
pulse_cross_clock eof_written_mclk_i (.rst(xrst2xn), .src_clk(~xclk2x), .dst_clk(mclk), .in_pulse(eof_written_xclk2xn), .out_pulse(eof_written_mclk),.busy());
pulse_cross_clock eof_written_mclk_i (.rst(xrst), .src_clk(xclk), .dst_clk(mclk), .in_pulse(eof_written_xclk), .out_pulse(eof_written_mclk),.busy());
`ifdef DISPLAY_COMPRESSED_DATA
integer stuffer_word_number;
always @ (posedge xclk) begin
if (stuffer_dv) begin
$display ("COMPRESSOR CHN%d 0x%x -> 0x%x", CMPRS_NUMBER, stuffer_word_number, stuffer_do);
end
if (stuffer_done) begin
$display ("COMPRESSOR CHN%d ***** DONE *****",CMPRS_NUMBER);
end
if (!stuffer_en || stuffer_done) stuffer_word_number = 0;
else if (stuffer_dv) stuffer_word_number = stuffer_word_number + 1;
end
`endif
`endif
// TODO: Add status module to combine/FF, re-clock status signals
......
fpga_version.vh
View file @ 62cf2722
parameter FPGA_VERSION = 32'h03930050;
\ No newline at end of file
parameter FPGA_VERSION = 32'h03930054; // 'old' sensor/converter with debug
// parameter FPGA_VERSION = 32'h03930053; // trying if(reset ) reg <- 'bx
\ No newline at end of file
includes/x393_parameters.vh
View file @ 62cf2722
......@@ -482,7 +482,7 @@
//sensor_fifo parameters
parameter SENSOR_DATA_WIDTH = 12,
parameter SENSOR_FIFO_2DEPTH = 4,
parameter SENSOR_FIFO_DELAY = 5, // 7,
parameter [3:0] SENSOR_FIFO_DELAY = 5, // 7,
//`endif
// other parameters for histogram_saxi module
......
sensor/sensor_channel.v
View file @ 62cf2722
......@@ -188,7 +188,7 @@ module sensor_channel#(
//sensor_fifo parameters
parameter SENSOR_DATA_WIDTH = 12,
parameter SENSOR_FIFO_2DEPTH = 4,
parameter SENSOR_FIFO_DELAY = 5, // 7,
parameter [3:0] SENSOR_FIFO_DELAY = 5, // 7,
`endif
// sens_parallel12 other parameters
......
sensor/sensor_fifo.v
View file @ 62cf2722
......@@ -23,7 +23,7 @@
module sensor_fifo #(
parameter SENSOR_DATA_WIDTH = 12,
parameter SENSOR_FIFO_2DEPTH = 4, // 4-bit address
parameter SENSOR_FIFO_DELAY = 5 // 7 // approxiametly half (1 << SENSOR_FIFO_2DEPTH) - how long to wait after getting HACT on FIFO before stering it on output
parameter [3:0] SENSOR_FIFO_DELAY = 5 // 7 // approxiametly half (1 << SENSOR_FIFO_2DEPTH) - how long to wait after getting HACT on FIFO before stering it on output
)(
// input rst,
input iclk, // input -synchronous clock
......
sensor/sensors393.v
View file @ 62cf2722
......@@ -188,7 +188,7 @@ module sensors393 #(
//sensor_fifo parameters
parameter SENSOR_DATA_WIDTH = 12,
parameter SENSOR_FIFO_2DEPTH = 4,
parameter SENSOR_FIFO_DELAY = 5, // 7,
parameter [3:0] SENSOR_FIFO_DELAY = 5, // 7,
`endif
// other parameters for histogram_saxi module
parameter HIST_SAXI_ADDR_MASK = 'h7f0,
......
system_defines.vh
View file @ 62cf2722
......@@ -4,10 +4,12 @@
`define PRELOAD_BRAMS
`define DISPLAY_COMPRESSED_DATA
// if HISPI is not defined, parallel sensor interface is used for all channels
`define HISPI
// `define HISPI
`define USE_PCLK2X
`define USE_XCLK2X
`define DEBUG_RING 1
// `define USE_PCLK2X
// `define DEBUG_RING 1
`define MEMBRIDGE_DEBUG_WRITE 1
// Enviroment-dependent options
`ifdef IVERILOG
......
util_modules/clocks393.v
View file @ 62cf2722
......@@ -50,11 +50,12 @@ module clocks393#(
parameter DIVCLK_DIVIDE_XCLK = 1,
parameter CLKFBOUT_MULT_XCLK = 20, // 50*20=1000 MHz
parameter CLKOUT_DIV_XCLK = 10, // 100 MHz
parameter BUF_CLK1X_XCLK = "BUFG",
`ifdef USE_XCLK2X
parameter CLKOUT_DIV_XCLK2X = 5, // 200 MHz
parameter PHASE_CLK2X_XCLK = 0.000,
parameter BUF_CLK1X_XCLK = "BUFG",
parameter BUF_CLK1X_XCLK2X = "BUFG",
`endif
parameter CLKIN_PERIOD_SYNC = 20, // 50MHz
parameter DIVCLK_DIVIDE_SYNC = 1,
parameter CLKFBOUT_MULT_SYNC = 20, // 50*20=1000 MHz
......@@ -106,7 +107,9 @@ module clocks393#(
output pclk2x, // global clock for sennors, 2x frequency (now 192MHz)
`endif
output xclk, // global clock for compressor (now 100MHz)
`ifdef USE_XCLK2X
output xclk2x, // global clock for compressor, 2x frequency (now 200MHz)
`endif
output sync_clk, // global clock for camsync module (96 MHz for 353 compatibility - switch to 100MHz)?
output time_ref, // non-global, just RTC (currently just mclk/8 = 25 MHz)
input [1:0] extra_status, // just extra two status bits from the top module
......@@ -232,16 +235,24 @@ module clocks393#(
.DIVCLK_DIVIDE (DIVCLK_DIVIDE_XCLK),
.CLKFBOUT_MULT (CLKFBOUT_MULT_XCLK),
.CLKOUT_DIV_CLK1X (CLKOUT_DIV_XCLK),
.BUF_CLK1X (BUF_CLK1X_XCLK),
`ifdef USE_XCLK2X
.CLKOUT_DIV_CLK2X (CLKOUT_DIV_XCLK2X),
.PHASE_CLK2X (PHASE_CLK2X_XCLK),
.BUF_CLK1X (BUF_CLK1X_XCLK),
.BUF_CLK2X (BUF_CLK1X_XCLK2X)
`else
.BUF_CLK2X ("NONE")
`endif
) dual_clock_xclk_i (
.rst (async_rst || reset_clk[2]), // input
.clk_in (aclk), // input
.pwrdwn (pwrdwn_clk[2]), // input
.clk1x (xclk), // output
`ifdef USE_XCLK2X
.clk2x (xclk2x), // output
`else
.clk2x (), // output
`endif
.locked (locked[2]) // output
);
......
x393.v
View file @ 62cf2722
......@@ -201,8 +201,9 @@ module x393 #(
`endif
// compressor pixel rate can be adjusted independently
wire xclk; // global clock, compressor pixel rate (100 MHz)?
`ifdef USE_XCLK2X
wire xclk2x; // global clock, compressor double pixel rate (200 MHz)
`endif
wire camsync_clk; // global clock used for external synchronization. 96MHz in x353.
// Make it independent of pixel, compressor and mclk so it can be frozen
wire logger_clk; // global clock for the event logger. Use 100 MHz, shared with camsync_clk
......@@ -1814,9 +1815,10 @@ assign axi_grst = axi_rst_pre;
`endif
) compressor393_i (
// .rst (axi_rst), // input
.xclk (xclk), // input
`ifdef USE_XCLK2X
.xclk2x (xclk2x), // input
`endif
.mclk (mclk), // input
.mrst (mrst), // input
.xrst (xrst), // input
......@@ -2178,10 +2180,12 @@ assign axi_grst = axi_rst_pre;
.DIVCLK_DIVIDE_XCLK (DIVCLK_DIVIDE_XCLK),
.CLKFBOUT_MULT_XCLK (CLKFBOUT_MULT_XCLK),
.CLKOUT_DIV_XCLK (CLKOUT_DIV_XCLK),
.BUF_CLK1X_XCLK (BUF_CLK1X_XCLK),
`ifdef USE_XCLK2X
.CLKOUT_DIV_XCLK2X (CLKOUT_DIV_XCLK2X),
.PHASE_CLK2X_XCLK (PHASE_CLK2X_XCLK),
.BUF_CLK1X_XCLK (BUF_CLK1X_XCLK),
.BUF_CLK1X_XCLK2X (BUF_CLK1X_XCLK2X),
`endif
.CLKIN_PERIOD_SYNC (CLKIN_PERIOD_SYNC),
.DIVCLK_DIVIDE_SYNC (DIVCLK_DIVIDE_SYNC),
.CLKFBOUT_MULT_SYNC (CLKFBOUT_MULT_SYNC),
......@@ -2228,7 +2232,9 @@ assign axi_grst = axi_rst_pre;
.pclk2x (pclk2x), // output
`endif
.xclk (xclk), // output
`ifdef USE_XCLK2X
.xclk2x (xclk2x), // output
`endif
.sync_clk (camsync_clk), // output
.time_ref (time_ref), // output
.extra_status ({1'b0,idelay_ctrl_rdy}), // input[1:0]
......
x393_testbench03.sav
View file @ 62cf2722
[*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Wed Oct 28 00:25:39 2015
[*] Wed Oct 28 16:58:42 2015
[*]
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench03-20151027170822692.fst"
[dumpfile_mtime] "Tue Oct 27 23:44:43 2015"
[dumpfile_size] 257689299
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench03-20151028094057171.fst"
[dumpfile_mtime] "Wed Oct 28 16:18:25 2015"
[dumpfile_size] 255725225
[savefile] "/home/andrey/git/x393/x393_testbench03.sav"
[timestart] 174721900
[size] 1823 1180
[timestart] 174980000
[size] 1823 1173
[pos] 1920 0
*-15.125204 174828500 108390000 148070000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-13.073349 175004500 108390000 148070000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_testbench03.
[treeopen] x393_testbench03.par12_hispi_psp4l0_i.
[treeopen] x393_testbench03.par12_hispi_psp4l0_i.cmprs_channel_block[0].
......@@ -20,15 +20,14 @@
[treeopen] x393_testbench03.simul_sensor12bits_2_i.
[treeopen] x393_testbench03.x393_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_27_32_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.huffman_merge_code_literal_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.
[treeopen] x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.
[treeopen] x393_testbench03.x393_i.compressor393_i.genblk3.
[treeopen] x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.
[treeopen] x393_testbench03.x393_i.mcntrl393_i.
[treeopen] x393_testbench03.x393_i.mcntrl393_i.mcntrl_linear_rw_chn1_i.
[treeopen] x393_testbench03.x393_i.mcntrl393_i.memctrl16_i.
......@@ -64,8 +63,8 @@
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.genblk1.
[sst_width] 244
[signals_width] 342
[sst_width] 294
[signals_width] 348
[sst_expanded] 1
[sst_vpaned_height] 514
@820
......@@ -1917,154 +1916,9 @@ x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.enco
-
@1401200
-encoderDCAC393
@800200
-huffman
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.en
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.di[15:0]
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.ds
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.rdy
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_or_full
@c00022
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_o[15:0]
@28
(0)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_o[15:0]
(1)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_o[15:0]
(2)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_o[15:0]
(3)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_o[15:0]
(4)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_o[15:0]
(5)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_o[15:0]
(6)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_o[15:0]
(7)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_o[15:0]
(8)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_o[15:0]
(9)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_o[15:0]
(10)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_o[15:0]
(11)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_o[15:0]
(12)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_o[15:0]
(13)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_o[15:0]
(14)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_o[15:0]
(15)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.fifo_o[15:0]
@1401200
-group_end
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.gotAC
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.gotDC
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.gotRLL
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.gotColor
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.gotEOB
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.gotLastBlock
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.gotLastWord
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.ready_to_flush
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.typeDC
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.typeAC
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.tbsel_YC0
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.tbsel_YC1
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.tbsel_YC2
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.tbsel_YC3
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.code_typ0[1:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.code_typ1[1:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.code_typ2[1:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.code_typ3
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.code_typ4
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.sval[11:0]
@28
(5)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.steps[5:0]
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.var_dl[3:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.var_dl_late[3:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.var_do[10:0]
@200
-table
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.tables_re_latch
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.haddr[8:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.tables_out[31:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.hlen_latch[3:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.hcode_latch[15:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.haddr_r[7:0]
@c00022
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.steps[5:0]
@28
(0)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.steps[5:0]
(1)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.steps[5:0]
(2)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.steps[5:0]
(3)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.steps[5:0]
(4)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.steps[5:0]
(5)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.steps[5:0]
@1401200
-group_end
@200
-
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.dv
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.dl[3:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.do[15:0]
@1000200
-huffman
@800200
-stuffer
@200
-
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.stb
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.dl[3:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.d[15:0]
@28
[color] 2
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.qv
@22
[color] 2
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.q[15:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.imgsz32[19:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.etrax_dma[3:0]
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.start_time_out
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.etrax_dma[3:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.size_count[23:0]
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.time_out
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.time_size_out
@800028
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.size_out[2:0]
@28
(0)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.size_out[2:0]
(1)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.size_out[2:0]
(2)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.size_out[2:0]
@1001200
-group_end
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.size_out_over
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.abort
@c00022
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.byteMask[7:0]
@28
(0)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.byteMask[7:0]
(1)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.byteMask[7:0]
(2)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.byteMask[7:0]
(3)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.byteMask[7:0]
(4)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.byteMask[7:0]
(5)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.byteMask[7:0]
(6)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.byteMask[7:0]
(7)x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.byteMask[7:0]
@1401200
-group_end
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.longMask[31:1]
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.send8
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.send8h
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer393_i.send8l
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.running
@1000200
-stuffer
@800200
@c00200
-huffman_singleclk
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.di[15:0]
......@@ -2136,9 +1990,9 @@ x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huff
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.huffman_snglclk_i.dv
@200
-
@1000200
@1401200
-huffman_singleclk
@800200
@c00200
-stuffer32
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_27_32_i.ds
......@@ -2177,9 +2031,9 @@ x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huff
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_27_32_i.flush_out
@1001200
-group_end
@1000200
@1401200
-stuffer32
@800200
@c00200
-stuffer_metadata
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.ts_data[7:0]
......@@ -2206,14 +2060,12 @@ x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huff
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.imgsz4[21:0]
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.meta_out
@29
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.meta_word[1:0]
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.zeros_out
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.trailer_done
@200
-
@1000200
@1401200
-stuffer_metadata
@800200
-new_compressor
......@@ -2251,40 +2103,19 @@ x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huff
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.running
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.imgsz4[21:0]
@200
-
@1000200
-new_compressor
@22
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.fifo_rdata0[63:0]
@29
x393_testbench03.x393_i.compressor393_i.genblk3.cmprs_afi0_mux_i.fifo_ren0
@200
-
@c00200
-varlen_encode_0
@200
-
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_varlen_encode.clk
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_varlen_encode.en
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_varlen_encode.start
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_varlen_encode.d[11:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_varlen_encode.l[3:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_varlen_encode.l_late[3:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_varlen_encode.d1[11:0]
@200
-
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_varlen_encode.codel0[1:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_varlen_encode.codel1[1:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_varlen_encode.codel2[1:0]
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_varlen_encode.codel[3:0]
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_varlen_encode.cycles[2:0]
@22
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_varlen_encode.q0[10:0]
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_varlen_encode.q[10:0]
@28
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_varlen_encode.this0
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_varlen_encode.this1
x393_testbench03.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.i_huffman.i_varlen_encode.this2
@1401200
-varlen_encode_0
@c00200
......
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