Commit 609af175 authored by Andrey Filippov's avatar Andrey Filippov

merged with lwir

parents 955c964c d6956f19
[*] [*]
[*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI [*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI
[*] Mon Mar 25 17:44:19 2019 [*] Thu Mar 28 02:06:10 2019
[*] [*]
[dumpfile] "/data_ssd/nc393/elphel393/fpga-elphel/x393/simulation/x393_dut-20190324201543111.fst" [dumpfile] "/data_ssd/nc393/elphel393/fpga-elphel/x393/simulation/x393_dut-20190327185524057.fst"
[dumpfile_mtime] "Mon Mar 25 17:44:02 2019" [dumpfile_mtime] "Thu Mar 28 02:04:11 2019"
[dumpfile_size] 396512624 [dumpfile_size] 520738951
[savefile] "/data_ssd/nc393/elphel393/fpga-elphel/x393/cocotb/x393_cocotb_03.sav" [savefile] "/data_ssd/nc393/elphel393/fpga-elphel/x393/cocotb/x393_cocotb_03.sav"
[timestart] 0 [timestart] 379540790
[size] 1804 1171 [size] 1804 1171
[pos] -1 -1 [pos] -1 -1
*-24.860163 0 212597388 212637388 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 *-14.159636 379618470 212597388 212637388 379925000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_dut. [treeopen] x393_dut.
[treeopen] x393_dut.simul_sensor12bits_2_i. [treeopen] x393_dut.simul_sensor12bits_2_i.
[treeopen] x393_dut.simul_sensor12bits_3_i. [treeopen] x393_dut.simul_sensor12bits_3_i.
[treeopen] x393_dut.simul_sensor12bits_i. [treeopen] x393_dut.simul_sensor12bits_i.
[treeopen] x393_dut.x393_i. [treeopen] x393_dut.x393_i.
[treeopen] x393_dut.x393_i.compressor393_i.
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0]. [treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i. [treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.chn_rd_buf_i.
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_frame_sync_i. [treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_frame_sync_i.
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i. [treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i. [treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[1]. [treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].
...@@ -33,6 +36,7 @@ ...@@ -33,6 +36,7 @@
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.cmprs_frame_sync_i. [treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.cmprs_frame_sync_i.
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.huffman_stuffer_meta_i. [treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.huffman_stuffer_meta_i.
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_27_32_i. [treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_27_32_i.
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.
[treeopen] x393_dut.x393_i.event_logger_i.i_imu_exttime. [treeopen] x393_dut.x393_i.event_logger_i.i_imu_exttime.
[treeopen] x393_dut.x393_i.event_logger_i.i_imu_exttime.timestamp_fifo_chn0_i. [treeopen] x393_dut.x393_i.event_logger_i.i_imu_exttime.timestamp_fifo_chn0_i.
[treeopen] x393_dut.x393_i.event_logger_i.i_imu_spi. [treeopen] x393_dut.x393_i.event_logger_i.i_imu_spi.
...@@ -41,12 +45,11 @@ ...@@ -41,12 +45,11 @@
[treeopen] x393_dut.x393_i.event_logger_i.i_nmea_decoder. [treeopen] x393_dut.x393_i.event_logger_i.i_nmea_decoder.
[treeopen] x393_dut.x393_i.event_logger_i.i_rs232_rcv. [treeopen] x393_dut.x393_i.event_logger_i.i_rs232_rcv.
[treeopen] x393_dut.x393_i.frame_sequencer_block[0].cmd_frame_sequencer_i. [treeopen] x393_dut.x393_i.frame_sequencer_block[0].cmd_frame_sequencer_i.
[treeopen] x393_dut.x393_i.mcntrl393_i.
[treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[0]. [treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].
[treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.
[treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i. [treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.
[treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[1].
[treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[2].
[treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[2].mcntrl_tiled_rd_compressor_i. [treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[2].mcntrl_tiled_rd_compressor_i.
[treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[3].
[treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[3].mcntrl_tiled_rd_compressor_i. [treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[3].mcntrl_tiled_rd_compressor_i.
[treeopen] x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i. [treeopen] x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.
[treeopen] x393_dut.x393_i.sensors393_i. [treeopen] x393_dut.x393_i.sensors393_i.
...@@ -56,6 +59,7 @@ ...@@ -56,6 +59,7 @@
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_mux_i. [treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_mux_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i. [treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i. [treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i. [treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_sync_i. [treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_sync_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i. [treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.
...@@ -66,8 +70,8 @@ ...@@ -66,8 +70,8 @@
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.sens_sync_i. [treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.sens_sync_i.
[treeopen] x393_dut.x393_i.timing393_i.camsync393_i. [treeopen] x393_dut.x393_i.timing393_i.camsync393_i.
[treeopen] x393_dut.x393_i.timing393_i.camsync393_i.i_frsync_pclk0. [treeopen] x393_dut.x393_i.timing393_i.camsync393_i.i_frsync_pclk0.
[sst_width] 465 [sst_width] 309
[signals_width] 254 [signals_width] 333
[sst_expanded] 1 [sst_expanded] 1
[sst_vpaned_height] 486 [sst_vpaned_height] 486
@820 @820
...@@ -2776,9 +2780,8 @@ x393_dut.IMU_TAPS[5:1] ...@@ -2776,9 +2780,8 @@ x393_dut.IMU_TAPS[5:1]
-IMU_ -IMU_
@800200 @800200
-debuf_frame_sync_x -debuf_frame_sync_x
@29
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.prst
@28 @28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.prst
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.dis_frame_sync x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.dis_frame_sync
@22 @22
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.line_dly_pclk[15:0] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.line_dly_pclk[15:0]
...@@ -2795,24 +2798,58 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_ ...@@ -2795,24 +2798,58 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sof x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sof
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.eof x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.eof
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sof_out x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sof_out
@800022 @c00022
x393_dut.x393_i.sof_out_pclk[3:0] x393_dut.x393_i.sof_out_pclk[3:0]
@28 @28
(0)x393_dut.x393_i.sof_out_pclk[3:0] (0)x393_dut.x393_i.sof_out_pclk[3:0]
(1)x393_dut.x393_i.sof_out_pclk[3:0] (1)x393_dut.x393_i.sof_out_pclk[3:0]
(2)x393_dut.x393_i.sof_out_pclk[3:0] (2)x393_dut.x393_i.sof_out_pclk[3:0]
(3)x393_dut.x393_i.sof_out_pclk[3:0] (3)x393_dut.x393_i.sof_out_pclk[3:0]
@1001200 @1401200
-group_end -group_end
@800022 @c00022
x393_dut.x393_i.sof_out_mclk[3:0] x393_dut.x393_i.sof_out_mclk[3:0]
@28 @28
(0)x393_dut.x393_i.sof_out_mclk[3:0] (0)x393_dut.x393_i.sof_out_mclk[3:0]
(1)x393_dut.x393_i.sof_out_mclk[3:0] (1)x393_dut.x393_i.sof_out_mclk[3:0]
(2)x393_dut.x393_i.sof_out_mclk[3:0] (2)x393_dut.x393_i.sof_out_mclk[3:0]
(3)x393_dut.x393_i.sof_out_mclk[3:0] (3)x393_dut.x393_i.sof_out_mclk[3:0]
@1001200 @1401200
-group_end -group_end
@200
-
@22
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.frame_start_r[4:0]
@28
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.pgm_param_w
@c00022
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.par_mod_r[8:0]
@28
(0)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.par_mod_r[8:0]
(1)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.par_mod_r[8:0]
(2)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.par_mod_r[8:0]
(3)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.par_mod_r[8:0]
(4)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.par_mod_r[8:0]
(5)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.par_mod_r[8:0]
(6)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.par_mod_r[8:0]
(7)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.par_mod_r[8:0]
(8)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.par_mod_r[8:0]
@1401200
-group_end
@28
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.calc_valid
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.aborting_r
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.suspend
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.pre_want_r1
@22
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.cmd_extra_pages[1:0]
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.page_cntr[2:0]
@28
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.pre_want
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.want_r
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.xfer_want
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.xfer_grant
(2)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.xfer_start_r[2:0]
@1000200 @1000200
-debuf_frame_sync_x -debuf_frame_sync_x
@c00200 @c00200
...@@ -2991,6 +3028,23 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c ...@@ -2991,6 +3028,23 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c
-i2c_seq_0 -i2c_seq_0
@800200 @800200
-sensor_channel0 -sensor_channel0
-buf
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.px_valid
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.wpage[1:0]
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.waddr[8:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.px_data[15:0]
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.mclk
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.buf_dout[63:0]
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.buf_rd
@200
-
@1000200
-buf
@28 @28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sof_out_mclk x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sof_out_mclk
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.eof_mclk x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.eof_mclk
...@@ -3006,12 +3060,15 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.frame_num_ ...@@ -3006,12 +3060,15 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.frame_num_
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.sof_out x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.sof_out
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.sof_late x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.sof_late
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.sof_out_pclk x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.sof_out_pclk
@200
-
@1000200 @1000200
-sesns_sync -sesns_sync
-sensor_channel0 -sensor_channel0
-sequencers_0 -sequencers_0
@22
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.window_height[16:0]
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.window_width[13:0]
@200
-
@c00200 @c00200
-sensor_channel_a -sensor_channel_a
@28 @28
...@@ -3366,8 +3423,417 @@ x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.huffman_stuf ...@@ -3366,8 +3423,417 @@ x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.huffman_stuf
@1401200 @1401200
-jpeg1 -jpeg1
@800200 @800200
-debug_raw_x
@c00022
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.mode_reg[14:0]
@28
(0)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.mode_reg[14:0]
(1)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.mode_reg[14:0]
(2)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.mode_reg[14:0]
(3)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.mode_reg[14:0]
(4)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.mode_reg[14:0]
(5)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.mode_reg[14:0]
(6)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.mode_reg[14:0]
(7)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.mode_reg[14:0]
(8)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.mode_reg[14:0]
(9)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.mode_reg[14:0]
(10)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.mode_reg[14:0]
(11)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.mode_reg[14:0]
(12)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.mode_reg[14:0]
(13)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.mode_reg[14:0]
(14)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.mode_reg[14:0]
@1401200
-group_end
@28
[color] 3
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.linear_mode
@22
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.window_y0[15:0]
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.line_unfinished_relw_r[15:0]
@28
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.chn_dis_delayed
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.frame_start_mod
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.busy_r
@c00022
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.recalc_r[8:0]
@28
(0)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.recalc_r[8:0]
(1)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.recalc_r[8:0]
(2)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.recalc_r[8:0]
(3)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.recalc_r[8:0]
(4)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.recalc_r[8:0]
(5)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.recalc_r[8:0]
(6)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.recalc_r[8:0]
(7)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.recalc_r[8:0]
(8)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.recalc_r[8:0]
@1401200
-group_end
@22
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.line_unfinished_r[15:0]
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.line_unfinished[15:0]
x393_dut.x393_i.mcntrl393_i.cmprs_line_unfinished_dst[63:0]
x393_dut.x393_i.cmprs_line_unfinished_dst[63:0]
@c00022
x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
@28
(0)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(1)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(2)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(3)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(4)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(5)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(6)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(7)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(8)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(9)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(10)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(11)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(12)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(13)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(14)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(15)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(16)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(17)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(18)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(19)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(20)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(21)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(22)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(23)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(24)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(25)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(26)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(27)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(28)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(29)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(30)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(31)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(32)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(33)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(34)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(35)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(36)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(37)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(38)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(39)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(40)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(41)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(42)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(43)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(44)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(45)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(46)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(47)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(48)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(49)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(50)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(51)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(52)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(53)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(54)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(55)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(56)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(57)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(58)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(59)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(60)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(61)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(62)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
(63)x393_dut.x393_i.compressor393_i.line_unfinished_dst[63:0]
@1401200
-group_end
@22
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.line_unfinished_dst[15:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_frame_sync_i.line_unfinished[15:0]
@200
-
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.frame_en
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.frame_en_jp
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.frame_en_raw
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.set_ctrl_reg_w
@22
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmd_data[31:0]
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_run_mclk
@1000200
-debug_raw_x
@800200
-raw_0
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.raw_be16
@22
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.raw_buf_ra[11:0]
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.raw_buf_rd[1:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.raw_flush
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.raw_prefb
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.raw_start
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.raw_ts_copy
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.page_ready_chn
@22
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.next_valid[2:0]
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.next_page_chn_raw
@c00022
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.needed_page[2:0]
@28
(0)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.needed_page[2:0]
(1)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.needed_page[2:0]
(2)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.needed_page[2:0]
@1401200
-group_end
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.frame_pre_start_r
@200
-
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.frame_pre_run
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.starting
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.stuffer_running
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.buf_ready_w
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.page_start
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.quad_last
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.page_end_w
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.page_end_r
(1)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.quad_r[3:0]
(0)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.quad_r[3:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.page_run
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.next_page_chn_jp
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.rows_last[1:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.buf_rd[1:0]
@22
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.buf_ra[11:0]
@800200
-buffer
-dbg
@28
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.set_window_start_w
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.set_window_wh_w
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.set_window_x0y0_w
@22
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.window_width[13:0]
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.window_height[16:0]
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.window_x0[12:0]
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.window_y0[15:0]
@1000200
-dbg
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.buf_wpage_nxt
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.chn_rd_buf_i.ext_clk
@22
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.chn_rd_buf_i.page[1:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.chn_rd_buf_i.waddr[6:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.chn_rd_buf_i.data_in[63:0]
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.chn_rd_buf_i.we
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.chn_rd_buf_i.wpage_in[1:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.chn_rd_buf_i.wpage_set
@22
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.chn_rd_buf_i.ext_data_out[7:0]
@c00022
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.chn_rd_buf_i.ext_raddr[11:0]
@28
(0)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.chn_rd_buf_i.ext_raddr[11:0]
(1)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.chn_rd_buf_i.ext_raddr[11:0]
(2)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.chn_rd_buf_i.ext_raddr[11:0]
(3)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.chn_rd_buf_i.ext_raddr[11:0]
(4)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.chn_rd_buf_i.ext_raddr[11:0]
(5)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.chn_rd_buf_i.ext_raddr[11:0]
(6)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.chn_rd_buf_i.ext_raddr[11:0]
(7)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.chn_rd_buf_i.ext_raddr[11:0]
(8)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.chn_rd_buf_i.ext_raddr[11:0]
(9)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.chn_rd_buf_i.ext_raddr[11:0]
(10)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.chn_rd_buf_i.ext_raddr[11:0]
(11)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.chn_rd_buf_i.ext_raddr[11:0]
@1401200
-group_end
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.chn_rd_buf_i.ext_rd
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.chn_rd_buf_i.ext_regen
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.chn_rd_buf_i.page_next
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.chn_rd_buf_i.wclk
@1000200
-buffer
@800200
-mcntrl_tiled_linear
@200
-
@1000200
-mcntrl_tiled_linear
-raw_0
@800200
-cmprs_raw_buf_iface_i
@200
-
@22
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.buf_diff[2:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.buf_ra[11:0]
@800028
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.buf_rd[1:0]
@28
(0)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.buf_rd[1:0]
(1)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.buf_rd[1:0]
@1001200
-group_end
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.buf_rd_r[1:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.buf_ready_w
@22
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.bufa_r[11:0]
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.cmprs_run_mclk
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.cmprs_run_xclk
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.frame_en
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.frame_en_r
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.frame_en_w
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.frame_finish_w
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.frame_go
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.frame_pre_run
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.frame_pre_start_r
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.frame_pre_start_w
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.frame_que_cntr[2:0]
[color] 2
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.frame_start_xclk
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.frame_start_xclk_r
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.frames_pending
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.mclk
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.mode_valid
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.mrst
@22
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.n_block_rows_m1[12:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.n_blocks_in_row_m1[12:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.needed_page[2:0]
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.next_page_chn
@22
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.next_valid[2:0]
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.nmrst
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.page_end_r
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.page_end_w
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.page_ready
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.page_ready_chn
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.page_run
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.page_start
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.quad_last
@22
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.quad_r[3:0]
@c00022
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.quads_left[14:0]
@28
(0)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.quads_left[14:0]
(1)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.quads_left[14:0]
(2)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.quads_left[14:0]
(3)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.quads_left[14:0]
(4)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.quads_left[14:0]
(5)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.quads_left[14:0]
(6)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.quads_left[14:0]
(7)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.quads_left[14:0]
(8)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.quads_left[14:0]
(9)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.quads_left[14:0]
(10)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.quads_left[14:0]
(11)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.quads_left[14:0]
(12)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.quads_left[14:0]
(13)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.quads_left[14:0]
(14)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.quads_left[14:0]
@1401200
-group_end
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.raw_be16
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.raw_flush
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.raw_prefb
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.raw_start
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.raw_ts_copy
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.release_buf
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.reset_page_rd
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.rows_last[1:0]
@22
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.rows_left[16:0]
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.starting
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.stuffer_running
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.xclk
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.xfer_reset_page_rd
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.xrst
@1000200
-cmprs_raw_buf_iface_i
@800200
-jpeg0 -jpeg0
-raw_dbg
@28 @28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.frame_en_raw
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.frame_en_jp
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.uncompressed
[color] 6
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.raw_mode
[color] 6
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.compressed_mode
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.en_huffman
@22
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.stuffer_do32[31:0]
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.reading_frame
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer_running
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer_done
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.stuffer_en
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.trailer_done
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.trailer
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.zeros_out
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.done
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.running
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.trailer_done
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.raw_prefb
@800022
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.raw_bs[3:0]
@28
(0)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.raw_bs[3:0]
(1)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.raw_bs[3:0]
(2)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.raw_bs[3:0]
(3)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.raw_bs[3:0]
@1001200
-group_end
@22
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.raw32[31:0]
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.raw_be16
@22
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.raw_bs[3:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.raw_bytes[7:0]
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.raw_flush
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.raw_mode
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.raw_prefb
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.raw_start
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.raw_stb
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.raw_ts_copy
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.data_out_valid
@22
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.data_out[31:0]
@200
-
@1000200
-raw_dbg
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.raw_prefb
@800022
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.raw_bs[3:0]
@28
(0)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.raw_bs[3:0]
(1)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.raw_bs[3:0]
(2)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.raw_bs[3:0]
(3)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.raw_bs[3:0]
@1001200
-group_end
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.stb
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.frame_finish_w
@22
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.frame_finish_r[3:0]
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.raw_flush
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.raw_stb
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.stb1
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.chn_rst x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.chn_rst
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.chn_en x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.chn_en
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.frame_en x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.frame_en
...@@ -3398,8 +3864,10 @@ x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.xfer ...@@ -3398,8 +3864,10 @@ x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.xfer
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.pending_xfers[1:0] x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.pending_xfers[1:0]
@28 @28
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.frame_done x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.frame_done
@29
[color] 2 [color] 2
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.busy_r x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.busy_r
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_en_mclk x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_en_mclk
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_run_mclk x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_run_mclk
@22 @22
...@@ -3407,7 +3875,30 @@ x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuf ...@@ -3407,7 +3875,30 @@ x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuf
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.data_out_valid x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.data_out_valid
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.stuffer_do32[31:0] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.stuffer_do32[31:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.stuffer_bytes[1:0] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.stuffer_bytes[1:0]
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.in_stb
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.bytes_in[1:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.flush
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.last_stb_4
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.raw_flush
@c00022
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.ts_in[3:0]
@28
(0)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.ts_in[3:0]
(1)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.ts_in[3:0]
(2)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.ts_in[3:0]
(3)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.ts_in[3:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.in_stb
@1401200
-group_end
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.write_size
@22
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.stuffer_dv x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.stuffer_dv
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.trailer
@22
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.imgsz4[21:0]
@c00200 @c00200
-bit_stuffer -bit_stuffer
@22 @22
......
/*!
* <b>Module:</b>bit_stuffer_raw_metadata
* @file bit_stuffer_raw_metadata.v
* @date 2015-10-25
* @author Andrey Filippov
*
* @brief Bit stuffer combines variable length fragments (up to 16 bits long)
* from the Huffman encoder to a byte stream, escapes every 0xff byte with
* 0x00 and adds file length and timestamp metadata
* Modified from bit_stuffer_metadata to include raw byte stream as alternative
*
* @copyright Copyright (c) 2015 Elphel, Inc .
*
* <b>License:</b>
*
* bit_stuffer_raw_metadata.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* bit_stuffer_raw_metadata.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module bit_stuffer_raw_metadata(
input mclk,
input mrst, // @posedge mclk, sync reset
input xclk,
input xrst, // @posedge xclk, sync reset
input last_block, // use it to copy timestamp from fifo // TODO: leading edge is Need for raw also
// time stamping - will copy time at the end of color_first (later than the first hact after vact in the current frame, but before the next one
// and before the data is needed for output
input ts_pre_stb, // @mclk - 1 cycle before receiving 8 bytes of timestamp data
input [7:0] ts_data, // timestamp data (s0,s1,s2,s3,us0,us1,us2,us3==0)
input color_first, // @fradv_clk only used for timestamp
input [31:0] din, // input data, MSB aligned
input [1:0] bytes_in, // number of bytes, valid @ ds (0 means 4)
input in_stb, // input data/bytes_in strobe
input flush, // end of input data
input abort, // @ any, extracts 0->1 and flushes (for both modes!)
// RAW mode ports, all @ xclk
input compressed_mode, // operating in raw mode (uncompressed)
input raw_mode, // operating in raw mode (uncompressed)
input raw_be16, // swap byte pairs to outut 16-bit big endian data
input [7:0] raw_bytes, // raw bypass byte data in little endian order
input raw_start, // single-cycle set "running"
input raw_prefb, // 1 cycle before sequence of 4 bytes
input raw_ts_copy, // single-cycle copy timestamp (some time before flush)
input raw_flush, // flush remaining data, length and timestamp
// outputs @ negedge clk
output reg [31:0] data_out, // [31:0] output data
output reg data_out_valid,// output data valid
output reg done, // reset by !en, goes high after some delay after flushing
output reg running // from registering timestamp until done
`ifdef DEBUG_RING
, output reg [3:0] dbg_etrax_dma
,output dbg_ts_rstb
,output [7:0] dbg_ts_dout
`endif
);
// Processing raw
reg [31:0] raw32;
reg raw_stb;
reg [3:0] raw_bs;
always @ (posedge xclk) begin
if (xrst) raw_bs <= 0;
else raw_bs <= raw_be16?
{raw_bs[0], raw_bs[3], raw_prefb, raw_bs[1]}:
{raw_bs[2], raw_bs[1], raw_bs[0], raw_prefb};
if (xrst) raw_stb <= 0;
else raw_stb <= raw_be16 ? raw_bs[2] : raw_bs[3];
if (raw_bs[0]) raw32[31:24] <= raw_bytes;
if (raw_bs[1]) raw32[23:16] <= raw_bytes;
if (raw_bs[2]) raw32[15: 8] <= raw_bytes;
if (raw_bs[3]) raw32[ 7: 0] <= raw_bytes;
end
reg [7:0] time_ram0[0:3]; // 0 - seconds, 1 - microseconds MSB in the output 32-bit word, byt LSB of the sec/usec
reg [7:0] time_ram1[0:3];
reg [7:0] time_ram2[0:3];
reg [7:0] time_ram3[0:3];
reg [3:0] ts_in=8;
reg last_block_d; // last_block delayed by one clock
reg color_first_r;
reg [2:0] abort_r;
reg force_flush;
// reg color_first_r; // registered with the same clock as color_first to extract leading edge
// stb_time[2] - single-cycle pulse after color_first goes low
// reg [19:0] imgsz32; // current image size in multiples of 32-bytes
reg [21:0] imgsz4; // current image size in multiples of 4-bytes
reg last_stb_4; // last stb_in was 4 bytes
reg trailer;
reg meta_out;
reg [1:0] meta_word;
reg raw_flush_d; // raw_flush delayed by 1 cysle
reg zeros_out; // output of 32 bytes (8 words) of zeros
wire trailer_done = (imgsz4[2:0] == 7) && zeros_out;
wire meta_last = (imgsz4[2:0] == 7) && meta_out;
// re-clock enable to this clock
// wire ts_rstb= raw_mode ? raw_ts_copy: (last_block && !last_block_d); // enough time to have timestamp data; // one cycle before getting timestamp data from FIFO
wire ts_rstb= (raw_mode && raw_ts_copy) || ( compressed_mode && last_block && !last_block_d); // enough time to have timestamp data; // one cycle before getting timestamp data from FIFO
wire [7:0] ts_dout; // timestamp data, byte at a time
wire write_size = (in_stb && (bytes_in != 0)) || (flush && last_stb_4) || raw_flush_d; // raw_flush; // TODO: never in raw mode?
// wire stb_start = raw_mode? raw_start: (!color_first && color_first_r) ;
wire stb_start = (raw_mode && raw_start) || (compressed_mode && !color_first && color_first_r) ;
wire stb = compressed_mode && in_stb && !trailer && !force_flush;
wire stb1 = raw_mode && raw_stb && !trailer && !force_flush;
always @ (posedge xclk) begin
raw_flush_d <= raw_mode && raw_flush;
if (xrst ||trailer_done) imgsz4 <= 0;
else if (stb || stb1 || trailer) imgsz4 <= imgsz4 + 1; // raw included
if (stb || stb1) last_stb_4 <= !raw_mode && (bytes_in == 0);
last_block_d <= last_block;
color_first_r <= color_first;
if (xrst) ts_in <= 8;
else if (ts_rstb) ts_in <= 0;
else if (!ts_in[3]) ts_in <= ts_in + 1;
if ((!ts_in[3] && (ts_in[1:0] == 0)) || write_size) time_ram0[ts_in[3:2]] <= ts_in[3]? ({imgsz4[5:0],(flush || raw_mode)?2'b0:bytes_in}):ts_dout; //ts_in[3:2] == 2'b10 when write_size
if ((!ts_in[3] && (ts_in[1:0] == 1)) || write_size) time_ram1[ts_in[3:2]] <= ts_in[3]? (imgsz4[13:6]):ts_dout;
if ((!ts_in[3] && (ts_in[1:0] == 2)) || write_size) time_ram2[ts_in[3:2]] <= ts_in[3]? (imgsz4[21:14]):ts_dout;
if ((!ts_in[3] && (ts_in[1:0] == 3)) || write_size) time_ram3[ts_in[3:2]] <= ts_in[3]? (8'hff):ts_dout;
if (xrst) trailer <= 0;
// else if (force_flush || (raw_mode ? raw_flush : flush)) trailer <= 1;
else if (force_flush || (raw_mode && raw_flush) || (compressed_mode && flush)) trailer <= 1;
else if (trailer_done) trailer <= 0;
if (xrst) meta_out <= 0;
else if (trailer && (imgsz4[2:0] == 4) &&!zeros_out) meta_out <= 1;
else if (meta_last) meta_out <= 0;
if (!meta_out) meta_word <= 0;
else meta_word <= meta_word + 1;
if (xrst) zeros_out <= 0;
else if (meta_last) zeros_out <= 1;
else if (trailer_done) zeros_out <= 0;
data_out <= ({32{stb1}} & raw32) | ({32{stb}} & din) | ({32{meta_out}} & {time_ram0[meta_word],time_ram1[meta_word],time_ram2[meta_word],time_ram3[meta_word]});
data_out_valid <= stb1 || stb || trailer;
/// if (xrst || trailer) running <= 0; // FIXME: Was this for quite a while? Was in intentional?
if (xrst || trailer_done) running <= 0;
else if (stb_start) running <= 1; // for raw need color_first trailing edge
done <= trailer_done;
// re-clock abort, extract leading edge
abort_r <= {abort_r[0] & ~abort_r[1], abort_r[0], abort & ~trailer};
if (xrst || trailer) force_flush <= 0;
else if (abort_r) force_flush <= 1;
end
// just for testing
`ifdef DEBUG_RING
assign dbg_ts_rstb = ts_rstb;
assign dbg_ts_dout = ts_dout;
always @ (posedge xclk) begin
dbg_etrax_dma <= imgsz4[3:0];
end
`endif
//color_first && color_first_r
timestamp_fifo timestamp_fifo_i (
.sclk (mclk), // input
.srst (mrst), // input
.pre_stb (ts_pre_stb), // input
.din (ts_data), // input[7:0]
.aclk (xclk), //fradv_clk), // input
.arst (xrst), //fradv_clk), // input
.advance (stb_start), // triggers at the 0->1
.rclk (xclk), // input
.rrst (xrst), //fradv_clk), // input
.rstb (ts_rstb), // input
.dout (ts_dout) // output[7:0] reg
);
endmodule
...@@ -66,7 +66,7 @@ module cmprs_buf_average#( ...@@ -66,7 +66,7 @@ module cmprs_buf_average#(
input [ 7:0] caddrw, input [ 7:0] caddrw,
input cwe, input cwe,
input [ 8:0] signed_c, input [ 8:0] signed_c,
output [ 9:0] do, // [9:0] data out (4:2:0) (signed, average=0) output [ 9:0] dout, // [9:0] data out (4:2:0) (signed, average=0)
// When is it valid? // When is it valid?
output [ 8:0] avr, // [8:0] DC (average value) - RAM output, no register. For Y components 9'h080..9'h07f, for C - 9'h100..9'h0ff! output [ 8:0] avr, // [8:0] DC (average value) - RAM output, no register. For Y components 9'h080..9'h07f, for C - 9'h100..9'h0ff!
output dv, // out data valid (will go high for at least 64 cycles) output dv, // out data valid (will go high for at least 64 cycles)
...@@ -170,7 +170,7 @@ module cmprs_buf_average#( ...@@ -170,7 +170,7 @@ module cmprs_buf_average#(
// assign output signals // assign output signals
assign avr = avr_r; // avermem[avr_ra[3:0]]; assign avr = avr_r; // avermem[avr_ra[3:0]];
assign do = do_r; assign dout = do_r;
assign tn[2:0] = raddr[8:6]; assign tn[2:0] = raddr[8:6];
// component_num,component_color,component_first for different converters vs tn (1 bit per tn (0..5) // component_num,component_color,component_first for different converters vs tn (1 bit per tn (0..5)
assign component_num[2:0]= {component_numsH[0],component_numsM[0],component_numsL[0]}; assign component_num[2:0]= {component_numsH[0],component_numsM[0],component_numsL[0]};
......
...@@ -73,7 +73,11 @@ ...@@ -73,7 +73,11 @@
// 3 - combine in window only // 3 - combine in window only
// [20] == 1 - set Bayer shift // [20] == 1 - set Bayer shift
// [19:18] Bayer shift // [19:18] Bayer shift
// [17:16] - unused // WAS: [17:16] - unused
// [17] == 1 - set BE16 mode
// [16] 0 - BE16 mode (1 - byte stream is little endian 16-bit, file is big endian 16 bits
// [15] == 1 - set single/multi frame mode // [15] == 1 - set single/multi frame mode
// [14] 0 - multiframe (compare frame numbers for 'suspend' output) // [14] 0 - multiframe (compare frame numbers for 'suspend' output)
// 1 - single frame buffer // 1 - single frame buffer
...@@ -85,7 +89,15 @@ ...@@ -85,7 +89,15 @@
// 4 - mono, 4 blocks (but still not actual monochrome JPEG as the blocks are scanned in 2x2 macroblocks) // 4 - mono, 4 blocks (but still not actual monochrome JPEG as the blocks are scanned in 2x2 macroblocks)
// 5 - jp4, 4 blocks, dc-improved // 5 - jp4, 4 blocks, dc-improved
// 6 - jp4, differential // 6 - jp4, differential
// 7 - 15 - reserved // 7 - jp4, 4 blocks, differential
// 8 - jp4, 4 blocks, differential, hdr
// 9 - jp4, 4 blocks, differential, divide by 2
// 10 - jp4, 4 blocks, differential, hdr,divide by 2
// 11 - mono JPEG (not yet implemented)
// 12-13 - RESERVED
// 14 - mono 4 blocks
// 15 - uncompressed
// [8:7] == 0,1 - NOP, 2 - disable, 3 - enable subtracting of average value (DC component), bypassing DCT // [8:7] == 0,1 - NOP, 2 - disable, 3 - enable subtracting of average value (DC component), bypassing DCT
// [6] == 1 - enable quantization bank select, 0 - disregard bits [5:3] // [6] == 1 - enable quantization bank select, 0 - disregard bits [5:3]
// [5:3] = quantization page number (0..7) // [5:3] = quantization page number (0..7)
...@@ -95,7 +107,7 @@ ...@@ -95,7 +107,7 @@
// 2 - enable compressor, compress single frame from memory (async) // 2 - enable compressor, compress single frame from memory (async)
// 3 - enable compressor, enable synchronous compression mode // 3 - enable compressor, enable synchronous compression mode
// TODO WARNING: Switching to/from raw(uncompressed) mode requires stopping/restarting compressor!
module cmprs_cmd_decode#( module cmprs_cmd_decode#(
// Bit-fields in compressor control word // Bit-fields in compressor control word
...@@ -109,6 +121,10 @@ module cmprs_cmd_decode#( ...@@ -109,6 +121,10 @@ module cmprs_cmd_decode#(
parameter CMPRS_CBIT_CMODE_BITS = 4, // number of bits to control compressor color modes parameter CMPRS_CBIT_CMODE_BITS = 4, // number of bits to control compressor color modes
parameter CMPRS_CBIT_FRAMES = 15, // bit # to control compressor multi/single frame buffer modes parameter CMPRS_CBIT_FRAMES = 15, // bit # to control compressor multi/single frame buffer modes
parameter CMPRS_CBIT_FRAMES_BITS = 1, // number of bits to control compressor multi/single frame buffer modes parameter CMPRS_CBIT_FRAMES_BITS = 1, // number of bits to control compressor multi/single frame buffer modes
parameter CMPRS_CBIT_BE16 = 17, // bit # to control compressor multi/single frame buffer modes
parameter CMPRS_CBIT_BE16_BITS = 1, // number of bits to control compressor multi/single frame buffer modes
parameter CMPRS_CBIT_BAYER = 20, // bit # to control compressor Bayer shift mode parameter CMPRS_CBIT_BAYER = 20, // bit # to control compressor Bayer shift mode
parameter CMPRS_CBIT_BAYER_BITS = 2, // number of bits to control compressor Bayer shift mode parameter CMPRS_CBIT_BAYER_BITS = 2, // number of bits to control compressor Bayer shift mode
parameter CMPRS_CBIT_FOCUS = 23, // bit # to control compressor focus display mode parameter CMPRS_CBIT_FOCUS = 23, // bit # to control compressor focus display mode
...@@ -118,6 +134,7 @@ module cmprs_cmd_decode#( ...@@ -118,6 +134,7 @@ module cmprs_cmd_decode#(
// parameter CMPRS_CBIT_RUN_DISABLE = 2'h1, // disable compression of the new frames, finish any already started // parameter CMPRS_CBIT_RUN_DISABLE = 2'h1, // disable compression of the new frames, finish any already started
parameter CMPRS_CBIT_RUN_STANDALONE = 2'h2, // enable compressor, compress single frame from memory (async) parameter CMPRS_CBIT_RUN_STANDALONE = 2'h2, // enable compressor, compress single frame from memory (async)
parameter CMPRS_CBIT_RUN_ENABLE = 2'h3, // enable compressor, enable synchronous compression mode parameter CMPRS_CBIT_RUN_ENABLE = 2'h3, // enable compressor, enable synchronous compression mode
parameter CMPRS_CBIT_CMODE_JPEG18 = 4'h0, // color 4:2:0 parameter CMPRS_CBIT_CMODE_JPEG18 = 4'h0, // color 4:2:0
parameter CMPRS_CBIT_CMODE_MONO6 = 4'h1, // mono 4:2:0 (6 blocks) parameter CMPRS_CBIT_CMODE_MONO6 = 4'h1, // mono 4:2:0 (6 blocks)
parameter CMPRS_CBIT_CMODE_JP46 = 4'h2, // jp4, 6 blocks, original parameter CMPRS_CBIT_CMODE_JP46 = 4'h2, // jp4, 6 blocks, original
...@@ -131,6 +148,8 @@ module cmprs_cmd_decode#( ...@@ -131,6 +148,8 @@ module cmprs_cmd_decode#(
parameter CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2 = 4'ha, // jp4, 4 blocks, differential, hdr,divide by 2 parameter CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2 = 4'ha, // jp4, 4 blocks, differential, hdr,divide by 2
parameter CMPRS_CBIT_CMODE_MONO1 = 4'hb, // mono JPEG (not yet implemented) parameter CMPRS_CBIT_CMODE_MONO1 = 4'hb, // mono JPEG (not yet implemented)
parameter CMPRS_CBIT_CMODE_MONO4 = 4'he, // mono 4 blocks parameter CMPRS_CBIT_CMODE_MONO4 = 4'he, // mono 4 blocks
parameter CMPRS_CBIT_CMODE_RAW = 4'hf, // uncompressed
parameter CMPRS_CBIT_FRAMES_SINGLE = 0, //1, // use a single-frame buffer for images parameter CMPRS_CBIT_FRAMES_SINGLE = 0, //1, // use a single-frame buffer for images
parameter CMPRS_COLOR18 = 0, // JPEG 4:2:0 with 18x18 overlapping tiles for de-bayer parameter CMPRS_COLOR18 = 0, // JPEG 4:2:0 with 18x18 overlapping tiles for de-bayer
...@@ -138,7 +157,8 @@ module cmprs_cmd_decode#( ...@@ -138,7 +157,8 @@ module cmprs_cmd_decode#(
parameter CMPRS_MONO16 = 2, // JPEG 4:2:0 with 16x16 non-overlapping tiles, color components zeroed parameter CMPRS_MONO16 = 2, // JPEG 4:2:0 with 16x16 non-overlapping tiles, color components zeroed
parameter CMPRS_JP4 = 3, // JP4 mode with 16x16 macroblocks parameter CMPRS_JP4 = 3, // JP4 mode with 16x16 macroblocks
parameter CMPRS_JP4DIFF = 4, // JP4DIFF mode TODO: see if correct parameter CMPRS_JP4DIFF = 4, // JP4DIFF mode TODO: see if correct
parameter CMPRS_MONO8 = 7, // Regular JPEG monochrome with 8x8 macroblocks (not yet implemented) parameter CMPRS_RAW = 6, // Not comressed, raw data
parameter CMPRS_MONO8 = 7, // Regular JPEG monochrome with 8x8 macroblocks (not yet implemented)
parameter CMPRS_FRMT_MBCM1 = 0, // bit # of number of macroblock columns minus 1 field in format word parameter CMPRS_FRMT_MBCM1 = 0, // bit # of number of macroblock columns minus 1 field in format word
parameter CMPRS_FRMT_MBCM1_BITS = 13, // number of bits in number of macroblock columns minus 1 field in format word parameter CMPRS_FRMT_MBCM1_BITS = 13, // number of bits in number of macroblock columns minus 1 field in format word
...@@ -152,11 +172,8 @@ module cmprs_cmd_decode#( ...@@ -152,11 +172,8 @@ module cmprs_cmd_decode#(
parameter CMPRS_CSAT_CR_BITS = 10, // number of bits in red scale field in color saturation word parameter CMPRS_CSAT_CR_BITS = 10, // number of bits in red scale field in color saturation word
parameter CMPRS_CORING_BITS = 3 // number of bits in coring mode parameter CMPRS_CORING_BITS = 3 // number of bits in coring mode
//parameter CMPRS_STUFFER_NEG = 1 // stuffer runs @ negedge xclk2x
)( )(
// input rst,
input xclk, // global clock input, compressor single clock rate input xclk, // global clock input, compressor single clock rate
input mclk, // global system/memory clock input mclk, // global system/memory clock
input mrst, // @posedge mclk, sync reset input mrst, // @posedge mclk, sync reset
...@@ -165,17 +182,14 @@ module cmprs_cmd_decode#( ...@@ -165,17 +182,14 @@ module cmprs_cmd_decode#(
input color_sat_we, // input - @mclk write color saturation values input color_sat_we, // input - @mclk write color saturation values
input coring_we, // input - @mclk write coring values input coring_we, // input - @mclk write coring values
// rs, // 0 - bit modes,
// // 1 - write ntiles;
input [31:0] di, // [15:0] data from CPU (sync to negedge sclk) input [31:0] di, // [15:0] data from CPU (sync to negedge sclk)
// cr_w, // data written to cr (1 cycle long) - just to reset legacy IRQ
// ntiles,//[17:0] - number of tiles in a frame to process
input frame_start, // @mclk input frame_start, // @mclk
output frame_start_xclk, // frame start, parameters are copied at this pulse output frame_start_xclk, // frame start, parameters are copied at this pulse
// outputs sync @ posedge mclk: // outputs sync @ posedge mclk:
output cmprs_en_mclk, // @mclk 0 resets immediately output cmprs_en_mclk, // @mclk 0 resets immediately
input cmprs_en_extend, // @mclk keep compressor enabled for graceful shutdown input cmprs_en_extend, // @mclk keep compressor enabled for graceful shutdown
input compressor_running, // @xclk - reading frame or running stuffer/trailer
output reg cmprs_run_mclk, // @mclk enable propagation of vsync_late to frame_start_dst in bonded(sync to src) mode output reg cmprs_run_mclk, // @mclk enable propagation of vsync_late to frame_start_dst in bonded(sync to src) mode
output reg cmprs_standalone, // @mclk single-cycle: generate a single frame_start_dst in unbonded (not synchronized) mode. output reg cmprs_standalone, // @mclk single-cycle: generate a single frame_start_dst in unbonded (not synchronized) mode.
...@@ -183,14 +197,13 @@ module cmprs_cmd_decode#( ...@@ -183,14 +197,13 @@ module cmprs_cmd_decode#(
output reg sigle_frame_buf, // memory controller uses a single frame buffer (frame_number_* == 0), use other sync output reg sigle_frame_buf, // memory controller uses a single frame buffer (frame_number_* == 0), use other sync
// outputs sync @ posedge xclk: // outputs sync @ posedge xclk:
output reg cmprs_en_xclk, // enable compressor, turn off immedaitely output reg cmprs_en_xclk, // enable compressor, turn off immedaitely
output reg cmprs_en_late_xclk, // enable stuffer, extends control fields for graceful shutdown output reg cmprs_en_xclk_jp, // enable compressor, turn off immedaitely
// cmprs_start, // single cycle when single or constant compression is turned on output reg cmprs_en_xclk_raw, // enable compressor, turn off immedaitely
// cmprs_repeat,// high in repetitive mode
output reg cmprs_en_late_xclk, // enable stuffer, extends control fields for graceful shutdown (should be for raw also?)
// outputs @posedge xclk, frozen when the new frame is requested // outputs @posedge xclk, frozen when the new frame is requested
output reg [ 2:0] cmprs_qpage, // [2:0] - quantizator page number (0..7) output reg [ 2:0] cmprs_qpage, // [2:0] - quantizator page number (0..7)
output reg cmprs_dcsub, // subtract dc level before DCT, restore later output reg cmprs_dcsub, // subtract dc level before DCT, restore later
// output reg [ 3:0] cmprs_mode, // [3:0] - compressor mode
// cmprs_shift, // tile shift from top left corner
output reg [ 1:0] cmprs_fmode, //[1:0] - focus mode output reg [ 1:0] cmprs_fmode, //[1:0] - focus mode
output reg [ 1:0] bayer_shift, // additional shift to bayer mosaic output reg [ 1:0] bayer_shift, // additional shift to bayer mosaic
...@@ -208,15 +221,11 @@ module cmprs_cmd_decode#( ...@@ -208,15 +221,11 @@ module cmprs_cmd_decode#(
output reg [CMPRS_CSAT_CB_BITS-1:0] color_sat_cb, // scale for Cb color component (color saturation) output reg [CMPRS_CSAT_CB_BITS-1:0] color_sat_cb, // scale for Cb color component (color saturation)
output reg [CMPRS_CSAT_CR_BITS-1:0] color_sat_cr, // scale for Cr color component (color saturation) output reg [CMPRS_CSAT_CR_BITS-1:0] color_sat_cr, // scale for Cr color component (color saturation)
output reg [CMPRS_CORING_BITS-1:0] coring // scale for Cb color component (color saturation) output reg [CMPRS_CORING_BITS-1:0] coring, // scale for Cb color component (color saturation)
output reg compressed, // late on, early off running compressor chain
output reg uncompressed, // late on, early off running raw chain
output reg be16
); );
// input is_compressing, // high from start of compressing till EOT (sync to posedge clk)
// abort_compress,
// input stuffer_done_mclk,
// output reg force_flush); // abort compress - generate flush pulse, force end of image over DMA, update counter
reg [30:0] di_r; reg [30:0] di_r;
reg ctrl_we_r; reg ctrl_we_r;
...@@ -252,9 +261,13 @@ module cmprs_cmd_decode#( ...@@ -252,9 +261,13 @@ module cmprs_cmd_decode#(
reg [30:0] format_xclk; // left margin and macroblock rows/columns reg [30:0] format_xclk; // left margin and macroblock rows/columns
reg [23:0] color_sat_xclk; // color saturation values (only 10 LSB in each 12 are used reg [23:0] color_sat_xclk; // color saturation values (only 10 LSB in each 12 are used
reg [ 2:0] coring_xclk; // color saturation values (only 10 LSB in each 12 are used reg [ 2:0] coring_xclk; // color saturation values (only 10 LSB in each 12 are used
// wire frame_start_xclk; wire uncompressed_mclk;
wire uncompressed_xclk;
assign cmprs_en_mclk = cmprs_en_mclk_r; assign cmprs_en_mclk = cmprs_en_mclk_r;
assign uncompressed_mclk = cmprs_mode_mclk[3:0] == CMPRS_CBIT_CMODE_RAW;
assign uncompressed_xclk = cmprs_mode_xclk[3:0] == CMPRS_CBIT_CMODE_RAW;
always @ (posedge mclk) begin always @ (posedge mclk) begin
if (mrst) ctrl_we_r <= 0; if (mrst) ctrl_we_r <= 0;
...@@ -279,12 +292,14 @@ module cmprs_cmd_decode#( ...@@ -279,12 +292,14 @@ module cmprs_cmd_decode#(
else if (ctrl_we_r && di_r[CMPRS_CBIT_RUN]) cmprs_run_mclk <= (di_r[CMPRS_CBIT_RUN-1 -:CMPRS_CBIT_RUN_BITS] == CMPRS_CBIT_RUN_ENABLE); else if (ctrl_we_r && di_r[CMPRS_CBIT_RUN]) cmprs_run_mclk <= (di_r[CMPRS_CBIT_RUN-1 -:CMPRS_CBIT_RUN_BITS] == CMPRS_CBIT_RUN_ENABLE);
if (mrst) cmprs_standalone <= 0; if (mrst) cmprs_standalone <= 0;
// else if (ctrl_we_r) cmprs_standalone <= ctrl_we_r && di_r[CMPRS_CBIT_RUN] && (di_r[CMPRS_CBIT_RUN-1 -:CMPRS_CBIT_RUN_BITS] == CMPRS_CBIT_RUN_STANDALONE);
else cmprs_standalone <= ctrl_we_r && di_r[CMPRS_CBIT_RUN] && (di_r[CMPRS_CBIT_RUN-1 -:CMPRS_CBIT_RUN_BITS] == CMPRS_CBIT_RUN_STANDALONE); else cmprs_standalone <= ctrl_we_r && di_r[CMPRS_CBIT_RUN] && (di_r[CMPRS_CBIT_RUN-1 -:CMPRS_CBIT_RUN_BITS] == CMPRS_CBIT_RUN_STANDALONE);
if (mrst) sigle_frame_buf <= 0; if (mrst) sigle_frame_buf <= 0;
else if (ctrl_we_r && di_r[CMPRS_CBIT_FRAMES]) sigle_frame_buf <= (di_r[CMPRS_CBIT_FRAMES-1 -:CMPRS_CBIT_FRAMES_BITS] == CMPRS_CBIT_FRAMES_SINGLE); else if (ctrl_we_r && di_r[CMPRS_CBIT_FRAMES]) sigle_frame_buf <= (di_r[CMPRS_CBIT_FRAMES-1 -:CMPRS_CBIT_FRAMES_BITS] == CMPRS_CBIT_FRAMES_SINGLE);
if (mrst) be16 <= 0;
else if (ctrl_we_r && di_r[CMPRS_CBIT_BE16]) be16 <= (di_r[CMPRS_CBIT_BE16-1 -:CMPRS_CBIT_BE16_BITS] == 1);
if (mrst) cmprs_qpage_mclk <= 0; if (mrst) cmprs_qpage_mclk <= 0;
else if (ctrl_we_r && di_r[CMPRS_CBIT_QBANK]) cmprs_qpage_mclk <= di_r[CMPRS_CBIT_QBANK-1 -:CMPRS_CBIT_QBANK_BITS]; else if (ctrl_we_r && di_r[CMPRS_CBIT_QBANK]) cmprs_qpage_mclk <= di_r[CMPRS_CBIT_QBANK-1 -:CMPRS_CBIT_QBANK_BITS];
...@@ -316,9 +331,14 @@ module cmprs_cmd_decode#( ...@@ -316,9 +331,14 @@ module cmprs_cmd_decode#(
always @ (posedge xclk) begin always @ (posedge xclk) begin
cmprs_en_xclk <= cmprs_en_mclk_r; cmprs_en_xclk <= cmprs_en_mclk_r;
cmprs_en_late_xclk <= cmprs_en_mclk_r || cmprs_en_extend; cmprs_en_late_xclk <= cmprs_en_mclk_r || cmprs_en_extend;
if (!cmprs_en_mclk_r) cmprs_en_xclk_jp <= 0;
else if (ctrl_we_xclk) cmprs_en_xclk_jp <= cmprs_en_mclk_r && !uncompressed_mclk;
if (!cmprs_en_mclk_r) cmprs_en_xclk_raw <= 0;
else if (ctrl_we_xclk) cmprs_en_xclk_raw <= cmprs_en_mclk_r && uncompressed_mclk;
end end
always @ (posedge xclk) if (ctrl_we_xclk) begin always @ (posedge xclk) if (ctrl_we_xclk) begin
// cmprs_en_late_xclk <= cmprs_en_mclk_r || cmprs_en_extend;
cmprs_qpage_xclk <= cmprs_qpage_mclk; cmprs_qpage_xclk <= cmprs_qpage_mclk;
cmprs_dcsub_xclk <= cmprs_dcsub_mclk; cmprs_dcsub_xclk <= cmprs_dcsub_mclk;
cmprs_mode_xclk <= cmprs_mode_mclk; cmprs_mode_xclk <= cmprs_mode_mclk;
...@@ -450,6 +470,11 @@ module cmprs_cmd_decode#( ...@@ -450,6 +470,11 @@ module cmprs_cmd_decode#(
jp4_dc_improved <= 0; jp4_dc_improved <= 0;
converter_type[2:0] <= CMPRS_MONO8; // 0 - color18, 1 - color20, 2 - mono, 3 - jp4, 4 - jp4-diff converter_type[2:0] <= CMPRS_MONO8; // 0 - color18, 1 - color20, 2 - mono, 3 - jp4, 4 - jp4-diff
end end
CMPRS_CBIT_CMODE_RAW: begin // uncompressed
converter_type[2:0] <= CMPRS_RAW; // 0 - color18, 1 - color20, 2 - mono, 3 - jp4, 4 - jp4-diff
end
default: begin // default: begin //
ignore_color <= 'bx; ignore_color <= 'bx;
four_blocks <= 'bx; four_blocks <= 'bx;
...@@ -457,9 +482,17 @@ module cmprs_cmd_decode#( ...@@ -457,9 +482,17 @@ module cmprs_cmd_decode#(
converter_type[2:0] <= 'bx; converter_type[2:0] <= 'bx;
end end
endcase endcase
// uncompressed <= cmprs_mode_xclk[3:0] == CMPRS_CBIT_CMODE_RAW;
end
always @ (posedge xclk) begin
if (!cmprs_en_mclk_r || (!uncompressed_xclk && !compressor_running)) uncompressed <= 0;
else if (frame_start_xclk) uncompressed <= uncompressed_xclk;
if (!cmprs_en_mclk_r || ( uncompressed_xclk && !compressor_running)) compressed <= 0;
else if (frame_start_xclk) compressed <= !uncompressed_xclk;
end
end
//frame_start_xclk //frame_start_xclk
pulse_cross_clock ctrl_we_xclk_i (.rst(mrst), .src_clk(mclk), .dst_clk(xclk), .in_pulse(ctrl_we_r), .out_pulse(ctrl_we_xclk),.busy()); pulse_cross_clock ctrl_we_xclk_i (.rst(mrst), .src_clk(mclk), .dst_clk(xclk), .in_pulse(ctrl_we_r), .out_pulse(ctrl_we_xclk),.busy());
pulse_cross_clock format_we_xclk_i (.rst(mrst), .src_clk(mclk), .dst_clk(xclk), .in_pulse(format_we_r), .out_pulse(format_we_xclk),.busy()); pulse_cross_clock format_we_xclk_i (.rst(mrst), .src_clk(mclk), .dst_clk(xclk), .in_pulse(format_we_r), .out_pulse(format_we_xclk),.busy());
......
...@@ -45,7 +45,6 @@ module cmprs_frame_sync#( ...@@ -45,7 +45,6 @@ module cmprs_frame_sync#(
parameter CMPRS_TIMEOUT= 1000 // mclk cycles parameter CMPRS_TIMEOUT= 1000 // mclk cycles
)( )(
// input rst,
input xclk, // global clock input, compressor single clock rate input xclk, // global clock input, compressor single clock rate
input mclk, // global system/memory clock input mclk, // global system/memory clock
input mrst, // @posedge mclk, sync reset input mrst, // @posedge mclk, sync reset
...@@ -88,7 +87,7 @@ module cmprs_frame_sync#( ...@@ -88,7 +87,7 @@ module cmprs_frame_sync#(
output reg force_flush_long, // force flush (abort frame), can be any clock and may last until stuffer_done_mclk output reg force_flush_long, // force flush (abort frame), can be any clock and may last until stuffer_done_mclk
// stuffer will re-clock and extract 0->1 transition // stuffer will re-clock and extract 0->1 transition
output stuffer_running_mclk, output stuffer_running_mclk,
output reading_frame, output reading_frame, // @mclk
output frame_started_mclk // use to store frame number output frame_started_mclk // use to store frame number
); );
/* /*
...@@ -101,8 +100,6 @@ module cmprs_frame_sync#( ...@@ -101,8 +100,6 @@ module cmprs_frame_sync#(
TODO: Simplify logic: instead of frame_start_pend_r - copy frame_number_srtc @ vsync_late, and start frame if it is not reading, TODO: Simplify logic: instead of frame_start_pend_r - copy frame_number_srtc @ vsync_late, and start frame if it is not reading,
in "run" mode, and frame_number_differ (in multi-frame mode) in "run" mode, and frame_number_differ (in multi-frame mode)
*/ */
// wire vsync_late_mclk; // single mclk cycle, reclocked from vsync_late
// wire frame_started_mclk;
reg bonded_mode; reg bonded_mode;
reg [5:0] frame_start_dst_r; reg [5:0] frame_start_dst_r;
reg frame_start_pend_r; // postpone frame_start_dst if previous frame was still being read during vsync_late reg frame_start_pend_r; // postpone frame_start_dst if previous frame was still being read during vsync_late
...@@ -111,14 +108,12 @@ module cmprs_frame_sync#( ...@@ -111,14 +108,12 @@ module cmprs_frame_sync#(
reg line_numbers_sync; // src unfinished line number is > this unfinished line number reg line_numbers_sync; // src unfinished line number is > this unfinished line number
reg reading_frame_r; // compressor is reading frame data (make sure input is done before starting next frame, otherwise make it a broken frame reg reading_frame_r; // compressor is reading frame data (make sure input is done before starting next frame, otherwise make it a broken frame
// reg broken_frame;
reg aborted_frame; reg aborted_frame;
reg stuffer_running_mclk_r; reg stuffer_running_mclk_r;
reg [CMPRS_TIMEOUT_BITS-1:0] timeout; reg [CMPRS_TIMEOUT_BITS-1:0] timeout;
reg cmprs_en_extend_r=0; reg cmprs_en_extend_r=0;
reg cmprs_en_d; reg cmprs_en_d;
reg suspend_end; // suspend at the end of the current frame until frame number changes reg suspend_end; // suspend at the end of the current frame until frame number changes
// reg cmprs_en_xclk;
wire last_mb_started_mclk; wire last_mb_started_mclk;
assign frame_start_dst = frame_start_dst_r[0]; assign frame_start_dst = frame_start_dst_r[0];
assign cmprs_en_extend = cmprs_en_extend_r; assign cmprs_en_extend = cmprs_en_extend_r;
...@@ -126,9 +121,6 @@ module cmprs_frame_sync#( ...@@ -126,9 +121,6 @@ module cmprs_frame_sync#(
assign stuffer_running_mclk = stuffer_running_mclk_r; assign stuffer_running_mclk = stuffer_running_mclk_r;
assign reading_frame = reading_frame_r; assign reading_frame = reading_frame_r;
// always @ (posedge xclk) begin
// cmprs_en_xclk <=cmprs_en;
// end
always @ (posedge mclk) begin always @ (posedge mclk) begin
if (mrst) cmprs_en_extend_r <= 0; if (mrst) cmprs_en_extend_r <= 0;
else if (cmprs_en) cmprs_en_extend_r <= 1; else if (cmprs_en) cmprs_en_extend_r <= 1;
...@@ -145,28 +137,18 @@ module cmprs_frame_sync#( ...@@ -145,28 +137,18 @@ module cmprs_frame_sync#(
cmprs_en_d <= cmprs_en; cmprs_en_d <= cmprs_en;
// broken_frame <= cmprs_en && cmprs_run && vsync_late && reading_frame_r; // single xclk pulse
aborted_frame <= cmprs_en_d && !cmprs_en && stuffer_running_mclk_r; aborted_frame <= cmprs_en_d && !cmprs_en && stuffer_running_mclk_r;
if (!stuffer_running_mclk_r ||!cmprs_en_extend_r) force_flush_long <= 0; if (!stuffer_running_mclk_r ||!cmprs_en_extend_r) force_flush_long <= 0;
// else if (broken_frame || aborted_frame) force_flush_long <= 1;
else if (aborted_frame) force_flush_long <= 1; else if (aborted_frame) force_flush_long <= 1;
// if (!cmprs_en || frame_done || (cmprs_run && vsync_late)) reading_frame_r <= 0;
// last_mb_start[2] is used as emergency turn off reading_frame if memory channel did not generate frame_done (i.e. wrong frame height)
// TODO: Consider the opposite - frame_done, but not got the last MB? // TODO: Consider the opposite - frame_done, but not got the last MB?
if (!cmprs_en || frame_done || last_mb_started_mclk) reading_frame_r <= 0; if (!cmprs_en || frame_done || last_mb_started_mclk) reading_frame_r <= 0;
else if (frame_started_mclk) reading_frame_r <= 1; else if (frame_started_mclk) reading_frame_r <= 1;
// if (!cmprs_run || frame_start_dst_r[0]) frame_start_pend_r <= 0; if (!cmprs_run || frame_start_conf) frame_start_pend_r <= 0;
if (!cmprs_run || frame_start_conf) frame_start_pend_r <= 0;
else if ((cmprs_run && vsync_late && reading_frame_r) || else if ((cmprs_run && vsync_late && reading_frame_r) ||
(frame_start_dst_r[5] && bonded_mode && frames_numbers_differ)) frame_start_pend_r <= 1; (frame_start_dst_r[5] && bonded_mode && frames_numbers_differ)) frame_start_pend_r <= 1;
// else if (frame_start_dst_r[0]) frame_start_pend_r <= 0;
// If started frame differs from tghe source one, needs to comrfess next frame after this is done, without vsync_late
// else if (frame_start_dst_r[5] ) frame_start_pend_r <= bonded_mode && frames_numbers_differ;
// if (!cmprs_en) suspend_end <= 0;
if (!cmprs_run) suspend_end <= 0; if (!cmprs_run) suspend_end <= 0;
else if (frame_done) suspend_end <= 1; else if (frame_done) suspend_end <= 1;
else if (frame_start_dst_r[3]) suspend_end <= 0; else if (frame_start_dst_r[3]) suspend_end <= 0;
...@@ -176,7 +158,6 @@ module cmprs_frame_sync#( ...@@ -176,7 +158,6 @@ module cmprs_frame_sync#(
cmprs_standalone); cmprs_standalone);
// modified - now bit 0 is disconnected from 1..5, 1 gets from memory channel controller, may be delayed // modified - now bit 0 is disconnected from 1..5, 1 gets from memory channel controller, may be delayed
if (!cmprs_en) frame_start_dst_r[5:1] <=0; if (!cmprs_en) frame_start_dst_r[5:1] <=0;
// else frame_start_dst_r[5:1] <= frame_start_dst_r[4:0];
else frame_start_dst_r[5:1] <= {frame_start_dst_r[4:1],frame_start_conf}; else frame_start_dst_r[5:1] <= {frame_start_dst_r[4:1],frame_start_conf};
if (!cmprs_en) bonded_mode <= 0; if (!cmprs_en) bonded_mode <= 0;
...@@ -188,14 +169,12 @@ module cmprs_frame_sync#( ...@@ -188,14 +169,12 @@ module cmprs_frame_sync#(
frames_numbers_differ <= !suspend_end && (frame_number_src != frame_number); // during end of frame, before frame number is incremented frames_numbers_differ <= !suspend_end && (frame_number_src != frame_number); // during end of frame, before frame number is incremented
/// line_numbers_sync <= (line_unfinished_src > line_unfinished);
line_numbers_sync <= (line_unfinished_src >= line_unfinished); line_numbers_sync <= (line_unfinished_src >= line_unfinished);
suspend <= bonded_mode && (!frames_in_sync || !((sigle_frame_buf ? frames_differ : frames_numbers_differ) || line_numbers_sync)); suspend <= bonded_mode && (!frames_in_sync || !((sigle_frame_buf ? frames_differ : frames_numbers_differ) || line_numbers_sync));
end end
// pulse_cross_clock vsync_late_mclk_i (.rst(xrst), .src_clk(xclk), .dst_clk(mclk), .in_pulse(cmprs_en_xclk && vsync_late), .out_pulse(vsync_late_mclk),.busy());
pulse_cross_clock frame_started_i (.rst(xrst), .src_clk(xclk), .dst_clk(mclk), .in_pulse(frame_started), .out_pulse(frame_started_mclk),.busy()); pulse_cross_clock frame_started_i (.rst(xrst), .src_clk(xclk), .dst_clk(mclk), .in_pulse(frame_started), .out_pulse(frame_started_mclk),.busy());
pulse_cross_clock last_mb_started_i (.rst(xrst), .src_clk(xclk), .dst_clk(mclk), .in_pulse(last_mb_started), .out_pulse(last_mb_started_mclk),.busy()); pulse_cross_clock last_mb_started_i (.rst(xrst), .src_clk(xclk), .dst_clk(mclk), .in_pulse(last_mb_started), .out_pulse(last_mb_started_mclk),.busy());
......
...@@ -117,7 +117,6 @@ module cmprs_pixel_buf_iface #( ...@@ -117,7 +117,6 @@ module cmprs_pixel_buf_iface #(
reg [ 2:0] mb_col_number; // number of tile column where macrobloc starts - valid 2 cycles before mb_pre_start reg [ 2:0] mb_col_number; // number of tile column where macrobloc starts - valid 2 cycles before mb_pre_start
wire [ 9:0] extra_start_addr_w = mb_col_number * mb_h_m1; //added to mb_start_addr when non-zero column wire [ 9:0] extra_start_addr_w = mb_col_number * mb_h_m1; //added to mb_start_addr when non-zero column
reg [ 5:0] extra_start_addr_r; reg [ 5:0] extra_start_addr_r;
// reg [ 5:0] mb_h; // macroblock height (lost MSB - OK)
reg [ 9:0] mb_start_addr; // was macroblock_x, noccrected for multi-column. valid with mb_pre_start reg [ 9:0] mb_start_addr; // was macroblock_x, noccrected for multi-column. valid with mb_pre_start
assign buf_ra = bufa_r; assign buf_ra = bufa_r;
...@@ -130,7 +129,6 @@ module cmprs_pixel_buf_iface #( ...@@ -130,7 +129,6 @@ module cmprs_pixel_buf_iface #(
assign mb_pre_end = mb_pre_end_r; assign mb_pre_end = mb_pre_end_r;
assign mb_release_buf = mb_release_buf_r; assign mb_release_buf = mb_release_buf_r;
assign buf_rd = buf_re[1:0]; assign buf_rd = buf_re[1:0];
// assign data_out = do_r;
assign pre_first_out = pre_first_out_r[0]; assign pre_first_out = pre_first_out_r[0];
assign pre2_first_out = pre_first_out_r[1]; assign pre2_first_out = pre_first_out_r[1];
`ifdef DEBUG_COMPRESSOR_SCRAMBLE `ifdef DEBUG_COMPRESSOR_SCRAMBLE
...@@ -147,7 +145,6 @@ module cmprs_pixel_buf_iface #( ...@@ -147,7 +145,6 @@ module cmprs_pixel_buf_iface #(
`endif `endif
always @(posedge xclk) begin always @(posedge xclk) begin
// mb_h <= mb_h_m1+1; // macroblock height
mb_col_number <= {macroblock_x[6:5],tile_col_width?1'b0:macroblock_x[4]}; mb_col_number <= {macroblock_x[6:5],tile_col_width?1'b0:macroblock_x[4]};
extra_start_addr_r <= extra_start_addr_w[5:0]; extra_start_addr_r <= extra_start_addr_w[5:0];
mb_start_addr <= {3'b0,macroblock_x} + {extra_start_addr_r,4'b0}; mb_start_addr <= {3'b0,macroblock_x} + {extra_start_addr_r,4'b0};
...@@ -164,10 +161,6 @@ module cmprs_pixel_buf_iface #( ...@@ -164,10 +161,6 @@ module cmprs_pixel_buf_iface #(
//mb_pre_start //mb_pre_start
if (!frame_en) pre_first_out_r <= 0; if (!frame_en) pre_first_out_r <= 0;
else pre_first_out_r <= {mb_pre_start, pre_first_out_r[CMPRS_BUF_EXTRA_LATENCY + 2 : 1]}; else pre_first_out_r <= {mb_pre_start, pre_first_out_r[CMPRS_BUF_EXTRA_LATENCY + 2 : 1]};
// else pre_first_out_r <= buf_re[CMPRS_BUF_EXTRA_LATENCY+1] && ! buf_re[CMPRS_BUF_EXTRA_LATENCY+2];
// if (!frame_en) pre2_first_out <= 0;
// else pre2_first_out <= buf_re[CMPRS_BUF_EXTRA_LATENCY + 0] && ! buf_re[CMPRS_BUF_EXTRA_LATENCY + 1];
if (mb_pre_start) rows_left <= mb_h_m1; if (mb_pre_start) rows_left <= mb_h_m1;
else if (last_col) rows_left <= rows_left - 1; else if (last_col) rows_left <= rows_left - 1;
...@@ -177,17 +170,14 @@ module cmprs_pixel_buf_iface #( ...@@ -177,17 +170,14 @@ module cmprs_pixel_buf_iface #(
if (!frame_en) buf_re[CMPRS_BUF_EXTRA_LATENCY+2:1] <= 0; if (!frame_en) buf_re[CMPRS_BUF_EXTRA_LATENCY+2:1] <= 0;
// if (buf_re[0]) last_col <= 0; // ????
if (!buf_re[0]) last_col <= 0; if (!buf_re[0]) last_col <= 0;
else last_col <= (cols_left == 1); else last_col <= (cols_left == 1);
// if (buf_re[0]) last_row <= 0;
if (!buf_re[0]) last_row <= 0; if (!buf_re[0]) last_row <= 0;
else if (last_col) last_row <= (rows_left == 1); else if (last_col) last_row <= (rows_left == 1);
first_col <= (mb_pre_start || (last_col && !last_row)); first_col <= (mb_pre_start || (last_col && !last_row));
// if (mb_pre_start) row_sa <= {start_page,3'b0,mb_start_addr}; // macroblock_x};
if (mb_pre_start) row_sa <= {start_page,mb_start_addr}; // macroblock_x}; if (mb_pre_start) row_sa <= {start_page,mb_start_addr}; // macroblock_x};
else if (first_col) row_sa <= row_sa + (tile_col_width ? 12'h20:12'h10); else if (first_col) row_sa <= row_sa + (tile_col_width ? 12'h20:12'h10);
...@@ -207,7 +197,6 @@ module cmprs_pixel_buf_iface #( ...@@ -207,7 +197,6 @@ module cmprs_pixel_buf_iface #(
else if (last_in_tile) bufa_r[11:10] <= bufa_r[11:10] + 1; else if (last_in_tile) bufa_r[11:10] <= bufa_r[11:10] + 1;
// Most time critical - calculation of the buffer address // Most time critical - calculation of the buffer address
// if (mb_pre_start) bufa_r[9:0] <= {3'b0,mb_start_addr}; // macroblock_x};
if (mb_pre_start) bufa_r[9:0] <= {mb_start_addr}; // macroblock_x}; if (mb_pre_start) bufa_r[9:0] <= {mb_start_addr}; // macroblock_x};
else if (last_col) bufa_r[9:0] <= row_sa[9:0]; // 'bx next cycle after AFTER mb_pre_start else if (last_col) bufa_r[9:0] <= row_sa[9:0]; // 'bx next cycle after AFTER mb_pre_start
else if (last_in_tile) bufa_r[9:0] <= tile_sa; else if (last_in_tile) bufa_r[9:0] <= tile_sa;
......
/*!
* <b>Module:</b>cmprs_raw_buf_iface
* @file cmprs_raw_buf_iface.v
* @date 2015-06-11
* @author Andrey Filippov
*
* @brief Communicates with compressor memory buffer in raw (uncompressed) mode
*
* @copyright Copyright (c) 2019 Elphel, Inc.
*
* <b>License:</b>
*
* cmprs_raw_buf_iface.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* cmprs_raw_buf_iface.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module cmprs_raw_buf_iface #(
// parameter DCT_PIPELINE_PAUSE = 48, // TODO: find really required value (minimal), adjust counter bits (now 6)
// // 48 seems to be OK (may be less)
parameter FRAME_QUEUE_WIDTH = 2
)(
input xclk, // global clock input, compressor single clock rate
input mclk, // global clock for commands (posedge) and write side of the memory buffer (negedge)
input mrst, // @posedge mclk, sync reset
input xrst, // @posedge xclk, sync reset
// Page is limited by 1kB or end of line
// buffer interface, DDR3 memory read
input xfer_reset_page_rd, // @ negedge mclk - reset ddr3 memory buffer. Use it to reset the read buffer too
input page_ready_chn, // single mclk (posedge)
output next_page_chn, // single mclk (posedge): Done with the page in the buffer, memory controller may read more data
// will be externally combined with "uncompressed"
input frame_en, // if 0 - will reset logic immediately (but not the page number)
input frame_start_xclk, // frame parameters are valid after this pulse (re-clocked from the memory controller)
input frame_go, // start frame: if idle, will start reading data (if available),
// if running - will not restart a new frame if 0.
input cmprs_run_mclk, // 0 - off or stopping, reset frame_pre_run
// input [ 4:0] left_marg, // left margin (for not-yet-implemented) mono JPEG (8 lines tile row) can need 7 bits (mod 32 - tile)
input [12:0] n_blocks_in_row_m1, // number of macroblocks in a macroblock row minus 1
input [12:0] n_block_rows_m1, // number of macroblock rows in a frame minus 1
input stuffer_running, // @xclk, active while bit stuffer or trailer are running
input raw_be16, // 0: bytes 0-1-2-3-4-5..., 1: bytes 1-0-3-2-5-4...
output [11:0] buf_ra, // buffer read address (2 MSB - page number)
output [ 1:0] buf_rd, // buf {regen, re}
output raw_start, // was color_first leading edge
output raw_prefb, // input
output raw_ts_copy, // input
output raw_flush // input
);
// TODO:
wire reset_page_rd; // xfer_reset_page_rd @ xclk
wire page_ready; // page_ready_chn @ xclk
wire frame_en_w;
reg frame_en_r;
wire frame_pre_start_w; // start sequence for a new frame
reg frame_pre_start_r;
reg frame_start_xclk_r; // next cycle after frame_start_xclk
reg cmprs_run_xclk;
reg frame_pre_run;
reg [FRAME_QUEUE_WIDTH:0] frame_que_cntr; // width+1
reg [3:0] frame_finish_r; // active after last macroblock in a frame
reg [ 2:0] next_valid; // number of next valid page (only 2 LSB are actual page number)
reg [ 2:0] needed_page; // calculate at MB start
wire [ 2:0] buf_diff; // difference between page needed and next valid - should be negative to have it ready
wire buf_ready_w; // External memory buffer has all the pages needed
reg [14:0] quads_left; // number of quad bytes left in a row (after this)
reg [16:0] rows_left; // number of rows left (after this)
reg [1:0] rows_last;
reg page_run; // on after page_start, off after quad_r[2], so during last quad_r[3] shold be off
reg [3:0] quad_r;
reg quad_last; // last quad byte in a row should be valid @quad_r[2]
wire page_start;
wire page_end_w;
wire release_buf; // send required "next_page" pulses to buffer. Having rather long minimal latency in the memory
wire frame_finish_w;
wire frames_pending;
reg starting; // from frame_start_r to first page start
reg mode_valid;// after parameters are valid, invalid whe mode is reset
reg page_end_r;
reg frame_done;
assign frame_en_w = frame_en && frame_go; // both are inputs
// one extra at the end of frame is needed (sequence will be short) ???
//// assign mb_pre_start_w = mb_pre_end_in || (frame_start_xclk_r && !frame_pre_run); // && !starting);
// repeated start (if some are pending) and for the first frame
assign frame_pre_start_w = (frames_pending && frame_finish_w) || (frame_start_xclk_r && !frame_pre_run && !starting);
assign buf_diff = needed_page - next_valid;
assign buf_ready_w = buf_diff[2];
// assign page_start = !page_run && buf_ready_w && ((frame_pre_run && starting && stuffer_running) || !frame_done); // frame_pre_run should deassert in time with frame end
assign page_start = !page_run && buf_ready_w && frame_pre_run && ((starting && stuffer_running) || !frame_done); // frame_pre_run should deassert in time with frame end
// reg page_restart_r;
assign raw_start = frame_pre_start_r; // for JP - leading edge of color_first
// assign page_end_w = frame_en && quad_r[2] && (&bufa_r[9:2] || quad_last);
assign page_end_w = frame_en && quad_r[1] && (&bufa_r[9:2] || quad_last);
// assign release_buf = page_end_w;
assign release_buf = page_end_r;
assign frame_finish_w = frame_finish_r[1] && !frame_finish_r[0]; // now just single-cycle, no need for frame_finish_r[0]
assign frames_pending = !frame_que_cntr[FRAME_QUEUE_WIDTH] && (|frame_que_cntr[FRAME_QUEUE_WIDTH-1:0]);
assign frame_en_w = frame_en && frame_go;
// assign raw_prefb = buf_rd_r[0]; // delay if memory registered more. TODO Add parameter if it already used
assign raw_prefb = quad_r[1]; // delay if memory registered more. TODO Add parameter if it already used
assign raw_ts_copy = frame_en_r && rows_last[0] && !rows_last[1];
reg [11:0] bufa_r; // buffer read address (2 MSB - page number)
reg [1:0] buf_rd_r;
assign raw_flush = frame_finish_r[3]; // frame_finish_w;
assign buf_ra = bufa_r;
assign buf_rd = buf_rd_r[1:0];
always @(posedge xclk) begin
// pages read from the external memory, previous one is the last in the buffer
if (reset_page_rd) next_valid <= 0;
else if (page_ready) next_valid <= next_valid + 1;
if (!frame_en) mode_valid <= 0;
// else if (frame_start_xclk) mode_valid <= frame_start_xclk;
else if (frame_pre_start_r) mode_valid <= 1; // frame_pre_start_r sets remaining quads, rows
cmprs_run_xclk <= cmprs_run_mclk;
frame_pre_start_r <= frame_pre_start_w; // same time as mb_pre_start
if (!frame_en) frame_start_xclk_r <= 0;
else frame_start_xclk_r <= frame_start_xclk;
if (!frame_en) starting <= 1'b0;
else if (frame_pre_start_w) starting <= 1'b1;
else if (page_start) starting <= 1'b0;
if (!frame_en) frame_en_r <= 0;
else frame_en_r <= frame_en_w; // stays on?
if (!cmprs_run_xclk) frame_que_cntr <= 0;
else if ( frame_start_xclk_r && !frame_pre_start_r) frame_que_cntr <= frame_que_cntr + 1;
else if (!frame_start_xclk_r && frame_pre_start_r) frame_que_cntr <= frame_que_cntr - 1;
if (reset_page_rd) needed_page[2:0] <= 0; // together with next_valid, next_invalid
else if (release_buf) begin
needed_page <= needed_page + 1;
end
page_end_r <= page_end_w; // quad_r[2] && (&bufa_r[9:2] || quad_last);
// page_run
if (!frame_pre_run) page_run <= 0;
else if (page_start) page_run <= 1;
// else if (quad_r[2] && page_end_r) page_run <= 0;
else if (page_end_r) page_run <= 0;
if (!frame_pre_run) quad_r <= 0;
else quad_r <= {quad_r[2:0], page_start | (quad_r[3] & page_run)};
buf_rd_r <= {buf_rd_r[0], page_start | (|quad_r[2:0] | (quad_r[3] & page_run))};
if (!frame_en) frame_finish_r <= 0;
else frame_finish_r <= {frame_finish_r[2:0], quad_r[2] & quad_last & rows_last[0]};
//quads_left
if (frame_pre_start_r || (quad_r[2] && quad_last)) quads_left <= {n_blocks_in_row_m1, 2'b11};
else if (quad_r[2]) quads_left <= quads_left - 1;
quad_last <= mode_valid && !(|quads_left); // valid from 2 after frame_pre_start_r or after quad_r[3]
if (frame_pre_start_r) rows_left <= {n_block_rows_m1, 4'b1111};
else if ((quad_r[2] && quad_last)) rows_left <= rows_left - 1;
rows_last <= {rows_last[0], mode_valid & ~(|rows_left)};
// if (frame_pre_start_r) bufa_r[11:10] <= needed_page[1:0];
if (page_start) bufa_r[11:10] <= needed_page[1:0];
// if (frame_pre_start_r) bufa_r[9:1] <= 0;
if (page_start) bufa_r[9:1] <= 0;
else if (quad_r[1] | quad_r[3]) bufa_r[9:1] <= bufa_r[9:1] + 1;
if (frame_pre_start_r) bufa_r[0] <= raw_be16;
else if (buf_rd_r[0]) bufa_r[0] <= ~bufa_r[0];
if (!frame_en || (!frames_pending && frame_finish_w)) frame_pre_run <= 0;
else if (frame_pre_start_w) frame_pre_run <= 1;
if (!frame_en || frame_pre_start_r) frame_done <= 0;
else if (quad_r[2] && quad_last && rows_last) frame_done <= 1; // valid @ quad_r[3], when page_run is already == 0
end
reg nmrst;
always @(negedge mclk) nmrst <= mrst;
// synchronization between mclk and xclk clock domains
// negedge mclk -> xclk (verify clock inversion is absorbed)
pulse_cross_clock reset_page_rd_i (.rst(nmrst), .src_clk(~mclk),.dst_clk(xclk), .in_pulse(xfer_reset_page_rd), .out_pulse(reset_page_rd), .busy());
// mclk -> xclk
pulse_cross_clock page_ready_i (.rst(mrst), .src_clk(mclk), .dst_clk(xclk), .in_pulse(page_ready_chn), .out_pulse(page_ready), .busy());
// xclk -> mclk
pulse_cross_clock next_page_chn_i (.rst(xrst), .src_clk(xclk), .dst_clk(mclk), .in_pulse(page_end_r), .out_pulse(next_page_chn), .busy());
endmodule
...@@ -78,6 +78,8 @@ module compressor393 # ( ...@@ -78,6 +78,8 @@ module compressor393 # (
parameter CMPRS_CBIT_CMODE_BITS = 4, // number of bits to control compressor color modes parameter CMPRS_CBIT_CMODE_BITS = 4, // number of bits to control compressor color modes
parameter CMPRS_CBIT_FRAMES = 15, // bit # to control compressor multi/single frame buffer modes parameter CMPRS_CBIT_FRAMES = 15, // bit # to control compressor multi/single frame buffer modes
parameter CMPRS_CBIT_FRAMES_BITS = 1, // number of bits to control compressor multi/single frame buffer modes parameter CMPRS_CBIT_FRAMES_BITS = 1, // number of bits to control compressor multi/single frame buffer modes
parameter CMPRS_CBIT_BE16 = 17, // bit # to control compressor multi/single frame buffer modes
parameter CMPRS_CBIT_BE16_BITS = 1, // number of bits to control compressor multi/single frame buffer modes
parameter CMPRS_CBIT_BAYER = 20, // bit # to control compressor Bayer shift mode parameter CMPRS_CBIT_BAYER = 20, // bit # to control compressor Bayer shift mode
parameter CMPRS_CBIT_BAYER_BITS = 2, // number of bits to control compressor Bayer shift mode parameter CMPRS_CBIT_BAYER_BITS = 2, // number of bits to control compressor Bayer shift mode
parameter CMPRS_CBIT_FOCUS = 23, // bit # to control compressor focus display mode parameter CMPRS_CBIT_FOCUS = 23, // bit # to control compressor focus display mode
...@@ -100,6 +102,7 @@ module compressor393 # ( ...@@ -100,6 +102,7 @@ module compressor393 # (
parameter CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2 = 4'ha, // jp4, 4 blocks, differential, hdr,divide by 2 parameter CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2 = 4'ha, // jp4, 4 blocks, differential, hdr,divide by 2
parameter CMPRS_CBIT_CMODE_MONO1 = 4'hb, // mono JPEG (not yet implemented) parameter CMPRS_CBIT_CMODE_MONO1 = 4'hb, // mono JPEG (not yet implemented)
parameter CMPRS_CBIT_CMODE_MONO4 = 4'he, // mono 4 blocks parameter CMPRS_CBIT_CMODE_MONO4 = 4'he, // mono 4 blocks
parameter CMPRS_CBIT_CMODE_RAW = 4'hf, // uncompressed
parameter CMPRS_CBIT_FRAMES_SINGLE = 0, //1, // use a single-frame buffer for images parameter CMPRS_CBIT_FRAMES_SINGLE = 0, //1, // use a single-frame buffer for images
parameter CMPRS_COLOR18 = 0, // JPEG 4:2:0 with 18x18 overlapping tiles for de-bayer parameter CMPRS_COLOR18 = 0, // JPEG 4:2:0 with 18x18 overlapping tiles for de-bayer
...@@ -107,7 +110,8 @@ module compressor393 # ( ...@@ -107,7 +110,8 @@ module compressor393 # (
parameter CMPRS_MONO16 = 2, // JPEG 4:2:0 with 16x16 non-overlapping tiles, color components zeroed parameter CMPRS_MONO16 = 2, // JPEG 4:2:0 with 16x16 non-overlapping tiles, color components zeroed
parameter CMPRS_JP4 = 3, // JP4 mode with 16x16 macroblocks parameter CMPRS_JP4 = 3, // JP4 mode with 16x16 macroblocks
parameter CMPRS_JP4DIFF = 4, // JP4DIFF mode TODO: see if correct parameter CMPRS_JP4DIFF = 4, // JP4DIFF mode TODO: see if correct
parameter CMPRS_MONO8 = 7, // Regular JPEG monochrome with 8x8 macroblocks (not yet implemented) parameter CMPRS_RAW = 6, // Not comressed, raw data
parameter CMPRS_MONO8 = 7, // Regular JPEG monochrome with 8x8 macroblocks (not yet implemented)
parameter CMPRS_FRMT_MBCM1 = 0, // bit # of number of macroblock columns minus 1 field in format word parameter CMPRS_FRMT_MBCM1 = 0, // bit # of number of macroblock columns minus 1 field in format word
parameter CMPRS_FRMT_MBCM1_BITS = 13, // number of bits in number of macroblock columns minus 1 field in format word parameter CMPRS_FRMT_MBCM1_BITS = 13, // number of bits in number of macroblock columns minus 1 field in format word
...@@ -372,6 +376,8 @@ module compressor393 # ( ...@@ -372,6 +376,8 @@ module compressor393 # (
.CMPRS_CBIT_CMODE_BITS (CMPRS_CBIT_CMODE_BITS), .CMPRS_CBIT_CMODE_BITS (CMPRS_CBIT_CMODE_BITS),
.CMPRS_CBIT_FRAMES (CMPRS_CBIT_FRAMES), .CMPRS_CBIT_FRAMES (CMPRS_CBIT_FRAMES),
.CMPRS_CBIT_FRAMES_BITS (CMPRS_CBIT_FRAMES_BITS), .CMPRS_CBIT_FRAMES_BITS (CMPRS_CBIT_FRAMES_BITS),
.CMPRS_CBIT_BE16 (CMPRS_CBIT_BE16),
.CMPRS_CBIT_BE16_BITS (CMPRS_CBIT_BE16_BITS),
.CMPRS_CBIT_BAYER (CMPRS_CBIT_BAYER), .CMPRS_CBIT_BAYER (CMPRS_CBIT_BAYER),
.CMPRS_CBIT_BAYER_BITS (CMPRS_CBIT_BAYER_BITS), .CMPRS_CBIT_BAYER_BITS (CMPRS_CBIT_BAYER_BITS),
.CMPRS_CBIT_FOCUS (CMPRS_CBIT_FOCUS), .CMPRS_CBIT_FOCUS (CMPRS_CBIT_FOCUS),
...@@ -392,12 +398,14 @@ module compressor393 # ( ...@@ -392,12 +398,14 @@ module compressor393 # (
.CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2 (CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2), .CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2 (CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2),
.CMPRS_CBIT_CMODE_MONO1 (CMPRS_CBIT_CMODE_MONO1), .CMPRS_CBIT_CMODE_MONO1 (CMPRS_CBIT_CMODE_MONO1),
.CMPRS_CBIT_CMODE_MONO4 (CMPRS_CBIT_CMODE_MONO4), .CMPRS_CBIT_CMODE_MONO4 (CMPRS_CBIT_CMODE_MONO4),
.CMPRS_CBIT_CMODE_RAW (CMPRS_CBIT_CMODE_RAW),
.CMPRS_CBIT_FRAMES_SINGLE (CMPRS_CBIT_FRAMES_SINGLE), .CMPRS_CBIT_FRAMES_SINGLE (CMPRS_CBIT_FRAMES_SINGLE),
.CMPRS_COLOR18 (CMPRS_COLOR18), .CMPRS_COLOR18 (CMPRS_COLOR18),
.CMPRS_COLOR20 (CMPRS_COLOR20), .CMPRS_COLOR20 (CMPRS_COLOR20),
.CMPRS_MONO16 (CMPRS_MONO16), .CMPRS_MONO16 (CMPRS_MONO16),
.CMPRS_JP4 (CMPRS_JP4), .CMPRS_JP4 (CMPRS_JP4),
.CMPRS_JP4DIFF (CMPRS_JP4DIFF), .CMPRS_JP4DIFF (CMPRS_JP4DIFF),
.CMPRS_RAW (CMPRS_RAW),
.CMPRS_MONO8 (CMPRS_MONO8), .CMPRS_MONO8 (CMPRS_MONO8),
.CMPRS_FRMT_MBCM1 (CMPRS_FRMT_MBCM1), .CMPRS_FRMT_MBCM1 (CMPRS_FRMT_MBCM1),
.CMPRS_FRMT_MBCM1_BITS (CMPRS_FRMT_MBCM1_BITS), .CMPRS_FRMT_MBCM1_BITS (CMPRS_FRMT_MBCM1_BITS),
......
...@@ -53,7 +53,7 @@ module encoderDCAC393( ...@@ -53,7 +53,7 @@ module encoderDCAC393(
input first_blockz, // first block input (@zds) input first_blockz, // first block input (@zds)
input zds, // strobe - one ahead of the DC component output input zds, // strobe - one ahead of the DC component output
output reg last, // output reg last, //
output reg [15:0] do, output reg [15:0] dout,
output reg dv, output reg dv,
// just for debug // just for debug
output comp_lastinmbo, output comp_lastinmbo,
...@@ -132,7 +132,7 @@ module encoderDCAC393( ...@@ -132,7 +132,7 @@ module encoderDCAC393(
(cntr[5:0]==6'h3f), (cntr[5:0]==6'h3f),
ac_in[11:0]}}; ac_in[11:0]}};
was_nonzero_AC <= en && (ac_in[11:0]!=12'b0) && DCACen; was_nonzero_AC <= en && (ac_in[11:0]!=12'b0) && DCACen;
if (pre_dv) do <= rll_out? {3'b0,val_r[12],6'b0,rll_cntr[5:0]}:{1'b1,val_r[14:0]}; if (pre_dv) dout <= rll_out? {3'b0,val_r[12],6'b0,rll_cntr[5:0]}:{1'b1,val_r[14:0]};
dv <= pre_dv; dv <= pre_dv;
DCACen <= en && (pre_DCACen || (DCACen && (cntr[5:0]!=6'h3f))); // adjust DCACen <= en && (pre_DCACen || (DCACen && (cntr[5:0]!=6'h3f))); // adjust
if (!DCACen) cntr[5:0] <=6'b0; if (!DCACen) cntr[5:0] <=6'b0;
......
...@@ -59,7 +59,7 @@ module focus_sharp393( ...@@ -59,7 +59,7 @@ module focus_sharp393(
input quant_ds, // quantizator ds input quant_ds, // quantizator ds
input [12:0] quant_d, // [11:0]quantizator data output input [12:0] quant_d, // [11:0]quantizator data output
input [15:0] quant_dc_tdo, // [15:0], MSB aligned coefficient for the DC component (used in focus module) input [15:0] quant_dc_tdo, // [15:0], MSB aligned coefficient for the DC component (used in focus module)
output reg [12:0] do, // [11:0] pixel data out, make timing ignore (valid 1.5 clk earlier that Quantizer output) output reg [12:0] dout, // [11:0] pixel data out, make timing ignore (valid 1.5 clk earlier that Quantizer output)
output reg ds, // data out strobe (one ahead of the start of dv) output reg ds, // data out strobe (one ahead of the start of dv)
output reg [31:0] hifreq); //[31:0]) // accumulated high frequency components in a frame sub-window output reg [31:0] hifreq); //[31:0]) // accumulated high frequency components in a frame sub-window
...@@ -248,7 +248,7 @@ module focus_sharp393( ...@@ -248,7 +248,7 @@ module focus_sharp393(
ds <= pre_ds; ds <= pre_ds;
pre_do[12:0] <= next_do[12:0]; pre_do[12:0] <= next_do[12:0];
need_corr_max <=luma_dc_out && (mode[1:0]!=2'h0); need_corr_max <=luma_dc_out && (mode[1:0]!=2'h0);
do[12:0] <= (need_corr_max && !pre_do[12] && (pre_do[11] || (pre_do[10:0]>quant_dc_tdo[15:5])) )? dout[12:0] <= (need_corr_max && !pre_do[12] && (pre_do[11] || (pre_do[10:0]>quant_dc_tdo[15:5])) )?
{2'b0,quant_dc_tdo[15:5]} : {2'b0,quant_dc_tdo[15:5]} :
pre_do[12:0]; pre_do[12:0];
end end
......
...@@ -4,7 +4,7 @@ ...@@ -4,7 +4,7 @@
* @date 2015-10-26 * @date 2015-10-26
* @author Andrey Filippov * @author Andrey Filippov
* *
* @brief Wrapper fior several JPEG/JP4 compression modules. It includes * @brief Wrapper for several JPEG/JP4 compression modules. It includes
* - Huffman encoder (huffman_snglclk), * - Huffman encoder (huffman_snglclk),
* - bit stuffer (bit_stuffer_27_32), * - bit stuffer (bit_stuffer_27_32),
* - escapes 0xff with 0x00 (bit_stuffer_escape) * - escapes 0xff with 0x00 (bit_stuffer_escape)
...@@ -66,7 +66,8 @@ module huffman_stuffer_meta( ...@@ -66,7 +66,8 @@ module huffman_stuffer_meta(
// and before the data is needed for output // and before the data is needed for output
input ts_pre_stb, // @mclk - 1 cycle before receiving 8 bytes of timestamp data input ts_pre_stb, // @mclk - 1 cycle before receiving 8 bytes of timestamp data
input [7:0] ts_data, // timestamp data (s0,s1,s2,s3,us0,us1,us2,us3==0) input [7:0] ts_data, // timestamp data (s0,s1,s2,s3,us0,us1,us2,us3==0)
input color_first, // @fradv_clk only used for timestamp //TODO: Should be generated fro raw also
input color_first, // @fradv_clk only used for timestamp
// outputs @ negedge clk // outputs @ negedge clk
output [31:0] data_out, // [31:0] output data output [31:0] data_out, // [31:0] output data
output data_out_valid,// output data valid output data_out_valid,// output data valid
...@@ -154,7 +155,8 @@ module huffman_stuffer_meta( ...@@ -154,7 +155,8 @@ module huffman_stuffer_meta(
.flush_out (escape_flush_out) // output reg .flush_out (escape_flush_out) // output reg
); );
bit_stuffer_metadata bit_stuffer_metadata_i ( // TODO: Insert raw data here, always 4x bytes (actually 16*16*(1..2))
bit_stuffer_raw_metadata bit_stuffer_metadata_i (
.mclk (mclk), // input .mclk (mclk), // input
.mrst (mrst), // input .mrst (mrst), // input
.xclk (xclk), // input .xclk (xclk), // input
......
/*!
* <b>Module:</b>huffman_stuffer_raw_meta
* @file huffman_stuffer_raw_meta.v
* @date 2015-10-26
* @author Andrey Filippov
*
* @brief Wrapper for several JPEG/JP4 compression modules. It includes
* - Huffman encoder (huffman_snglclk),
* - bit stuffer (bit_stuffer_27_32),
* - escapes 0xff with 0x00 (bit_stuffer_escape)
* - inserts meta-data (timestamp and data length) (bit_stuffer_metadata)
*
* This is a "new" (made for x393 project) part of the JPEG/JP4 comressor
* that eliminates use of the double frequency clock.
*
* @copyright Copyright (c) 2015 Elphel, Inc .
*
* <b>License:</b>
*
* huffman_stuffer_raw_meta.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* huffman_stuffer_raw_meta.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module huffman_stuffer_raw_meta(
input mclk, // system clock to write tables
input mrst,
input xclk, // pixel clock, sync to incoming data
input en_huffman, // @xclk
input en_stuffer, // @xclk
input abort_stuffer, // @ any, valid ffor raw also
// Interface to program Huffman tables
input tser_we, // enable write to a table
input tser_a_not_d, // address/not data distributed to submodules
input [ 7:0] tser_d, // byte-wide serialized tables address/data to submodules
// Input data
input [15:0] di, // [15:0] specially RLL prepared 16-bit data (to FIFO) (sync to xclk)
input ds, // di valid strobe (sync to xclk)
// time stamping - will copy time at the end of color_first (later than the first hact after vact in the current frame, but before the next one
// and before the data is needed for output
input ts_pre_stb, // @mclk - 1 cycle before receiving 8 bytes of timestamp data
input [7:0] ts_data, // timestamp data (s0,s1,s2,s3,us0,us1,us2,us3==0)
//TODO: Should be generated for raw also
input color_first, // @fradv_clk only used for timestamp
// RAW mode ports, all @ xclk
input compressed_mode, // operating in raw mode (uncompressed)
input raw_mode, // operating in raw mode (uncompressed)
input raw_be16, // swap byte pairs to outut 16-bit big endian data
input [7:0] raw_bytes, // raw bypass byte data in little endian order
input raw_start, // single-cycle set "running"
input raw_prefb, // 1 cycle before sequence of 4 bytes
input raw_ts_copy, // single-cycle copy timestamp (some time before flush)
input raw_flush, // flush remaining data, length and timestamp
// outputs @ negedge clk
output [31:0] data_out, // [31:0] output data
output data_out_valid,// output data valid
output done, // reset by !en, goes high after some delay after flushing
output running, // from registering timestamp until done
input clk_flush, // other clock to generate synchronized 1-cycle flush_clk output
output flush_clk // 1-cycle flush output @ clk_flush
`ifdef DEBUG_RING
,output test_lbw,
output gotLastBlock, // last block done - flush the rest bits
output [3:0] dbg_etrax_dma
,output dbg_ts_rstb
,output [7:0] dbg_ts_dout
`endif
);
wire [26:0] huffman_do27;
wire [4:0] huffman_dl;
wire huffman_dv;
wire huffman_flush;
wire huffman_last_block;
wire [31:0] stuffer_do32;
wire [1:0] stuffer_bytes;
wire stuffer_dv;
wire stuffer_flush_out;
wire [31:0] escape_do32;
wire [1:0] escape_bytes;
wire escape_dv;
wire escape_flush_out;
huffman_snglclk huffman_snglclk_i (
.xclk (xclk), // input
.rst (~en_huffman), // input
.mclk (mclk), // input
.tser_we (tser_we), // input
.tser_a_not_d (tser_a_not_d), // input
.tser_d (tser_d), // input[7:0]
.di (di), // input[15:0]
.ds (ds), // input
.do27 (huffman_do27), // output[26:0]
.dl (huffman_dl), // output[4:0]
.dv (huffman_dv), // output
.flush (huffman_flush), // output
.last_block (huffman_last_block), // output
`ifdef DEBUG_RING
.test_lbw (test_lbw),
.gotLastBlock (gotLastBlock), // last block done - flush the rest bits
`else
.test_lbw (),
.gotLastBlock (), // last block done - flush the rest bits
`endif
.clk_flush (clk_flush), // input
.flush_clk (flush_clk), // output
.fifo_or_full() // output
);
bit_stuffer_27_32 #(
.DIN_LEN(27)
) bit_stuffer_27_32_i (
.xclk (xclk), // input
.rst (~en_huffman), // input
.din (huffman_do27), // input[26:0]
.dlen (huffman_dl), // input[4:0]
.ds (huffman_dv), // input
.flush_in (huffman_flush), // input
.d_out (stuffer_do32), // output[31:0]
.bytes_out (stuffer_bytes), // output[1:0] reg
.dv (stuffer_dv), // output reg
.flush_out (stuffer_flush_out) // output reg
);
bit_stuffer_escape bit_stuffer_escape_i (
.xclk (xclk), // input
.rst (~en_huffman), // input
.din (stuffer_do32), // input[31:0]
.bytes_in (stuffer_bytes), // input[1:0]
.in_stb (stuffer_dv), // input
.flush_in (stuffer_flush_out), // input
.d_out (escape_do32), // output[31:0] reg
.bytes_out (escape_bytes), // output[1:0] reg
.dv (escape_dv), // output reg
.flush_out (escape_flush_out) // output reg
);
// TODO: Insert raw data here, always 4x bytes (actually 16*16*(1..2))
bit_stuffer_raw_metadata bit_stuffer_metadata_i (
.mclk (mclk), // input
.mrst (mrst), // input
.xclk (xclk), // input
.xrst (~en_stuffer), // input
.last_block (huffman_last_block), // input TODO: leading edge is needed for raw (to xfer timestamp) - not anymore
.ts_pre_stb (ts_pre_stb), // input
.ts_data (ts_data), // input[7:0]
.color_first (color_first), // input
.din (escape_do32), // input[31:0]
.bytes_in (escape_bytes), // input[1:0]
.in_stb (escape_dv), // input
.flush (escape_flush_out), // input
.abort (abort_stuffer), // input
.compressed_mode(compressed_mode), // input
.raw_mode (raw_mode), // input
.raw_be16 (raw_be16), // input
.raw_bytes (raw_bytes), // input[7:0]
.raw_start (raw_start), // input
.raw_prefb (raw_prefb), // input
.raw_ts_copy (raw_ts_copy), // input
.raw_flush (raw_flush), // input
.data_out (data_out), // output[31:0] reg
.data_out_valid (data_out_valid), // output reg
.done (done), // output reg
.running (running) // output reg
`ifdef DEBUG_RING
,.dbg_etrax_dma (dbg_etrax_dma), // output[3:0] reg
.dbg_ts_rstb (dbg_ts_rstb), // output
.dbg_ts_dout (dbg_ts_dout) // output[7:0]
`endif
);
endmodule
...@@ -72,6 +72,8 @@ module jp_channel#( ...@@ -72,6 +72,8 @@ module jp_channel#(
parameter CMPRS_CBIT_CMODE_BITS = 4, // number of bits to control compressor color modes parameter CMPRS_CBIT_CMODE_BITS = 4, // number of bits to control compressor color modes
parameter CMPRS_CBIT_FRAMES = 15, // bit # to control compressor multi/single frame buffer modes parameter CMPRS_CBIT_FRAMES = 15, // bit # to control compressor multi/single frame buffer modes
parameter CMPRS_CBIT_FRAMES_BITS = 1, // number of bits to control compressor multi/single frame buffer modes parameter CMPRS_CBIT_FRAMES_BITS = 1, // number of bits to control compressor multi/single frame buffer modes
parameter CMPRS_CBIT_BE16 = 17, // bit # to control compressor multi/single frame buffer modes
parameter CMPRS_CBIT_BE16_BITS = 1, // number of bits to control compressor multi/single frame buffer modes
parameter CMPRS_CBIT_BAYER = 20, // bit # to control compressor Bayer shift mode parameter CMPRS_CBIT_BAYER = 20, // bit # to control compressor Bayer shift mode
parameter CMPRS_CBIT_BAYER_BITS = 2, // number of bits to control compressor Bayer shift mode parameter CMPRS_CBIT_BAYER_BITS = 2, // number of bits to control compressor Bayer shift mode
parameter CMPRS_CBIT_FOCUS = 23, // bit # to control compressor focus display mode parameter CMPRS_CBIT_FOCUS = 23, // bit # to control compressor focus display mode
...@@ -94,6 +96,8 @@ module jp_channel#( ...@@ -94,6 +96,8 @@ module jp_channel#(
parameter CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2 = 4'ha, // jp4, 4 blocks, differential, hdr,divide by 2 parameter CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2 = 4'ha, // jp4, 4 blocks, differential, hdr,divide by 2
parameter CMPRS_CBIT_CMODE_MONO1 = 4'hb, // mono JPEG (not yet implemented) parameter CMPRS_CBIT_CMODE_MONO1 = 4'hb, // mono JPEG (not yet implemented)
parameter CMPRS_CBIT_CMODE_MONO4 = 4'he, // mono 4 blocks parameter CMPRS_CBIT_CMODE_MONO4 = 4'he, // mono 4 blocks
parameter CMPRS_CBIT_CMODE_RAW = 4'hf, // uncompressed
parameter CMPRS_CBIT_FRAMES_SINGLE = 0, //1, // use a single-frame buffer for images parameter CMPRS_CBIT_FRAMES_SINGLE = 0, //1, // use a single-frame buffer for images
parameter CMPRS_COLOR18 = 0, // JPEG 4:2:0 with 18x18 overlapping tiles for de-bayer parameter CMPRS_COLOR18 = 0, // JPEG 4:2:0 with 18x18 overlapping tiles for de-bayer
...@@ -101,8 +105,12 @@ module jp_channel#( ...@@ -101,8 +105,12 @@ module jp_channel#(
parameter CMPRS_MONO16 = 2, // JPEG 4:2:0 with 16x16 non-overlapping tiles, color components zeroed parameter CMPRS_MONO16 = 2, // JPEG 4:2:0 with 16x16 non-overlapping tiles, color components zeroed
parameter CMPRS_JP4 = 3, // JP4 mode with 16x16 macroblocks parameter CMPRS_JP4 = 3, // JP4 mode with 16x16 macroblocks
parameter CMPRS_JP4DIFF = 4, // JP4DIFF mode TODO: see if correct parameter CMPRS_JP4DIFF = 4, // JP4DIFF mode TODO: see if correct
parameter CMPRS_RAW = 6, // Not comressed, raw data
parameter CMPRS_MONO8 = 7, // Regular JPEG monochrome with 8x8 macroblocks (not yet implemented) parameter CMPRS_MONO8 = 7, // Regular JPEG monochrome with 8x8 macroblocks (not yet implemented)
// TODO: For raw - use:
// 13 bits hor (x16 bytes), 13 bits vert (x16 lines) + 5 bits (left margin in bytes, skip)
// lines per page?
parameter CMPRS_FRMT_MBCM1 = 0, // bit # of number of macroblock columns minus 1 field in format word parameter CMPRS_FRMT_MBCM1 = 0, // bit # of number of macroblock columns minus 1 field in format word
parameter CMPRS_FRMT_MBCM1_BITS = 13, // number of bits in number of macroblock columns minus 1 field in format word parameter CMPRS_FRMT_MBCM1_BITS = 13, // number of bits in number of macroblock columns minus 1 field in format word
parameter CMPRS_FRMT_MBRM1 = 13, // bit # of number of macroblock rows minus 1 field in format word parameter CMPRS_FRMT_MBRM1 = 13, // bit # of number of macroblock rows minus 1 field in format word
...@@ -143,14 +151,12 @@ module jp_channel#( ...@@ -143,14 +151,12 @@ module jp_channel#(
// Buffer interface (buffer to be a part of the memory controller - it is connected there by a 64-bit data, here - by an 9-bit one // Buffer interface (buffer to be a part of the memory controller - it is connected there by a 64-bit data, here - by an 9-bit one
input xfer_reset_page_rd, // from mcntrl_tiled_rw ( input xfer_reset_page_rd, // from mcntrl_tiled_rw (
input buf_wpage_nxt, // advance to next page memory interface writes to input buf_wpage_nxt, // advance to next page memory interface writes to
input buf_we, // @!mclk write buffer from memory, increment write input buf_we, // @!mclk write buffer from memory, increment write
input [63:0] buf_din, // data out input [63:0] buf_din, // data out
input page_ready_chn, // single mclk (posedge) input page_ready_chn, // single mclk (posedge)
output next_page_chn, // single mclk (posedge): Done with the page in the buffer, memory controller may read more data output next_page_chn, // single mclk (posedge): Done with the page in the buffer, memory controller may read more data
// Master(sensor)/slave(compressor) synchronization signals // Master(sensor)/slave(compressor) synchronization signals
output frame_start_dst, // @mclk - trigger receive (tiledc) memory channel (it will take care of single/repetitive output frame_start_dst, // @mclk - trigger receive (tiledc) memory channel (it will take care of single/repetitive
// this output either follows vsync_late (reclocks it) or generated in non-bonded mode // this output either follows vsync_late (reclocks it) or generated in non-bonded mode
...@@ -222,10 +228,13 @@ module jp_channel#( ...@@ -222,10 +228,13 @@ module jp_channel#(
// Control signals to be defined // Control signals to be defined
wire frame_en; // if 0 - will reset logic immediately (but not page number) wire frame_en; // if 0 - will reset logic immediately (but not page number)
wire frame_en_jp; // if 0 - will reset logic immediately (but not page number)
wire frame_en_raw; // if 0 - will reset logic immediately (but not page number)
wire frame_start_xclk; // re-clocked, parameters are copied at this pulse wire frame_start_xclk; // re-clocked, parameters are copied at this pulse
wire stuffer_en; // extended enable to allow stuffer to gracefully finish wire stuffer_en; // extended enable to allow stuffer to gracefully finish
wire frame_go=frame_en; // start frame: if idle, will start reading data (if available), wire frame_go_jp=frame_en_jp; // start frame: if idle, will start reading data (if available),
wire frame_go_raw=frame_en_raw; // start frame: if idle, will start reading data (if available),
// if running - will not restart a new frame if 0. // if running - will not restart a new frame if 0.
wire [CMPRS_FRMT_LMARG_BITS-1:0] left_marg; // left margin (for not-yet-implemented) mono JPEG (8 lines tile row) can need 7 bits (mod 32 - tile) wire [CMPRS_FRMT_LMARG_BITS-1:0] left_marg; // left margin (for not-yet-implemented) mono JPEG (8 lines tile row) can need 7 bits (mod 32 - tile)
wire [CMPRS_FRMT_MBCM1_BITS-1:0] n_blocks_in_row_m1; // number of macroblocks in a macroblock row minus 1 wire [CMPRS_FRMT_MBCM1_BITS-1:0] n_blocks_in_row_m1; // number of macroblocks in a macroblock row minus 1
...@@ -267,11 +276,14 @@ module jp_channel#( ...@@ -267,11 +276,14 @@ module jp_channel#(
wire last_mb; // output wire last_mb; // output
// signals connecting modules: cmprs_pixel_buf_iface_i and chn_rd_buf_i: // signals connecting modules: cmprs_pixel_buf_iface_i and chn_rd_buf_i:
// wire [ 7:0] buf_di; // data from the buffer
// wire [11:0] buf_ra; // buffer read address (2 MSB - page number)
wire [ 1:0] buf_rd; // buf {regen, re} wire [ 1:0] buf_rd; // buf {regen, re}
wire [ 7:0] buf_pxd; // 8-bit pixel data from the memory buffer wire [ 7:0] buf_pxd; // 8-bit pixel data from the memory buffer
wire [11:0] buf_ra; // Memory buffer read address wire [11:0] buf_ra; // Memory buffer read address
wire [ 1:0] raw_buf_rd; // buf {regen, re} in raw mode
wire [11:0] raw_buf_ra; // Memory buffer read address in raw mode
// signals connecting modules: chn_rd_buf_i and ???: // signals connecting modules: chn_rd_buf_i and ???:
wire [ 7:0] mb_data_out; // Macroblock data out in scanline order wire [ 7:0] mb_data_out; // Macroblock data out in scanline order
wire mb_pre_first_out; // Macroblock data out strobe - 1 cycle just before data valid wire mb_pre_first_out; // Macroblock data out strobe - 1 cycle just before data valid
...@@ -370,12 +382,27 @@ module jp_channel#( ...@@ -370,12 +382,27 @@ module jp_channel#(
wire [15:0] quant_dc_tdo;// MSB aligned coefficient for the DC component (used in focus module) wire [15:0] quant_dc_tdo;// MSB aligned coefficient for the DC component (used in focus module)
wire [ 2:0] cmprs_qpage; wire [ 2:0] cmprs_qpage;
wire [ 2:0] coring_num; wire [ 2:0] coring_num;
wire compressed;
wire uncompressed;
wire raw_be16; // raw bytes in little-endian order need to be converted to big endian 16-bit ones
wire raw_start; // input
wire raw_prefb; // input
wire raw_ts_copy; // input
wire raw_flush; // input
reg dcc_en; reg dcc_en;
wire [15:0] dccdata; // was not used in late nc353 wire [15:0] dccdata; // was not used in late nc353
wire dccvld; // was not used in late nc353 wire dccvld; // was not used in late nc353
wire next_page_chn_jp;
wire next_page_chn_raw;
assign next_page_chn = next_page_chn_jp | next_page_chn_raw;
assign set_ctrl_reg_w = cmd_we && (cmd_a== CMPRS_CONTROL_REG); assign set_ctrl_reg_w = cmd_we && (cmd_a== CMPRS_CONTROL_REG);
assign set_status_w = cmd_we && (cmd_a== CMPRS_STATUS_CNTRL); assign set_status_w = cmd_we && (cmd_a== CMPRS_STATUS_CNTRL);
assign set_format_w = cmd_we && (cmd_a== CMPRS_FORMAT); assign set_format_w = cmd_we && (cmd_a== CMPRS_FORMAT);
...@@ -385,11 +412,6 @@ module jp_channel#( ...@@ -385,11 +412,6 @@ module jp_channel#(
assign set_tables_w = cmd_we && ((cmd_a & 6)== CMPRS_TABLES); assign set_tables_w = cmd_we && ((cmd_a & 6)== CMPRS_TABLES);
`ifdef USE_XCLK2X
// re-sync to posedge xclk2x
reg xrst2xn;
always @ (negedge xclk2x) xrst2xn <= xrst;
`endif
`ifdef DEBUG_RING `ifdef DEBUG_RING
`ifndef USE_XCLK2X `ifndef USE_XCLK2X
...@@ -456,11 +478,7 @@ module jp_channel#( ...@@ -456,11 +478,7 @@ module jp_channel#(
`endif `endif
timestamp_to_parallel dbg_timestamp_to_parallel_i ( timestamp_to_parallel dbg_timestamp_to_parallel_i (
`ifdef USE_XCLK2X
.clk (~xclk2x), // input
`else
.clk (xclk), // input .clk (xclk), // input
`endif
.pre_stb (dbg_ts_rstb), // input .pre_stb (dbg_ts_rstb), // input
.tdata (dbg_ts_dout), // input[7:0] .tdata (dbg_ts_dout), // input[7:0]
.sec (dbg_sec), // output[31:0] reg .sec (dbg_sec), // output[31:0] reg
...@@ -470,11 +488,7 @@ module jp_channel#( ...@@ -470,11 +488,7 @@ module jp_channel#(
// cmprs_standalone - use to reset flush // cmprs_standalone - use to reset flush
`ifdef USE_XCLK2X
always @ (posedge ~xclk2x) begin
`else
always @ (posedge xclk) begin always @ (posedge xclk) begin
`endif
dbg_reset_fifo <= fifo_rst; dbg_reset_fifo <= fifo_rst;
if (xrst2xn || dbg_reset_fifo) debug_fifo_in <= 0; if (xrst2xn || dbg_reset_fifo) debug_fifo_in <= 0;
else if (stuffer_dv) debug_fifo_in <= debug_fifo_in + 1; else if (stuffer_dv) debug_fifo_in <= debug_fifo_in + 1;
...@@ -514,8 +528,8 @@ module jp_channel#( ...@@ -514,8 +528,8 @@ module jp_channel#(
else if (stuffer_running_mclk) dbg_stuffer_ext_running <= 1; else if (stuffer_running_mclk) dbg_stuffer_ext_running <= 1;
end end
/// Just for debugging, keeping in both compressed/raw modes
always @ (posedge xclk) begin always @ (posedge xclk) begin
if (!frame_en) pre_start_cntr <= 0; if (!frame_en) pre_start_cntr <= 0;
else if (mb_pre_start) pre_start_cntr <= pre_start_cntr + 1; else if (mb_pre_start) pre_start_cntr <= pre_start_cntr + 1;
...@@ -656,11 +670,11 @@ module jp_channel#( ...@@ -656,11 +670,11 @@ module jp_channel#(
.LOG2WIDTH_RD(3) // 64 bit external interface .LOG2WIDTH_RD(3) // 64 bit external interface
) chn_rd_buf_i ( ) chn_rd_buf_i (
.ext_clk (xclk), // input .ext_clk (xclk), // input
.ext_raddr (buf_ra), // input[11:0] .ext_raddr (uncompressed?raw_buf_ra: buf_ra), // input[11:0]
.ext_rd (buf_rd[0]), // input .ext_rd (uncompressed?raw_buf_rd[0]: buf_rd[0]), // input
.ext_regen (buf_rd[1]), // input .ext_regen (uncompressed?raw_buf_rd[1] :buf_rd[1]), // input
.ext_data_out (buf_pxd), // output[7:0] .ext_data_out (buf_pxd), // output[7:0]
// .emul64 (1'b0), //emul64), // input Modify buffer addresses (used for JP4 until a 64-wide mode is implemented) // Memory interface
.wclk (!mclk), // input .wclk (!mclk), // input
.wpage_in (2'b0), // input[1:0] .wpage_in (2'b0), // input[1:0]
.wpage_set (xfer_reset_page_rd), // input TODO: Generate @ negedge mclk on frame start .wpage_set (xfer_reset_page_rd), // input TODO: Generate @ negedge mclk on frame start
...@@ -681,6 +695,8 @@ module jp_channel#( ...@@ -681,6 +695,8 @@ module jp_channel#(
.CMPRS_CBIT_CMODE_BITS (CMPRS_CBIT_CMODE_BITS), .CMPRS_CBIT_CMODE_BITS (CMPRS_CBIT_CMODE_BITS),
.CMPRS_CBIT_FRAMES (CMPRS_CBIT_FRAMES), .CMPRS_CBIT_FRAMES (CMPRS_CBIT_FRAMES),
.CMPRS_CBIT_FRAMES_BITS (CMPRS_CBIT_FRAMES_BITS), .CMPRS_CBIT_FRAMES_BITS (CMPRS_CBIT_FRAMES_BITS),
.CMPRS_CBIT_BE16 (CMPRS_CBIT_BE16),
.CMPRS_CBIT_BE16_BITS (CMPRS_CBIT_BE16_BITS),
.CMPRS_CBIT_BAYER (CMPRS_CBIT_BAYER), .CMPRS_CBIT_BAYER (CMPRS_CBIT_BAYER),
.CMPRS_CBIT_BAYER_BITS (CMPRS_CBIT_BAYER_BITS), .CMPRS_CBIT_BAYER_BITS (CMPRS_CBIT_BAYER_BITS),
.CMPRS_CBIT_FOCUS (CMPRS_CBIT_FOCUS), .CMPRS_CBIT_FOCUS (CMPRS_CBIT_FOCUS),
...@@ -701,12 +717,14 @@ module jp_channel#( ...@@ -701,12 +717,14 @@ module jp_channel#(
.CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2 (CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2), .CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2 (CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2),
.CMPRS_CBIT_CMODE_MONO1 (CMPRS_CBIT_CMODE_MONO1), .CMPRS_CBIT_CMODE_MONO1 (CMPRS_CBIT_CMODE_MONO1),
.CMPRS_CBIT_CMODE_MONO4 (CMPRS_CBIT_CMODE_MONO4), .CMPRS_CBIT_CMODE_MONO4 (CMPRS_CBIT_CMODE_MONO4),
.CMPRS_CBIT_CMODE_RAW (CMPRS_CBIT_CMODE_RAW),
.CMPRS_CBIT_FRAMES_SINGLE (CMPRS_CBIT_FRAMES_SINGLE), .CMPRS_CBIT_FRAMES_SINGLE (CMPRS_CBIT_FRAMES_SINGLE),
.CMPRS_COLOR18 (CMPRS_COLOR18), .CMPRS_COLOR18 (CMPRS_COLOR18),
.CMPRS_COLOR20 (CMPRS_COLOR20), .CMPRS_COLOR20 (CMPRS_COLOR20),
.CMPRS_MONO16 (CMPRS_MONO16), .CMPRS_MONO16 (CMPRS_MONO16),
.CMPRS_JP4 (CMPRS_JP4), .CMPRS_JP4 (CMPRS_JP4),
.CMPRS_JP4DIFF (CMPRS_JP4DIFF), .CMPRS_JP4DIFF (CMPRS_JP4DIFF),
.CMPRS_RAW (CMPRS_RAW),
.CMPRS_MONO8 (CMPRS_MONO8), .CMPRS_MONO8 (CMPRS_MONO8),
.CMPRS_FRMT_MBCM1 (CMPRS_FRMT_MBCM1), .CMPRS_FRMT_MBCM1 (CMPRS_FRMT_MBCM1),
.CMPRS_FRMT_MBCM1_BITS (CMPRS_FRMT_MBCM1_BITS), .CMPRS_FRMT_MBCM1_BITS (CMPRS_FRMT_MBCM1_BITS),
...@@ -720,7 +738,6 @@ module jp_channel#( ...@@ -720,7 +738,6 @@ module jp_channel#(
.CMPRS_CSAT_CR_BITS (CMPRS_CSAT_CR_BITS), .CMPRS_CSAT_CR_BITS (CMPRS_CSAT_CR_BITS),
.CMPRS_CORING_BITS (CMPRS_CORING_BITS) .CMPRS_CORING_BITS (CMPRS_CORING_BITS)
) cmprs_cmd_decode_i ( ) cmprs_cmd_decode_i (
// .rst (rst), // input
.xclk (xclk), // input - global clock input, compressor single clock rate .xclk (xclk), // input - global clock input, compressor single clock rate
.mclk (mclk), // input - global system/memory clock .mclk (mclk), // input - global system/memory clock
.mrst (mrst), // input .mrst (mrst), // input
...@@ -729,22 +746,23 @@ module jp_channel#( ...@@ -729,22 +746,23 @@ module jp_channel#(
.color_sat_we (set_color_saturation_w), // input - write color saturation values .color_sat_we (set_color_saturation_w), // input - write color saturation values
.coring_we (set_coring_w), // input - write color saturation values .coring_we (set_coring_w), // input - write color saturation values
.di (cmd_data), // input[31:0] - 32-bit data to write to control register (24LSB are used) .di (cmd_data), // input[31:0] - 32-bit data to write to control register (24LSB are used)
// .frame_start (frame_start_dst), // input @mclk
.frame_start (frame_start_conf), // input @mclk .frame_start (frame_start_conf), // input @mclk
.frame_start_xclk (frame_start_xclk), // output re-clocked, parameters are copied during this pulse .frame_start_xclk (frame_start_xclk), // output re-clocked, parameters are copied during this pulse
.cmprs_en_mclk (cmprs_en_mclk), // output .cmprs_en_mclk (cmprs_en_mclk), // output
.cmprs_en_extend (cmprs_en_extend), // input .cmprs_en_extend (cmprs_en_extend), // input
.compressor_running (reading_frame || stuffer_running), // input
.cmprs_run_mclk (cmprs_run_mclk), // output reg .cmprs_run_mclk (cmprs_run_mclk), // output reg
.cmprs_standalone (cmprs_standalone), // output reg .cmprs_standalone (cmprs_standalone), // output reg
.sigle_frame_buf (sigle_frame_buf), // output reg .sigle_frame_buf (sigle_frame_buf), // output reg
.cmprs_en_xclk (frame_en), // output reg .cmprs_en_xclk (frame_en), // output reg
.cmprs_en_xclk_jp (frame_en_jp), // output reg
.cmprs_en_xclk_raw (frame_en_raw), // output reg
.cmprs_en_late_xclk (stuffer_en), // output reg - extended enable to allow stuffer to gracefully finish .cmprs_en_late_xclk (stuffer_en), // output reg - extended enable to allow stuffer to gracefully finish
.cmprs_qpage (cmprs_qpage), // output[2:0] reg .cmprs_qpage (cmprs_qpage), // output[2:0] reg
.cmprs_dcsub (subtract_dc), // output reg .cmprs_dcsub (subtract_dc), // output reg
.cmprs_fmode (cmprs_fmode), // output[1:0] reg .cmprs_fmode (cmprs_fmode), // output[1:0] reg
.bayer_shift (bayer_phase), // output[1:0] reg .bayer_shift (bayer_phase), // output[1:0] reg
.ignore_color (ignore_color), // output reg .ignore_color (ignore_color), // output reg
// .four_blocks (four_blocks), // output reg Not used?
.four_blocks (), // output reg Not used? .four_blocks (), // output reg Not used?
.jp4_dc_improved (jp4_dc_improved), // output reg .jp4_dc_improved (jp4_dc_improved), // output reg
.converter_type (converter_type), // output[2:0] reg .converter_type (converter_type), // output[2:0] reg
...@@ -755,7 +773,10 @@ module jp_channel#( ...@@ -755,7 +773,10 @@ module jp_channel#(
.n_block_rows_m1 (n_block_rows_m1), // output[12:0] reg .n_block_rows_m1 (n_block_rows_m1), // output[12:0] reg
.color_sat_cb (m_cb), // output[9:0] reg .color_sat_cb (m_cb), // output[9:0] reg
.color_sat_cr (m_cr), // output[9:0] reg .color_sat_cr (m_cr), // output[9:0] reg
.coring (coring_num) // output[2:0] reg .coring (coring_num), // output[2:0] reg
.compressed (compressed), // output reg
.uncompressed (uncompressed), // output reg
.be16 (raw_be16) // output reg
); );
// set derived parameters from converter_type // set derived parameters from converter_type
...@@ -783,7 +804,6 @@ module jp_channel#( ...@@ -783,7 +804,6 @@ module jp_channel#(
.CMPRS_TIMEOUT_BITS (CMPRS_TIMEOUT_BITS), .CMPRS_TIMEOUT_BITS (CMPRS_TIMEOUT_BITS),
.CMPRS_TIMEOUT (CMPRS_TIMEOUT) .CMPRS_TIMEOUT (CMPRS_TIMEOUT)
) cmprs_frame_sync_i ( ) cmprs_frame_sync_i (
// .rst (rst), // input
.xclk (xclk), // input - global clock input, compressor single clock rate .xclk (xclk), // input - global clock input, compressor single clock rate
.mclk (mclk), // input - global system/memory clock .mclk (mclk), // input - global system/memory clock
.mrst (mrst), // input .mrst (mrst), // input
...@@ -814,25 +834,25 @@ module jp_channel#( ...@@ -814,25 +834,25 @@ module jp_channel#(
.frame_done (frame_done_dst), // input - single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory .frame_done (frame_done_dst), // input - single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory
.last_mb_started (last_mb && mb_pre2_first_out), // input .last_mb_started (last_mb && mb_pre2_first_out), // input
.suspend (suspend), // output reg - suspend reading data for this channel - waiting for the source data .suspend (suspend), // output reg - suspend reading data for this channel - waiting for the source data
.stuffer_running (stuffer_running), // input .stuffer_running (stuffer_running), // input
.force_flush_long (force_flush_long), // output reg - @ mclk tried to start frame compression before the previous one was finished .force_flush_long (force_flush_long), // output reg - @ mclk tried to start frame compression before the previous one was finished, raw also
.stuffer_running_mclk(stuffer_running_mclk), // output .stuffer_running_mclk(stuffer_running_mclk), // output
.reading_frame (reading_frame), // output .reading_frame (reading_frame), // output
.frame_started_mclk (frame_started_mclk) .frame_started_mclk (frame_started_mclk)
); );
cmprs_macroblock_buf_iface cmprs_macroblock_buf_iface_i ( cmprs_macroblock_buf_iface cmprs_macroblock_buf_iface_i (
// .rst (rst), // input
.xclk (xclk), // input .xclk (xclk), // input
.mclk (mclk), // input .mclk (mclk), // input
.mrst (mrst), // input .mrst (mrst), // input
.xrst (xrst), // input .xrst (xrst), // input
.xfer_reset_page_rd (xfer_reset_page_rd), // input .xfer_reset_page_rd (xfer_reset_page_rd), // input
.page_ready_chn (page_ready_chn), // input .page_ready_chn (page_ready_chn), // input
.next_page_chn (next_page_chn), // output .next_page_chn (next_page_chn_jp), // output
.frame_en (frame_en), // input .frame_en (frame_en_jp), // input
.frame_start_xclk (frame_start_xclk), // input@posedge xclk - parameters are copied @ this pulse .frame_start_xclk (frame_start_xclk), // input@posedge xclk - parameters are copied @ this pulse
.frame_go (frame_go), // input - do not use - assign to frame_en? Running frames can be controlled by other means .frame_go (frame_go_jp), // input - do not use - assign to frame_en? Running frames can be controlled by other means
.cmprs_run_mclk (cmprs_run_mclk), // input used to reset frame_pre_run (enable vsync_late for the new frame after stop) .cmprs_run_mclk (cmprs_run_mclk), // input used to reset frame_pre_run (enable vsync_late for the new frame after stop)
.left_marg (left_marg), // input[4:0] .left_marg (left_marg), // input[4:0]
.n_blocks_in_row_m1 (n_blocks_in_row_m1), // input[12:0] .n_blocks_in_row_m1 (n_blocks_in_row_m1), // input[12:0]
...@@ -853,6 +873,32 @@ module jp_channel#( ...@@ -853,6 +873,32 @@ module jp_channel#(
`endif `endif
); );
cmprs_raw_buf_iface #(
.FRAME_QUEUE_WIDTH(2)
) cmprs_raw_buf_iface_i (
.xclk (xclk), // input
.mclk (mclk), // input
.mrst (mrst), // input
.xrst (xrst), // input
.xfer_reset_page_rd (xfer_reset_page_rd), // input
.page_ready_chn (page_ready_chn), // input
.next_page_chn (next_page_chn_raw), // output
.frame_en (frame_en_raw), // input
.frame_start_xclk (frame_start_xclk), // input
.frame_go (frame_go_raw), // input
.cmprs_run_mclk (cmprs_run_mclk), // input
.n_blocks_in_row_m1 (n_blocks_in_row_m1), // input[12:0]
.n_block_rows_m1 (n_block_rows_m1), // input[12:0]
.stuffer_running (stuffer_running), // input
.raw_be16 (raw_be16), // input
.buf_ra (raw_buf_ra), // output[11:0]
.buf_rd (raw_buf_rd), // output[1:0]
.raw_start (raw_start), // output
.raw_prefb (raw_prefb), // output
.raw_ts_copy (raw_ts_copy), // output
.raw_flush (raw_flush) // output
);
cmprs_pixel_buf_iface #( cmprs_pixel_buf_iface #(
.CMPRS_PREEND_EARLY (6), // TODO:Check / Adjust .CMPRS_PREEND_EARLY (6), // TODO:Check / Adjust
.CMPRS_RELEASE_EARLY (16), .CMPRS_RELEASE_EARLY (16),
...@@ -866,7 +912,7 @@ module jp_channel#( ...@@ -866,7 +912,7 @@ module jp_channel#(
) cmprs_pixel_buf_iface_i ( ) cmprs_pixel_buf_iface_i (
.xclk (xclk), // input .xclk (xclk), // input
.frame_en (frame_en), // input .frame_en (frame_en_jp), // input
.buf_di (buf_pxd), // input[7:0] .buf_di (buf_pxd), // input[7:0]
.buf_ra (buf_ra), // output[11:0] .buf_ra (buf_ra), // output[11:0]
.buf_rd (buf_rd), // output[1:0] .buf_rd (buf_rd), // output[1:0]
...@@ -882,7 +928,6 @@ module jp_channel#( ...@@ -882,7 +928,6 @@ module jp_channel#(
.macroblock_x (macroblock_x), // input[6:0] .macroblock_x (macroblock_x), // input[6:0]
.data_out (mb_data_out), // output[7:0] // Macroblock data out in scanline order .data_out (mb_data_out), // output[7:0] // Macroblock data out in scanline order
.pre_first_out (mb_pre_first_out), // output // Macroblock data out strobe - 1 cycle just before data valid == old pre_first_pixel? .pre_first_out (mb_pre_first_out), // output // Macroblock data out strobe - 1 cycle just before data valid == old pre_first_pixel?
// .data_valid (mb_data_valid) // output // Macroblock data out valid
.pre2_first_out (mb_pre2_first_out), // output reg .pre2_first_out (mb_pre2_first_out), // output reg
.data_valid () // output reg // Macroblock data out valid Unused .data_valid () // output reg // Macroblock data out valid Unused
); );
...@@ -896,7 +941,7 @@ module jp_channel#( ...@@ -896,7 +941,7 @@ module jp_channel#(
.CMPRS_MONO8 (CMPRS_MONO8) .CMPRS_MONO8 (CMPRS_MONO8)
) csconvert_i ( ) csconvert_i (
.xclk (xclk), // input .xclk (xclk), // input
.frame_en (frame_en), // input .frame_en (frame_en_jp), // input
.converter_type (converter_type), // input[2:0] .converter_type (converter_type), // input[2:0]
.ignore_color (ignore_color), // input .ignore_color (ignore_color), // input
.scale_diff (scale_diff), // input .scale_diff (scale_diff), // input
...@@ -928,7 +973,7 @@ module jp_channel#( ...@@ -928,7 +973,7 @@ module jp_channel#(
.CMPRS_MONO8 (CMPRS_MONO8) .CMPRS_MONO8 (CMPRS_MONO8)
) cmprs_buf_average_i ( ) cmprs_buf_average_i (
.xclk (xclk), // input .xclk (xclk), // input
.frame_en (frame_en), // input .frame_en (frame_en_jp), // input
.converter_type (converter_type), // input[2:0] .converter_type (converter_type), // input[2:0]
.pre_first_in (mb_pre_first_out), // input .pre_first_in (mb_pre_first_out), // input
.yc_pre_first_out (yc_pre_first_out), // input .yc_pre_first_out (yc_pre_first_out), // input
...@@ -944,7 +989,7 @@ module jp_channel#( ...@@ -944,7 +989,7 @@ module jp_channel#(
.caddrw (caddrw), // input[7:0] .caddrw (caddrw), // input[7:0]
.cwe (cwe), // input .cwe (cwe), // input
.signed_c (signed_c), // input[8:0] .signed_c (signed_c), // input[8:0]
.do (yc_nodc), // output[9:0] .dout (yc_nodc), // output[9:0]
.avr (yc_avr), // output[8:0] .avr (yc_avr), // output[8:0]
// .dv (yc_nodc_dv), // output // .dv (yc_nodc_dv), // output
.dv (), // output unused? .dv (), // output unused?
...@@ -1011,7 +1056,7 @@ module jp_channel#( ...@@ -1011,7 +1056,7 @@ module jp_channel#(
.DSP_P_WIDTH (48) .DSP_P_WIDTH (48)
) dct2d8x8_chen_i ( ) dct2d8x8_chen_i (
.clk (xclk), // input .clk (xclk), // input
.rst (!frame_en), // input .rst (!frame_en_jp), // input
.start (dct_start), // input .start (dct_start), // input
.xin (yc_nodc), // input[9:0] signed .xin (yc_nodc), // input[9:0] signed
.last_in (dct_last_in), // output reg .last_in (dct_last_in), // output reg
...@@ -1064,7 +1109,7 @@ module jp_channel#( ...@@ -1064,7 +1109,7 @@ module jp_channel#(
quantizer393 quantizer393_i ( quantizer393 quantizer393_i (
.clk (xclk), // input .clk (xclk), // input
.en (frame_en), // input .en (frame_en_jp), // input
.mclk (mclk), // input system clock, twqe, twce, ta,tdi - valid @posedge (ra, tdi - 2 cycles ahead (was negedge) .mclk (mclk), // input system clock, twqe, twce, ta,tdi - valid @posedge (ra, tdi - 2 cycles ahead (was negedge)
.tser_qe (tser_qe), // input - write to a quantization table .tser_qe (tser_qe), // input - write to a quantization table
.tser_ce (tser_ce), // input - write to a coring table .tser_ce (tser_ce), // input - write to a coring table
...@@ -1079,7 +1124,7 @@ module jp_channel#( ...@@ -1079,7 +1124,7 @@ module jp_channel#(
.first_in (first_block_dct), // input - first block in (valid @ start) .first_in (first_block_dct), // input - first block in (valid @ start)
.first_out (first_block_quant), // output reg - valid @ ds .first_out (first_block_quant), // output reg - valid @ ds
.di (dct_out[12:0]), // input[12:0] - pixel data in (signed) .di (dct_out[12:0]), // input[12:0] - pixel data in (signed)
.do (quant_do[12:0]), // output[12:0] - pixel data out (AC is only 9 bits long?) - changed to 10 .dout (quant_do[12:0]), // output[12:0] - pixel data out (AC is only 9 bits long?) - changed to 10
.dv (), // output reg - data out valid .dv (), // output reg - data out valid
.ds (quant_ds), // output reg - data out strobe (one ahead of the start of dv) .ds (quant_ds), // output reg - data out strobe (one ahead of the start of dv)
.dc_tdo (quant_dc_tdo[15:0]), // output[15:0] reg - MSB aligned coefficient for the DC component (used in focus module) .dc_tdo (quant_dc_tdo[15:0]), // output[15:0] reg - MSB aligned coefficient for the DC component (used in focus module)
...@@ -1099,12 +1144,8 @@ module jp_channel#( ...@@ -1099,12 +1144,8 @@ module jp_channel#(
// TODO: Verify focus_sharp393: quantizer output (with strobes) is now 2 cycles later than in 353 (relative to xdct out). Seems to be OK. // TODO: Verify focus_sharp393: quantizer output (with strobes) is now 2 cycles later than in 353 (relative to xdct out). Seems to be OK.
focus_sharp393 focus_sharp393_i ( focus_sharp393 focus_sharp393_i (
.clk (xclk), // input - pixel clock .clk (xclk), // input - pixel clock
`ifdef USE_XCLK2X
.clk2x (xclk2x), // input 2x pixel clock
`else
.clk2x (xclk), // FIXME: fix the module not to use xclk2x .clk2x (xclk), // FIXME: fix the module not to use xclk2x
`endif .en (frame_en_jp), // input
.en (frame_en), // input
.mclk (mclk), // input system clock to write tables .mclk (mclk), // input system clock to write tables
.tser_we (tser_fe), // input - write to a focus sharpness table .tser_we (tser_fe), // input - write to a focus sharpness table
...@@ -1121,33 +1162,21 @@ module jp_channel#( ...@@ -1121,33 +1162,21 @@ module jp_channel#(
.quant_ds (quant_ds), // input quantizator ds .quant_ds (quant_ds), // input quantizator ds
.quant_d (quant_do[12:0]), // input[12:0] quantizator data output .quant_d (quant_do[12:0]), // input[12:0] quantizator data output
.quant_dc_tdo (quant_dc_tdo), // input[15:0] MSB aligned coefficient for the DC component (used in focus module) .quant_dc_tdo (quant_dc_tdo), // input[15:0] MSB aligned coefficient for the DC component (used in focus module)
.do (focus_do[12:0]), // output[12:0] reg pixel data out, make timing ignore (valid 1.5 clk earlier that Quantizer output) .dout (focus_do[12:0]), // output[12:0] reg pixel data out, make timing ignore (valid 1.5 clk earlier that Quantizer output)
.ds (focus_ds), // output reg data out strobe (one ahead of the start of dv) .ds (focus_ds), // output reg data out strobe (one ahead of the start of dv)
.hifreq (hifreq[31:0]) // output[31:0] reg accumulated high frequency components in a frame sub-window .hifreq (hifreq[31:0]) // output[31:0] reg accumulated high frequency components in a frame sub-window
); );
// Format DC components to be output as a mini-frame. Was not used in the late NC353 as the dma1 channel was used for IMU instead of dcc // Format DC components to be output as a mini-frame. Was not used in the late NC353 as the dma1 channel was used for IMU instead of dcc
wire finish_dcc; wire finish_dcc;
`ifdef USE_XCLK2X
wire [15:0] stuffer_do;
`else
wire [31:0] stuffer_do; wire [31:0] stuffer_do;
`endif
wire stuffer_dv; wire stuffer_dv;
wire stuffer_done; wire stuffer_done;
`ifdef USE_XCLK2X
pulse_cross_clock finish_dcc_i (.rst(xrst2xn), .src_clk(~xclk2x), .dst_clk(xclk2x), .in_pulse(stuffer_done), .out_pulse(finish_dcc),.busy());
`else
assign finish_dcc = stuffer_done; assign finish_dcc = stuffer_done;
`endif
dcc_sync393 dcc_sync393_i ( dcc_sync393 dcc_sync393_i (
`ifdef USE_XCLK2X
.sclk (xclk2x), // input
`else
.sclk (xclk), // input .sclk (xclk), // input
`endif
.dcc_en (dcc_en), // input xclk rising, sync with start of the frame .dcc_en (dcc_en), // input xclk rising, sync with start of the frame
.finish_dcc (finish_dcc), // input @ sclk rising .finish_dcc (finish_dcc), // input @ sclk rising
.dcc_vld (dccvld), // input xclk rising .dcc_vld (dccvld), // input xclk rising
...@@ -1161,7 +1190,7 @@ module jp_channel#( ...@@ -1161,7 +1190,7 @@ module jp_channel#(
// encoderDCAC is updated to handle 13-bit signed data instead of the 12-bit. It will limit the values on ot's own // encoderDCAC is updated to handle 13-bit signed data instead of the 12-bit. It will limit the values on ot's own
encoderDCAC393 encoderDCAC393_i ( encoderDCAC393 encoderDCAC393_i (
.clk (xclk), // input .clk (xclk), // input
.en (frame_en), // input .en (frame_en_jp), // input
.lasti (color_last), // input - was "last MCU in a frame" (@ stb) .lasti (color_last), // input - was "last MCU in a frame" (@ stb)
.first_blocki (first_block_color), // input - first block in frame - save fifo write address (@ stb) .first_blocki (first_block_color), // input - first block in frame - save fifo write address (@ stb)
.comp_numberi (component_num[2:0]), // input[2:0] - component number 0..2 in color, 0..3 - in jp4diff, >= 4 - don't use (@ stb) .comp_numberi (component_num[2:0]), // input[2:0] - component number 0..2 in color, 0..3 - in jp4diff, >= 4 - don't use (@ stb)
...@@ -1177,7 +1206,7 @@ module jp_channel#( ...@@ -1177,7 +1206,7 @@ module jp_channel#(
`else `else
.last (), // output reg - not used .last (), // output reg - not used
`endif `endif
.do (enc_do[15:0]), // output[15:0] reg .dout (enc_do[15:0]), // output[15:0] reg
.dv (enc_dv) // output reg .dv (enc_dv) // output reg
`ifdef DEBUG_RING `ifdef DEBUG_RING
,.comp_lastinmbo (dbg_comp_lastinmbo) ,.comp_lastinmbo (dbg_comp_lastinmbo)
...@@ -1195,141 +1224,12 @@ module jp_channel#( ...@@ -1195,141 +1224,12 @@ module jp_channel#(
// wire [2:0] dbg_block_mem_wa; // wire [2:0] dbg_block_mem_wa;
// wire [2:0] dbg_block_mem_wa_save; // wire [2:0] dbg_block_mem_wa_save;
`ifdef USE_XCLK2X
huffman393 i_huffman (
.xclk (xclk), // input
.xclk2x (xclk2x), // input
.en (frame_en), // input
.mclk (mclk), // input system clock to write tables
.tser_we (tser_he), // input - write to a quantization table
.tser_a_not_d (tser_a_not_d), // input - address/not data to tables
.tser_d (tser_d), // input[7:0] - byte-wide data to tables
.di (enc_do[15:0]), // input[15:0] - specially RLL prepared 16-bit data (to FIFO)
.ds (enc_dv), // input - di valid strobe
.rdy (stuffer_rdy), // input - receiver (bit stuffer) is ready to accept data
.do (huff_do[15:0]), // output[15:0] reg
.dl (huff_dl[3:0]), // output[3:0] reg
.dv (huff_dv), // output reg
.flush (flush), // output reg
.last_block (last_block), // output reg
`ifdef DEBUG_RING
.test_lbw (dbg_test_lbw), // output reg ??
.gotLastBlock (dbg_gotLastBlock), // output ?? - unused (was for debug)
`else
.test_lbw (), // output reg ??
.gotLastBlock (), // output ?? - unused (was for debug)
`endif
.clk_flush (hclk), // input
.flush_clk (flush_hclk), // output
`ifdef DEBUG_RING
.fifo_or_full (dbg_fifo_or_full) // FIFO output register full - just for debuging
`else
.fifo_or_full () // FIFO output register full - just for debuging
`endif
);
stuffer393 stuffer393_i (
// .rst (rst), // input
.mclk (mclk), // input
.mrst (mrst), // input
.xrst (xrst), // input
.last_block (last_block), // input @negedge xclk2x - use it to copy timestamp from fifo
.ts_pre_stb (ts_pre_stb), // input 1 cycle before timestamp data, @mclk
.ts_data (ts_data), // input[7:0] 8-byte timestamp data (s0,s1,s2,s3,us0,us1,us2,us3==0)
.color_first (color_first), // input valid @xclk - only for sec/usec
.fradv_clk (xclk), // input
.clk (xclk2x), // input clock - uses negedge inside
.en_in (stuffer_en), //
.flush (flush), // input - flush output data (fill byte with 0, long word with FFs)
.abort (force_flush_long), // @ any, extracts 0->1 and flushes
.stb (huff_dv), // input
.dl (huff_dl), // input[3:0] number of bits to send (0 - 16) (0-16??)
.d (huff_do), // input[15:0] data to shift (only lower huff_dl bits are valid)
// outputs valid @negedge xclk2x
.rdy (stuffer_rdy), // output - enable huffman encoder to proceed. Used as CE for many huffman encoder registers
.q (stuffer_do), // output[15:0] reg - output data
.qv (stuffer_dv), // output reg - output data valid
.done (stuffer_done), // output
`ifdef DEBUG_RING
.flushing (dbg_flushing), // output reg Not used?
`else
.flushing (), // output reg Not used?
`endif
.running (stuffer_running) // from registering timestamp until done
`ifdef DEBUG_RING
, .dbg_etrax_dma (etrax_dma)
,.dbg_ts_rstb (dbg_ts_rstb) // output
,.dbg_ts_dout (dbg_ts_dout) //output [7:0]
`endif
`ifdef debug_stuffer
,.etrax_dma_r(tst_stuf_etrax[3:0]) // [3:0] just for testing
,.test_cntr(test_cntr[3:0])
,.test_cntr1(test_cntr1[7:0])
`endif
);
//cat x393_testbench03-latest.log | grep "COMPRESSOR[32 ]*CHN" > compressors_out32.log
wire eof_written_xclk2xn;
pulse_cross_clock stuffer_done_mclk_i (.rst(xrst2xn), .src_clk(~xclk2x), .dst_clk(mclk), .in_pulse(stuffer_done), .out_pulse(stuffer_done_mclk),.busy());
cmprs_out_fifo cmprs_out_fifo_i (
// source (stuffer) clock domain
.wclk (~xclk2x), // input source clock (2x pixel clock, inverted) - same as stuffer out
.wrst (xrst2xn), // input mostly for simulation
.we (stuffer_dv), // @ posedge(~xclk2x) input write data from stuffer
.wdata ({stuffer_do[7:0],stuffer_do[15:8]}), // input[15:0] data from stuffer module;
.wa_rst (!stuffer_en), // input reset low address bits when stuffer is disabled (to make sure it is multiple of 32 bytes
.wlast (stuffer_done), // input - written last 32 bytes of a frame (flush FIFO) - stuffer_done (has to be later than we)
.eof_written_wclk (eof_written_xclk2xn), // output - AFI had transferred frame data to the system memory
// AFI clock domain
.rclk (hclk), // @posedge(hclk) input - AFI clock
.rrst (hrst), // input - AFI clock
.rst_fifo (fifo_rst), // input - reset FIFO (set read address to write, reset count)
.ren (fifo_ren), // input - fifo read from AFI channel mux
.rdata (fifo_rdata), // output[63:0] - data to AFI channel mux (latency == 2 from fifo_ren)
.eof (fifo_eof), // output single hclk pulse signalling EOF
.eof_written (eof_written), // input single hclk pulse confirming frame data is written to the system memory
.flush_fifo (fifo_flush), // output level signalling that FIFO has data from the current frame (use short AXI burst if needed)
.fifo_count (fifo_count) // output[7:0] - number of 32-byte chunks available in FIFO
);
pulse_cross_clock eof_written_mclk_i (.rst(xrst2xn), .src_clk(~xclk2x), .dst_clk(mclk), .in_pulse(eof_written_xclk2xn), .out_pulse(eof_written_mclk),.busy());
// pulse_cross_clock eof_written_mclk_i (.rst(xrst2xn), .src_clk(~xclk2x), .dst_clk(mclk), .in_pulse(eof_written_xclk2xn), .out_pulse(eof_written_mclk),.busy());
`ifdef DISPLAY_COMPRESSED_DATA
integer dbg_stuffer_word_number;
reg dbg_odd_stuffer_dv;
reg [15:0] dbg_even_stuffer_do;
wire [31:0] dbg_stuffer_do32 = {dbg_even_stuffer_do, stuffer_do};
always @ (negedge xclk2x) begin
if (stuffer_dv && dbg_odd_stuffer_dv) begin huffman_stuffer_raw_meta huffman_stuffer_meta_i (
$display ("COMPRESSOR CHN%d 0x%x -> 0x%x", CMPRS_NUMBER, dbg_stuffer_word_number, dbg_stuffer_do32);
end
if (stuffer_done) begin
$display ("COMPRESSOR CHN%d ***** DONE *****",CMPRS_NUMBER);
end
if (stuffer_dv && !dbg_odd_stuffer_dv) dbg_even_stuffer_do = stuffer_do;
if (!stuffer_en || stuffer_done) dbg_stuffer_word_number = 0;
else if (stuffer_dv && dbg_odd_stuffer_dv) dbg_stuffer_word_number = dbg_stuffer_word_number + 1;
if (!stuffer_en) dbg_odd_stuffer_dv = 0;
else if (stuffer_dv) dbg_odd_stuffer_dv = ~dbg_odd_stuffer_dv;
end
`endif
`else
huffman_stuffer_meta huffman_stuffer_meta_i (
.mclk (mclk), // input .mclk (mclk), // input
.mrst (mrst), // input .mrst (mrst), // input
.xclk (xclk), // input .xclk (xclk), // input
.en_huffman (frame_en), // input .en_huffman (frame_en_jp), // input
.en_stuffer (stuffer_en), // input .en_stuffer (stuffer_en), // input
.abort_stuffer (force_flush_long), // input .abort_stuffer (force_flush_long), // input
.tser_we (tser_he), // input .tser_we (tser_he), // input
...@@ -1340,10 +1240,20 @@ module jp_channel#( ...@@ -1340,10 +1240,20 @@ module jp_channel#(
.ts_pre_stb (ts_pre_stb), // input .ts_pre_stb (ts_pre_stb), // input
.ts_data (ts_data), // input[7:0] .ts_data (ts_data), // input[7:0]
.color_first (color_first), // input valid @xclk - only for sec/usec .color_first (color_first), // input valid @xclk - only for sec/usec
.compressed_mode (compressed), // input
.raw_mode (uncompressed), // input
.raw_be16 (1'b0), // raw_be16), // input
.raw_bytes (buf_pxd), // input[7:0]
.raw_start (raw_start), // input
.raw_prefb (raw_prefb), // input
.raw_ts_copy (raw_ts_copy), // input
.raw_flush (raw_flush), // input
.data_out (stuffer_do), // output[31:0] .data_out (stuffer_do), // output[31:0]
.data_out_valid (stuffer_dv), // output .data_out_valid (stuffer_dv), // output
.done (stuffer_done), // output .done (stuffer_done), // output // after trailer
.running (stuffer_running), // output .running (stuffer_running), // output // DID not include trailer (bug?), now includes (after raw debugging)
.clk_flush (hclk), // input .clk_flush (hclk), // input
.flush_clk (flush_hclk) // output .flush_clk (flush_hclk) // output
...@@ -1394,7 +1304,6 @@ module jp_channel#( ...@@ -1394,7 +1304,6 @@ module jp_channel#(
end end
`endif `endif
`endif
// TODO: Add status module to combine/FF, re-clock status signals // TODO: Add status module to combine/FF, re-clock status signals
......
...@@ -58,7 +58,7 @@ module quantizer393( ...@@ -58,7 +58,7 @@ module quantizer393(
input first_in, // first block in (valid @ start) input first_in, // first block in (valid @ start)
output reg first_out, // valid @ ds output reg first_out, // valid @ ds
input [12:0] di, // [11:0] pixel data in (signed) input [12:0] di, // [11:0] pixel data in (signed)
output reg [12:0] do, // [11:0] pixel data out (AC is only 9 bits long?) - changed to 10 output reg [12:0] dout, // [11:0] pixel data out (AC is only 9 bits long?) - changed to 10
output dv, // data out valid output dv, // data out valid
output ds, // data out strobe (one ahead of the start of dv) output ds, // data out strobe (one ahead of the start of dv)
output reg [15:0] dc_tdo, //[15:0], MSB aligned coefficient for the DC component (used in focus module) output reg [15:0] dc_tdo, //[15:0], MSB aligned coefficient for the DC component (used in focus module)
...@@ -157,13 +157,11 @@ module quantizer393( ...@@ -157,13 +157,11 @@ module quantizer393(
assign dcc_data[15:0]=sel_satnum? assign dcc_data[15:0]=sel_satnum?
{n255[7:0],n000[7:0]}: {n255[7:0],n000[7:0]}:
{dcc_first || (!dcc_Y && dcc_acc[12]) ,(!dcc_Y && dcc_acc[12]), (!dcc_Y && dcc_acc[12]), dcc_acc[12:0]}; {dcc_first || (!dcc_Y && dcc_acc[12]) ,(!dcc_Y && dcc_acc[12]), (!dcc_Y && dcc_acc[12]), dcc_acc[12:0]};
// assign do[12:0]=zigzag_q[12:0];
assign qmul[27:0]=tdor[15:0]*d3[11:0]; assign qmul[27:0]=tdor[15:0]*d3[11:0];
assign start_out = zwe && (zwa[5:0]== 6'h3f); //adjust? assign start_out = zwe && (zwa[5:0]== 6'h3f); //adjust?
assign copy_dc_tdo = zwe && (zwa[5:0]== 6'h37); // not critical assign copy_dc_tdo = zwe && (zwa[5:0]== 6'h37); // not critical
// assign next_dv=en && (ds || (dv && (zra[5:0]!=6'h00)));
always @ (posedge clk) begin always @ (posedge clk) begin
d1[12:0] <= di[12:0]; d1[12:0] <= di[12:0];
//inv_sign //inv_sign
...@@ -218,7 +216,7 @@ module quantizer393( ...@@ -218,7 +216,7 @@ module quantizer393(
if (!en) ren[3:1] <= 0; if (!en) ren[3:1] <= 0;
else ren[3:1] <= ren [2:0]; else ren[3:1] <= ren [2:0];
if (ren[2]) do[12:0] <= zigzag_q[12:0]; if (ren[2]) dout[12:0] <= zigzag_q[12:0];
if (start_a) first_interm <= first_in; if (start_a) first_interm <= first_in;
if (start_out) first_out <=first_interm; if (start_out) first_out <=first_interm;
......
...@@ -36,7 +36,8 @@ ...@@ -36,7 +36,8 @@
* with at least one of the Free Software programs. * with at least one of the Free Software programs.
*/ */
parameter FPGA_VERSION = 32'h03930103; // serial - 17.4 - trigger polarity on GP1 inverted parameter FPGA_VERSION = 32'h03930104; // serial - 17.4 - added RAW mode (for tiff files) timing met
// parameter FPGA_VERSION = 32'h03930103; // serial - 17.4 - trigger polarity on GP1 inverted
// parameter FPGA_VERSION = 32'h03930102; // serial - 17.4 - disabling SOF when setting interface, bug fix // parameter FPGA_VERSION = 32'h03930102; // serial - 17.4 - disabling SOF when setting interface, bug fix
// parameter FPGA_VERSION = 32'h03930101; // serial - 17.4 - disabling SOF when setting interface - met // parameter FPGA_VERSION = 32'h03930101; // serial - 17.4 - disabling SOF when setting interface - met
// parameter FPGA_VERSION = 32'h03930100; // serial - 17.4 - disabling SOF when setting interface timing OK // parameter FPGA_VERSION = 32'h03930100; // serial - 17.4 - disabling SOF when setting interface timing OK
......
...@@ -292,6 +292,7 @@ ...@@ -292,6 +292,7 @@
parameter MCONTR_LINTILE_EXTRAPG_BITS = 2, // number of bits to use for extra pages parameter MCONTR_LINTILE_EXTRAPG_BITS = 2, // number of bits to use for extra pages
parameter MCONTR_LINTILE_KEEP_OPEN = 5, // keep banks open (will be used only if number of rows <= 8) parameter MCONTR_LINTILE_KEEP_OPEN = 5, // keep banks open (will be used only if number of rows <= 8)
parameter MCONTR_LINTILE_BYTE32 = 6, // use 32-byte wide columns in each tile (false - 16-byte) parameter MCONTR_LINTILE_BYTE32 = 6, // use 32-byte wide columns in each tile (false - 16-byte)
parameter MCONTR_LINTILE_LINEAR = 7, // Use linear mode instead of tiled
parameter MCONTR_LINTILE_RST_FRAME = 8, // reset frame number parameter MCONTR_LINTILE_RST_FRAME = 8, // reset frame number
parameter MCONTR_LINTILE_SINGLE = 9, // read/write a single page parameter MCONTR_LINTILE_SINGLE = 9, // read/write a single page
parameter MCONTR_LINTILE_REPEAT = 10, // read/write pages until disabled parameter MCONTR_LINTILE_REPEAT = 10, // read/write pages until disabled
...@@ -712,6 +713,8 @@ ...@@ -712,6 +713,8 @@
parameter CMPRS_CBIT_CMODE_BITS = 4, // number of bits to control compressor color modes parameter CMPRS_CBIT_CMODE_BITS = 4, // number of bits to control compressor color modes
parameter CMPRS_CBIT_FRAMES = 15, // bit # to control compressor multi/single frame buffer modes parameter CMPRS_CBIT_FRAMES = 15, // bit # to control compressor multi/single frame buffer modes
parameter CMPRS_CBIT_FRAMES_BITS = 1, // number of bits to control compressor multi/single frame buffer modes parameter CMPRS_CBIT_FRAMES_BITS = 1, // number of bits to control compressor multi/single frame buffer modes
parameter CMPRS_CBIT_BE16 = 17, // bit # to control compressor multi/single frame buffer modes
parameter CMPRS_CBIT_BE16_BITS = 1, // number of bits to control compressor multi/single frame buffer modes
parameter CMPRS_CBIT_BAYER = 20, // bit # to control compressor Bayer shift mode parameter CMPRS_CBIT_BAYER = 20, // bit # to control compressor Bayer shift mode
parameter CMPRS_CBIT_BAYER_BITS = 2, // number of bits to control compressor Bayer shift mode parameter CMPRS_CBIT_BAYER_BITS = 2, // number of bits to control compressor Bayer shift mode
parameter CMPRS_CBIT_FOCUS = 23, // bit # to control compressor focus display mode parameter CMPRS_CBIT_FOCUS = 23, // bit # to control compressor focus display mode
...@@ -734,6 +737,7 @@ ...@@ -734,6 +737,7 @@
parameter CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2 = 4'ha, // jp4, 4 blocks, differential, hdr,divide by 2 parameter CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2 = 4'ha, // jp4, 4 blocks, differential, hdr,divide by 2
parameter CMPRS_CBIT_CMODE_MONO1 = 4'hb, // mono JPEG (not yet implemented) parameter CMPRS_CBIT_CMODE_MONO1 = 4'hb, // mono JPEG (not yet implemented)
parameter CMPRS_CBIT_CMODE_MONO4 = 4'he, // mono, 4 blocks (but still not actual monochrome JPEG as the blocks are scanned in 2x2 macroblocks) parameter CMPRS_CBIT_CMODE_MONO4 = 4'he, // mono, 4 blocks (but still not actual monochrome JPEG as the blocks are scanned in 2x2 macroblocks)
parameter CMPRS_CBIT_CMODE_RAW = 4'hf, // uncompressed
parameter CMPRS_CBIT_FRAMES_SINGLE = 0, //1, // use a single-frame buffer for images parameter CMPRS_CBIT_FRAMES_SINGLE = 0, //1, // use a single-frame buffer for images
...@@ -742,6 +746,7 @@ ...@@ -742,6 +746,7 @@
parameter CMPRS_MONO16 = 2, // JPEG 4:2:0 with 16x16 non-overlapping tiles, color components zeroed parameter CMPRS_MONO16 = 2, // JPEG 4:2:0 with 16x16 non-overlapping tiles, color components zeroed
parameter CMPRS_JP4 = 3, // JP4 mode with 16x16 macroblocks parameter CMPRS_JP4 = 3, // JP4 mode with 16x16 macroblocks
parameter CMPRS_JP4DIFF = 4, // JP4DIFF mode TODO: see if correct parameter CMPRS_JP4DIFF = 4, // JP4DIFF mode TODO: see if correct
parameter CMPRS_RAW = 6, // Not comressed, raw data
parameter CMPRS_MONO8 = 7, // Regular JPEG monochrome with 8x8 macroblocks (not yet implemented) parameter CMPRS_MONO8 = 7, // Regular JPEG monochrome with 8x8 macroblocks (not yet implemented)
parameter CMPRS_FRMT_MBCM1 = 0, // bit # of number of macroblock columns minus 1 field in format word parameter CMPRS_FRMT_MBCM1 = 0, // bit # of number of macroblock columns minus 1 field in format word
......
...@@ -255,7 +255,8 @@ module mcntrl393 #( ...@@ -255,7 +255,8 @@ module mcntrl393 #(
parameter MCONTR_LINTILE_EXTRAPG = 3, // extra pages (over 1) needed by the client simultaneously parameter MCONTR_LINTILE_EXTRAPG = 3, // extra pages (over 1) needed by the client simultaneously
parameter MCONTR_LINTILE_EXTRAPG_BITS = 2, // number of bits to use for extra pages parameter MCONTR_LINTILE_EXTRAPG_BITS = 2, // number of bits to use for extra pages
parameter MCONTR_LINTILE_KEEP_OPEN = 5, // keep banks open (will be used only if number of rows <= 8) parameter MCONTR_LINTILE_KEEP_OPEN = 5, // keep banks open (will be used only if number of rows <= 8)
parameter MCONTR_LINTILE_BYTE32 = 6, // use 32-byte wide columns in each tile (false - 16-byte) parameter MCONTR_LINTILE_BYTE32 = 6, // use 32-byte wide columns in each tile (false - 16-byte)
parameter MCONTR_LINTILE_LINEAR = 7, // Use linear mode instead of tiled
parameter MCONTR_LINTILE_RST_FRAME = 8, // reset frame number parameter MCONTR_LINTILE_RST_FRAME = 8, // reset frame number
parameter MCONTR_LINTILE_SINGLE = 9, // read/write a single page parameter MCONTR_LINTILE_SINGLE = 9, // read/write a single page
parameter MCONTR_LINTILE_REPEAT = 10, // read/write pages until disabled parameter MCONTR_LINTILE_REPEAT = 10, // read/write pages until disabled
...@@ -587,6 +588,7 @@ module mcntrl393 #( ...@@ -587,6 +588,7 @@ module mcntrl393 #(
wire [3:0] cmprs_channel_pgm_en; wire [3:0] cmprs_channel_pgm_en;
wire [3:0] cmprs_reject = 4'h0; wire [3:0] cmprs_reject = 4'h0;
wire [3:0] cmprs_start_rdlin;
wire [3:0] cmprs_start_rd16; wire [3:0] cmprs_start_rd16;
wire [3:0] cmprs_start_rd32; wire [3:0] cmprs_start_rd32;
wire [11:0] cmprs_bank; // output[2:0] wire [11:0] cmprs_bank; // output[2:0]
...@@ -596,6 +598,7 @@ module mcntrl393 #( ...@@ -596,6 +598,7 @@ module mcntrl393 #(
wire [4*MAX_TILE_WIDTH-1:0] cmprs_num_rows_m1; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64) wire [4*MAX_TILE_WIDTH-1:0] cmprs_num_rows_m1; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire [4*MAX_TILE_HEIGHT-1:0] cmprs_num_cols_m1; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64) wire [4*MAX_TILE_HEIGHT-1:0] cmprs_num_cols_m1; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
wire [3:0] cmprs_keep_open; // start generating commands wire [3:0] cmprs_keep_open; // start generating commands
wire [4*6-1:0] cmprs_num128; // output[5:0]
wire [3:0] cmprs_partial; // output wire [3:0] cmprs_partial; // output
wire [3:0] cmprs_seq_done; // input : sequence over wire [3:0] cmprs_seq_done; // input : sequence over
// assign cmprs_page_ready = cmprs_seq_done;// mcntrl_tiled_rw does not generate page_ready pulse as it is the same as xfer_done input // assign cmprs_page_ready = cmprs_seq_done;// mcntrl_tiled_rw does not generate page_ready pulse as it is the same as xfer_done input
...@@ -1160,7 +1163,8 @@ module mcntrl393 #( ...@@ -1160,7 +1163,8 @@ module mcntrl393 #(
`endif `endif
); );
mcntrl_tiled_rw #(
mcntrl_tiled_linear_rw #(
.ADDRESS_NUMBER (ADDRESS_NUMBER), .ADDRESS_NUMBER (ADDRESS_NUMBER),
.COLADDR_NUMBER (COLADDR_NUMBER), .COLADDR_NUMBER (COLADDR_NUMBER),
.FRAME_WIDTH_BITS (FRAME_WIDTH_BITS), .FRAME_WIDTH_BITS (FRAME_WIDTH_BITS),
...@@ -1190,13 +1194,13 @@ module mcntrl393 #( ...@@ -1190,13 +1194,13 @@ module mcntrl393 #(
.MCONTR_LINTILE_EXTRAPG_BITS (MCONTR_LINTILE_EXTRAPG_BITS), .MCONTR_LINTILE_EXTRAPG_BITS (MCONTR_LINTILE_EXTRAPG_BITS),
.MCONTR_LINTILE_KEEP_OPEN (MCONTR_LINTILE_KEEP_OPEN), .MCONTR_LINTILE_KEEP_OPEN (MCONTR_LINTILE_KEEP_OPEN),
.MCONTR_LINTILE_BYTE32 (MCONTR_LINTILE_BYTE32), .MCONTR_LINTILE_BYTE32 (MCONTR_LINTILE_BYTE32),
.MCONTR_LINTILE_LINEAR (MCONTR_LINTILE_LINEAR), // Use linear mode instead of tiled
.MCONTR_LINTILE_RST_FRAME (MCONTR_LINTILE_RST_FRAME), .MCONTR_LINTILE_RST_FRAME (MCONTR_LINTILE_RST_FRAME),
.MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE), .MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE),
.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT), .MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT),
.MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED), .MCONTR_LINTILE_DIS_NEED (MCONTR_LINTILE_DIS_NEED),
.MCONTR_LINTILE_COPY_FRAME (MCONTR_LINTILE_COPY_FRAME), .MCONTR_LINTILE_COPY_FRAME (MCONTR_LINTILE_COPY_FRAME),
.MCONTR_LINTILE_ABORT_LATE (MCONTR_LINTILE_ABORT_LATE) .MCONTR_LINTILE_ABORT_LATE (MCONTR_LINTILE_ABORT_LATE)
) mcntrl_tiled_rd_compressor_i ( ) mcntrl_tiled_rd_compressor_i (
.mrst (mrst), // input .mrst (mrst), // input
.mclk (mclk), // input .mclk (mclk), // input
...@@ -1216,30 +1220,29 @@ module mcntrl393 #( ...@@ -1216,30 +1220,29 @@ module mcntrl393 #(
.frames_in_sync (cmprs_frames_in_sync[i]), // output .frames_in_sync (cmprs_frames_in_sync[i]), // output
.master_frame (cmprs_frame_number_src[i * LAST_FRAME_BITS +: LAST_FRAME_BITS]), // input[15:0] .master_frame (cmprs_frame_number_src[i * LAST_FRAME_BITS +: LAST_FRAME_BITS]), // input[15:0]
.master_set (sens_frame_set[i]), // input .master_set (sens_frame_set[i]), // input
// .master_follow (master_follow[i]), // input
.xfer_want (cmprs_want[i]), // output .xfer_want (cmprs_want[i]), // output
.xfer_need (cmprs_need[i]), // output .xfer_need (cmprs_need[i]), // output
.xfer_grant (cmprs_channel_pgm_en[i]), // input .xfer_grant (cmprs_channel_pgm_en[i]), // input
.xfer_start_rd (cmprs_start_rd16[i]), // output .xfer_start_lin_rd (cmprs_start_rdlin[i]), // output
.xfer_start_lin_wr (), // output
.xfer_start_rd (cmprs_start_rd16[i]), // output // TODO: start rd (wr too?) linear
.xfer_start_wr (), // output .xfer_start_wr (), // output
.xfer_start32_rd (cmprs_start_rd32[i]), // output .xfer_start32_rd (cmprs_start_rd32[i]), // output
.xfer_start32_wr (), // output .xfer_start32_wr (), // output
.xfer_bank (cmprs_bank[i * 3 +: 3]), // output[2:0] .xfer_bank (cmprs_bank[i * 3 +: 3]), // output[2:0]
.xfer_row (cmprs_row[ADDRESS_NUMBER * i +: ADDRESS_NUMBER]), // output[14:0] .xfer_row (cmprs_row[ADDRESS_NUMBER * i +: ADDRESS_NUMBER]), // output[14:0]
.xfer_col (cmprs_col[COL_WDTH * i +: COL_WDTH]), // output[6:0] .xfer_col (cmprs_col[COL_WDTH * i +: COL_WDTH]), // output[6:0]
// 5:0: add xfer_num128[5:0]
.rowcol_inc (cmprs_rowcol_inc[i * FRAME_WBP1 +: FRAME_WBP1]), // output[13:0] .rowcol_inc (cmprs_rowcol_inc[i * FRAME_WBP1 +: FRAME_WBP1]), // output[13:0]
.num_rows_m1 (cmprs_num_rows_m1[i * MAX_TILE_WIDTH +: MAX_TILE_WIDTH]), // output[5:0] .num_rows_m1 (cmprs_num_rows_m1[i * MAX_TILE_WIDTH +: MAX_TILE_WIDTH]), // output[5:0]
.num_cols_m1 (cmprs_num_cols_m1[i * MAX_TILE_HEIGHT +: MAX_TILE_HEIGHT]), // output[5:0] .num_cols_m1 (cmprs_num_cols_m1[i * MAX_TILE_HEIGHT +: MAX_TILE_HEIGHT]), // output[5:0]
.keep_open (cmprs_keep_open[i]), // output .keep_open (cmprs_keep_open[i]), // output
.xfer_num128 (cmprs_num128[i * 6 +: 6]), // output[5:0] //** new**
.xfer_partial (cmprs_partial[i]), // output .xfer_partial (cmprs_partial[i]), // output
.xfer_page_done (cmprs_seq_done[i]), // input .xfer_page_done (cmprs_seq_done[i]), // input
.xfer_page_rst_wr (), // output .xfer_page_rst_wr (), // output
.xfer_page_rst_rd (cmprs_xfer_reset_page_rd[i]) // output @negedge .xfer_page_rst_rd (cmprs_xfer_reset_page_rd[i]) // output @negedge
); );
end end
endgenerate endgenerate
...@@ -1423,6 +1426,7 @@ module mcntrl393 #( ...@@ -1423,6 +1426,7 @@ module mcntrl393 #(
.MCONTR_LINTILE_EXTRAPG_BITS (MCONTR_LINTILE_EXTRAPG_BITS), .MCONTR_LINTILE_EXTRAPG_BITS (MCONTR_LINTILE_EXTRAPG_BITS),
.MCONTR_LINTILE_KEEP_OPEN (MCONTR_LINTILE_KEEP_OPEN), .MCONTR_LINTILE_KEEP_OPEN (MCONTR_LINTILE_KEEP_OPEN),
.MCONTR_LINTILE_BYTE32 (MCONTR_LINTILE_BYTE32), .MCONTR_LINTILE_BYTE32 (MCONTR_LINTILE_BYTE32),
.MCONTR_LINTILE_LINEAR (MCONTR_LINTILE_LINEAR), // Use linear mode instead of tiled
.MCONTR_LINTILE_RST_FRAME (MCONTR_LINTILE_RST_FRAME), .MCONTR_LINTILE_RST_FRAME (MCONTR_LINTILE_RST_FRAME),
.MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE), .MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE),
.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT), .MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT),
...@@ -1441,12 +1445,12 @@ module mcntrl393 #( ...@@ -1441,12 +1445,12 @@ module mcntrl393 #(
.next_page (next_page_chn2), // input .next_page (next_page_chn2), // input
.frame_done (frame_done_chn2), // output .frame_done (frame_done_chn2), // output
.frame_finished (), // output .frame_finished (), // output
.line_unfinished (line_unfinished_chn2), // output[15:0] .line_unfinished (line_unfinished_chn2), // output[15:0]
.suspend (suspend_chn2), // input .suspend (suspend_chn2), // input
.frame_number (frame_number_chn2), .frame_number (frame_number_chn2), // output[15:0]
.frames_in_sync(), // output .frames_in_sync(), // output
.master_frame (16'b0), // input[15:0] .master_frame (16'b0), // input[15:0] // Set master frame number value
.master_set (1'b0), // input .master_set (1'b0), // input // set master frame strobe
// .master_follow (1'b0), // input // .master_follow (1'b0), // input
.xfer_want (want_rq2), // output .xfer_want (want_rq2), // output
.xfer_need (need_rq2), // output .xfer_need (need_rq2), // output
...@@ -1497,6 +1501,7 @@ module mcntrl393 #( ...@@ -1497,6 +1501,7 @@ module mcntrl393 #(
.MCONTR_LINTILE_EXTRAPG_BITS (MCONTR_LINTILE_EXTRAPG_BITS), .MCONTR_LINTILE_EXTRAPG_BITS (MCONTR_LINTILE_EXTRAPG_BITS),
.MCONTR_LINTILE_KEEP_OPEN (MCONTR_LINTILE_KEEP_OPEN), .MCONTR_LINTILE_KEEP_OPEN (MCONTR_LINTILE_KEEP_OPEN),
.MCONTR_LINTILE_BYTE32 (MCONTR_LINTILE_BYTE32), .MCONTR_LINTILE_BYTE32 (MCONTR_LINTILE_BYTE32),
.MCONTR_LINTILE_LINEAR (MCONTR_LINTILE_LINEAR), // Use linear mode instead of tiled
.MCONTR_LINTILE_RST_FRAME (MCONTR_LINTILE_RST_FRAME), .MCONTR_LINTILE_RST_FRAME (MCONTR_LINTILE_RST_FRAME),
.MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE), .MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE),
.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT), .MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT),
...@@ -1640,6 +1645,32 @@ module mcntrl393 #( ...@@ -1640,6 +1645,32 @@ module mcntrl393 #(
.partial11 (sens_partial[3]), // input .partial11 (sens_partial[3]), // input
.start11_wr (sens_start_wr[3]), // input .start11_wr (sens_start_wr[3]), // input
.bank12 (cmprs_bank[0 * 3 +: 3]), // input[2:0]
.row12 (cmprs_row[0 * ADDRESS_NUMBER +: ADDRESS_NUMBER]), // input[14:0]
.start_col12 (cmprs_col[0 * COL_WDTH +: COL_WDTH]), // input[6:0]
.num128_12 (cmprs_num128[0 * 6 +: 6]), // input[5:0]
.partial12 (cmprs_partial[0]), // input
.start12_rd (cmprs_start_rdlin[0]), // input
.bank13 (cmprs_bank[1 * 3 +: 3]), // input[2:0]
.row13 (cmprs_row[1 * ADDRESS_NUMBER +: ADDRESS_NUMBER]), // input[14:0]
.start_col13 (cmprs_col[1 * COL_WDTH +: COL_WDTH]), // input[6:0]
.num128_13 (cmprs_num128[1 * 6 +: 6]), // input[5:0]
.partial13 (cmprs_partial[1]), // input
.start13_rd (cmprs_start_rdlin[1]), // input
.bank14 (cmprs_bank[2 * 3 +: 3]), // input[2:0]
.row14 (cmprs_row[2 * ADDRESS_NUMBER +: ADDRESS_NUMBER]), // input[14:0]
.start_col14 (cmprs_col[2 * COL_WDTH +: COL_WDTH]), // input[6:0]
.num128_14 (cmprs_num128[2 * 6 +: 6]), // input[5:0]
.partial14 (cmprs_partial[2]), // input
.start14_rd (cmprs_start_rdlin[2]), // input
.bank15 (cmprs_bank[3 * 3 +: 3]), // input[2:0]
.row15 (cmprs_row[3 * ADDRESS_NUMBER +: ADDRESS_NUMBER]), // input[14:0]
.start_col15 (cmprs_col[3 * COL_WDTH +: COL_WDTH]), // input[6:0]
.num128_15 (cmprs_num128[3 * 6 +: 6]), // input[5:0]
.partial15 (cmprs_partial[3]), // input
.start15_rd (cmprs_start_rdlin[3]), // input
.bank (lin_rw_bank), // output[2:0] .bank (lin_rw_bank), // output[2:0]
.row (lin_rw_row), // output[14:0] .row (lin_rw_row), // output[14:0]
.start_col (lin_rw_col), // output[6:0] .start_col (lin_rw_col), // output[6:0]
......
...@@ -101,7 +101,6 @@ module mcntrl_linear_rw #( ...@@ -101,7 +101,6 @@ module mcntrl_linear_rw #(
input frame_start, // resets page, x,y, and initiates transfer requests (in write mode will wait for next_page) input frame_start, // resets page, x,y, and initiates transfer requests (in write mode will wait for next_page)
output frame_run, // @mclk - enable pixels from sensor to memory buffer output frame_run, // @mclk - enable pixels from sensor to memory buffer
input next_page, // page was read/written from/to 4*1kB on-chip buffer input next_page, // page was read/written from/to 4*1kB on-chip buffer
// output page_ready, // == xfer_done, connect externally | Single-cycle pulse indicating that a page was read/written from/to DDR3 memory
output frame_done, // single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory output frame_done, // single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory
output frame_finished,// turns on and stays on after frame_done output frame_finished,// turns on and stays on after frame_done
// optional I/O for channel synchronization // optional I/O for channel synchronization
...@@ -154,27 +153,27 @@ module mcntrl_linear_rw #( ...@@ -154,27 +153,27 @@ module mcntrl_linear_rw #(
reg [FRAME_WIDTH_BITS:0] frame_full_width_r; // (14 bit) register to be absorbed by MPY reg [FRAME_WIDTH_BITS:0] frame_full_width_r; // (14 bit) register to be absorbed by MPY
reg [MPY_WIDTH-1:0] mul_rslt; reg [MPY_WIDTH-1:0] mul_rslt;
reg [NUM_RC_BURST_BITS-1:0] start_addr_r; // 22 bit - to be absorbed by DSP reg [NUM_RC_BURST_BITS-1:0] start_addr_r; // 22 bit - to be absorbed by DSP
// reg [2:0] bank_reg [2:0];
reg [3 * 3 - 1:0] bank_reg; reg [3 * 3 - 1:0] bank_reg;
wire [FRAME_WIDTH_BITS+FRAME_HEIGHT_BITS-3:0] mul_rslt_w; wire [FRAME_WIDTH_BITS+FRAME_HEIGHT_BITS-3:0] mul_rslt_w;
reg [FRAME_WIDTH_BITS:0] row_left; // number of 8-bursts left in the current row reg [FRAME_WIDTH_BITS:0] row_left; // number of 8-bursts left in the current row
reg last_in_row; reg last_in_row;
reg [COLADDR_NUMBER-3:0] mem_page_left; // number of 8-bursts left in the pointed memory page reg [COLADDR_NUMBER-3:0] mem_page_left; // number of 8-bursts left in the pointed memory page
reg [COLADDR_NUMBER-4:0] line_start_page_left; // number of 8-burst left in the memory page from the start of the frame line reg [COLADDR_NUMBER-4:0] line_start_page_left; // number of 8-burst left in the memory page from the start of the frame line
reg [NUM_XFER_BITS:0] lim_by_xfer; // number of bursts left limited by the longest transfer (currently 64) reg [NUM_XFER_BITS:0] lim_by_xfer; // number of bursts left limited by the longest transfer (currently 64)
// reg [MAX_TILE_WIDTH:0] lim_by_tile_width; // number of bursts left limited by the longest transfer (currently 64) // reg [MAX_TILE_WIDTH:0] lim_by_tile_width; // number of bursts left limited by the longest transfer (currently 64)
wire [COLADDR_NUMBER-3:0] remainder_in_xfer ;//remainder_tile_width; // number of bursts postponed to the next partial tile (because of the page crossing) MSB-sign wire [COLADDR_NUMBER-3:0] remainder_in_xfer ;//remainder_tile_width; // number of bursts postponed to the next partial tile (because of the page crossing) MSB-sign
reg continued_xfer; //continued_tile; // this is a continued tile (caused by page crossing) - only once reg continued_xfer; //continued_tile; // this is a continued tile (caused by page crossing) - only once
reg [NUM_XFER_BITS-1:0] leftover; //[MAX_TILE_WIDTH-1:0] leftover_cols; // valid with continued_tile, number of columns left reg [NUM_XFER_BITS-1:0] leftover; //[MAX_TILE_WIDTH-1:0] leftover_cols; // valid with continued_tile, number of columns left
reg [NUM_XFER_BITS:0] xfer_num128_r; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 reg [NUM_XFER_BITS:0] xfer_num128_r; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8
// reg [NUM_XFER_BITS-1:0] xfer_num128_m1_r; // number of 128-bit words to transfer minus 1 (8*16 bits) - full bursts of 8 // reg [NUM_XFER_BITS-1:0] xfer_num128_m1_r; // number of 128-bit words to transfer minus 1 (8*16 bits) - full bursts of 8
wire pgm_param_w; // program one of the parameters, invalidate calculated results for PAR_MOD_LATENCY wire pgm_param_w; // program one of the parameters, invalidate calculated results for PAR_MOD_LATENCY
reg [2:0] xfer_start_r; // 1 hot started by xfer start only (not by parameter change) reg [2:0] xfer_start_r; // 1 hot started by xfer start only (not by parameter change)
reg xfer_start_rd_r; reg xfer_start_rd_r;
reg xfer_start_wr_r; reg xfer_start_wr_r;
reg [PAR_MOD_LATENCY-1:0] par_mod_r; reg [PAR_MOD_LATENCY-1:0] par_mod_r;
reg [PAR_MOD_LATENCY-1:0] recalc_r; // 1-hot CE for re-calculating registers reg [PAR_MOD_LATENCY-1:0] recalc_r; // 1-hot CE for re-calculating registers
// SuppressWarnings VEditor unused // SuppressWarnings VEditor unused
...@@ -210,7 +209,6 @@ module mcntrl_linear_rw #( ...@@ -210,7 +209,6 @@ module mcntrl_linear_rw #(
reg frame_finished_r; reg frame_finished_r;
wire last_in_row_w; wire last_in_row_w;
wire last_row_w; wire last_row_w;
// wire last_block_w;
reg last_block; reg last_block;
reg [MCNTRL_SCANLINE_PENDING_CNTR_BITS-1:0] pending_xfers; // number of requested,. but not finished block transfers reg [MCNTRL_SCANLINE_PENDING_CNTR_BITS-1:0] pending_xfers; // number of requested,. but not finished block transfers
reg [NUM_RC_BURST_BITS-1:0] row_col_r; reg [NUM_RC_BURST_BITS-1:0] row_col_r;
...@@ -258,7 +256,6 @@ module mcntrl_linear_rw #( ...@@ -258,7 +256,6 @@ module mcntrl_linear_rw #(
reg [LAST_FRAME_BITS-1:0] frame_number_current; reg [LAST_FRAME_BITS-1:0] frame_number_current;
reg is_last_frame; reg is_last_frame;
// reg [2:0] frame_start_r;
reg [4:0] frame_start_r; // increased length to have time from line_unfinished to suspend (external) reg [4:0] frame_start_r; // increased length to have time from line_unfinished to suspend (external)
reg [FRAME_WIDTH_BITS:0] frame_full_width; // (programmed) increment combined row/col when moving to the next line reg [FRAME_WIDTH_BITS:0] frame_full_width; // (programmed) increment combined row/col when moving to the next line
...@@ -270,6 +267,7 @@ module mcntrl_linear_rw #( ...@@ -270,6 +267,7 @@ module mcntrl_linear_rw #(
reg [FRAME_HEIGHT_BITS-1:0] window_y0; // (programmed) window top reg [FRAME_HEIGHT_BITS-1:0] window_y0; // (programmed) window top
reg [FRAME_WIDTH_BITS-1:0] start_x; // (programmed) normally 0, copied to curr_x on frame_start_late reg [FRAME_WIDTH_BITS-1:0] start_x; // (programmed) normally 0, copied to curr_x on frame_start_late
reg [FRAME_HEIGHT_BITS-1:0] start_y; // (programmed) normally 0, copied to curr_y on frame_start_late reg [FRAME_HEIGHT_BITS-1:0] start_y; // (programmed) normally 0, copied to curr_y on frame_start_late
reg xfer_done_d; // xfer_done delayed by 1 cycle (also includes xfer_skipped) reg xfer_done_d; // xfer_done delayed by 1 cycle (also includes xfer_skipped)
reg [MCNTRL_SCANLINE_DLY_WIDTH-1:0] start_delay; // how much to delay frame start reg [MCNTRL_SCANLINE_DLY_WIDTH-1:0] start_delay; // how much to delay frame start
reg [MCNTRL_SCANLINE_DLY_WIDTH:0] start_delay_cntr = {MCNTRL_SCANLINE_DLY_WIDTH+1{1'b1}}; // start delay counter reg [MCNTRL_SCANLINE_DLY_WIDTH:0] start_delay_cntr = {MCNTRL_SCANLINE_DLY_WIDTH+1{1'b1}}; // start delay counter
...@@ -311,12 +309,7 @@ module mcntrl_linear_rw #( ...@@ -311,12 +309,7 @@ module mcntrl_linear_rw #(
if (mrst) rst_frame_num_r <= 0; if (mrst) rst_frame_num_r <= 0;
else rst_frame_num_r <= {rst_frame_num_r[0], rst_frame_num_w }; // now only at specific command else rst_frame_num_r <= {rst_frame_num_r[0], rst_frame_num_w }; // now only at specific command
/*
|
set_start_addr_w |
set_last_frame_w |
set_frame_size_w};
*/
if (mrst) start_range_addr <= 0; if (mrst) start_range_addr <= 0;
else if (set_start_addr_w) start_range_addr <= cmd_data[NUM_RC_BURST_BITS-1:0]; else if (set_start_addr_w) start_range_addr <= cmd_data[NUM_RC_BURST_BITS-1:0];
...@@ -331,7 +324,6 @@ module mcntrl_linear_rw #( ...@@ -331,7 +324,6 @@ module mcntrl_linear_rw #(
else if (set_frame_width_w) frame_full_width <= {lsw13_zero,cmd_data[FRAME_WIDTH_BITS-1:0]}; else if (set_frame_width_w) frame_full_width <= {lsw13_zero,cmd_data[FRAME_WIDTH_BITS-1:0]};
if (mrst) is_last_frame <= 0; if (mrst) is_last_frame <= 0;
// else is_last_frame <= frame_number_cntr == last_frame_number;
else is_last_frame <= frame_number_cntr >= last_frame_number; // trying to make it safe else is_last_frame <= frame_number_cntr >= last_frame_number; // trying to make it safe
`ifdef REPORT_FRAME_NUMBER `ifdef REPORT_FRAME_NUMBER
...@@ -342,7 +334,6 @@ module mcntrl_linear_rw #( ...@@ -342,7 +334,6 @@ module mcntrl_linear_rw #(
// if (mrst) frame_start_r <= 0; // if (mrst) frame_start_r <= 0;
// else frame_start_r <= {frame_start_r[3:0], frame_start_late & frame_en}; // else frame_start_r <= {frame_start_r[3:0], frame_start_late & frame_en};
// if (mrst) frame_en <= 0;
if (!chn_en) frame_en <= 0; if (!chn_en) frame_en <= 0;
else if (single_frame_r || repeat_frames) frame_en <= 1; else if (single_frame_r || repeat_frames) frame_en <= 1;
else if (frame_start_late) frame_en <= 0; else if (frame_start_late) frame_en <= 0;
...@@ -407,9 +398,9 @@ module mcntrl_linear_rw #( ...@@ -407,9 +398,9 @@ module mcntrl_linear_rw #(
assign xfer_start_rd= xfer_start_rd_r; assign xfer_start_rd= xfer_start_rd_r;
assign xfer_start_wr= xfer_start_wr_r; assign xfer_start_wr= xfer_start_wr_r;
assign calc_valid= par_mod_r[PAR_MOD_LATENCY-1]; // MSB, longest 0 assign calc_valid= par_mod_r[PAR_MOD_LATENCY-1]; // MSB, longest 0
assign xfer_page_rst_wr= xfer_page_rst_r; assign xfer_page_rst_wr= xfer_page_rst_r;
assign xfer_page_rst_rd= xfer_page_rst_neg; assign xfer_page_rst_rd= xfer_page_rst_neg;
assign xfer_partial= xfer_limited_by_mem_page_r; assign xfer_partial= xfer_limited_by_mem_page_r;
assign frame_done= frame_done_r; assign frame_done= frame_done_r;
...@@ -430,7 +421,7 @@ module mcntrl_linear_rw #( ...@@ -430,7 +421,7 @@ module mcntrl_linear_rw #(
assign xfer_row= row_col_r[NUM_RC_BURST_BITS-1:COLADDR_NUMBER-3] ; // memory row assign xfer_row= row_col_r[NUM_RC_BURST_BITS-1:COLADDR_NUMBER-3] ; // memory row
assign xfer_col= row_col_r[COLADDR_NUMBER-4:0]; // start memory column in 8-bursts assign xfer_col= row_col_r[COLADDR_NUMBER-4:0]; // start memory column in 8-bursts
assign line_unfinished = line_unfinished_r; // [FRAME_HEIGHT_BITS +: FRAME_HEIGHT_BITS]; assign line_unfinished = line_unfinished_r; // [FRAME_HEIGHT_BITS +: FRAME_HEIGHT_BITS];
assign chn_en = mode_reg[MCONTR_LINTILE_NRESET] & mode_reg[MCONTR_LINTILE_EN]; // enable requests by channel (continue ones in progress) assign chn_en = mode_reg[MCONTR_LINTILE_NRESET] & mode_reg[MCONTR_LINTILE_EN]; // enable requests by channel (continue ones in progress)
assign chn_rst = ~mode_reg[MCONTR_LINTILE_NRESET]; // resets command, including fifo; assign chn_rst = ~mode_reg[MCONTR_LINTILE_NRESET]; // resets command, including fifo;
assign cmd_wrmem = mode_reg[MCONTR_LINTILE_WRITE];// 0: read from memory, 1:write to memory assign cmd_wrmem = mode_reg[MCONTR_LINTILE_WRITE];// 0: read from memory, 1:write to memory
assign cmd_extra_pages = mode_reg[MCONTR_LINTILE_EXTRAPG+:MCONTR_LINTILE_EXTRAPG_BITS]; // external module needs more than 1 page assign cmd_extra_pages = mode_reg[MCONTR_LINTILE_EXTRAPG+:MCONTR_LINTILE_EXTRAPG_BITS]; // external module needs more than 1 page
...@@ -448,7 +439,8 @@ module mcntrl_linear_rw #( ...@@ -448,7 +439,8 @@ module mcntrl_linear_rw #(
assign status_data= {frame_finished_r, busy_r}; // TODO: Add second bit? assign status_data= {frame_finished_r, busy_r}; // TODO: Add second bit?
`endif `endif
`endif `endif
assign pgm_param_w= cmd_we; assign pgm_param_w= cmd_we;
localparam [COLADDR_NUMBER-3-NUM_XFER_BITS-1:0] EXTRA_BITS=0; localparam [COLADDR_NUMBER-3-NUM_XFER_BITS-1:0] EXTRA_BITS=0;
assign remainder_in_xfer = {EXTRA_BITS, lim_by_xfer}-mem_page_left; assign remainder_in_xfer = {EXTRA_BITS, lim_by_xfer}-mem_page_left;
...@@ -575,10 +567,6 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r; ...@@ -575,10 +567,6 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
// calculate number to read (min of row_left, maximal xfer and what is left in the DDR3 page // calculate number to read (min of row_left, maximal xfer and what is left in the DDR3 page
always @(posedge mclk) begin always @(posedge mclk) begin
// acceletaring pre_want // acceletaring pre_want
// pre_want_r1 <= chn_en && !frame_done_r && busy_r && par_mod_r[PAR_MOD_LATENCY-2] && !(|frame_start_r[4:1]) && !last_block;
//last_block is too late for pre_want_r1, moving upsteram
// pre_want_r1 <= chn_en && !frame_done_r && busy_r && par_mod_r[PAR_MOD_LATENCY-2] && !(|frame_start_r[4:1]);
pre_want_r1 <= !chn_rst && !frame_done_r && busy_r && par_mod_r[PAR_MOD_LATENCY-2] && !(|frame_start_r[4:1]); pre_want_r1 <= !chn_rst && !frame_done_r && busy_r && par_mod_r[PAR_MOD_LATENCY-2] && !(|frame_start_r[4:1]);
if (mrst) par_mod_r<=0; if (mrst) par_mod_r<=0;
else if (pgm_param_w || else if (pgm_param_w ||
......
/*!
* <b>Module:</b>mcntrl_tiled_linear_rw
* @file mcntrl_tiled_linear_rw.v
* @date 2015-02-03
* @author Andrey Filippov
*
* @brief Organize paged R/W from DDR3 memory in tiled order
* with window support
* Tiles spreading over two different frames is not yet supported (needed for
* line-scan mode in JPEG (JP4 - OK)
*
* @copyright Copyright (c) 2015 Elphel, Inc.
*
* <b>License:</b>
*
* mcntrl_tiled_linear_rw.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* mcntrl_tiled_linear_rw.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
`define REPORT_FRAME_NUMBER 1
`undef DEBUG_MCNTRL_TILED_EXTRA_STATUS
module mcntrl_tiled_linear_rw#(
parameter ADDRESS_NUMBER= 15,
parameter COLADDR_NUMBER= 10,
parameter FRAME_WIDTH_BITS= 13, // Maximal frame width - 8-word (16 bytes) bursts
parameter FRAME_HEIGHT_BITS= 16, // Maximal frame height
parameter MAX_TILE_WIDTH= 6, // number of bits to specify maximal tile (width-1) (6 -> 64). Used as NUM_XFER_BITS in LINEAR mode
parameter MAX_TILE_HEIGHT= 6, // number of bits to specify maximal tile (height-1) (6 -> 64)
parameter LAST_FRAME_BITS= 16, // number of bits in frame counter (before rolls over)
parameter MCNTRL_TILED_ADDR= 'h120,
parameter MCNTRL_TILED_MASK= 'h7f0, // both channels 0 and 1
parameter MCNTRL_TILED_MODE= 'h0, // set mode register: {byte32,keep_open,extra_pages[1:0],write_mode,enable,!reset}
parameter MCNTRL_TILED_STATUS_CNTRL= 'h1, // control status reporting
parameter MCNTRL_TILED_STARTADDR= 'h2, // 22-bit frame start address (3 CA LSBs==0. BA==0)
parameter MCNTRL_TILED_FRAME_SIZE= 'h3, // 22-bit frame start address increment (3 CA LSBs==0. BA==0)
parameter MCNTRL_TILED_FRAME_LAST= 'h4, // 16-bit last frame number in the buffer
parameter MCNTRL_TILED_FRAME_FULL_WIDTH='h5, // Padded line length (8-row increment), in 8-bursts (16 bytes)
parameter MCNTRL_TILED_WINDOW_WH= 'h6, // low word - 13-bit window width (0->'h4000), high word - 16-bit frame height (0->'h10000)
parameter MCNTRL_TILED_WINDOW_X0Y0= 'h7, // low word - 13-bit window left, high word - 16-bit window top
parameter MCNTRL_TILED_WINDOW_STARTXY= 'h8, // low word - 13-bit start X (relative to window), high word - 16-bit start y
// Start XY can be used when read command to start from the middle
// TODO: Add number of blocks to R/W? (blocks can be different) - total length?
// Read back current address (for debugging)?
parameter MCNTRL_TILED_TILE_WHS= 'h9, // low byte - 6-bit tile width in 8-bursts, second byte - tile height (0 - > 64),
// 3-rd byte - vertical step (to control tile vertical overlap)
parameter MCNTRL_TILED_STATUS_REG_ADDR= 'h5,
parameter MCNTRL_TILED_PENDING_CNTR_BITS=2, // Number of bits to count pending trasfers, currently 2 is enough, but may increase
// if memory controller will allow programming several sequences in advance to
// spread long-programming (tiled) over fast-programming (linear) requests.
// But that should not be too big to maintain 2-level priorities
parameter MCNTRL_TILED_FRAME_PAGE_RESET =1'b0, // reset internal page number to zero at the frame start (false - only when hard/soft reset)
// bits in mode control word
parameter MCONTR_LINTILE_NRESET = 0, // reset if 0
parameter MCONTR_LINTILE_EN = 1, // enable requests
parameter MCONTR_LINTILE_WRITE = 2, // write to memory mode
parameter MCONTR_LINTILE_EXTRAPG = 3, // extra pages (over 1) needed by the client simultaneously
parameter MCONTR_LINTILE_EXTRAPG_BITS = 2, // number of bits to use for extra pages
parameter MCONTR_LINTILE_KEEP_OPEN = 5, // keep banks open (will be used only if number of rows <= 8)
parameter MCONTR_LINTILE_BYTE32 = 6, // use 32-byte wide columns in each tile (false - 16-byte)
parameter MCONTR_LINTILE_LINEAR = 7, // Use linear mode instead of tiled
parameter MCONTR_LINTILE_RST_FRAME = 8, // reset frame number
parameter MCONTR_LINTILE_SINGLE = 9, // read/write a single page
parameter MCONTR_LINTILE_REPEAT = 10, // read/write pages until disabled
parameter MCONTR_LINTILE_DIS_NEED = 11, // disable 'need' request
// parameter MCONTR_LINTILE_SKIP_LATE = 12, // skip actual R/W operation when it is too late, advance pointers NEW: Copied from LINEAR
parameter MCONTR_LINTILE_COPY_FRAME = 13, // copy frame number from the master channel (single event, not a persistent mode)
parameter MCONTR_LINTILE_ABORT_LATE = 14 // abort frame if not finished by the new frame sync (wait pending memory)
)(
input mrst,
input mclk,
// programming interface
input [7:0] cmd_ad, // byte-serial command address/data (up to 6 bytes: AL-AH-D0-D1-D2-D3
input cmd_stb, // strobe (with first byte) for the command a/d
output [7:0] status_ad, // byte-wide address/data
output status_rq, // request to send downstream (last byte with rq==0)
input status_start, // acknowledge of address (first byte) from downsteram
input frame_start, // resets page, x,y, and initiates transfer requests (in write mode will wait for next_page)
output frame_start_conf, // frame start modified by memory controller. Normally delayed by 1 cycle,
// or more if memory transactions are to be finished
input next_page, // page was read/written from/to 4*1kB on-chip buffer
output frame_done, // single-cycle pulse when the full frame (window) was transferred to/from DDR3 memory
output frame_finished,// turns on and stays on after frame_done
// optional I/O for channel synchronization
// after the last tile in a frame, before starting a new frame line_unfinished will point to non-existent (too high) line in the same frame
output [FRAME_HEIGHT_BITS-1:0] line_unfinished, // number of the current (unfinished ) line, RELATIVE TO FRAME, NOT WINDOW.
input suspend, // suspend transfers (from external line number comparator)
output [LAST_FRAME_BITS-1:0] frame_number, // current frame number (for multi-frame ranges)
output frames_in_sync, // frame number valid for bonded mode //LINEAR: frame_set, // frame number is just set to a new value (can be used by slave to sync)
input [LAST_FRAME_BITS-1:0] master_frame, // current frame number of a master channel // LINEAR: nothing
input master_set, // master frame number set (1-st cycle when new value is valid) // LINEAR: nothing
output xfer_want, // "want" data transfer
output xfer_need, // "need" - really need a transfer (only 1 page/ room for 1 page left in a buffer), want should still be set.
input xfer_grant, // sequencer programming access granted, deassert wait/need
// LINEAR: output xfer_reject, // reject granted access (when skipping) (not used for compressor)
//
output xfer_start_lin_rd, // LINEAR: initiate a transfer (next cycle after xfer_grant), following signals (up to xfer_partial) are valid
output xfer_start_lin_wr, // LINEAR: initiate a transfer (next cycle after xfer_grant), following signals (up to xfer_partial) are valid
output xfer_start_rd, // initiate a transfer (next cycle after xfer_grant), following signals (up to xfer_partial) are valid // LINEAR: DNU
output xfer_start_wr, // initiate a transfer (next cycle after xfer_grant), following signals (up to xfer_partial) are valid // LINEAR: DNU
output xfer_start32_rd, // initiate a transfer to 32-byte wide colums scanning in each tile // LINEAR: DNU
output xfer_start32_wr, // initiate a transfer to 32-byte wide colums scanning in each tile // LINEAR: DNU
output [2:0] xfer_bank, // start bank address
output [ADDRESS_NUMBER-1:0] xfer_row, // memory row
output [COLADDR_NUMBER-4:0] xfer_col, // start memory column in 8-bursts
output [FRAME_WIDTH_BITS:0] rowcol_inc, // increment row+col (after bank) for the new scan line in 8-bursts (externally pad with 0)
output [MAX_TILE_WIDTH-1:0] num_rows_m1, // number of rows to read minus 1
output [MAX_TILE_HEIGHT-1:0] num_cols_m1, // number of 16-pixel columns to read (rows first, then columns) - 1
output keep_open, // (programmable bit)keep banks open (for <=8 banks only // LINEAR: DNU
// LINEAR: [NUM_XFER_BITS-1:0] xfer_num128, // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
output [MAX_TILE_WIDTH-1:0] xfer_num128, // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
// assign xfer_num128= num_cols_r[NUM_XFER_BITS-1:0]; // One bit less!
output xfer_partial, // partial tile (first of 2) , sequencer will not generate page_next at the end of block
input xfer_page_done, // transfer to/from the buffer finished (partial transfers should not generate), use rpage_nxt_chn@mclk
output xfer_page_rst_wr, // reset buffer internal page - at each frame start or when specifically reset (write to memory channel), @posedge
output xfer_page_rst_rd // reset buffer internal page - at each frame start or when specifically reset (read memory channel), @negedge
);
// FIXME: not all tile heights are valid (because of the banks)
//MAX_TILE_WIDTH
localparam NUM_RC_BURST_BITS=ADDRESS_NUMBER+COLADDR_NUMBER-3; //to spcify row and col8 == 22
localparam MPY_WIDTH= NUM_RC_BURST_BITS; // 22
localparam PAR_MOD_LATENCY= 9; // TODO: Find actual worst-case latency for:
reg [FRAME_WIDTH_BITS-1:0] curr_x; // (calculated) start of transfer x (relative to window left)
reg [FRAME_HEIGHT_BITS-1:0] curr_y; // (calculated) start of transfer y (relative to window top)
reg [FRAME_HEIGHT_BITS:0] next_y; // (calculated) next row number
reg [NUM_RC_BURST_BITS-1:0] line_start_addr;// (calculated) Line start (in {row,col8} in burst8
reg [COLADDR_NUMBER-4:0] line_start_page_left; // number of 8-burst left in the memory page from the start of the frame line (LINEAR: DNU)
// calculating full width from the frame width
//WARNING: [Synth 8-3936] Found unconnected internal register 'frame_y_reg' and it is trimmed from '16' to '3' bits. [memctrl/mcntrl_tiled_linear_rw.v:307]
// Throblem seems to be that frame_y8_r_reg (load of trimmed bits of the frame_y_reg) is (as intended) absorbed into DSP48. The lower 3 bits are used
// outside of the DSP 48. "dont_touch" seems to work here
`ifndef IGNORE_ATTR
(* keep = "true" *)
`endif
reg [FRAME_HEIGHT_BITS-1:0] frame_y; // current line number referenced to the frame top
reg [FRAME_WIDTH_BITS-1:0] frame_x; // current column number referenced to the frame left
reg [FRAME_HEIGHT_BITS-4:0] frame_y8_r; // (13 bits) current row with bank removed, latency2 (to be absorbed when inferred DSP multipler)
reg [FRAME_WIDTH_BITS:0] frame_full_width_r; // (14 bit) register to be absorbed by MPY
reg [MPY_WIDTH-1:0] mul_rslt;
reg [NUM_RC_BURST_BITS-1:0] start_addr_r; // 22 bit - to be absorbed by DSP
reg [3 * 3 - 1:0] bank_reg;
wire [FRAME_WIDTH_BITS+FRAME_HEIGHT_BITS-3:0] mul_rslt_w;
reg [FRAME_WIDTH_BITS:0] row_left; // number of 8-bursts left in the current row
reg last_in_row;
reg [COLADDR_NUMBER-3:0] mem_page_left; // number of 8-bursts left in the pointed memory page
// (LINEAR: DNU)
reg [MAX_TILE_WIDTH:0] lim_by_tile_width; // number of bursts left limited by the longest transfer (currently 64) (LINEAR: DNU)
wire [COLADDR_NUMBER-3:0] remainder_tile_width; // number of bursts postponed to the next partial tile (because of the page crossing) MSB-sign
reg continued_tile; // this is a continued tile (caused by page crossing) - only once
reg [MAX_TILE_WIDTH-1:0] leftover_cols; // valid with continued_tile, number of columns left
// (TILED: DNU)
// reg [NUM_XFER_BITS:0] lim_by_xfer; // number of bursts left limited by the longest transfer (currently 64) - using lim_by_tile_width for lim_by_xfer
// reg [MAX_TILE_WIDTH:0] lim_by_tile_width; // number of bursts left limited by the longest transfer (currently 64)
// wire [COLADDR_NUMBER-3:0] remainder_in_xfer ;// Use remainder_tile_width; // number of bursts postponed to the next partial tile (because of the page crossing) MSB-sign
// TODO: in linear mode use continued_tile instead of continued_xfer !
/// reg continued_xfer; //continued_tile; // this is a continued tile (caused by page crossing) - only once
// reg [NUM_XFER_BITS-1:0] leftover; //[MAX_TILE_WIDTH-1:0] leftover_cols; // valid with continued_tile, number of columns left
// LINEAR using leftover_cols instead of leftover
// TODO: LINEAR: use num_cols_r instead of xfer_num128_r
// reg [NUM_XFER_BITS:0] xfer_num128_r; // number of 128-bit words to transfer (8*16 bits) - full bursts of 8
// end of (TILED: DNU)
wire pgm_param_w; // program one of the parameters, invalidate calculated results for PAR_MOD_LATENCY
reg [2:0] xfer_start_r;
// (LINEAR: DNU)
reg xfer_start_rd_r;
reg xfer_start_wr_r;
reg xfer_start32_rd_r;
reg xfer_start32_wr_r;
// (TILED: DNU)
reg xfer_start_lin_rd_r;
reg xfer_start_lin_wr_r;
// end of (TILED: DNU)
reg [PAR_MOD_LATENCY-1:0] par_mod_r;
reg [PAR_MOD_LATENCY-1:0] recalc_r; // 1-hot CE for re-calculating registers
// SuppressWarnings VEditor unused
wire calc_valid; // calculated registers have valid values - just for simulation
wire chn_en; // enable requests by channel (continue ones in progress), enable frame_start inputs
wire chn_rst; // resets command, including fifo;
reg chn_rst_d; // delayed by 1 cycle do detect turning off
wire abort_en; // enable frame abort (mode register bit)
reg aborting_r; // waiting pending memory transactions at if the frame was not finished at frame sync
reg aborting_d; // aborting_r delayed by 1 cycle // (LINEAR: DNU)
// LINEAR: wire with the same name wire frame_start_mod = (frame_start_late && !busy_r) || frame_start_delayed; // when frame_start_delayed it will completely miss a frame_start_late
reg frame_start_mod; // either original frame start pulse or delayed during abort (delayed by 1 cycle)
reg xfer_page_rst_r=1;
reg xfer_page_rst_pos=1;
reg xfer_page_rst_neg=1;
reg [2:0] page_cntr; // to maintain requests - difference between client requests and generated requests
// partial (truncated by memory page) generated requests should not count
wire cmd_wrmem; //= MCNTRL_TILED_WRITE_MODE; // 0: read from memory, 1:write to memory (change to parameter?) // (LINEAR: DNU)
wire [1:0] cmd_extra_pages; // external module needs more than 1 page
// wire skip_too_late; // from LINEAR
wire linear_mode; // use linear mode instead of tiles // (LINEAR: DNU)
wire byte32; // use 32-byte wide colums in each tile (0 - use 16-byte ones) // (LINEAR: DNU)
wire disable_need; // do not assert need, only want
wire repeat_frames; // mode bit
wire single_frame_w; // pulse
wire rst_frame_num_w;
wire set_copy_frame_num_w; // (LINEAR: DNU)
reg single_frame_r; // pulse
reg [1:0] rst_frame_num_r; // reset frame number/next start address
reg frame_en; // enable next frame
reg busy_r;
reg want_r;
reg want_d; // want_r delayed (no gap to pending_xfers)
reg need_r;
reg frame_done_r;
reg frame_finished_r;
wire last_in_row_w;
wire last_row_w;
reg last_block;
// MCNTRL_TILED_PENDING_CNTR_BITS == LINEAR:MCNTRL_SCANLINE_PENDING_CNTR_BITS
reg [MCNTRL_TILED_PENDING_CNTR_BITS-1:0] pending_xfers; // number of requested,. but not finished block transfers (to genearate frame done) // LINEAR:MCNTRL_SCANLINE_PENDING_CNTR_BITS
reg [NUM_RC_BURST_BITS-1:0] row_col_r;
reg [FRAME_HEIGHT_BITS-1:0] line_unfinished_relw_r;
reg [FRAME_HEIGHT_BITS-1:0] line_unfinished_r;
wire pre_want;
reg pre_want_r1; // LINEAR (equivalent)
`ifdef DEBUG_MCNTRL_TILED_EXTRA_STATUS
wire [13:0] status_data;
`else
`ifdef REPORT_FRAME_NUMBER
wire [LAST_FRAME_BITS+1:0] status_data;
`else
wire [1:0] status_data;
`endif
`endif
wire [3:0] cmd_a;
wire [31:0] cmd_data;
wire cmd_we;
wire set_mode_w;
wire set_status_w;
wire set_start_addr_w;
wire set_frame_size_w;
wire set_last_frame_w;
wire set_frame_width_w;
wire set_window_wh_w;
wire set_window_x0y0_w;
wire set_window_start_w;
wire set_tile_whs_w;
wire lsw13_zero=!(|cmd_data[FRAME_WIDTH_BITS-1:0]); // LSW 13 (FRAME_WIDTH_BITS) low bits are all 0 - set carry bit
wire msw_zero= !(|cmd_data[31:16]); // MSW all bits are 0 - set carry bit
wire tile_width_zero= !(|cmd_data[ 0+:MAX_TILE_WIDTH]); // (LINEAR: DNU)
wire tile_height_zero=!(|cmd_data[ 8+:MAX_TILE_HEIGHT]); // (LINEAR: DNU)
wire tile_vstep_zero= !(|cmd_data[16+:MAX_TILE_HEIGHT]); // (LINEAR: DNU)
reg [14:0] mode_reg;//mode register: {dis_need,repet,single,rst_frame,na,byte32,keep_open,extra_pages[1:0],write_mode,enable,!reset}
reg [NUM_RC_BURST_BITS-1:0] start_range_addr; // (programmed) First frame in range start (in {row,col8} in burst8, bank ==0
reg [NUM_RC_BURST_BITS-1:0] frame_size; // (programmed) First frame in range start (in {row,col8} in burst8, bank ==0
reg [LAST_FRAME_BITS-1:0] last_frame_number;
reg [NUM_RC_BURST_BITS-1:0] start_addr; // (programmed) Frame start (in {row,col8} in burst8, bank ==0
reg [NUM_RC_BURST_BITS-1:0] next_frame_start_addr;
reg [LAST_FRAME_BITS-1:0] frame_number_cntr;
reg [LAST_FRAME_BITS-1:0] frame_number_current;
reg is_last_frame;
reg [4:0] frame_start_r; // increased length to have time from line_unfinished to suspend (external)
// (LINEAR: DNU)
reg [MAX_TILE_WIDTH:0] tile_cols; // full number of columns in a tile (in bursts?)
reg [MAX_TILE_HEIGHT:0] tile_rows; // full number of rows in a tile
reg [MAX_TILE_HEIGHT:0] tile_vstep; // vertical step between rows of tiles
reg [MAX_TILE_WIDTH:0] num_cols_r; // full number of columns to transfer (not minus 1)
wire [MAX_TILE_WIDTH:0] num_cols_m1_w; // full number of columns to transfer minus 1 with extra bit
wire [MAX_TILE_HEIGHT:0] num_rows_m1_w; // full number of columns to transfer minus 1 with extra bit
// end of (LINEAR: DNU)
reg [FRAME_WIDTH_BITS:0] frame_full_width; // (programmed) increment combined row/col when moving to the next line
// frame_width rounded up to max transfer (half page) if frame_width> max transfer/2,
// otherwise (smaller widths) round up to the nearest power of 2
reg [FRAME_WIDTH_BITS:0] window_width; // (programmed) 0- max
reg [FRAME_HEIGHT_BITS:0] window_height; // (programmed) 0- max
reg [FRAME_WIDTH_BITS-1:0] window_x0; // (programmed) window left
reg [FRAME_HEIGHT_BITS-1:0] window_y0; // (programmed) window top
reg [FRAME_WIDTH_BITS-1:0] start_x; // (programmed) normally 0, copied to curr_x on frame_start
reg [FRAME_HEIGHT_BITS-1:0] start_y; // (programmed) normally 0, copied to curr_y on frame_start
// (LINEAR: DNU)
reg xfer_page_done_d; // next cycle after xfer_page_done
reg frame_master_pend; // set frame counter from the master frame number at next master_set
reg set_frame_from_master; // single-clock copy frame counter from the master channel
reg frames_in_sync_r;
// (TILED: DNU)
// reg xfer_done_d; // xfer_done delayed by 1 cycle (also includes xfer_skipped)
// reg [MCNTRL_SCANLINE_DLY_WIDTH-1:0] start_delay; // how much to delay frame start
// reg [MCNTRL_SCANLINE_DLY_WIDTH:0] start_delay_cntr = {MCNTRL_SCANLINE_DLY_WIDTH+1{1'b1}}; // start delay counter
// reg frame_start_late;
// wire set_start_delay_w;
// end of (TILED: DNU)
reg buf_reset_pend; // reset buffer page at next (late)frame sync (compressor should be disabled
// if total number of pages in a frame is not multiple of 4
wire chn_dis_delayed = chn_rst || (!chn_en && !busy_r); // reset if real reset or disabled and frame finished
`ifdef REPORT_FRAME_NUMBER
reg [LAST_FRAME_BITS-1:0] done_frame_number;
`endif
assign frames_in_sync = frames_in_sync_r; // (LINEAR: DNU)
assign frame_number = frame_number_current;
assign set_mode_w = cmd_we && (cmd_a== MCNTRL_TILED_MODE);
assign set_status_w = cmd_we && (cmd_a== MCNTRL_TILED_STATUS_CNTRL);
assign set_start_addr_w = cmd_we && (cmd_a== MCNTRL_TILED_STARTADDR);
assign set_frame_size_w = cmd_we && (cmd_a== MCNTRL_TILED_FRAME_SIZE);
assign set_last_frame_w = cmd_we && (cmd_a== MCNTRL_TILED_FRAME_LAST);
assign set_frame_width_w = cmd_we && (cmd_a== MCNTRL_TILED_FRAME_FULL_WIDTH);
assign set_window_wh_w = cmd_we && (cmd_a== MCNTRL_TILED_WINDOW_WH);
assign set_window_x0y0_w = cmd_we && (cmd_a== MCNTRL_TILED_WINDOW_X0Y0);
assign set_window_start_w = cmd_we && (cmd_a== MCNTRL_TILED_WINDOW_STARTXY);
assign set_tile_whs_w = cmd_we && (cmd_a== MCNTRL_TILED_TILE_WHS); // (LINEAR: DNU)
// assign set_start_delay_w = cmd_we && (cmd_a== MCNTRL_SCANLINE_START_DELAY); // (TILED: DNU)
assign single_frame_w = cmd_we && (cmd_a== MCNTRL_TILED_MODE) && cmd_data[MCONTR_LINTILE_SINGLE];
assign rst_frame_num_w = cmd_we && (cmd_a== MCNTRL_TILED_MODE) && cmd_data[MCONTR_LINTILE_RST_FRAME];
assign set_copy_frame_num_w = cmd_we && (cmd_a== MCNTRL_TILED_MODE) && cmd_data[MCONTR_LINTILE_COPY_FRAME]; // self-clearing bit // (LINEAR: DNU)
assign frame_start_conf = frame_start_r[3]; // frame_number valid ; // (LINEAR: DNU)
// assign frame_run = busy_r; // (TILED: DNU)
// assign frame_set = frame_start_r[3]; // (TILED: DNU)
// Set parameter registers
always @(posedge mclk) begin
if (mrst) mode_reg <= 0;
else if (set_mode_w) mode_reg <= cmd_data[14:0]; // [5:0];
if (mrst) single_frame_r <= 0;
else single_frame_r <= single_frame_w;
if (mrst) rst_frame_num_r <= 0;
else rst_frame_num_r <= {rst_frame_num_r[0], rst_frame_num_w}; // resetting only at specific command
if (mrst) start_range_addr <= 0;
else if (set_start_addr_w) start_range_addr <= cmd_data[NUM_RC_BURST_BITS-1:0];
if (mrst) frame_size <= 0;
else if (set_start_addr_w) frame_size <= 1; // default number of frames - just one
else if (set_frame_size_w) frame_size <= cmd_data[NUM_RC_BURST_BITS-1:0];
if (mrst) last_frame_number <= 0;
else if (set_last_frame_w) last_frame_number <= cmd_data[LAST_FRAME_BITS-1:0];
if (mrst) frame_full_width <= 0;
else if (set_frame_width_w) frame_full_width <= {lsw13_zero,cmd_data[FRAME_WIDTH_BITS-1:0]};
if (mrst) is_last_frame <= 0;
else is_last_frame <= frame_number_cntr >= last_frame_number; // trying to make it safe
`ifdef REPORT_FRAME_NUMBER
if (mrst) done_frame_number <= 0;
else if (frame_done_r) done_frame_number <= frame_number_cntr;
`endif
if (mrst) frame_start_r <= 0;
else frame_start_r <= {frame_start_r[3:0], frame_start_mod & frame_en}; // frame_start // LINEAR: frame_start_mod wire, not reg - compare?
if (!chn_en) frame_en <= 0;
else if (single_frame_r || repeat_frames) frame_en <= 1;
else if (frame_start_mod) frame_en <= 0; // LINEAR: frame_start_late
// (LINEAR: DNU)
if (mrst ||master_set) frame_master_pend <= 0;
else if (set_copy_frame_num_w) frame_master_pend <= 1;
// after channel was disabled frame number reported is incorrect, until updated by master_set
// Without this signal compressor was reading data between the time source frame number was updated and this one.
if (chn_dis_delayed) frames_in_sync_r <= 0; // do not invalidate frames_in_sync_r until busy_r is off
else if (frame_start_r[3]) frames_in_sync_r <= 1; // to match line_unfinished
// end of (LINEAR: DNU)
// will reset buffer page at next frame start
if (mrst ||frame_start_r[0]) buf_reset_pend <= 0;
else if (rst_frame_num_r[0]) buf_reset_pend <= 1;
set_frame_from_master <= master_set && frame_master_pend; // (LINEAR: DNU)
if (mrst) frame_number_cntr <= 0;
else if (rst_frame_num_r[0]) frame_number_cntr <= 0;
else if (set_frame_from_master) frame_number_cntr <= master_frame; // (LINEAR: DNU)
else if (frame_start_r[2]) frame_number_cntr <= is_last_frame?{LAST_FRAME_BITS{1'b0}}:(frame_number_cntr+1);
if (mrst) frame_number_current <= 0;
else if (rst_frame_num_r[0]) frame_number_current <= 0;
else if (frame_start_r[2]) frame_number_current <= frame_number_cntr;
if (mrst) next_frame_start_addr <= start_range_addr; // just to use rst
else if (rst_frame_num_r[1]) next_frame_start_addr <= start_range_addr;
else if (frame_start_r[2]) next_frame_start_addr <= is_last_frame? start_range_addr : (start_addr+frame_size);
if (mrst) start_addr <= start_range_addr; // just to use rst
else if (frame_start_r[0]) start_addr <= next_frame_start_addr;
if (mrst) begin
window_width <= 0;
window_height <= 0;
end else if (set_window_wh_w) begin
window_width <= {lsw13_zero,cmd_data[FRAME_WIDTH_BITS-1:0]};
window_height <= {msw_zero,cmd_data[FRAME_HEIGHT_BITS+15:16]};
end
// (LINEAR: DNU)
if (mrst) begin
tile_cols <= 0;
tile_rows <= 0;
tile_vstep <= 0;
end else if (set_tile_whs_w) begin
tile_cols <= {tile_width_zero, cmd_data[ 0+:MAX_TILE_WIDTH]};
tile_rows <= {tile_height_zero, cmd_data[ 8+:MAX_TILE_HEIGHT]};
tile_vstep <= {tile_vstep_zero, cmd_data[16+:MAX_TILE_HEIGHT]};
end
// end of (LINEAR: DNU)
if (mrst) begin
window_x0 <= 0;
window_y0 <= 0;
end else if (set_window_x0y0_w) begin
window_x0 <= cmd_data[FRAME_WIDTH_BITS-1:0];
window_y0 <=cmd_data[FRAME_HEIGHT_BITS+15:16];
end
if (mrst) begin
start_x <= 0;
start_y <= 0;
end else if (set_window_start_w) begin
start_x <= cmd_data[FRAME_WIDTH_BITS-1:0];
start_y <=cmd_data[FRAME_HEIGHT_BITS+15:16];
end
// (TILED: DNU)
// if (mrst) start_delay <= MCNTRL_SCANLINE_DLY_DEFAULT;
// else if (set_start_delay_w) start_delay <= cmd_data[MCNTRL_SCANLINE_DLY_WIDTH-1:0];
// if (mrst) start_delay_cntr <= {MCNTRL_SCANLINE_DLY_WIDTH+1{1'b1}};
// else if (frame_start) start_delay_cntr <= {1'b0, start_delay};
// else if (!start_delay_cntr[MCNTRL_SCANLINE_DLY_WIDTH]) start_delay_cntr <= start_delay_cntr - 1;
// frame_start_late <= start_delay_cntr == 0;
// end of (TILED: DNU)
end
assign mul_rslt_w= frame_y8_r * frame_full_width_r; // 5 MSBs will be discarded
assign xfer_num128= num_cols_r[MAX_TILE_WIDTH-1:0]; // One bit less! (TODO: for LINEAR)
// assign xfer_start= xfer_start_r[0];
assign xfer_start_lin_rd= xfer_start_lin_rd_r; // NEW
assign xfer_start_lin_wr= xfer_start_lin_wr_r; // NEW
assign xfer_start_rd= xfer_start_rd_r;
assign xfer_start_wr= xfer_start_wr_r;
assign xfer_start32_rd= xfer_start32_rd_r; // (LINEAR: DNU)
assign xfer_start32_wr= xfer_start32_wr_r; // (LINEAR: DNU)
assign calc_valid= par_mod_r[PAR_MOD_LATENCY-1]; // MSB, longest 0
assign xfer_page_rst_wr= xfer_page_rst_r; // MOVED to match LINEAR
assign xfer_page_rst_rd= xfer_page_rst_neg; // MOVED to match LINEAR
assign xfer_partial= xfer_limited_by_mem_page_r; // MOVED to match LINEAR
assign frame_done= frame_done_r;
assign frame_finished= frame_finished_r;
// Was, now using from linear - faster/equivalent
// assign pre_want= !chn_rst && busy_r && !want_r && !xfer_start_r[0] && calc_valid && !last_block && !suspend && !(|frame_start_r) && !aborting_r;
// LINEAR:
assign pre_want= pre_want_r1 && !want_r && !xfer_start_r[0] && !last_block && !suspend && !aborting_r;
assign last_in_row_w=(row_left=={{(FRAME_WIDTH_BITS-MAX_TILE_WIDTH){1'b0}},num_cols_r}); // what if it crosses page? OK, num_cols_r & row_left know that
// TODO: LINEAR: use num_cols_r instead of xfer_num128_r
// tiles must completely fit window
// all window should be covered (tiles may extend):
assign last_row_w= next_y >= window_height; // LINEAR: "++" instead of ">="
//window_m_tile_height
assign xfer_want= want_r;
assign xfer_need= need_r;
assign xfer_bank= bank_reg[2*3 +: 3]; // TODO: just a single reg layer
assign xfer_row= row_col_r[NUM_RC_BURST_BITS-1:COLADDR_NUMBER-3] ; // memory row
assign xfer_col= row_col_r[COLADDR_NUMBER-4:0]; // start memory column in 8-bursts
assign line_unfinished = line_unfinished_r;
assign chn_en = mode_reg[MCONTR_LINTILE_NRESET] & mode_reg[MCONTR_LINTILE_EN]; // enable requests by channel (continue ones in progress)
assign chn_rst = ~mode_reg[MCONTR_LINTILE_NRESET]; // resets command, including fifo;
assign cmd_wrmem = mode_reg[MCONTR_LINTILE_WRITE];// 0: read from memory, 1:write to memory
assign cmd_extra_pages = mode_reg[MCONTR_LINTILE_EXTRAPG+:MCONTR_LINTILE_EXTRAPG_BITS]; // external module needs more than 1 page
assign keep_open= mode_reg[MCONTR_LINTILE_KEEP_OPEN]; // keep banks open (will be used only if number of rows <= 8
assign byte32= mode_reg[MCONTR_LINTILE_BYTE32]; // use 32-byte wide columns in each tile (false - 16-byte)
assign linear_mode = mode_reg[MCONTR_LINTILE_LINEAR]; // NEW
assign repeat_frames= mode_reg[MCONTR_LINTILE_REPEAT];
assign disable_need = mode_reg[MCONTR_LINTILE_DIS_NEED];
// assign skip_too_late = mode_reg[MCONTR_LINTILE_SKIP_LATE]; // from LINEAR
assign abort_en = mode_reg[MCONTR_LINTILE_ABORT_LATE];
`ifdef DEBUG_MCNTRL_TILED_EXTRA_STATUS
assign status_data= {frames_in_sync, suspend, last_row_w, last_in_row,line_unfinished[7:0], frame_finished_r, busy_r};
`else
`ifdef REPORT_FRAME_NUMBER
assign status_data= {done_frame_number, frame_finished_r, busy_r}; // TODO: Add second bit?
`else
assign status_data= {frame_finished_r, busy_r}; // TODO: Add second bit?
`endif
`endif
assign pgm_param_w= cmd_we;
// LINEAR: matched
assign rowcol_inc= frame_full_width;
assign num_cols_m1_w= num_cols_r-1;
assign num_rows_m1_w= tile_rows-1; // now number of rows == tile height
assign num_cols_m1= num_cols_m1_w[MAX_TILE_WIDTH-1:0]; // remove MSB
assign num_rows_m1= num_rows_m1_w[MAX_TILE_HEIGHT-1:0]; // remove MSB
assign remainder_tile_width = {EXTRA_BITS,lim_by_tile_width} - mem_page_left;
integer i;
localparam [COLADDR_NUMBER-3-MAX_TILE_WIDTH-1:0] EXTRA_BITS=0;
wire xfer_limited_by_mem_page;
reg xfer_limited_by_mem_page_r;
assign xfer_limited_by_mem_page= keep_open && (mem_page_left < {EXTRA_BITS,lim_by_tile_width}); // if not keep_open - no need to break
//LINEAR - start match
always @(posedge mclk) begin // TODO: Match latencies (is it needed?) Reduce consumption by CE?
// cycle 1
if (recalc_r[0]) begin
frame_x <= curr_x + window_x0;
frame_y <= curr_y + window_y0;
next_y <= curr_y + (linear_mode? 1 : tile_vstep); // LINEAR: next_y <= curr_y + 1;
row_left <= window_width - curr_x; // 14 bits - 13 bits
end
// registers to be absorbed in DSP block
frame_y8_r <= frame_y[FRAME_HEIGHT_BITS-1:3]; // lat=2 // if (recalc_r[2]) begin
frame_full_width_r <= frame_full_width; //(cycle 2) // if (recalc_r[2]) begin
start_addr_r <= start_addr; // // if (recalc_r[2]) begin
mul_rslt <= mul_rslt_w[MPY_WIDTH-1:0]; // frame_y8_r * frame_width_r; // 7 bits will be discarded lat=3; if (recalc_r[3]) begin
line_start_addr <= start_addr_r+mul_rslt; // lat=4 if (recalc_r[4]) begin
// TODO: Verify MPY/register timing above
if (recalc_r[5]) begin // cycle 6
row_col_r <= line_start_addr+frame_x;
line_start_page_left <= - line_start_addr[COLADDR_NUMBER-4:0]; // 7 bits
end
bank_reg[0 +: 3] <= frame_y[2:0]; //TODO: is it needed - a pipeline for the bank? - remove!
for (i=0; i<2; i = i+1)
bank_reg[(i+1)*3 +: 3] <= bank_reg[i*3 +: 3];
if (recalc_r[6]) begin // cycle 7
mem_page_left <= {1'b1,line_start_page_left} - frame_x[COLADDR_NUMBER-4:0];
/*
lim_by_tile_width <= (|row_left[FRAME_WIDTH_BITS:MAX_TILE_WIDTH] || (row_left[MAX_TILE_WIDTH:0] >= tile_cols))?
tile_cols:
row_left[MAX_TILE_WIDTH:0]; // 7 bits, max 'h40
lim_by_xfer <= (|row_left[FRAME_WIDTH_BITS:NUM_XFER_BITS])? // TODO: used in LINEAR
(1<<NUM_XFER_BITS):
row_left[NUM_XFER_BITS:0]; // 7 bits, max 'h40
*/
lim_by_tile_width <= (|row_left[FRAME_WIDTH_BITS:MAX_TILE_WIDTH] || (!linear_mode && (row_left[MAX_TILE_WIDTH:0] >= tile_cols)))?
(linear_mode ? {(MAX_TILE_WIDTH + 1){1'b1}} : tile_cols):
row_left[MAX_TILE_WIDTH:0]; // 7 bits, max 'h40
end
//LINEAR - start match
if (recalc_r[7]) begin // cycle 8
xfer_limited_by_mem_page_r <= xfer_limited_by_mem_page && !continued_tile; // LINEAR continued_xfer -> continued_tile
/*
num_cols_r<= continued_tile? // LINEAR xfer_num128_r<= continued_xfer?
{EXTRA_BITS,leftover_cols}: // LINEAR {EXTRA_BITS,leftover}:
(xfer_limited_by_mem_page?
mem_page_left[MAX_TILE_WIDTH:0]: // LINEAR: mem_page_left[NUM_XFER_BITS:0]:
lim_by_tile_width[MAX_TILE_WIDTH:0]); // LINEAR lim_by_xfer[NUM_XFER_BITS:0]);
leftover_cols <= remainder_tile_width[MAX_TILE_WIDTH-1:0]; // TODO: !!! LINEAR - see next line
// LINEAR: if (!continued_xfer) leftover <= remainder_in_xfer[NUM_XFER_BITS-1:0]; // {EXTRA_BITS, lim_by_xfer}-mem_page_left;
*/
num_cols_r<= continued_tile? // LINEAR xfer_num128_r<= continued_xfer?
{EXTRA_BITS,leftover_cols}: // LINEAR : using leftover instead of leftover_cols {EXTRA_BITS,leftover}:
(xfer_limited_by_mem_page?
mem_page_left[MAX_TILE_WIDTH:0]: // LINEAR: mem_page_left[NUM_XFER_BITS:0]:
lim_by_tile_width[MAX_TILE_WIDTH:0]); // LINEAR lim_by_xfer[NUM_XFER_BITS:0]);
if (!linear_mode || continued_tile) leftover_cols <= remainder_tile_width[MAX_TILE_WIDTH-1:0];
end
if (recalc_r[8]) begin // cycle 9
last_in_row <= last_in_row_w;
end
// LINEAR: matched
end
// now have row start address, bank and row_left ;
// calculate number to read (min of row_left, maximal xfer and what is left in the DDR3 page
wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
always @(posedge mclk) begin
// acceletaring pre_want - copied from LINEAR (faster, equivalent), start matching
// pre_want_r1 <= !chn_rst && !frame_done_r && busy_r && par_mod_r[PAR_MOD_LATENCY-2] && !(|frame_start_r[4:1]);
// FIXME: Same in LINEAR module?
pre_want_r1 <= !chn_rst && !frame_done_r && busy_r && par_mod_r[PAR_MOD_LATENCY-2] && !(|frame_start_r[4:1]) &&!xfer_start_r[0];
if (mrst) par_mod_r<=0;
else if (pgm_param_w ||
xfer_start_r[0] ||
chn_rst ||
frame_start_r[0]) par_mod_r<=0;
else par_mod_r <= {par_mod_r[PAR_MOD_LATENCY-2:0], 1'b1};
if (mrst) chn_rst_d <= 0;
else chn_rst_d <= chn_rst;
if (mrst) recalc_r<=0;
else if (chn_rst) recalc_r<=0;
else recalc_r <= {recalc_r[PAR_MOD_LATENCY-2:0],
((xfer_start_r[0] | frame_start_r[0]) & ~chn_rst) | pgm_param_w | (chn_rst_d & ~chn_rst)};
if (mrst) busy_r <= 0;
else if (chn_rst) busy_r <= 0;
else if (frame_start_r[0]) busy_r <= 1;
else if (frame_done_r) busy_r <= 0;
if (mrst) xfer_page_done_d <= 0;
else xfer_page_done_d <= xfer_page_done; // LINEAR: xfer_done_skipped;
if (mrst) xfer_start_r <= 0;
else xfer_start_r <= {xfer_start_r[1:0],xfer_grant && !chn_rst}; // LINEAR uses skip_run
// LINEAR matched
// TILED and TILED_LIN only:
if (mrst) xfer_start_rd_r <= 0;
else xfer_start_rd_r <= xfer_grant && !chn_rst && !cmd_wrmem && !byte32;
if (mrst) xfer_start_wr_r <= 0;
else xfer_start_wr_r <= xfer_grant && !chn_rst && cmd_wrmem && !byte32;
if (mrst) xfer_start32_rd_r <= 0;
else xfer_start32_rd_r <= xfer_grant && !chn_rst && !cmd_wrmem && byte32;
if (mrst) xfer_start32_wr_r <= 0;
else xfer_start32_wr_r <= xfer_grant && !chn_rst && cmd_wrmem && byte32;
if (mrst) xfer_start_lin_rd_r <= 0;
else xfer_start_lin_rd_r <= xfer_grant && !chn_rst && !cmd_wrmem && linear_mode;
if (mrst) xfer_start_lin_wr_r <= 0;
else xfer_start_lin_wr_r <= xfer_grant && !chn_rst && cmd_wrmem && linear_mode;
// end TILED
if (mrst) continued_tile <= 1'b0; // LINEAR: replace continued_xfer with continued_tile
else if (chn_rst) continued_tile <= 1'b0;
else if (frame_start_r[0]) continued_tile <= 1'b0;
else if (xfer_start_r[0]) continued_tile <= xfer_limited_by_mem_page_r; // only set after actual start if it was partial, not after parameter change
// LINEAR matching start
if (mrst || disable_need) need_r <= 0;
else if (chn_rst || xfer_grant) need_r <= 0; // LINEAR else if (chn_rst || xfer_grant || start_skip_r) need_r <= 0;
else if ((pre_want || want_r) && (page_cntr>=3)) need_r <= 1; // may raise need if want was already set
if (mrst) want_r <= 0;
else if (chn_rst || xfer_grant) want_r <= 0; // LINEAR else if (chn_rst || xfer_grant || start_skip_r) want_r <= 0;
else if (pre_want && (page_cntr>{1'b0,cmd_extra_pages})) want_r <= 1;
want_d <= want_r;
if (mrst) page_cntr <= 0;
// else if (frame_start_r[0]) page_cntr <= cmd_wrmem?0:4; // reset here, but compressor is not// LINEAR: not commented out
else if (xfer_page_rst_pos) page_cntr <= cmd_wrmem?0:4; // reset here, but compressor is not
else if ( start_not_partial && !next_page) page_cntr <= page_cntr - 1;
else if (!start_not_partial && next_page) page_cntr <= page_cntr + 1;
if (mrst) xfer_page_rst_r <= 1;
else xfer_page_rst_r <= chn_rst || (buf_reset_pend && (MCNTRL_TILED_FRAME_PAGE_RESET ? (frame_start_r[0] & cmd_wrmem):1'b0));
if (mrst) xfer_page_rst_pos <= 1;
else xfer_page_rst_pos <= chn_rst || (buf_reset_pend && (MCNTRL_TILED_FRAME_PAGE_RESET ? (frame_start_r[0] & ~cmd_wrmem):1'b0));
// increment x,y (two cycles)
// TODO: LINEAR: use num_cols_r instead of xfer_num128_r
if (mrst) curr_x <= 0;
else if (chn_rst || frame_start_r[0]) curr_x <= start_x;
else if (xfer_start_r[0]) curr_x <= last_in_row?0: curr_x + num_cols_r; // LINEAR: xfer_num128_r;
if (mrst) curr_y <= 0;
else if (chn_rst || frame_start_r[0]) curr_y <= start_y;
else if (xfer_start_r[0] && last_in_row) curr_y <= next_y[FRAME_HEIGHT_BITS-1:0];
if (mrst) last_block <= 0;
else if (chn_rst || !busy_r) last_block <= 0;
else if (xfer_start_r[0]) last_block <= last_row_w && last_in_row_w;
// start_not_partial is not generated when partial (first of 2, caused by a tile crossing memory page) transfer is requested
// here we need to cout all requests - partial or not
if (mrst) pending_xfers <= 0;
else if (chn_rst || !busy_r) pending_xfers <= 0;
else if ( xfer_start_r[0] && !xfer_page_done) pending_xfers <= pending_xfers + 1; // LINEAR use xfer_done_skipped
else if (!xfer_start_r[0] && xfer_page_done) pending_xfers <= pending_xfers - 1; // page done is not generated on partial (first) pages // LINEAR use xfer_done_skipped
if (mrst) frame_done_r <= 0;
else frame_done_r <= busy_r && (pending_xfers==0) &&
((last_block && xfer_page_done_d) || (aborting_r && !want_r && !want_d)); // LINEAR use xfer_done_d instead of xfer_page_done_d (same)
if (!busy_r) aborting_r <= 0;
else if (abort_en && busy_r && frame_start) aborting_r <= 1;
aborting_d <= aborting_r; // (LINEAR: DNU)
frame_start_mod <= (frame_start && !busy_r) || (aborting_d && !aborting_r); // LINEAR: wire with the same name wire
// turns and stays on (used in status)
if (mrst) frame_finished_r <= 0;
else if (chn_rst || frame_start_r[0]) frame_finished_r <= 0;
else if (frame_done_r) frame_finished_r <= 1;
//TODO: ALready modified to include linear mode
// TILED: if (recalc_r[0]) line_unfinished_relw_r <= curr_y + (cmd_wrmem ? 0: tile_rows);
// LINEAR: if (recalc_r[0]) line_unfinished_relw_r <= curr_y + (cmd_wrmem ? 0: 1);
if (recalc_r[0]) line_unfinished_relw_r <= curr_y + (cmd_wrmem ? 0: (linear_mode? 1: tile_rows));
if (mrst || (frame_start_mod || chn_dis_delayed)) line_unfinished_r <= {FRAME_HEIGHT_BITS{~cmd_wrmem}}; // lowest/highest value until valid
else if (recalc_r[2] && busy_r) line_unfinished_r <= line_unfinished_relw_r + window_y0;
// LINEAR matching end
end
always @ (negedge mclk) begin
xfer_page_rst_neg <= xfer_page_rst_pos;
end
cmd_deser #(
.ADDR (MCNTRL_TILED_ADDR),
.ADDR_MASK (MCNTRL_TILED_MASK),
.NUM_CYCLES (6),
.ADDR_WIDTH (4),
.DATA_WIDTH (32)
) cmd_deser_32bit_i (
.rst (1'b0), // input
.clk (mclk), // input
.srst (mrst), // input
.ad (cmd_ad), // input[7:0]
.stb (cmd_stb), // input
.addr (cmd_a), // output[15:0]
.data (cmd_data), // output[31:0]
.we (cmd_we) // output
);
status_generate #(
.STATUS_REG_ADDR (MCNTRL_TILED_STATUS_REG_ADDR),
`ifdef DEBUG_MCNTRL_TILED_EXTRA_STATUS
.PAYLOAD_BITS (14)
`else
`ifdef REPORT_FRAME_NUMBER
.PAYLOAD_BITS (2 + LAST_FRAME_BITS)
`else
.PAYLOAD_BITS (2)
`endif
`endif
) status_generate_i (
.rst (1'b0), // input
.clk (mclk), // input
.srst (mrst), // input
.we (set_status_w), // input
.wd (cmd_data[7:0]), // input[7:0]
.status (status_data), // input[25:0]
.ad (status_ad), // output[7:0]
.rq (status_rq), // output
.start (status_start) // input
);
endmodule
...@@ -79,7 +79,8 @@ module mcntrl_tiled_rw#( ...@@ -79,7 +79,8 @@ module mcntrl_tiled_rw#(
parameter MCONTR_LINTILE_EXTRAPG = 3, // extra pages (over 1) needed by the client simultaneously parameter MCONTR_LINTILE_EXTRAPG = 3, // extra pages (over 1) needed by the client simultaneously
parameter MCONTR_LINTILE_EXTRAPG_BITS = 2, // number of bits to use for extra pages parameter MCONTR_LINTILE_EXTRAPG_BITS = 2, // number of bits to use for extra pages
parameter MCONTR_LINTILE_KEEP_OPEN = 5, // keep banks open (will be used only if number of rows <= 8) parameter MCONTR_LINTILE_KEEP_OPEN = 5, // keep banks open (will be used only if number of rows <= 8)
parameter MCONTR_LINTILE_BYTE32 = 6, // use 32-byte wide columns in each tile (false - 16-byte) parameter MCONTR_LINTILE_BYTE32 = 6, // use 32-byte wide columns in each tile (false - 16-byte)
parameter MCONTR_LINTILE_LINEAR = 7, // Use linear mode instead of tiled
parameter MCONTR_LINTILE_RST_FRAME = 8, // reset frame number parameter MCONTR_LINTILE_RST_FRAME = 8, // reset frame number
parameter MCONTR_LINTILE_SINGLE = 9, // read/write a single page parameter MCONTR_LINTILE_SINGLE = 9, // read/write a single page
parameter MCONTR_LINTILE_REPEAT = 10, // read/write pages until disabled parameter MCONTR_LINTILE_REPEAT = 10, // read/write pages until disabled
......
...@@ -974,7 +974,7 @@ class X393ExportC(object): ...@@ -974,7 +974,7 @@ class X393ExportC(object):
(("X393_CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2","",vrlg.CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2,0,None, None, "", "jp4, 4 blocks, differential, hdr,divide by 2")), (("X393_CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2","",vrlg.CMPRS_CBIT_CMODE_JP4DIFFHDRDIV2,0,None, None, "", "jp4, 4 blocks, differential, hdr,divide by 2")),
(("X393_CMPRS_CBIT_CMODE_MONO1", "", vrlg.CMPRS_CBIT_CMODE_MONO1 , 0, None, None, "", "Mono JPEG (not yet implemented)")), (("X393_CMPRS_CBIT_CMODE_MONO1", "", vrlg.CMPRS_CBIT_CMODE_MONO1 , 0, None, None, "", "Mono JPEG (not yet implemented)")),
(("X393_CMPRS_CBIT_CMODE_MONO4", "", vrlg.CMPRS_CBIT_CMODE_MONO4 , 0, None, None, "", "Mono, 4 blocks (2x2 macroblocks)")), (("X393_CMPRS_CBIT_CMODE_MONO4", "", vrlg.CMPRS_CBIT_CMODE_MONO4 , 0, None, None, "", "Mono, 4 blocks (2x2 macroblocks)")),
(("X393_CMPRS_CBIT_CMODE_RAW", "", vrlg.CMPRS_CBIT_CMODE_RAW , 0, None, None, "", "Uncompressed (raw), specify width/height in 16x16 byte macroblocks (in 16-bit 8 pixels wide)")),
(("X393_CMPRS_CBIT_FRAMES_SINGLE", "", vrlg.CMPRS_CBIT_FRAMES_SINGLE , 0, None, None, "", "Use single-frame buffer")), (("X393_CMPRS_CBIT_FRAMES_SINGLE", "", vrlg.CMPRS_CBIT_FRAMES_SINGLE , 0, None, None, "", "Use single-frame buffer")),
(("X393_CMPRS_CBIT_FRAMES_MULTI", "", 1 , 0, None, None, "", "Use multi-frame buffer"))] (("X393_CMPRS_CBIT_FRAMES_MULTI", "", 1 , 0, None, None, "", "Use multi-frame buffer"))]
ba = vrlg.CMPRS_GROUP_ADDR ba = vrlg.CMPRS_GROUP_ADDR
...@@ -1691,6 +1691,7 @@ class X393ExportC(object): ...@@ -1691,6 +1691,7 @@ class X393ExportC(object):
dw.append(("extra_pages", vrlg.MCONTR_LINTILE_EXTRAPG, vrlg.MCONTR_LINTILE_EXTRAPG_BITS,0, "2-bit number of extra pages that need to stay (not to be overwritten) in the buffer")) dw.append(("extra_pages", vrlg.MCONTR_LINTILE_EXTRAPG, vrlg.MCONTR_LINTILE_EXTRAPG_BITS,0, "2-bit number of extra pages that need to stay (not to be overwritten) in the buffer"))
dw.append(("keep_open", vrlg.MCONTR_LINTILE_KEEP_OPEN,1,0, "for 8 or less rows - do not close page between accesses (not used in scanline mode)")) dw.append(("keep_open", vrlg.MCONTR_LINTILE_KEEP_OPEN,1,0, "for 8 or less rows - do not close page between accesses (not used in scanline mode)"))
dw.append(("byte32", vrlg.MCONTR_LINTILE_BYTE32,1,1, "32-byte columns (0 - 16-byte), not used in scanline mode")) dw.append(("byte32", vrlg.MCONTR_LINTILE_BYTE32,1,1, "32-byte columns (0 - 16-byte), not used in scanline mode"))
dw.append(("linear", vrlg.MCONTR_LINTILE_LINEAR,1,1, "Use linear mode instead of tiled (for raw image files): extra_pages=0, keep_open=x, byte32=x"))
dw.append(("reset_frame", vrlg.MCONTR_LINTILE_RST_FRAME,1,0, "reset frame number (also resets buffer at next frame start). NEEDED after initial set up to propagate start address!")) dw.append(("reset_frame", vrlg.MCONTR_LINTILE_RST_FRAME,1,0, "reset frame number (also resets buffer at next frame start). NEEDED after initial set up to propagate start address!"))
dw.append(("single", vrlg.MCONTR_LINTILE_SINGLE,1,0, "run single frame")) dw.append(("single", vrlg.MCONTR_LINTILE_SINGLE,1,0, "run single frame"))
dw.append(("repetitive", vrlg.MCONTR_LINTILE_REPEAT,1,1, "run repetitive frames")) dw.append(("repetitive", vrlg.MCONTR_LINTILE_REPEAT,1,1, "run repetitive frames"))
...@@ -2312,6 +2313,8 @@ class X393ExportC(object): ...@@ -2312,6 +2313,8 @@ class X393ExportC(object):
dw.append(("cmode_set" , vrlg.CMPRS_CBIT_CMODE, 1, 0, "Set 'cmode'")) dw.append(("cmode_set" , vrlg.CMPRS_CBIT_CMODE, 1, 0, "Set 'cmode'"))
dw.append(("multiframe", vrlg.CMPRS_CBIT_FRAMES - vrlg.CMPRS_CBIT_FRAMES_BITS, vrlg.CMPRS_CBIT_FRAMES_BITS, 0, "Multi/single frame mode")) dw.append(("multiframe", vrlg.CMPRS_CBIT_FRAMES - vrlg.CMPRS_CBIT_FRAMES_BITS, vrlg.CMPRS_CBIT_FRAMES_BITS, 0, "Multi/single frame mode"))
dw.append(("multiframe_set", vrlg.CMPRS_CBIT_FRAMES, 1, 0, "Set 'multiframe'")) dw.append(("multiframe_set", vrlg.CMPRS_CBIT_FRAMES, 1, 0, "Set 'multiframe'"))
dw.append(("raw_be16", vrlg.CMPRS_CBIT_BE16 - vrlg.CMPRS_CBIT_BE16_BITS, vrlg.CMPRS_CBIT_BE16_BITS, 0, "Swap bytes in each pair (raw mode only), use with 16-bit data"))
dw.append(("raw_be16_set", vrlg.CMPRS_CBIT_BE16, 1, 0, "Set 'multiframe'"))
dw.append(("bayer", vrlg.CMPRS_CBIT_BAYER - vrlg.CMPRS_CBIT_BAYER_BITS, vrlg.CMPRS_CBIT_BAYER_BITS, 0, "Bayer shift")) dw.append(("bayer", vrlg.CMPRS_CBIT_BAYER - vrlg.CMPRS_CBIT_BAYER_BITS, vrlg.CMPRS_CBIT_BAYER_BITS, 0, "Bayer shift"))
dw.append(("bayer_set", vrlg.CMPRS_CBIT_BAYER, 1, 0, "Set 'bayer'")) dw.append(("bayer_set", vrlg.CMPRS_CBIT_BAYER, 1, 0, "Set 'bayer'"))
dw.append(("focus", vrlg.CMPRS_CBIT_FOCUS - vrlg.CMPRS_CBIT_FOCUS_BITS, vrlg.CMPRS_CBIT_FOCUS_BITS, 0, "Focus mode")) dw.append(("focus", vrlg.CMPRS_CBIT_FOCUS - vrlg.CMPRS_CBIT_FOCUS_BITS, vrlg.CMPRS_CBIT_FOCUS_BITS, 0, "Focus mode"))
......
...@@ -46,7 +46,7 @@ ...@@ -46,7 +46,7 @@
// https://forums.xilinx.com/t5/Embedded-Processor-System-Design/AXI4-Bursts-4KB-Address-Boundary-Limitation/td-p/216413 // https://forums.xilinx.com/t5/Embedded-Processor-System-Design/AXI4-Bursts-4KB-Address-Boundary-Limitation/td-p/216413
// Interconnect does not have 4K limit, and compressed data can only go to interconnect (memory), so it is OK to violate AXI specs here // Interconnect does not have 4K limit, and compressed data can only go to interconnect (memory), so it is OK to violate AXI specs here
`define AXI_4K_LIMIT_DISABLE // Current x393 code (only simulation modules) does not have it implemented, defining it causes mismatch synth/sim `define AXI_4K_LIMIT_DISABLE // Current x393 code (only simulation modules) does not have it implemented, defining it causes mismatch synth/sim
`define DEBUG_COMPRESSOR_SCRAMBLE `define DEBUG_COMPRESSOR_SCRAMBLE // ======== WTF? ======== is undefined in synthesis mode
`define DEBUG_DCT1D // undefine after debugging is over `define DEBUG_DCT1D // undefine after debugging is over
// `define USE_OLD_DCT // `define USE_OLD_DCT
...@@ -64,7 +64,7 @@ ...@@ -64,7 +64,7 @@
`define PRELOAD_BRAMS `define PRELOAD_BRAMS
`define DISPLAY_COMPRESSED_DATA `define DISPLAY_COMPRESSED_DATA
// if HISPI is not defined, parallel sensor interface is used for all channels // if HISPI is not defined, parallel sensor interface is used for all channels
`define HISPI /*************** CHANGE here and x393_hispi/x393_parallel in bitstream tool settings ****************/ // `define HISPI /*************** CHANGE here and x393_hispi/x393_parallel in bitstream tool settings ****************/
`define MON_HISPI // Measure HISPI timing `define MON_HISPI // Measure HISPI timing
// `define USE_OLD_XDCT393 // `define USE_OLD_XDCT393
// `define USE_PCLK2X // `define USE_PCLK2X
...@@ -188,32 +188,32 @@ ...@@ -188,32 +188,32 @@
`define def_scanline_chn11 `define def_scanline_chn11
`undef def_tiled_chn11 `undef def_tiled_chn11
// chn 12 is tiled read (compressor channel 0) // chn 12 is tiled read + scanline read (for Tiff) (compressor channel 0)
`define def_enable_mem_chn12 `define def_enable_mem_chn12
`define def_read_mem_chn12 `define def_read_mem_chn12
`undef def_write_mem_chn12 `undef def_write_mem_chn12
`undef def_scanline_chn12 `define def_scanline_chn12
`define def_tiled_chn12 `define def_tiled_chn12
// chn 12 is tiled read (compressor channel 1) // chn 13 is tiled read + scanline read (for Tiff) (compressor channel 1)
`define def_enable_mem_chn13 `define def_enable_mem_chn13
`define def_read_mem_chn13 `define def_read_mem_chn13
`undef def_write_mem_chn13 `undef def_write_mem_chn13
`undef def_scanline_chn13 `define def_scanline_chn13
`define def_tiled_chn13 `define def_tiled_chn13
// chn 12 is tiled read (compressor channel 2) // chn 14 is tiled read + scanline read (for Tiff) (compressor channel 2)
`define def_enable_mem_chn14 `define def_enable_mem_chn14
`define def_read_mem_chn14 `define def_read_mem_chn14
`undef def_write_mem_chn14 `undef def_write_mem_chn14
`undef def_scanline_chn14 `define def_scanline_chn14
`define def_tiled_chn14 `define def_tiled_chn14
// chn 12 is tiled read (compressor channel 3) // chn 15 is tiled read + scanline read (for Tiff) (compressor channel 3)
`define def_enable_mem_chn15 `define def_enable_mem_chn15
`define def_read_mem_chn15 `define def_read_mem_chn15
`undef def_write_mem_chn15 `undef def_write_mem_chn15
`undef def_scanline_chn15 `define def_scanline_chn15
`define def_tiled_chn15 `define def_tiled_chn15
`endif `endif
\ No newline at end of file
...@@ -1317,6 +1317,7 @@ assign axi_grst = axi_rst_pre; ...@@ -1317,6 +1317,7 @@ assign axi_grst = axi_rst_pre;
.MCONTR_LINTILE_EXTRAPG_BITS (MCONTR_LINTILE_EXTRAPG_BITS), .MCONTR_LINTILE_EXTRAPG_BITS (MCONTR_LINTILE_EXTRAPG_BITS),
.MCONTR_LINTILE_KEEP_OPEN (MCONTR_LINTILE_KEEP_OPEN), .MCONTR_LINTILE_KEEP_OPEN (MCONTR_LINTILE_KEEP_OPEN),
.MCONTR_LINTILE_BYTE32 (MCONTR_LINTILE_BYTE32), .MCONTR_LINTILE_BYTE32 (MCONTR_LINTILE_BYTE32),
.MCONTR_LINTILE_LINEAR (MCONTR_LINTILE_LINEAR), // Use linear mode instead of tiled
.MCONTR_LINTILE_RST_FRAME (MCONTR_LINTILE_RST_FRAME), .MCONTR_LINTILE_RST_FRAME (MCONTR_LINTILE_RST_FRAME),
.MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE), .MCONTR_LINTILE_SINGLE (MCONTR_LINTILE_SINGLE),
.MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT), .MCONTR_LINTILE_REPEAT (MCONTR_LINTILE_REPEAT),
...@@ -2042,6 +2043,8 @@ assign axi_grst = axi_rst_pre; ...@@ -2042,6 +2043,8 @@ assign axi_grst = axi_rst_pre;
.CMPRS_CBIT_CMODE_BITS (CMPRS_CBIT_CMODE_BITS), .CMPRS_CBIT_CMODE_BITS (CMPRS_CBIT_CMODE_BITS),
.CMPRS_CBIT_FRAMES (CMPRS_CBIT_FRAMES), .CMPRS_CBIT_FRAMES (CMPRS_CBIT_FRAMES),
.CMPRS_CBIT_FRAMES_BITS (CMPRS_CBIT_FRAMES_BITS), .CMPRS_CBIT_FRAMES_BITS (CMPRS_CBIT_FRAMES_BITS),
.CMPRS_CBIT_BE16 (CMPRS_CBIT_BE16),
.CMPRS_CBIT_BE16_BITS (CMPRS_CBIT_BE16_BITS),
.CMPRS_CBIT_BAYER (CMPRS_CBIT_BAYER), .CMPRS_CBIT_BAYER (CMPRS_CBIT_BAYER),
.CMPRS_CBIT_BAYER_BITS (CMPRS_CBIT_BAYER_BITS), .CMPRS_CBIT_BAYER_BITS (CMPRS_CBIT_BAYER_BITS),
.CMPRS_CBIT_FOCUS (CMPRS_CBIT_FOCUS), .CMPRS_CBIT_FOCUS (CMPRS_CBIT_FOCUS),
......
No preview for this file type
...@@ -258,7 +258,24 @@ end ...@@ -258,7 +258,24 @@ end
endmodule endmodule
`endif `endif
module gtxe2_chnl_clocking( module gtxe2_chnl_clocking#(
parameter [23:0] CPLL_CFG = 29'h00BC07DC,
parameter integer CPLL_FBDIV = 4,
parameter integer CPLL_FBDIV_45 = 5,
parameter [23:0] CPLL_INIT_CFG = 24'h00001E,
parameter [15:0] CPLL_LOCK_CFG = 16'h01E8,
parameter integer CPLL_REFCLK_DIV = 1,
parameter SATA_CPLL_CFG = "VCO_3000MHZ",
parameter [1:0] PMA_RSV3 = 1,
parameter TXOUT_DIV = 2,
//parameter TXRATE = 3'b000;
parameter RXOUT_DIV = 2,
//parameter RXRATE = 3'b000;
parameter TX_INT_DATAWIDTH = 0,
parameter TX_DATA_WIDTH = 20,
parameter RX_INT_DATAWIDTH = 0,
parameter RX_DATA_WIDTH = 20
)(
// top-level interfaces // top-level interfaces
input wire [2:0] CPLLREFCLKSEL, input wire [2:0] CPLLREFCLKSEL,
input wire GTREFCLK0, input wire GTREFCLK0,
...@@ -314,6 +331,7 @@ module gtxe2_chnl_clocking( ...@@ -314,6 +331,7 @@ module gtxe2_chnl_clocking(
input [19:0] TSTIN input [19:0] TSTIN
); );
// CPLL // CPLL
/*
parameter [23:0] CPLL_CFG = 29'h00BC07DC; parameter [23:0] CPLL_CFG = 29'h00BC07DC;
parameter integer CPLL_FBDIV = 4; parameter integer CPLL_FBDIV = 4;
parameter integer CPLL_FBDIV_45 = 5; parameter integer CPLL_FBDIV_45 = 5;
...@@ -332,18 +350,8 @@ parameter TX_INT_DATAWIDTH = 0; ...@@ -332,18 +350,8 @@ parameter TX_INT_DATAWIDTH = 0;
parameter TX_DATA_WIDTH = 20; parameter TX_DATA_WIDTH = 20;
parameter RX_INT_DATAWIDTH = 0; parameter RX_INT_DATAWIDTH = 0;
parameter RX_DATA_WIDTH = 20; parameter RX_DATA_WIDTH = 20;
/*
localparam tx_serial_divider = TXRATE == 3'b001 ? 1
: TXRATE == 3'b010 ? 2
: TXRATE == 3'b011 ? 4
: TXRATE == 3'b100 ? 8
: TXRATE == 3'b101 ? 16 : TXOUT_DIV ;
localparam rx_serial_divider = RXRATE == 3'b001 ? 1
: RXRATE == 3'b010 ? 2
: RXRATE == 3'b011 ? 4
: RXRATE == 3'b100 ? 8
: RXRATE == 3'b101 ? 16 : RXOUT_DIV ;
*/ */
localparam tx_pma_divider1 = TX_INT_DATAWIDTH == 1 ? 4 : 2; localparam tx_pma_divider1 = TX_INT_DATAWIDTH == 1 ? 4 : 2;
localparam tx_pcs_divider1 = tx_pma_divider1; localparam tx_pcs_divider1 = tx_pma_divider1;
localparam tx_pma_divider2 = TX_DATA_WIDTH == 20 | TX_DATA_WIDTH == 40 | TX_DATA_WIDTH == 80 ? 5 : 4; localparam tx_pma_divider2 = TX_DATA_WIDTH == 20 | TX_DATA_WIDTH == 40 | TX_DATA_WIDTH == 80 ? 5 : 4;
...@@ -360,6 +368,11 @@ wire TXPLLREFCLK_DIV2; ...@@ -360,6 +368,11 @@ wire TXPLLREFCLK_DIV2;
wire RXPLLREFCLK_DIV1; wire RXPLLREFCLK_DIV1;
wire RXPLLREFCLK_DIV2; wire RXPLLREFCLK_DIV2;
assign GTREFCLKMONITOR = 'bx; // Was not assigned
assign TXOUTCLKFABRIC = 'bx; // Was not assigned
assign RXOUTCLKFABRIC = 'bx; // Was not assigned
assign tx_phy_clk = TXSYSCLKSEL[0] ? QPLLCLK : cpll_clk_out; assign tx_phy_clk = TXSYSCLKSEL[0] ? QPLLCLK : cpll_clk_out;
assign TXPLLREFCLK_DIV1 = TXSYSCLKSEL[1] ? QPLLREFCLK : clk_mux_out; assign TXPLLREFCLK_DIV1 = TXSYSCLKSEL[1] ? QPLLREFCLK : clk_mux_out;
assign rx_phy_clk = RXSYSCLKSEL[0] ? QPLLCLK : cpll_clk_out; assign rx_phy_clk = RXSYSCLKSEL[0] ? QPLLCLK : cpll_clk_out;
...@@ -2358,6 +2371,8 @@ rx( ...@@ -2358,6 +2371,8 @@ rx(
.serial_clk (rx_serial_clk) .serial_clk (rx_serial_clk)
); );
wire tx_piso_clk;
wire rx_sipo_clk;
gtxe2_chnl_clocking #( gtxe2_chnl_clocking #(
.CPLL_CFG (CPLL_CFG), .CPLL_CFG (CPLL_CFG),
.CPLL_FBDIV (CPLL_FBDIV), .CPLL_FBDIV (CPLL_FBDIV),
...@@ -2374,8 +2389,7 @@ gtxe2_chnl_clocking #( ...@@ -2374,8 +2389,7 @@ gtxe2_chnl_clocking #(
.TX_DATA_WIDTH (TX_DATA_WIDTH), .TX_DATA_WIDTH (TX_DATA_WIDTH),
.RX_INT_DATAWIDTH (RX_INT_DATAWIDTH), .RX_INT_DATAWIDTH (RX_INT_DATAWIDTH),
.RX_DATA_WIDTH (RX_DATA_WIDTH) .RX_DATA_WIDTH (RX_DATA_WIDTH)
) ) clocking_i ( // was "clocking" w/o "_i" - is it a keyword?
clocking(
.CPLLREFCLKSEL (CPLLREFCLKSEL), .CPLLREFCLKSEL (CPLLREFCLKSEL),
.GTREFCLK0 (GTREFCLK0), .GTREFCLK0 (GTREFCLK0),
.GTREFCLK1 (GTREFCLK1), .GTREFCLK1 (GTREFCLK1),
...@@ -2410,7 +2424,7 @@ clocking( ...@@ -2410,7 +2424,7 @@ clocking(
.TXOUTCLK (TXOUTCLK), .TXOUTCLK (TXOUTCLK),
.TXOUTCLKFABRIC (TXOUTCLKFABRIC), .TXOUTCLKFABRIC (TXOUTCLKFABRIC),
.tx_serial_clk (tx_serial_clk), .tx_serial_clk (tx_serial_clk),
.tx_piso_clk (), .tx_piso_clk (tx_piso_clk),
.GTRSVD (GTRSVD), .GTRSVD (GTRSVD),
.PCSRSVDIN (PCSRSVDIN), .PCSRSVDIN (PCSRSVDIN),
...@@ -2425,9 +2439,10 @@ clocking( ...@@ -2425,9 +2439,10 @@ clocking(
.RXOUTCLK (RXOUTCLK), .RXOUTCLK (RXOUTCLK),
.RXOUTCLKFABRIC (RXOUTCLKFABRIC), .RXOUTCLKFABRIC (RXOUTCLKFABRIC),
.rx_serial_clk (rx_serial_clk), .rx_serial_clk (rx_serial_clk),
.rx_sipo_clk () .rx_sipo_clk (rx_sipo_clk)
); );
endmodule endmodule
module GTXE2_GPL( module GTXE2_GPL(
......
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