Commit 6030b5c1 authored by Andrey Filippov's avatar Andrey Filippov

minor clean up

parent e5eb5f5e
...@@ -182,7 +182,7 @@ module mcntrl_linear_rw #( ...@@ -182,7 +182,7 @@ module mcntrl_linear_rw #(
reg frame_finished_r; reg frame_finished_r;
wire last_in_row_w; wire last_in_row_w;
wire last_row_w; wire last_row_w;
wire last_block_w; // wire last_block_w;
reg last_block; reg last_block;
reg [MCNTRL_SCANLINE_PENDING_CNTR_BITS-1:0] pending_xfers; // number of requested,. but not finished block transfers reg [MCNTRL_SCANLINE_PENDING_CNTR_BITS-1:0] pending_xfers; // number of requested,. but not finished block transfers
reg [NUM_RC_BURST_BITS-1:0] row_col_r; reg [NUM_RC_BURST_BITS-1:0] row_col_r;
......
...@@ -36,7 +36,7 @@ ...@@ -36,7 +36,7 @@
//`define DEBUG_FIFO 1 //`define DEBUG_FIFO 1
`include "system_defines.vh" `include "system_defines.vh"
module x393 #( module x393 #(
`include "includes/x393_parameters.vh" `include "includes/x393_parameters.vh" // SuppressThisWarning VEditor - some not used
)( )(
// Sensors interface: I/O pads, pin names match circuit diagram (each sensor) // Sensors interface: I/O pads, pin names match circuit diagram (each sensor)
`ifdef HISPI `ifdef HISPI
...@@ -481,7 +481,7 @@ module x393 #( ...@@ -481,7 +481,7 @@ module x393 #(
wire [255:0] sens_buf_dout; // (), // output[63:0] wire [255:0] sens_buf_dout; // (), // output[63:0]
wire [3:0] sens_page_written; // single mclk pulse: buffer page (full or partial) is written to the memory buffer wire [3:0] sens_page_written; // single mclk pulse: buffer page (full or partial) is written to the memory buffer
// TODO: Add counter(s) to count sens_xfer_skipped pulses // TODO: Add counter(s) to count sens_xfer_skipped pulses
wire [3:0] sens_xfer_skipped; // single mclk pulse on every skipped (not written) block to record error statistics wire [3:0] sens_xfer_skipped; // single mclk pulse on every skipped (not written) block to record error statistics // SuppressThisWarning VEditor - unused
wire [3:0] sens_first_wr_in_frame; // single mclk pulse on first write block in each frame wire [3:0] sens_first_wr_in_frame; // single mclk pulse on first write block in each frame
wire trigger_mode; // (), // input wire trigger_mode; // (), // input
...@@ -1327,6 +1327,7 @@ assign axi_grst = axi_rst_pre; ...@@ -1327,6 +1327,7 @@ assign axi_grst = axi_rst_pre;
.cmprs_buf_din (cmprs_buf_din), // output[255:0] .cmprs_buf_din (cmprs_buf_din), // output[255:0]
.cmprs_page_ready (cmprs_page_ready), // output[3:0] .cmprs_page_ready (cmprs_page_ready), // output[3:0]
.cmprs_next_page (cmprs_next_page), // input[3:0] .cmprs_next_page (cmprs_next_page), // input[3:0]
.cmprs_first_rd_in_frame (), // output[3:0] reg
.cmprs_frame_start_dst (cmprs_frame_start_dst), // input[3:0] .cmprs_frame_start_dst (cmprs_frame_start_dst), // input[3:0]
.cmprs_line_unfinished_src (cmprs_line_unfinished_src), // output[63:0] .cmprs_line_unfinished_src (cmprs_line_unfinished_src), // output[63:0]
.cmprs_frame_number_src (cmprs_frame_number_src), // output[63:0] .cmprs_frame_number_src (cmprs_frame_number_src), // output[63:0]
......
...@@ -64,8 +64,6 @@ wire axi_rst; ...@@ -64,8 +64,6 @@ wire axi_rst;
wire hclk; wire hclk;
wire comb_rst; wire comb_rst;
reg axi_rst_pre; reg axi_rst_pre;
reg axi_rst_pre;
wire [31:0] maxi1_araddr; wire [31:0] maxi1_araddr;
......
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