implemented 4-channel data transfer to the system memory over a single s_axi

axi/cmprs_afi_mux.v

@@ -49,7 +49,7 @@ module  cmprs_afi_mux#(
     output                        fifo_ren0,
     input                  [63:0] fifo_rdata0,
 //    input                         fifo_eof0,        // single rclk pulse signalling EOF
-    output                        eof_written0,   // confirm frame written ofer AFI to the system memory (single rclk pulse)
+    output                        eof_written0,   // confirm frame written over AFI to the system memory (single hclk pulse)
     input                         fifo_flush0,    // EOF, need to output all what is in FIFO (Stays active until enough data chunks are read)
     input                  [7:0]  fifo_count0,     // number of 32-byte chunks in FIFO
 
@@ -58,7 +58,7 @@ module  cmprs_afi_mux#(
     output                        fifo_ren1,
     input                  [63:0] fifo_rdata1,
 //    input                         fifo_eof1,        // single rclk pulse signalling EOF
-    output                        eof_written1,   // confirm frame written ofer AFI to the system memory (single rclk pulse)
+    output                        eof_written1,   // confirm frame written over AFI to the system memory (single hclk pulse)
     input                         fifo_flush1,    // EOF, need to output all what is in FIFO (Stays active until enough data chunks are read)
     input                  [7:0]  fifo_count1,     // number of 32-byte chunks in FIFO
 
@@ -67,7 +67,7 @@ module  cmprs_afi_mux#(
     output                        fifo_ren2,
     input                  [63:0] fifo_rdata2,
 //    input                         fifo_eof2,        // single rclk pulse signalling EOF
-    output                        eof_written2,   // confirm frame written ofer AFI to the system memory (single rclk pulse)
+    output                        eof_written2,   // confirm frame written over AFI to the system memory (single hclk pulse)
     input                         fifo_flush2,    // EOF, need to output all what is in FIFO (Stays active until enough data chunks are read)
     input                  [7:0]  fifo_count2,     // number of 32-byte chunks in FIFO
 
@@ -76,7 +76,7 @@ module  cmprs_afi_mux#(
     output                        fifo_ren3,
     input                  [63:0] fifo_rdata3,
 //    input                         fifo_eof3,        // single rclk pulse signalling EOF
-    output                        eof_written3,   // confirm frame written ofer AFI to the system memory (single rclk pulse)
+    output                        eof_written3,   // confirm frame written over AFI to the system memory (single hclk pulse)
     input                         fifo_flush3,    // EOF, need to output all what is in FIFO (Stays active until enough data chunks are read)
     input                  [7:0]  fifo_count3,     // number of 32-byte chunks in FIFO
     

axi/cmprs_afi_mux_ptr.v

@@ -28,10 +28,10 @@ module  cmprs_afi_mux_ptr(
     input                  [ 2:0] sa_len_wa,          // channel address to write sa/lengths
     input                         sa_len_we,          // write enable sa/length data
     
-    input                         en,                 // 0 - resets, 0->1 resets all pointers. While rezset allows write response
+    input                         en,                 // 0 - resets, 0->1 resets all pointers. While reset allows write response
     input                  [ 3:0] reset_pointers,     // per-channel - reset pointers
     input                         pre_busy_w,         // combinatorial signal - one before busy[0] (depends on ptr_resetting)
-    input                  [ 1:0] winner_channel,     // channel that won arbitration for AXI axxess, valid @ pre_busy_w
+    input                  [ 1:0] winner_channel,     // channel that won arbitration for AXI access, valid @ pre_busy_w
     input                         need_to_bother,     // whants to start access if address and data FIFO permit
     input                   [2:0] chunk_inc,          // how much to increment chunk pointer (1..4) - valid witrh busy[0]
     

axi/cmprs_afi_mux_ptr_wresp.v

@@ -28,7 +28,7 @@ module  cmprs_afi_mux_ptr_wresp(
     input                  [ 1:0] length_wa,          // channel address to write lengths
     input                         length_we,          // write enable length data
     
-    input                         en,                 // 0 - resets, 0->1 resets all pointers. While rezset allows write response
+    input                         en,                 // 0 - resets, 0->1 resets all pointers. While reset allows write response
     input                  [ 3:0] reset_pointers,     // per-channel - reset pointers
     
     input                  [ 2:0] chunk_ptr_ra,       // chunk pointer read address {eof, chn[1:0]}

axi/histogram_saxi.v

@@ -31,7 +31,7 @@ module  histogram_saxi#(
       parameter HIST_SAXI_EN =           0,
       parameter HIST_SAXI_NRESET =       1,
       parameter HIST_CONFIRM_WRITE =     2, // wait write confirmation for each block
-      parameter HIST_SAXI_AWCACHE =      4, //..7 cache mode (4 bits, default 4'h3)
+      parameter HIST_SAXI_AWCACHE =      4'h3, //..7 cache mode (4 bits, default 4'h3)
       
     parameter HIST_SAXI_MODE_ADDR_MASK = 'h3ff,
 //    parameter HIST_SAXI_STATUS_REG =     'h34,
@@ -237,10 +237,10 @@ module  histogram_saxi#(
     assign saxi_wstrb =    4'hf; // All bytes
     
       
-    // TODO: MAybe reduce pause between 16-burst pages? Allow some overlap? 
+    // TODO: Maybe reduce pause between 16-burst pages? Allow some overlap? 
     assign buf_re_w = en_aclk && (|pages_in_buf_rd) && !fifo_half_full && !(&page_ra) && page_read_run; // will stay off until next page
     assign fifo_re= saxi_wvalid && saxi_wready;
-    // currently waiting for SAXI to get confirmnation of all data in the current page before proceeding to teh next
+    // currently waiting for SAXI to get confirmnation of all data in the current page before proceeding to the next
     //
 //    assign confirm_write
     assign block_end = !(|block_start_r) && (confirm_write? (!(|num_bursts_pending)):(!(|num_bursts_in_buf)));
@@ -390,7 +390,7 @@ module  histogram_saxi#(
         .stb         (cmd_stb), // input
         .addr        (cmd_wa), // output[3:0] 
         .data        (cmd_data), // output[31:0] 
-        .we          ({we_addr,we_mode}) // output
+        .we          ({we_mode,we_addr}) // output
     );
 
     ram_var_w_var_r #(
@@ -419,9 +419,9 @@ module  histogram_saxi#(
         .clk       (aclk), // input
         .sync_rst  (!en_aclk), // input
         .we        (buf_re[2]), // input
-        .re        (), // input
-        .data_in   (inter_buf_data), // input[15:0] 
-        .data_out  (saxi_wdata), // output[15:0] 
+        .re        (fifo_re), // input 
+        .data_in   (inter_buf_data), // input[31:0] 
+        .data_out  (saxi_wdata), // output[31:0] 
         .nempty    (fifo_nempty), // output
         .half_full (fifo_half_full) // output reg 
     );

axi/mul_saxi_wr_chn.v

+/*******************************************************************************
+ * Module: mul_saxi_wr_chn
+ * Date:2015-07-10  
+ * Author: andrey     
+ * Description: One channel of the mult_saxi_wr (read/write common buffer)
+ *
+ * Copyright (c) 2015 Elphel, Inc .
+ * mul_saxi_wr_chn.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  mul_saxi_wr_chn.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module  mult_saxi_wr_chn #(
+    parameter MULT_SAXI_HALF_BRAM =      1,     // 0 - use full 36Kb BRAM for the buffer, 1 - use just half
+    parameter MULT_SAXI_BSLOG =          4,     // number of bits to represent burst size (4 - b.s. = 16, 0 - b.s = 1)
+    parameter MULT_SAXI_ADV_WR =         4,     // number of clock cycles before end of write to genearte adv_wr_done
+    parameter MULT_SAXI_ADV_RD =         3      // number of clock cycles before end of read to genearte wdata_busy (if !fifo_half_full)
+) (
+    input                                mclk,       // system clock
+    input                                aclk,       // global clock to run s_axi (@150MHz?)
+    input                                en,         // enable this channle ( 0 - reset)  
+    input                                has_burst,  // channel has at least 1 burst (should go down immediately after read_burst if no more data)
+    // use grant_wr to request reading external data
+//    output                               read_burst, // request to read a burst of data from the channel
+    input                                valid,      // data valid (same latency)
+    output                               rq_wr,      // request to write to the buffer FIFO
+    input                                grant_wr,   // single-cycle 
+    output [(MULT_SAXI_HALF_BRAM?6:7):0] wa, // write buffer address (w/o 2 MSB - channel)
+    output reg                           adv_wr_done, // outputs grant_wr for short bursts, or several clocks before end of wr
+//    output                               pre_we,     // will be registered after mux - use valid
+    output reg                           rq_out,
+    input                                grant_out, // single-cycle
+    input                                fifo_half_full, // output fifo is half full - use it to suspend readout
+    output [(MULT_SAXI_HALF_BRAM?6:7):0] ra, // read buffer address (w/o 2 MSB - channel)
+    output                               pre_re,     // will be registerd after the MUX
+    output reg                           first_re,   // reading first word (next cycle after corresponding pre_re)
+    output reg                           last_re,    // reading lastt word (next cycle after corresponding pre_re)
+    
+    output reg                           wdata_busy    
+
+);
+    localparam BURSTS_BITS= (MULT_SAXI_HALF_BRAM ? 9 : 10 ) - MULT_SAXI_BSLOG - 2; // number of bits to count number of bursts in 0-th quarter of the buffer
+    
+    reg     [BURSTS_BITS-1:0] wr_burst;
+    reg [MULT_SAXI_BSLOG-1:0] wr_word;
+    reg       [BURSTS_BITS:0] wr_num_burst; // number of bursts in the buffer chn0, as seen from the write side
+
+    reg     [BURSTS_BITS-1:0] rd_burst;
+    reg [MULT_SAXI_BSLOG-1:0] rd_word;
+    reg       [BURSTS_BITS:0] rd_num_burst; // number of bursts in the buffer chn0, as seen from the read side
+    reg                       rq_wr_r;
+    reg                       rq_wr_busy;
+//    reg                       early_wr_done; // single-cycle pulse several clock before end of write busy
+//    reg                       grant_wr_r;
+//    wire                      grant_wr_sngl;
+//    wire                      grant_wr_aclk;
+    wire                      write_last_in_burst;
+    wire                      burst_written_aclk;
+//    reg                       grant_out_r;
+//   wire                      grant_out_sngl;
+    wire                      grant_out_mclk;
+    reg                       en_aclk;
+    wire                      last_word_busy;  
+    reg                       pre_re_r;  // may be interrupted if fifo_half_full
+    reg                       out_busy;  // output data in progress
+    
+    assign wa = {wr_burst, wr_word};
+    assign ra = {rd_burst, rd_word};
+    assign rq_wr = rq_wr_r;
+//    assign grant_wr_sngl = grant_wr && !grant_wr_r;
+//    assign grant_out_sngl = grant_out && ~grant_out_r;
+    assign last_word_busy = &wr_word ; // make it earlier, use BURSTS_BITS selection (& (word | (1 <<???)))
+    assign write_last_in_burst = valid && (&wr_word);
+    assign pre_re = pre_re_r;
+
+    localparam ADV_WR_COUNT=(1 << MULT_SAXI_BSLOG) - MULT_SAXI_ADV_WR;
+    localparam ADV_RD_COUNT=(1 << MULT_SAXI_BSLOG) - MULT_SAXI_ADV_RD;
+    
+    
+    always @ (posedge mclk) begin
+        adv_wr_done <= rq_wr_busy && (wr_word == ((ADV_WR_COUNT >= 0)? ADV_WR_COUNT : 0));
+        
+        if      (!en)                     rq_wr_busy <= 0;
+        else if (grant_wr)                rq_wr_busy <= 1;
+        else if (valid && last_word_busy) rq_wr_busy <= 0;
+        
+        
+        rq_wr_r <= has_burst & (~wr_num_burst[BURSTS_BITS] & ~(&wr_num_burst[BURSTS_BITS-1:0])) & ~grant_wr & ~rq_wr_busy;
+        // Number of bursts in fifo as seen from the input
+        if      (!en)                               wr_num_burst <= 0;
+        else if ( grant_wr && !grant_out_mclk) wr_num_burst <= wr_num_burst + 1;
+        else if (!grant_wr &&  grant_out_mclk) wr_num_burst <= wr_num_burst - 1;
+
+        if (!en || grant_wr) wr_word <= 0;
+        else if (valid)      wr_word <= wr_word + 1;
+        
+        if      (!en)                 wr_burst <= 0;
+        else if (write_last_in_burst) wr_burst <= wr_burst + 1;
+        
+        
+    end
+    
+    reg                       early_busy;  // output data in progress
+
+    always @ (posedge aclk) begin
+        en_aclk <= en;
+        // Number of bursts in fifo as seen from the output
+        if      (!en_aclk)                          rd_num_burst <= 0;
+        else if ( burst_written_aclk && !grant_out) rd_num_burst <= rd_num_burst + 1;
+        else if (!burst_written_aclk &&  grant_out) rd_num_burst <= rd_num_burst - 1;
+        
+        if      (!en_aclk)                          rq_out <= 0;
+        else if ( burst_written_aclk && !grant_out) rq_out <= 1;
+        else if (!burst_written_aclk &&  grant_out) rq_out <= |rd_num_burst[BURSTS_BITS:1]; // >=2
+        
+        if (! en_aclk || grant_out)      rd_word <= 0;
+        else if (pre_re_r)               rd_word <=rd_word +1;
+        
+        if (!en_aclk)                    rd_burst <= wr_burst; // <= 0 is OK too
+        else if (pre_re_r && (&rd_word)) rd_burst <= rd_burst + 1;
+        
+        if      (!en_aclk)               out_busy <= 0;
+        else if (grant_out)              out_busy <= 1;
+        else if ((&rd_word) && pre_re_r) out_busy <= 0;
+
+        if (!en_aclk || fifo_half_full || ((&rd_word) && pre_re_r))  pre_re_r <= 0;
+        else                                                         pre_re_r <= out_busy;
+        
+        first_re <= pre_re_r && !(|rd_word); // will be used to copy channel/axi_wid
+        last_re <=  pre_re_r && (&rd_word); // will be used to generate axi_wlast
+        
+        if (!en_aclk || (ADV_RD_COUNT > 0)) early_busy <= 0; // small counts will never get busy
+        else if (grant_out)                 early_busy <= 1;
+        else if (rd_word == ADV_RD_COUNT)   early_busy <= 0;
+        
+        if (!en_aclk)                                                         wdata_busy <= 0;
+        else if (grant_out)                                                   wdata_busy <= 1;
+        else if ((!fifo_half_full && !early_busy) || (&rd_word) || !out_busy) wdata_busy <= 0; 
+    end
+    
+    pulse_cross_clock grant_out_mclk_i (
+        .rst         (!en), // input
+        .src_clk     (aclk), // input
+        .dst_clk     (mclk), // input
+        .in_pulse    (grant_out), // input
+        .out_pulse   (grant_out_mclk), // output
+        .busy() // output
+    );
+    pulse_cross_clock write_last_in_burst_i (
+        .rst         (!en_aclk), // input
+        .src_clk     (mclk), // input
+        .dst_clk     (aclk), // input
+        .in_pulse    (write_last_in_burst), // input
+        .out_pulse   (burst_written_aclk), // output
+        .busy() // output
+    );
+endmodule

axi/mult_saxi_wr_pointers.v

+/*******************************************************************************
+ * Module: mult_saxi_wr_pointers
+ * Date:2015-07-10  
+ * Author: andrey     
+ * Description: Process pointers for mult_saxi_wr
+ *
+ * Copyright (c) 2015 Elphel, Inc .
+ * mult_saxi_wr_pointers.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  mult_saxi_wr_pointers.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module  mult_saxi_wr_pointers#(
+    parameter MULT_SAXI_BSLOG0 =          4,     // number of bits to represent burst size (4 - b.s. = 16, 0 - b.s = 1)
+    parameter MULT_SAXI_BSLOG1 =          4,
+    parameter MULT_SAXI_BSLOG2 =          4,
+    parameter MULT_SAXI_BSLOG3 =          4
+)(
+    input                         mclk,             // system clock
+    input                         aclk,             // global clock to run s_axi (@150MHz?)
+    input                   [3:0] chn_en_mclk,      // enable this channle ( 0 - reset)
+    input                  [29:0] sa_len_di,        // input data to write pointers address/data
+    input                  [ 2:0] sa_len_wa,        // channel address to write sa/lengths
+    input                         sa_len_we,        // write enable sa/length data
+    input                  [ 1:0] chn,              // selected channel number, valid with start
+    input                         start,            // start address generation/pointer increment
+    output                        busy,             // suspend new accesses (check latencies)
+    // provide address and burst length for AXI @aclk, will stay until ackn
+    output reg             [29:0] axi_addr,
+    output reg              [3:0] axi_len,
+    // write data to external pointre memory (to be read out by PIO) @ aclk
+    // alternatively - read out directly from ptr_ram?
+    output                 [29:0] pntr_wd, // @aclk
+    output                  [1:0] pntr_wa,
+    output                        pntr_we
+);
+    reg   [3:0] chn_en_mclk_r;
+    reg   [3:0] chn_en_aclk;
+    wire        rst =      !(|chn_en_mclk);    // just for simulation
+    wire        rst_aclk = !(|chn_en_aclk);    // just for simulation
+    wire  [3:0] chn_wr_mclk = {(sa_len_wa[2:1]==3),(sa_len_wa[2:1]==2),(sa_len_wa[2:1]==1),(sa_len_wa[2:1]==0)};
+    wire  [3:0] rst_pntr_mclk =  (chn_en_mclk & ~chn_en_mclk_r) | (sa_len_we ? chn_wr_mclk : 4'b0);
+    wire  [3:0] rst_pntr_aclk;
+    wire        start_resetting_w;
+    reg   [1:0] resetting;              // resetting chunk_pointer and eof_pointer
+    reg         busy_r;
+    reg   [3:0] reset_rq;               // request to reset pointers when ready
+    reg   [3:0] reset_rq_pri;           // one-hot reset rq 
+    wire  [1:0] reset_rq_enc;           // encoded reset_rq_pri
+    wire        en_aclk = |chn_en_aclk;
+    reg   [1:0] chn_r;                  // registered channel being processed (or reset)
+    reg   [1:0] seq;                    // 1-hot sequence of address generation
+    wire [29:0] sa_len_ram_out;
+    wire [29:0] ptr_ram_out;
+    wire  [2:0] sa_len_ra;
+    reg         ptr_we;                 // write to the pointer memory
+    reg  [29:0] ptr_inc;                // incremented pointer
+    reg  [30:0] ptr_rollover;
+    reg   [4:0] burst_size;             // ROM
+    wire [29:0] ptr_wd;
+    
+    assign reset_rq_enc = {reset_rq_pri[3] | reset_rq_pri[2],
+                           reset_rq_pri[3] | reset_rq_pri[1]};
+    
+    assign start_resetting_w = en_aclk && !busy_r && !resetting[0] && (|reset_rq);
+    assign busy = busy_r; //?
+    assign ptr_wd = resetting[1] ? 30'b0 : (ptr_rollover[30]? ptr_inc : ptr_rollover[29:0]);
+    
+    assign pntr_wd = ptr_wd;
+    assign pntr_we = ptr_we;
+    assign pntr_wa = chn_r;
+    
+    assign sa_len_ra = {chn_r,seq[1]};
+    always @ (posedge mclk) begin
+        chn_en_mclk_r <= chn_en_mclk;
+    end
+    
+//  8x30 RAM for address/length    
+    reg  [29:0] sa_len_ram[0:7];           // start chunk/num cunks in a buffer (write port @mclk)
+    always @ (posedge mclk) begin
+        if (sa_len_we) sa_len_ram[sa_len_wa] <= sa_len_di;
+    end
+    assign sa_len_ram_out = sa_len_ram[sa_len_ra];
+
+// 4 x 30 RAM for current pointers
+    reg  [29:0] ptr_ram[0:3];           // start chunk/num cunks in a buffer (write port @mclk)
+    always @ (posedge aclk) begin
+        if (ptr_we) ptr_ram[chn_r] <= ptr_wd; 
+    end
+    assign ptr_ram_out = ptr_ram[chn_r];
+
+    always @ (posedge aclk) if (start) case (chn) // small ROM
+        'h0 : burst_size <= 1 << MULT_SAXI_BSLOG0;
+        'h1 : burst_size <= 1 << MULT_SAXI_BSLOG1;
+        'h2 : burst_size <= 1 << MULT_SAXI_BSLOG2;
+        'h3 : burst_size <= 1 << MULT_SAXI_BSLOG3;
+    endcase
+    
+    always @ (posedge aclk) begin
+        chn_en_aclk <= chn_en_mclk;
+        reset_rq <= rst_pntr_aclk | (reset_rq  & ~({4{resetting[0] &~ resetting[1]}} & reset_rq_pri));        
+        if (start_resetting_w)  reset_rq_pri <= {reset_rq[3] & ~(|reset_rq[2:0]),
+                                                 reset_rq[2] & ~(|reset_rq[1:0]),
+                                                 reset_rq[1] &     ~reset_rq[0],
+                                                 reset_rq[0]};
+        if (rst_aclk) resetting <= 0;
+        else          resetting <= {resetting[0], start_resetting_w | (resetting[0] & ~resetting[1])};
+        
+        if (rst_aclk)                        busy_r <= 0;
+        else if (start_resetting_w || start) busy_r <= 1;
+        else if (ptr_we)                     busy_r <= 0;
+
+        if (rst_aclk)                        seq <= 0;
+        else                                 seq <= {seq[0],start};
+        
+        if (resetting == 2'b1)               chn_r[1:0] <= reset_rq_enc; // during reset pointers
+        else if (start)                      chn_r[1:0] <= chn;          // during normal address generation
+        
+        if (seq[0]) axi_addr <= sa_len_ram_out + ptr_ram_out;
+        if (seq[0]) case (chn_r) // small ROM
+            'h0 : axi_len <= (1 << MULT_SAXI_BSLOG0) - 1;
+            'h1 : axi_len <= (1 << MULT_SAXI_BSLOG1) - 1;
+            'h2 : axi_len <= (1 << MULT_SAXI_BSLOG2) - 1;
+            'h3 : axi_len <= (1 << MULT_SAXI_BSLOG3) - 1;
+        endcase
+        
+        if (seq[0]) ptr_inc <= ptr_ram_out + burst_size;
+
+        if (seq[1]) ptr_rollover <= {1'b0, ptr_inc} -sa_len_ram_out; //sa_len_ram_out is now length
+        
+        ptr_we <= resetting[0] || seq[1];
+        
+        // add one extra register layer here?
+    
+    end
+
+    pulse_cross_clock #(.EXTRA_DLY(1)) rst_pntr_aclk0_i (.rst(rst), .src_clk(mclk), .dst_clk(aclk), .in_pulse(rst_pntr_mclk[0]), .out_pulse(rst_pntr_aclk[0]),.busy());
+    pulse_cross_clock #(.EXTRA_DLY(1)) rst_pntr_aclk1_i (.rst(rst), .src_clk(mclk), .dst_clk(aclk), .in_pulse(rst_pntr_mclk[1]), .out_pulse(rst_pntr_aclk[1]),.busy());
+    pulse_cross_clock #(.EXTRA_DLY(1)) rst_pntr_aclk2_i (.rst(rst), .src_clk(mclk), .dst_clk(aclk), .in_pulse(rst_pntr_mclk[2]), .out_pulse(rst_pntr_aclk[2]),.busy());
+    pulse_cross_clock #(.EXTRA_DLY(1)) rst_pntr_aclk3_i (.rst(rst), .src_clk(mclk), .dst_clk(aclk), .in_pulse(rst_pntr_mclk[3]), .out_pulse(rst_pntr_aclk[3]),.busy());
+
+endmodule
+

util_modules/round_robin.v

+/*******************************************************************************
+ * Module: round_robin
+ * Date:2015-07-10  
+ * Author: andrey     
+ * Description: Round-robin arbiter
+ *
+ * Copyright (c) 2015 Elphel, Inc .
+ * round_robin.v is free software; you can redistribute it and/or modify
+ * it under the terms of the GNU General Public License as published by
+ * the Free Software Foundation, either version 3 of the License, or
+ * (at your option) any later version.
+ *
+ *  round_robin.v is distributed in the hope that it will be useful,
+ * but WITHOUT ANY WARRANTY; without even the implied warranty of
+ * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
+ * GNU General Public License for more details.
+ *
+ * You should have received a copy of the GNU General Public License
+ * along with this program.  If not, see <http://www.gnu.org/licenses/> .
+ *******************************************************************************/
+`timescale 1ns/1ps
+
+module  round_robin #(
+    parameter FIXED_PRIORITY = 0, // 0 - round-robin, 1 - fixed channel priority (0 - highest)
+    parameter BITS =           2  // number of bits to encode channel number (1 << BITS) - number of inputs
+)(
+    input                         clk,
+    input                         srst, // sync. reset - needed to reset current channel
+    input      [(1 << BITS) -1:0] rq,   // request vector
+    input                         en,    // enable to grant highest priority request (should be reset by grant)
+    output reg                    grant, // changed to 1-cycle long (was: stays on until reset by !en)
+    output             [BITS-1:0] chn,
+    output reg [(1 << BITS) -1:0] grant_chn);  // 1-hot grant output per-channel, single-clock pulse
+    
+    reg           [BITS-1:0] last_chn;
+    wire                     valid;
+    wire          [BITS-1:0] next_chn;
+    wire                     pre_grant_w;
+    reg                      grant_r;
+    
+    assign pre_grant_w = en && valid &&!grant_r;
+//    assign grant = grant_r;
+    assign chn =   last_chn;
+    
+    assign {valid, next_chn}= func_selrr (rq, FIXED_PRIORITY?((1 << BITS) -1):last_chn);
+    always @ (posedge clk) begin
+        if      (srst)        last_chn <= (1 << BITS) -1;
+        else if (pre_grant_w) last_chn <= next_chn;
+        
+        if (srst || !en) grant_r <= 0;
+        else if (valid)  grant_r <= 1; // grant will stay on until reset by !en
+        
+        grant_chn <= func_demux (!srst && pre_grant_w, next_chn);
+
+        grant <= !srst && pre_grant_w;
+        
+    end
+    
+    // round-robin priority encode
+    function [BITS : 0] func_selrr; // returns {valid, chn}
+        input [(1 << BITS) -1:0] rq;       // request vector
+        input         [BITS-1:0] cur_chn;  // current (last served) channel - lowest priority
+        reg                      valid;    // at least one request
+        reg         [BITS - 1:0] chn, sample_chn;
+        integer                  i;
+        begin
+            valid = 0;
+            chn   = 0;
+            for (i = 0; i < (1 << BITS); i = i+1) begin
+                sample_chn = (cur_chn - i) % (1 << BITS);
+                if (rq[sample_chn]) begin
+                    valid = 1;
+                    chn = sample_chn;
+                end    
+            end
+            func_selrr = {valid,chn};
+        end
+    endfunction
+    
+    function  [(1 << BITS) -1:0] func_demux;
+        input              en;
+        input [BITS - 1:0] sel;
+        integer i;
+        begin
+            for (i=0; i < (1 << BITS); i = i + 1) begin
+                func_demux[i] = en && (sel == i); 
+            end
+        end
+    endfunction
+    
+endmodule