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Commit 5cc1817c authored by Andrey Filippov's avatar Andrey Filippov
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merged with lwir, tiff for both sensors

parents f894cd31 cc525170
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.gitignore
View file @ 5cc1817c
......@@ -49,6 +49,7 @@ x393_testbench03_01.sav
simulation_data/*.dat
simulation_data/*.jpeg
#these two project files are now in .eclipse_project_setup directory
py393/.project
/.project
/.pydevproject
/.settings
......
cocotb/x393_cocotb_03.sav
View file @ 5cc1817c
This diff is collapsed.
cocotb/x393_dut.v
View file @ 5cc1817c
......@@ -418,14 +418,16 @@ module x393_dut#(
parameter PF_STRIPES=WOI_HEIGHT/PF_HEIGHT;
`else
parameter PF_HEIGHT=0; // SuppressThisWarning VEditor - not used
parameter FULL_HEIGHT=WOI_HEIGHT+4;
parameter PF_STRIPES=0; // SuppressThisWarning VEditor - not used
`endif
parameter WOI_MARGINS = 0; // 4;
parameter VIRTUAL_WIDTH= FULL_WIDTH + HBLANK;
parameter VIRTUAL_HEIGHT= FULL_HEIGHT + BLANK_ROWS_BEFORE + BLANK_ROWS_AFTER; //SuppressThisWarning Veditor UNUSED
parameter TRIG_INTERFRAME= 100; /// extra 100 clock cycles between frames //SuppressThisWarning Veditor UNUSED
parameter TRIG_DELAY= 200; /// delay in sensor clock cycles // SuppressThisWarning VEditor - not used
parameter FULL_WIDTH= WOI_WIDTH+4;
parameter FULL_WIDTH= WOI_WIDTH + WOI_MARGINS;
parameter FULL_HEIGHT= WOI_HEIGHT + WOI_MARGINS;
// localparam SENSOR_MEMORY_WIDTH_BURSTS = (FULL_WIDTH + 15) >> 4;
// localparam SENSOR_MEMORY_MASK = (1 << (FRAME_WIDTH_ROUND_BITS-4)) -1;
// localparam SENSOR_MEMORY_FULL_WIDTH_BURSTS = (SENSOR_MEMORY_WIDTH_BURSTS + SENSOR_MEMORY_MASK) & (~SENSOR_MEMORY_MASK);
......@@ -670,22 +672,35 @@ module x393_dut#(
`else
//connect parallel12 sensor to sensor port 2 (all data rotated left by 1 bit)
assign sns2_dp[6:1] = {PX2_D[9], PX2_D[7], PX2_D[5], PX2_D[3], PX2_D[1], PX2_HACT};
assign sns2_dn[6:0] = {PX2_D[10], PX2_D[8], PX2_D[6], PX2_D[4], PX2_D[2], PX2_VACT, PX2_DCLK};
assign sns2_clkn = PX2_D[11]; // inout CNVSYNC/TDI
assign sns2_clkp = PX2_D[0]; // CNVCLK/TDO
/// assign sns2_dp[6:1] = {PX2_D[9], PX2_D[7], PX2_D[5], PX2_D[3], PX2_D[1], PX2_HACT};
/// assign sns2_dn[6:0] = {PX2_D[10], PX2_D[8], PX2_D[6], PX2_D[4], PX2_D[2], PX2_VACT, PX2_DCLK};
/// assign sns2_clkn = PX2_D[11]; // inout CNVSYNC/TDI
/// assign sns2_clkp = PX2_D[0]; // CNVCLK/TDO
assign sns2_dp[6:1] = {PX2_D[10], PX2_D[8], PX2_D[6], PX2_D[4], PX2_D[2], PX2_HACT};
assign sns2_dn[6:0] = {PX2_D[11], PX2_D[9], PX2_D[7], PX2_D[5], PX2_D[3], PX2_VACT, PX2_DCLK};
assign sns2_clkn = PX2_D[0]; // inout CNVSYNC/TDI
assign sns2_clkp = PX2_D[1]; // CNVCLK/TDO
//connect parallel12 sensor to sensor port 3 (all data rotated left by 2 bits
assign sns3_dp[6:1] = {PX3_D[8], PX3_D[6], PX3_D[4], PX3_D[2], PX3_D[0], PX3_HACT};
assign sns3_dn[6:0] = {PX3_D[9], PX3_D[7], PX3_D[5], PX3_D[3], PX3_D[1], PX3_VACT, PX3_DCLK};
assign sns3_clkn = PX3_D[10]; // inout CNVSYNC/TDI
assign sns3_clkp = PX3_D[11]; // CNVCLK/TDO
/// assign sns3_dp[6:1] = {PX3_D[8], PX3_D[6], PX3_D[4], PX3_D[2], PX3_D[0], PX3_HACT};
/// assign sns3_dn[6:0] = {PX3_D[9], PX3_D[7], PX3_D[5], PX3_D[3], PX3_D[1], PX3_VACT, PX3_DCLK};
/// assign sns3_clkn = PX3_D[10]; // inout CNVSYNC/TDI
/// assign sns3_clkp = PX3_D[11]; // CNVCLK/TDO
assign sns3_dp[6:1] = {PX3_D[10], PX3_D[8], PX3_D[6], PX3_D[4], PX3_D[2], PX3_HACT};
assign sns3_dn[6:0] = {PX3_D[11], PX3_D[9], PX3_D[7], PX3_D[5], PX3_D[3], PX3_VACT, PX3_DCLK};
assign sns3_clkn = PX3_D[0]; // inout CNVSYNC/TDI
assign sns3_clkp = PX3_D[1]; // CNVCLK/TDO
//connect parallel12 sensor to sensor port 4 (all data rotated left by 3 bits
assign sns4_dp[6:1] = {PX4_D[5], PX4_D[3], PX4_D[1], PX4_D[11], PX4_D[9], PX4_HACT};
assign sns4_dn[6:0] = {PX4_D[6], PX4_D[4], PX4_D[2], PX4_D[0], PX4_D[10], PX4_VACT, PX4_DCLK};
assign sns4_clkn = PX4_D[7]; // inout CNVSYNC/TDI
assign sns4_clkp = PX4_D[8]; // CNVCLK/TDO
/// assign sns4_dp[6:1] = {PX4_D[5], PX4_D[3], PX4_D[1], PX4_D[11], PX4_D[9], PX4_HACT};
/// assign sns4_dn[6:0] = {PX4_D[6], PX4_D[4], PX4_D[2], PX4_D[0], PX4_D[10], PX4_VACT, PX4_DCLK};
/// assign sns4_clkn = PX4_D[7]; // inout CNVSYNC/TDI
/// assign sns4_clkp = PX4_D[8]; // CNVCLK/TDO
assign sns4_dp[6:1] = {PX4_D[10], PX4_D[8], PX4_D[6], PX4_D[4], PX4_D[2], PX4_HACT};
assign sns4_dn[6:0] = {PX4_D[11], PX4_D[9], PX4_D[7], PX4_D[5], PX4_D[3], PX4_VACT, PX4_DCLK};
assign sns4_clkn = PX4_D[0]; // inout CNVSYNC/TDI
assign sns4_clkp = PX4_D[1]; // CNVCLK/TDO
`endif
`endif
......@@ -1552,6 +1567,40 @@ simul_axi_hp_wr #(
.clk_out (PX4_MCLK) // output
);
/* Instance template for module simul_lwir160x120_vospi */
wire lwir1_miso;
simul_lwir160x120_vospi #(
.DATA_FILE ("/data_ssd/nc393/elphel393/fpga-elphel/x393/input_data/pattern_160_120_14.dat"),
.WINDOW_WIDTH (160),
.WINDOW_HEIGHT (120),
.TELEMETRY (2), // 1),
.FRAME_PERIOD (946969),
.FRAME_DELAY (100),
.MS_PERIOD (25) // 1us instead of 1 ms
) simul_lwir160x120_vospi_i (
.mclk (x393_i.ps7_i.SAXIHP0ACLK), // PX1_MCLK), // input temporarily made faster
.nrst ( PX1_MRST), // input
.sck ( 1'b0), // input
.ncs ( 1'b0), // inout
.miso ( lwir1_miso), // output
.telemetry_rev ( 16'h7654), // input[15:0]
.telemetry_status ( 32'h137f1248), // input[31:0]
.telemetry_srev (64'h0123456789abcdef), // input[63:0]
.telemetry_temp_counts ( 16'd59000), // input[15:0]
.telemetry_temp_kelvin ( 16'd29500), // input[15:0]
.telemetry_temp_last_kelvin ( 16'd29300), // input[15:0]
.telemetry_time_last_ms ( 32'h12345678), // input[31:0]
.telemetry_agc_roi_top ( 16'd0), // input[15:0]
.telemetry_agc_roi_left ( 16'd0), // input[15:0]
.telemetry_agc_roi_bottom ( 16'd119), // input[15:0]
.telemetry_agc_roi_right ( 16'd159), // input[15:0]
.telemetry_agc_high (16'd19200), // input[15:0]
.telemetry_agc_low ( 16'd200), // input[15:0]
.telemetry_video_format (32'haaaa5555) // input[31:0]
);
simul_sensor12bits #(
.SENSOR_IMAGE_TYPE (SENSOR_IMAGE_TYPE0),
.lline (VIRTUAL_WIDTH), // SENSOR12BITS_LLINE),
......@@ -1572,7 +1621,8 @@ simul_axi_hp_wr #(
.tDDO1 (SENSOR12BITS_TDDO1),
.trigdly (TRIG_LINES), // SENSOR12BITS_TRIGDLY),
.ramp (0), //SENSOR12BITS_RAMP),
.new_bayer (0) // was 1 SENSOR12BITS_NEW_BAYER)
.new_bayer (0), // was 1 SENSOR12BITS_NEW_BAYER)
.EXTRA_PERIOD(0)
) simul_sensor12bits_i (
.MCLK (PX1_MCLK), // input
.MRST (PX1_MRST), // input
......@@ -1611,7 +1661,9 @@ simul_axi_hp_wr #(
.tDDO1 (SENSOR12BITS_TDDO1),
.trigdly (TRIG_LINES), // SENSOR12BITS_TRIGDLY),
.ramp (0), //SENSOR12BITS_RAMP),
.new_bayer (0) //SENSOR12BITS_NEW_BAYER) was 1
.new_bayer (0), //SENSOR12BITS_NEW_BAYER) was 1
.EXTRA_PERIOD (50)
) simul_sensor12bits_2_i (
.MCLK (PX2_MCLK), // input
`ifdef DISABLE_SENSOR_2
......@@ -1653,7 +1705,8 @@ simul_axi_hp_wr #(
.tDDO1 (SENSOR12BITS_TDDO1),
.trigdly (TRIG_LINES), // SENSOR12BITS_TRIGDLY),
.ramp (0), // SENSOR12BITS_RAMP),
.new_bayer (0) // was 1SENSOR12BITS_NEW_BAYER)
.new_bayer (0), // was 1SENSOR12BITS_NEW_BAYER)
.EXTRA_PERIOD(100)
) simul_sensor12bits_3_i (
.MCLK (PX3_MCLK), // input
.MRST (PX3_MRST), // input
......@@ -1691,7 +1744,8 @@ simul_axi_hp_wr #(
.tDDO1 (SENSOR12BITS_TDDO1),
.trigdly (TRIG_LINES), // SENSOR12BITS_TRIGDLY),
.ramp (0),// SENSOR12BITS_RAMP),
.new_bayer (0) // was 1SENSOR12BITS_NEW_BAYER)
.new_bayer (0), // was 1SENSOR12BITS_NEW_BAYER)
.EXTRA_PERIOD(120)
) simul_sensor12bits_4_i (
.MCLK (PX4_MCLK), // input
.MRST (PX4_MRST), // input
......
fpga_version.vh
View file @ 5cc1817c
......@@ -35,8 +35,12 @@
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
parameter FPGA_VERSION = 32'h03930105; // parallel - 17.4 - fixing wide raw frames
parameter FPGA_VERSION = 32'h03930107; // parallel - 17.4 - restored delay after linear, foxed bug, all met
// parameter FPGA_VERSION = 32'h03930110; //A serial - 17.4 - restored delay after linear, foxed bug, timing met
// parameter FPGA_VERSION = 32'h03930110; // serial - 17.4 - restored delay after linear, foxed bug, timing failed
// parameter FPGA_VERSION = 32'h03930107; // parallel - 17.4 - restored delay after linear, foxed bug, all met
// parameter FPGA_VERSION = 32'h03930106; // parallel - 17.4 - increased delay after linear read all met
// parameter FPGA_VERSION = 32'h03930105; // parallel - 17.4 - fixed wide raw frames all met
// parameter FPGA_VERSION = 32'h03930104; // parallel - 17.4 - added RAW mode (for tiff files) timing met
// parameter FPGA_VERSION = 32'h03930103; // serial - 17.4 - trigger polarity on GP1 inverted
// parameter FPGA_VERSION = 32'h03930102; // serial - 17.4 - disabling SOF when setting interface, bug fix
......
includes/x393_simulation_parameters.vh
View file @ 5cc1817c
......@@ -79,17 +79,43 @@
// parameter SENSOR_IMAGE_TYPE2 = "NORM11", // 4",
// parameter SENSOR_IMAGE_TYPE3 = "NORM12",
parameter SENSOR_IMAGE_TYPE0 = "TEST01-1044X36", // "NORM13",
parameter SENSOR_IMAGE_TYPE1 = "TEST01-1044X36", // "NORM13",
parameter SENSOR_IMAGE_TYPE2 = "TEST01-1044X36", // "NORM14", // 4",
parameter SENSOR_IMAGE_TYPE3 = "TEST01-1044X36", // "NORM15",
parameter SIMULATE_CMPRS_CMODE0 = CMPRS_CBIT_CMODE_JPEG18,
parameter SIMULATE_CMPRS_CMODE1 = CMPRS_CBIT_CMODE_JPEG18,
parameter SIMULATE_CMPRS_CMODE2 = CMPRS_CBIT_CMODE_JP4,
parameter SIMULATE_CMPRS_CMODE3 = CMPRS_CBIT_CMODE_JP4,
// parameter SENSOR_IMAGE_TYPE0 = "TEST01-1044X36", // "NORM13",
// parameter SENSOR_IMAGE_TYPE1 = "TEST01-1044X36", // "NORM13",
// parameter SENSOR_IMAGE_TYPE2 = "TEST01-1044X36", // "NORM14", // 4",
// parameter SENSOR_IMAGE_TYPE3 = "TEST01-1044X36", // "NORM15",
// parameter SENSOR_IMAGE_TYPE0 = "TEST01-260X36", // "NORM13",
// parameter SENSOR_IMAGE_TYPE1 = "TEST01-260X36", // "NORM13",
// parameter SENSOR_IMAGE_TYPE2 = "TEST01-260X36", // "NORM14", // 4",
// parameter SENSOR_IMAGE_TYPE3 = "TEST01-260X36", // "NORM15",
// parameter SENSOR_IMAGE_TYPE0 = "TEST01-260X68", // "NORM13",
// parameter SENSOR_IMAGE_TYPE1 = "TEST01-260X68", // "NORM13",
// parameter SENSOR_IMAGE_TYPE2 = "TEST01-260X68", // "NORM14", // 4",
// parameter SENSOR_IMAGE_TYPE3 = "TEST01-260X68", // "NORM15",
// parameter SENSOR_IMAGE_TYPE0 = "260X260A", // "NORM13",
// parameter SENSOR_IMAGE_TYPE1 = "260X260A", // "NORM13",
// parameter SENSOR_IMAGE_TYPE2 = "260X260A", // "NORM14", // 4",
// parameter SENSOR_IMAGE_TYPE3 = "260X260A", // "NORM15",
parameter SENSOR_IMAGE_TYPE0 = "256X256A", // "NORM13",
parameter SENSOR_IMAGE_TYPE1 = "256X256A", // "NORM13",
parameter SENSOR_IMAGE_TYPE2 = "256X256A", // "NORM14", // 4",
parameter SENSOR_IMAGE_TYPE3 = "256X256A", // "NORM15",
// parameter SENSOR_IMAGE_TYPE0 = "512X512A", // "NORM13",
// parameter SENSOR_IMAGE_TYPE1 = "512X512A", // "NORM13",
// parameter SENSOR_IMAGE_TYPE2 = "512X512A", // "NORM14", // 4",
// parameter SENSOR_IMAGE_TYPE3 = "512X512A", // "NORM15",
//
parameter SIMULATE_CMPRS_CMODE0 = CMPRS_CBIT_CMODE_JP4, // CMPRS_CBIT_CMODE_JPEG18,
parameter SIMULATE_CMPRS_CMODE1 = CMPRS_CBIT_CMODE_JP4, // CMPRS_CBIT_CMODE_JPEG18,
parameter SIMULATE_CMPRS_CMODE2 = CMPRS_CBIT_CMODE_JP4, // CMPRS_CBIT_CMODE_JPEG18, // CMPRS_CBIT_CMODE_JP4,
parameter SIMULATE_CMPRS_CMODE3 = CMPRS_CBIT_CMODE_JP4, // CMPRS_CBIT_CMODE_JPEG18, // CMPRS_CBIT_CMODE_JP4,
// parameter SIMULATE_CMPRS_CMODE2 = CMPRS_CBIT_CMODE_JPEG18,
// parameter SIMULATE_CMPRS_CMODE3 = CMPRS_CBIT_CMODE_JPEG18,
// CMPRS_CBIT_CMODE_JPEG18, //input [31:0] cmode; // [13:9] color mode:
......@@ -134,8 +160,8 @@
parameter HISTOGRAM_START_PAGE = 20'h12345,
parameter FRAME_WIDTH_ROUND_BITS = 9, // multiple of 512 pixels (32 16-byte bursts) (11 - ful SDRAM page)
parameter WOI_WIDTH= 1040, // 64,
parameter WOI_HEIGHT= 32,
parameter WOI_WIDTH= 256, // 512, // 256, //1040, // 64,
parameter WOI_HEIGHT= 256, // 512, // 256, // 64, // 32,
parameter QUADRANTS_PXD_HACT_VACT = 6'h01, // 2 bits each: data-0, hact - 1, vact - 2
// 90-degree shifts for data [1:0], hact [3:2] and vact [5:4]
......
input_data/img256x256-12b.dat 0 → 100644
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input_data/img260x260-12b.dat 0 → 100644
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input_data/img260x260x12b.dat 0 → 100644
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input_data/img516x516-12b.dat 0 → 100644
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input_data/marching1_12b_260x36.dat 0 → 100644
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input_data/marching1_12b_260x68.dat 0 → 100644
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input_data/pattern_160_120_14.dat 0 → 100644
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memctrl/mcntrl_tiled_linear_rw.v
View file @ 5cc1817c
......@@ -595,7 +595,8 @@ module mcntrl_tiled_linear_rw#(
row_left[NUM_XFER_BITS:0]; // 7 bits, max 'h40
*/
lim_by_tile_width <= (|row_left[FRAME_WIDTH_BITS:MAX_TILE_WIDTH] || (!linear_mode && (row_left[MAX_TILE_WIDTH:0] >= tile_cols)))?
(linear_mode ? (1<< NUM_XFER_BITS) : tile_cols):
// (linear_mode ? (1<< NUM_XFER_BITS) : tile_cols):
(linear_mode ? {1'b1,{NUM_XFER_BITS{1'b0}}} : tile_cols):
row_left[MAX_TILE_WIDTH:0]; // 7 bits, max 'h40
end
......@@ -668,16 +669,16 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
// LINEAR matched
// TILED and TILED_LIN only:
if (mrst) xfer_start_rd_r <= 0;
else xfer_start_rd_r <= xfer_grant && !chn_rst && !cmd_wrmem && !byte32;
else xfer_start_rd_r <= xfer_grant && !chn_rst && !cmd_wrmem && !byte32 && !linear_mode;
if (mrst) xfer_start_wr_r <= 0;
else xfer_start_wr_r <= xfer_grant && !chn_rst && cmd_wrmem && !byte32;
else xfer_start_wr_r <= xfer_grant && !chn_rst && cmd_wrmem && !byte32 && !linear_mode;
if (mrst) xfer_start32_rd_r <= 0;
else xfer_start32_rd_r <= xfer_grant && !chn_rst && !cmd_wrmem && byte32;
else xfer_start32_rd_r <= xfer_grant && !chn_rst && !cmd_wrmem && byte32 && !linear_mode;
if (mrst) xfer_start32_wr_r <= 0;
else xfer_start32_wr_r <= xfer_grant && !chn_rst && cmd_wrmem && byte32;
else xfer_start32_wr_r <= xfer_grant && !chn_rst && cmd_wrmem && byte32 && !linear_mode;
if (mrst) xfer_start_lin_rd_r <= 0;
else xfer_start_lin_rd_r <= xfer_grant && !chn_rst && !cmd_wrmem && linear_mode;
......
py393/.project
View file @ 5cc1817c
......@@ -14,4 +14,11 @@
<natures>
<nature>org.python.pydev.pythonNature</nature>
</natures>
<linkedResources>
<link>
<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
<location>/data_ssd/nc393/elphel393/fpga-elphel/x393/py393/vivado_logs/VivadoSynthesis-20190404120819591.log</location>
</link>
</linkedResources>
</projectDescription>
py393/x393_sens_cmprs.py
View file @ 5cc1817c
......@@ -155,7 +155,7 @@ class X393SensCmprs(object):
x393Rtc = None
x393Membridge = None
def __init__(self, debug_mode=1,dry_mode=True, saveFileName=None):
def __init__(self, debug_mode=1,dry_mode=True, saveFileName=None, nomargins = True): # False):
# global BUFFER_ADDRESS, BUFFER_LEN
global BUFFER_ADDRESS, BUFFER_LEN, COMMAND_ADDRESS, DATAIN_ADDRESS, DATAOUT_ADDRESS
global BUFFER_ADDRESS_H2D, BUFFER_LEN_H2D, BUFFER_ADDRESS_D2H, BUFFER_LEN_D2H, BUFFER_ADDRESS_BIDIR, BUFFER_LEN_BIDIR
......@@ -173,6 +173,13 @@ class X393SensCmprs(object):
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_HISPI]["height"]= vrlg.WOI_HEIGHT + 4
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_HISPI]["top"]= 0
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_HISPI]["left"]= 0
if nomargins:
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_PARALLEL]["width"]= vrlg.WOI_WIDTH + 0 # 4
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_PARALLEL]["height"]= vrlg.WOI_HEIGHT + 0
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_HISPI]["width"]= vrlg.WOI_WIDTH + 0 #4
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_HISPI]["height"]= vrlg.WOI_HEIGHT + 0
print ("Using simulation size sensor defaults ",SENSOR_DEFAULTS)
except:
......@@ -628,12 +635,15 @@ class X393SensCmprs(object):
# moved before camsync to have a valid timestamo w/o special waiting
if verbose >0 :
print ("===================== MEMORY_SENSOR =========================")
print ("===================== MEMORY_SENSOR =========================, mode= %d"%(cmode))
window_height_memory = window_height
if cmode==vrlg.CMPRS_CBIT_CMODE_JP4:
if (cmode==vrlg.CMPRS_CBIT_CMODE_JP4) or (cmode==15): # vrlg.CMPRS_CBIT_CMODE_RAW):
window_height_memory &= 0xfff0 # do not need extra margins
num_burst_in_line &= 0xfffe # make even (assuming left=0)
print ("===================== Mode is JP4 or raw =========================")
else:
print ("===================== Mode is neither JP4 nor raw =========================")
self.x393Sensor.setup_sensor_memory (
num_sensor = num_sensor, # input [1:0] num_sensor;
......
py393/x393_tiff_verilog.py 100644 → 100755
View file @ 5cc1817c
#!/usr/bin/env python
# encoding: utf-8
from __future__ import division
from __future__ import print_function
......@@ -47,7 +49,7 @@ except:
try:
outname = sys.argv[3]
except IndexError:
outname = fname.replace(".tiff",".vh")
outname = fname.replace(".tiff",".dat")
tif = Image.open(fname)
......
simulation_modules/simul_lwir160x120_telemetry.v 0 → 100644
View file @ 5cc1817c
/*!
* <b>Module:</b> simul_lwir160x120_telemetry
* @file simul_lwir160x120_telemetry.v
* @date 2019-04-01
* @author Andrey Filippov
*
* @brief Combine telemetry data into vospi packet payload
*
* @copyright Copyright (c) 2019 Elphel, Inc.
*
* <b>License </b>
*
* simul_lwir160x120_telemetry.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* simul_lwir160x120_telemetry.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module simul_lwir160x120_telemetry(
input clk,
input en, // write all telemetry, but average
input en_avg, // write frame average (may be simultaneous)
// telemetry data
input [15:0] telemetry_rev,
input [31:0] telemetry_time,
input [31:0] telemetry_status,
input [63:0] telemetry_srev,
input [31:0] telemetry_frame,
input [15:0] telemetry_mean,
input [15:0] telemetry_temp_counts,
input [15:0] telemetry_temp_kelvin,
input [15:0] telemetry_temp_last_kelvin,
input [31:0] telemetry_time_last_ms,
input [15:0] telemetry_agc_roi_top,
input [15:0] telemetry_agc_roi_left,
input [15:0] telemetry_agc_roi_bottom,
input [15:0] telemetry_agc_roi_right,
input [15:0] telemetry_agc_high,
input [15:0] telemetry_agc_low,
input [31:0] telemetry_video_format, //???
output reg [160*16-1:0] telemetry_a,
output reg [160*16-1:0] telemetry_b
);
always @(posedge clk) if (en) begin
telemetry_a <= {
telemetry_rev [15:0], // word 0
telemetry_time [31:0], // words 1.. 2
telemetry_status [31:0], // words 3.. 4
{8{16'b0}}, // words 5..12
telemetry_srev [63:0], // words 13..16
{3{16'b0}}, // words 17..19
telemetry_frame [31:0], // words 20..21
en_avg?telemetry_mean[15:0]:telemetry_a[(159-22)*16 +: 16], // words 22
telemetry_temp_counts [15:0], // words 23
telemetry_temp_kelvin [15:0], // words 24
{4{16'b0}}, // words 25..28
telemetry_temp_last_kelvin[15:0], // words 29
telemetry_time_last_ms [31:0], // words 30..31
{2{16'b0}}, // words 32..33
telemetry_agc_roi_top [15:0], // words 34
telemetry_agc_roi_left [15:0], // words 35
telemetry_agc_roi_bottom [15:0], // words 36
telemetry_agc_roi_right [15:0], // words 37
telemetry_agc_high [15:0], // words 38
telemetry_agc_low [15:0], // words 39
{32{16'b0}}, // words 40..71
telemetry_video_format [31:0], // words 72..73
{86{16'b0}} // words 74..159
};
telemetry_b <= 0;
end else if (en_avg) begin
telemetry_a[(159-22)*16 +: 16] <= telemetry_mean[15:0];
end
endmodule
simulation_modules/simul_lwir160x120_vospi.v 0 → 100644
View file @ 5cc1817c
This diff is collapsed.
simulation_modules/simul_sensor12bits.v
View file @ 5cc1817c
......@@ -55,7 +55,8 @@ module simul_sensor12bits # (
parameter tDDO1 = 5, //
parameter trigdly = 8, // delay between trigger input and start of output (VACT) in lines
parameter ramp = 1, // 1 - ramp, 0 - random (now - sensor.dat)
parameter new_bayer = 0 // 0 - old (16x16), 1 - new (18x18)
parameter new_bayer = 0, // 0 - old (16x16), 1 - new (18x18)
parameter EXTRA_PERIOD = 0 // add these clockc before VACT
) (
input MCLK, // Master clock
input MRST, // Master Reset - active low
......@@ -83,7 +84,7 @@ module simul_sensor12bits # (
localparam s_lastline= 7;
localparam s_frame_done=8;
localparam t_preVACT= lline* trigdly;
localparam t_preVACT= lline* trigdly + EXTRA_PERIOD;
localparam t_firstline=nrowb*lline+1; // 1664
localparam t_BPF= nbpf; // 16
localparam t_preHACT= ngp1; // 8
......@@ -92,7 +93,9 @@ module simul_sensor12bits # (
localparam t_lastline= nrowa*lline+1; // 1664
//reg [15:0] sensor_data[0:4095]; // up to 64 x 64 pixels // SuppressThisWarning VEditor - Will be assigned by $readmem
reg [15:0] sensor_data[0:65535]; // up to 1024 x 64 pixels // SuppressThisWarning VEditor - Will be assigned by $readmem
///reg [15:0] sensor_data[0:65535]; // up to 1024 x 64 pixels // SuppressThisWarning VEditor - Will be assigned by $readmem
reg [15:0] sensor_data[0: nrows * ncols -1]; // up to 1024 x 64 pixels // SuppressThisWarning VEditor - Will be assigned by $readmem
// $readmemh("sensor.dat",sensor_data);
......@@ -192,6 +195,11 @@ initial begin
else if (SENSOR_IMAGE_TYPE == "NORM15") $readmemh({`ROOTPATH,"/input_data/sensor_15.dat"},sensor_data);
else if (SENSOR_IMAGE_TYPE == "NORM16") $readmemh({`ROOTPATH,"/input_data/sensor_16.dat"},sensor_data);
else if (SENSOR_IMAGE_TYPE == "TEST01-1044X36") $readmemh({`ROOTPATH,"/input_data/test01-1044x36.dat"},sensor_data);
else if (SENSOR_IMAGE_TYPE == "TEST01-260X36") $readmemh({`ROOTPATH,"/input_data/marching1_12b_260x36.dat"},sensor_data);
else if (SENSOR_IMAGE_TYPE == "TEST01-260X68") $readmemh({`ROOTPATH,"/input_data/marching1_12b_260x68.dat"},sensor_data);
else if (SENSOR_IMAGE_TYPE == "260X260A") $readmemh({`ROOTPATH,"/input_data/img260x260x12b.dat"},sensor_data);
else if (SENSOR_IMAGE_TYPE == "256X256A") $readmemh({`ROOTPATH,"/input_data/img256x256-12b.dat"},sensor_data);
else if (SENSOR_IMAGE_TYPE == "512X512A") $readmemh({`ROOTPATH,"/input_data/img516x516-12b.dat"},sensor_data);
else begin
$display ("WARNING: Unrecognized sensor image :'%s', using default 'NORM': input_data/sensor.dat",SENSOR_IMAGE_TYPE);
$readmemh({`ROOTPATH,"/input_data/sensor.dat"},sensor_data);
......
simulation_modules/vospi.v 0 → 100644
View file @ 5cc1817c
/*!
* <b>Module:</b> vospi
* @file vospi.v
* @date 2019-03-31
* @author Andrey Filippov
*
* @brief single packet ;processing with a ping-pong buffer
*
* @copyright Copyright (c) 2019 Elphel, Inc.
*
* <b>License </b>
*
* vospi.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* vospi.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module vospi(
input clk,
input srst,
input [15:0] data_in,
output packet_rdy, // @clk
input sck, // SPI clk
input ncs, // SPI active-low CS
output miso // SPI data out
);
endmodule
util_modules/crc16_x16x12x5x0.v 0 → 100644
View file @ 5cc1817c
/*!
* <b>Module:</b> crc16_x16x12x5x0
* @file crc16_x16x12x5x0.v
* @date 2019-03-31
* @author Andrey Filippov
*
* @brief calculates CRC x^16+x^12+x^5+x^0 16-bit parallel
*
* @copyright Copyright (c) 2019 Elphel, Inc.
*
* <b>License </b>
*
* crc16_x16x12x5x0.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* crc16_x16x12x5x0.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module crc16_x16x12x5x0(
input clk,
input srst,
input en,
input [15:0] din,
output [15:0] dout
);
reg [15:0] crc;
assign dout = crc;
always@ (posedge clk) begin
if (srst) crc <= 0;
else if (en) crc <= din ^ {
crc[10]^crc[3]^crc[7]^crc[11],
crc[14]^crc[9]^crc[2],
crc[1]^crc[12]^crc[6]^crc[10]^crc[14]^crc[5]^crc[9],
crc[12]^crc[7]^crc[0]^crc[4]^crc[15],
crc[11]^crc[15]^crc[6]^crc[10]^crc[14],
crc[10]^crc[14]^crc[5]^crc[9]^crc[13],
crc[9]^crc[13]^crc[4]^crc[15]^crc[8]^crc[12],
crc[8]^crc[12]^crc[3]^crc[14]^crc[7]^crc[11]^crc[15],
crc[7]^crc[11]^crc[15]^crc[2]^crc[13],
crc[1]^crc[12]^crc[5]^crc[9]^crc[13],
crc[5]^crc[9]^crc[13]^crc[0]^crc[11]^crc[4]^crc[8]^crc[12],
crc[4]^crc[15]^crc[8]^crc[12],
crc[3]^crc[14]^crc[7]^crc[11]^crc[15],
crc[2]^crc[13],
crc[1]^crc[12]^crc[6]^crc[10]^crc[14]^crc[5]^crc[9]^crc[13],
crc[0]^crc[11]^crc[4]^crc[8]^crc[12]
};
end
endmodule
x393_hispi.bit
View file @ 5cc1817c
No preview for this file type
x393_hispi.timing_summary_impl 0 → 100644
View file @ 5cc1817c
This diff is collapsed.
x393_hispi_utilization.report 0 → 100644
View file @ 5cc1817c
This diff is collapsed.
x393_parallel.bit
View file @ 5cc1817c
No preview for this file type
x393_parallel.timing_summary_impl 0 → 100644
View file @ 5cc1817c
This diff is collapsed.
x393_parallel_utilization.report 0 → 100644
View file @ 5cc1817c
This diff is collapsed.
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