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x393
Commit 5cc1817c authored by Andrey Filippov's avatar Andrey Filippov
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merged with lwir, tiff for both sensors

parents f894cd31 cc525170
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Showing with 11247 additions and 77 deletions
.gitignore
View file @ 5cc1817c
......@@ -49,6 +49,7 @@ x393_testbench03_01.sav
simulation_data/*.dat
simulation_data/*.jpeg
#these two project files are now in .eclipse_project_setup directory
py393/.project
/.project
/.pydevproject
/.settings
......
cocotb/x393_cocotb_03.sav
View file @ 5cc1817c
[*]
[*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI
[*] Sat Mar 30 21:44:35 2019
[*] Thu Apr 4 15:14:53 2019
[*]
[dumpfile] "/data_ssd/nc393/elphel393/fpga-elphel/x393/simulation/x393_dut-20190330003307254.fst"
[dumpfile_mtime] "Sat Mar 30 08:20:05 2019"
[dumpfile_size] 828570003
[dumpfile] "/data_ssd/nc393/elphel393/fpga-elphel/x393/simulation/x393_dut-20190403200123296.fst"
[dumpfile_mtime] "Thu Apr 4 02:19:11 2019"
[dumpfile_size] 92419986
[savefile] "/data_ssd/nc393/elphel393/fpga-elphel/x393/cocotb/x393_cocotb_03.sav"
[timestart] 389800000
[timestart] 71920000
[size] 1804 1171
[pos] -1 -1
*-24.894814 449301250 447727388 448849888 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-23.676386 109647388 447727388 448849888 102260291 102291500 102322774 102354054 3061832388 143392388 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_dut.
[treeopen] x393_dut.simul_lwir160x120_vospi_i.
[treeopen] x393_dut.simul_sensor12bits_2_i.
[treeopen] x393_dut.simul_sensor12bits_3_i.
[treeopen] x393_dut.simul_sensor12bits_4_i.
[treeopen] x393_dut.simul_sensor12bits_i.
[treeopen] x393_dut.x393_i.
[treeopen] x393_dut.x393_i.compressor393_i.
......@@ -23,12 +25,16 @@
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_buf_iface_i.
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.cmprs_frame_sync_i.
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.huffman_stuffer_meta_i.
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.cmprs_frame_sync_i.
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.huffman_stuffer_meta_i.
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_27_32_i.
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.cmprs_frame_sync_i.
[treeopen] x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.huffman_stuffer_meta_i.
......@@ -44,39 +50,153 @@
[treeopen] x393_dut.x393_i.frame_sequencer_block[0].cmd_frame_sequencer_i.
[treeopen] x393_dut.x393_i.mcntrl393_i.
[treeopen] x393_dut.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.
[treeopen] x393_dut.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.
[treeopen] x393_dut.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.
[treeopen] x393_dut.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.
[treeopen] x393_dut.x393_i.mcntrl393_i.memctrl16_i.
[treeopen] x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.
[treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].
[treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.
[treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.
[treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[1].
[treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[2].
[treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[2].mcntrl_linear_wr_sensor_i.
[treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[2].mcntrl_tiled_rd_compressor_i.
[treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[3].
[treeopen] x393_dut.x393_i.mcntrl393_i.sens_comp_block[3].mcntrl_tiled_rd_compressor_i.
[treeopen] x393_dut.x393_i.mult_saxi_wr_i.mult_saxi_wr_pointers_i.
[treeopen] x393_dut.x393_i.sensors393_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.genblk1.sens_histogram_0_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.lens_flat393_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_histogram_mux_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_membuf_i.chn1wr_buf_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[1].
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.lens_flat393_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_sync_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[2].
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.sens_histogram_0_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.lens_flat393_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.sens_sync_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.lens_flat393_i.
[treeopen] x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.sens_sync_i.
[treeopen] x393_dut.x393_i.timing393_i.camsync393_i.
[treeopen] x393_dut.x393_i.timing393_i.camsync393_i.i_frsync_pclk0.
[sst_width] 580
[signals_width] 275
[sst_width] 351
[signals_width] 322
[sst_expanded] 1
[sst_vpaned_height] 486
[sst_vpaned_height] 727
@820
x393_dut.TEST_TITLE[639:0]
@c00200
-LWIR0
@28
x393_dut.simul_lwir160x120_vospi_i.mclk
x393_dut.simul_lwir160x120_vospi_i.miso
x393_dut.simul_lwir160x120_vospi_i.ncs
x393_dut.simul_lwir160x120_vospi_i.nrst
x393_dut.simul_lwir160x120_vospi_i.sck
@22
x393_dut.simul_lwir160x120_vospi_i.copy_packet[7:0]
@28
x393_dut.simul_lwir160x120_vospi_i.frame_start
x393_dut.simul_lwir160x120_vospi_i.copy_run
x393_dut.simul_lwir160x120_vospi_i.copy_page
x393_dut.simul_lwir160x120_vospi_i.copy_done
x393_dut.simul_lwir160x120_vospi_i.copy_crc
@8022
x393_dut.simul_lwir160x120_vospi_i.copy_packet[7:0]
@c08022
x393_dut.simul_lwir160x120_vospi_i.copy_word[6:0]
@28
(0)x393_dut.simul_lwir160x120_vospi_i.copy_word[6:0]
(1)x393_dut.simul_lwir160x120_vospi_i.copy_word[6:0]
(2)x393_dut.simul_lwir160x120_vospi_i.copy_word[6:0]
(3)x393_dut.simul_lwir160x120_vospi_i.copy_word[6:0]
(4)x393_dut.simul_lwir160x120_vospi_i.copy_word[6:0]
(5)x393_dut.simul_lwir160x120_vospi_i.copy_word[6:0]
(6)x393_dut.simul_lwir160x120_vospi_i.copy_word[6:0]
@1401200
-group_end
@22
x393_dut.simul_lwir160x120_vospi_i.copy_packet_full[7:0]
x393_dut.simul_lwir160x120_vospi_i.copy_packet_indx[11:0]
x393_dut.simul_lwir160x120_vospi_i.copy_packet_segment[7:0]
@c00022
x393_dut.simul_lwir160x120_vospi_i.copy_packet_ttt[7:0]
@28
(0)x393_dut.simul_lwir160x120_vospi_i.copy_packet_ttt[7:0]
(1)x393_dut.simul_lwir160x120_vospi_i.copy_packet_ttt[7:0]
(2)x393_dut.simul_lwir160x120_vospi_i.copy_packet_ttt[7:0]
(3)x393_dut.simul_lwir160x120_vospi_i.copy_packet_ttt[7:0]
(4)x393_dut.simul_lwir160x120_vospi_i.copy_packet_ttt[7:0]
(5)x393_dut.simul_lwir160x120_vospi_i.copy_packet_ttt[7:0]
(6)x393_dut.simul_lwir160x120_vospi_i.copy_packet_ttt[7:0]
(7)x393_dut.simul_lwir160x120_vospi_i.copy_packet_ttt[7:0]
@1401200
-group_end
@28
x393_dut.simul_lwir160x120_vospi_i.copy_pix_only
x393_dut.simul_lwir160x120_vospi_i.copy_pix_or_tel
x393_dut.simul_lwir160x120_vospi_i.copy_pixels_pix
@22
x393_dut.simul_lwir160x120_vospi_i.copy_pxd[15:0]
x393_dut.simul_lwir160x120_vospi_i.copy_d[15:0]
x393_dut.simul_lwir160x120_vospi_i.copy_din[15:0]
@8022
x393_dut.simul_lwir160x120_vospi_i.copy_wa[6:0]
x393_dut.simul_lwir160x120_vospi_i.copy_wa_full[15:0]
@28
x393_dut.simul_lwir160x120_vospi_i.copy_run
x393_dut.simul_lwir160x120_vospi_i.copy_tel_only
@22
x393_dut.simul_lwir160x120_vospi_i.copy_telemetry_d[15:0]
@c00022
x393_dut.simul_lwir160x120_vospi_i.copy_telemetry_packet[7:0]
@28
(0)x393_dut.simul_lwir160x120_vospi_i.copy_telemetry_packet[7:0]
(1)x393_dut.simul_lwir160x120_vospi_i.copy_telemetry_packet[7:0]
(2)x393_dut.simul_lwir160x120_vospi_i.copy_telemetry_packet[7:0]
(3)x393_dut.simul_lwir160x120_vospi_i.copy_telemetry_packet[7:0]
(4)x393_dut.simul_lwir160x120_vospi_i.copy_telemetry_packet[7:0]
(5)x393_dut.simul_lwir160x120_vospi_i.copy_telemetry_packet[7:0]
(6)x393_dut.simul_lwir160x120_vospi_i.copy_telemetry_packet[7:0]
(7)x393_dut.simul_lwir160x120_vospi_i.copy_telemetry_packet[7:0]
@1401200
-group_end
@22
x393_dut.simul_lwir160x120_vospi_i.copy_wa[6:0]
x393_dut.simul_lwir160x120_vospi_i.copy_wa_full[15:0]
x393_dut.simul_lwir160x120_vospi_i.copy_word[6:0]
x393_dut.simul_lwir160x120_vospi_i.crc_in[15:0]
x393_dut.simul_lwir160x120_vospi_i.crc_out[15:0]
@28
x393_dut.simul_lwir160x120_vospi_i.en_avg
@22
x393_dut.simul_lwir160x120_vospi_i.frame_average32[31:0]
x393_dut.simul_lwir160x120_vospi_i.frame_average[15:0]
@8022
x393_dut.simul_lwir160x120_vospi_i.frame_dly_cntr[19:0]
@22
x393_dut.simul_lwir160x120_vospi_i.frame_sum[30:0]
@8022
x393_dut.simul_lwir160x120_vospi_i.ms_cntr[31:0]
x393_dut.simul_lwir160x120_vospi_i.time_ms[31:0]
@28
x393_dut.simul_lwir160x120_vospi_i.mclk
x393_dut.simul_lwir160x120_vospi_i.mrst
x393_dut.simul_lwir160x120_vospi_i.nrst
@200
-
@1401200
-LWIR0
@800200
-SENSOR0
@28
......@@ -103,6 +223,7 @@ x393_dut.simul_sensor12bits_i.ivact
@22
x393_dut.simul_sensor12bits_i.state[3:0]
x393_dut.simul_sensor12bits_i.stated[3:0]
x393_dut.simul_sensor12bits_i.cntrd[15:0]
@8022
x393_dut.simul_sensor12bits_i.cntr[15:0]
@1000200
......@@ -118,6 +239,8 @@ x393_dut.simul_sensor12bits_2_i.D[11:0]
x393_dut.simul_sensor12bits_2_i.VACT
x393_dut.simul_sensor12bits_2_i.HACT
x393_dut.simul_sensor12bits_2_i.stopped
@22
x393_dut.simul_sensor12bits_2_i.cntr[15:0]
@1401200
-SENSOR1
@c00200
......@@ -148,7 +271,7 @@ x393_dut.simul_sensor12bits_3_i.stated[3:0]
x393_dut.simul_sensor12bits_3_i.cntr[15:0]
@1401200
-SENSOR2
@c00200
@800200
-SENSOR3
@28
x393_dut.simul_sensor12bits_4_i.ARO
......@@ -159,7 +282,9 @@ x393_dut.simul_sensor12bits_4_i.D[11:0]
x393_dut.simul_sensor12bits_4_i.VACT
x393_dut.simul_sensor12bits_4_i.HACT
x393_dut.simul_sensor12bits_4_i.stopped
@1401200
@22
x393_dut.simul_sensor12bits_4_i.cntr[15:0]
@1000200
-SENSOR3
@c00200
-ARO
......@@ -2779,7 +2904,7 @@ x393_dut.IMU_SDA
x393_dut.IMU_TAPS[5:1]
@1401200
-IMU_
@800200
@c00200
-debuf_frame_sync_x
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.prst
......@@ -2851,7 +2976,7 @@ x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.want
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.xfer_want
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.xfer_grant
(2)x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.xfer_start_r[2:0]
@1000200
@1401200
-debuf_frame_sync_x
@c00200
-camsync_ext_int
......@@ -3001,6 +3126,7 @@ x393_dut.x393_i.timing393_i.camsync393_i.restart_cntr[31:0]
@28
x393_dut.x393_i.frame_sequencer_block[0].cmd_frame_sequencer_i.frame_sync
@22
[color] 2
x393_dut.x393_i.frame_sequencer_block[0].cmd_frame_sequencer_i.frame_no[3:0]
@1000200
-cmd_frame_seq0
......@@ -3027,10 +3153,18 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sensor_i2c_io_i.sensor_i2c_i.use_eof
@1401200
-i2c_seq_0
@c00200
@800200
-sensor_channel0
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.bit16
@22
x393_dut.PX1_D[11:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.pxd[11:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_parallel12_i.pxd_out[11:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.pxd[11:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.lens_flat393_i.pxd_in[15:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.lens_flat393_i.pxd_in[15:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.lens_flat393_i.pxd_out[15:0]
@800200
-buf
@28
......@@ -3080,9 +3214,50 @@ x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_
x393_dut.x393_i.sensors393_i.sensor_channel_block[0].sensor_channel_i.sens_sync_i.sof_out_pclk
@1000200
-sesns_sync
@1401200
-sensor_channel0
@800200
-sensor_channel1
@22
x393_dut.PX2_D[11:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.sens_parallel12_i.pxd[11:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.pxd[11:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.lens_flat393_i.pxd_in[15:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_channel_i.lens_flat393_i.pxd_out[15:0]
@800200
-buf
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_membuf_i.px_valid
x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_membuf_i.wpage[1:0]
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_membuf_i.waddr[8:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_membuf_i.px_data[15:0]
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_membuf_i.mclk
@22
x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_membuf_i.buf_dout[63:0]
@28
x393_dut.x393_i.sensors393_i.sensor_channel_block[1].sensor_membuf_i.buf_rd
@1000200
-buf
-sensor_channel1
@800200
-sensor_channel2
@22
x393_dut.PX3_D[11:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.lens_flat393_i.pxd_in[15:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.lens_flat393_i.pxd_out[15:0]
@200
-
@1000200
-sensor_channel2
@800200
-sensor_channel3
@22
x393_dut.PX4_D[11:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.lens_flat393_i.pxd_in[15:0]
x393_dut.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.lens_flat393_i.pxd_out[15:0]
@1000200
-sensor_channel3
-sequencers_0
@22
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.window_height[16:0]
......@@ -3135,18 +3310,22 @@ x393_dut.x393_i.sof_out_mclk[3:0]
(3)x393_dut.x393_i.sof_out_mclk[3:0]
@1401200
-group_end
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.buf_we
@22
x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.buf_din[63:0]
@c00200
-jpeg3
@800200
-memsensor3
@22
x393_dut.x393_i.mcntrl393_i.sens_comp_block[2].mcntrl_linear_wr_sensor_i.window_height[16:0]
x393_dut.x393_i.mcntrl393_i.sens_comp_block[2].mcntrl_linear_wr_sensor_i.window_width[13:0]
x393_dut.x393_i.mcntrl393_i.sens_comp_block[3].mcntrl_linear_wr_sensor_i.window_height[16:0]
x393_dut.x393_i.mcntrl393_i.sens_comp_block[3].mcntrl_linear_wr_sensor_i.window_width[13:0]
@1000200
-memsensor3
@22
x393_dut.x393_i.mcntrl393_i.sens_comp_block[2].mcntrl_tiled_rd_compressor_i.window_height[16:0]
x393_dut.x393_i.mcntrl393_i.sens_comp_block[2].mcntrl_tiled_rd_compressor_i.window_width[13:0]
x393_dut.x393_i.mcntrl393_i.sens_comp_block[3].mcntrl_tiled_rd_compressor_i.window_height[16:0]
x393_dut.x393_i.mcntrl393_i.sens_comp_block[3].mcntrl_tiled_rd_compressor_i.window_width[13:0]
x393_dut.x393_i.mcntrl393_i.sens_comp_block[2].mcntrl_tiled_rd_compressor_i.tile_rows[6:0]
x393_dut.x393_i.mcntrl393_i.sens_comp_block[2].mcntrl_tiled_rd_compressor_i.tile_vstep[6:0]
@28
......@@ -3282,8 +3461,21 @@ x393_dut.x393_i.compressor393_i.cmprs_channel_block[3].jp_channel_i.huffman_stuf
@1401200
-bit_stuffer_27_32
-jpeg3
@c00200
@800200
-jpeg2
-memsensor2
@22
x393_dut.x393_i.mcntrl393_i.sens_comp_block[2].mcntrl_linear_wr_sensor_i.window_height[16:0]
x393_dut.x393_i.mcntrl393_i.sens_comp_block[2].mcntrl_linear_wr_sensor_i.window_width[13:0]
@1000200
-memsensor2
@22
x393_dut.x393_i.mcntrl393_i.sens_comp_block[2].mcntrl_tiled_rd_compressor_i.window_height[16:0]
x393_dut.x393_i.mcntrl393_i.sens_comp_block[2].mcntrl_tiled_rd_compressor_i.window_width[13:0]
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.buf_we
@22
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.buf_din[63:0]
@28
x393_dut.x393_i.mcntrl393_i.sens_comp_block[2].mcntrl_tiled_rd_compressor_i.chn_en
x393_dut.x393_i.mcntrl393_i.sens_comp_block[2].mcntrl_tiled_rd_compressor_i.chn_rst
......@@ -3328,6 +3520,9 @@ x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.huffman_stuf
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.huffman_stuffer_meta_i.stuffer_bytes[1:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.huffman_stuffer_meta_i.stuffer_dv
x393_dut.x393_i.mcntrl393_i.sens_comp_block[2].mcntrl_tiled_rd_compressor_i.xfer_start32_rd
x393_dut.x393_i.mcntrl393_i.sens_comp_block[2].mcntrl_tiled_rd_compressor_i.xfer_start_rd
x393_dut.x393_i.mcntrl393_i.sens_comp_block[2].mcntrl_tiled_rd_compressor_i.xfer_start_lin_rd
@c00200
-bit_stuffer
@28
......@@ -3393,9 +3588,23 @@ x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.huffman_stuf
-
@1401200
-bit_stuffer
@1000200
-jpeg2
@c00200
@800200
-jpeg1
-memsensor1
@22
x393_dut.x393_i.mcntrl393_i.sens_comp_block[1].mcntrl_linear_wr_sensor_i.window_height[16:0]
x393_dut.x393_i.mcntrl393_i.sens_comp_block[1].mcntrl_linear_wr_sensor_i.window_width[13:0]
@1000200
-memsensor1
@22
x393_dut.x393_i.mcntrl393_i.sens_comp_block[1].mcntrl_tiled_rd_compressor_i.window_height[16:0]
x393_dut.x393_i.mcntrl393_i.sens_comp_block[1].mcntrl_tiled_rd_compressor_i.window_width[13:0]
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.buf_we
@22
x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.buf_din[63:0]
@28
x393_dut.x393_i.mcntrl393_i.sens_comp_block[1].mcntrl_tiled_rd_compressor_i.chn_en
x393_dut.x393_i.mcntrl393_i.sens_comp_block[1].mcntrl_tiled_rd_compressor_i.chn_rst
......@@ -3440,7 +3649,11 @@ x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.huffman_stuf
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.huffman_stuffer_meta_i.stuffer_bytes[1:0]
x393_dut.x393_i.compressor393_i.cmprs_channel_block[2].jp_channel_i.huffman_stuffer_meta_i.stuffer_dv
@1401200
@200
-
@22
x393_dut.x393_i.compressor393_i.cmprs_channel_block[1].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.imgsz4[21:0]
@1000200
-jpeg1
@c00200
-debug_raw_x
......@@ -3581,6 +3794,7 @@ x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_run_mc
@800200
-debug_interference_raw0
@28
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.xfer_need
[color] 3
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.xfer_want
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.xfer_grant
......@@ -3597,6 +3811,9 @@ x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.chn_rd_buf_i
@28
x393_dut.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.enc_done
x393_dut.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.enc_wr
@22
x393_dut.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.enc_cmd[31:0]
@28
x393_dut.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.gen_run
@22
x393_dut.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_wr_i.num128[6:0]
......@@ -3620,6 +3837,9 @@ x393_dut.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.start
-encode_tiled_rd
@28
x393_dut.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.enc_wr
@22
x393_dut.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.enc_cmd[31:0]
@28
x393_dut.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.enc_done
x393_dut.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.gen_run
x393_dut.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.pre_act
......@@ -3628,7 +3848,7 @@ x393_dut.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.pre_don
x393_dut.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.start
@1000200
-encode_tiled_rd
@800200
@c00200
-mcntrl_sheduler
@c00022
x393_dut.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.want_conf[15:0]
......@@ -3658,9 +3878,9 @@ x393_dut.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.grant_r
@22
x393_dut.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.grant_chn[3:0]
x393_dut.x393_i.mcntrl393_i.memctrl16_i.scheduler16_i.grant_chn_r[3:0]
@1000200
@1401200
-mcntrl_sheduler
@800200
@c00200
-mcntrl_sequencer
@28
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.ext_buf_rd
......@@ -3704,10 +3924,11 @@ x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.buf_rdata[63:0]
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.buf_wr
@22
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.buf_wdata[63:0]
@1000200
@1401200
-mcntrl_sequencer
@1000200
-debug_interference_raw0
@800200
@c00200
-raw_0
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.raw_be16
......@@ -3946,7 +4167,6 @@ x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.mem_
-
@1401200
-mcntrl_tiled_linear
@1000200
-raw_0
@c00200
-cmprs_raw_buf_iface_i
......@@ -4066,6 +4286,19 @@ x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_raw_bu
-cmprs_raw_buf_iface_i
@800200
-jpeg0
-memsensor0
@22
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.window_height[16:0]
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.window_width[13:0]
@1000200
-memsensor0
@22
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.window_height[16:0]
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.window_width[13:0]
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.buf_we
@22
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.buf_din[63:0]
@c00200
-raw_dbg
@28
......@@ -4121,7 +4354,7 @@ x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuf
-
@1401200
-raw_dbg
@c00200
@800200
-stuffer_raw0
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.raw_prefb
......@@ -4148,6 +4381,204 @@ x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.chn_
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.frame_en
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.frame_start
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_frame_sync_i.frames_numbers_differ
@800200
-mem
@22
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.window_width[13:0]
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.window_height[16:0]
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.next_y[16:0]
@28
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.last_row_w
@8028
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.last_in_row_w
@22
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.curr_x[12:0]
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.row_left[13:0]
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.recalc_r[8:0]
[color] 3
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.line_unfinished_relw_r[15:0]
[color] 3
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.line_unfinished_r[15:0]
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.row_left[13:0]
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.row_col_r[21:0]
@28
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.frame_done
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.frame_finished
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.busy_r
@8022
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.pending_xfers[1:0]
@28
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.xfer_limited_by_mem_page_r
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.start_not_partial
[color] 2
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.next_page
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.xfer_want
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.xfer_grant
@22
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.page_cntr[2:0]
@8028
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.xfer_start_r[2:0]
@28
x393_dut.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_tiled_rd_compressor_i.xfer_page_done
@1000200
-mem
@800200
-encode_lin_rd
@28
x393_dut.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.start
@22
x393_dut.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.bank[2:0]
x393_dut.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.row[14:0]
x393_dut.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.start_col[6:0]
x393_dut.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.num128_in[5:0]
@c00022
x393_dut.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.enc_cmd[31:0]
@28
(0)x393_dut.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.enc_cmd[31:0]
(1)x393_dut.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.enc_cmd[31:0]
(2)x393_dut.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.enc_cmd[31:0]
(3)x393_dut.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.enc_cmd[31:0]
(4)x393_dut.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.enc_cmd[31:0]
(5)x393_dut.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.enc_cmd[31:0]
(6)x393_dut.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.enc_cmd[31:0]
(7)x393_dut.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.enc_cmd[31:0]
(8)x393_dut.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.enc_cmd[31:0]
(9)x393_dut.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.enc_cmd[31:0]
(10)x393_dut.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.enc_cmd[31:0]
(11)x393_dut.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.enc_cmd[31:0]
(12)x393_dut.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.enc_cmd[31:0]
(13)x393_dut.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.enc_cmd[31:0]
(14)x393_dut.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.enc_cmd[31:0]
(15)x393_dut.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.enc_cmd[31:0]
(16)x393_dut.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.enc_cmd[31:0]
(17)x393_dut.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.enc_cmd[31:0]
(18)x393_dut.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.enc_cmd[31:0]
(19)x393_dut.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.enc_cmd[31:0]
(20)x393_dut.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.enc_cmd[31:0]
(21)x393_dut.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.enc_cmd[31:0]
(22)x393_dut.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.enc_cmd[31:0]
(23)x393_dut.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.enc_cmd[31:0]
(24)x393_dut.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.enc_cmd[31:0]
(25)x393_dut.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.enc_cmd[31:0]
(26)x393_dut.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.enc_cmd[31:0]
(27)x393_dut.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.enc_cmd[31:0]
(28)x393_dut.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.enc_cmd[31:0]
(29)x393_dut.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.enc_cmd[31:0]
(30)x393_dut.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.enc_cmd[31:0]
(31)x393_dut.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.enc_cmd[31:0]
@1401200
-group_end
@28
x393_dut.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.enc_wr
x393_dut.x393_i.mcntrl393_i.cmd_encod_linear_rw_i.cmd_encod_linear_rd_i.enc_done
@1000200
-encode_lin_rd
@800200
-encode_tiled_rd
@28
x393_dut.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.start
@22
x393_dut.x393_i.mcntrl393_i.cmd_encod_tiled_32_rw_i.cmd_encod_tiled_rd_i.bank[2:0]
@200
-
@1000200
-encode_tiled_rd
@800200
-mseq
@22
x393_dut.x393_i.mcntrl393_i.memctrl16_i.seq_data[31:0]
@28
x393_dut.x393_i.mcntrl393_i.memctrl16_i.seq_wr
x393_dut.x393_i.mcntrl393_i.memctrl16_i.seq_set
x393_dut.x393_i.mcntrl393_i.memctrl16_i.grant_r
@22
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd1_addr[9:0]
@28
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd1_we
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.ren1
@22
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_addr[9:0]
@c00022
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_word[31:0]
@28
(0)x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_word[31:0]
(1)x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_word[31:0]
(2)x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_word[31:0]
(3)x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_word[31:0]
(4)x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_word[31:0]
(5)x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_word[31:0]
(6)x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_word[31:0]
(7)x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_word[31:0]
(8)x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_word[31:0]
(9)x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_word[31:0]
(10)x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_word[31:0]
(11)x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_word[31:0]
(12)x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_word[31:0]
(13)x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_word[31:0]
(14)x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_word[31:0]
(15)x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_word[31:0]
(16)x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_word[31:0]
(17)x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_word[31:0]
(18)x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_word[31:0]
(19)x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_word[31:0]
(20)x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_word[31:0]
(21)x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_word[31:0]
(22)x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_word[31:0]
(23)x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_word[31:0]
(24)x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_word[31:0]
(25)x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_word[31:0]
(26)x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_word[31:0]
(27)x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_word[31:0]
(28)x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_word[31:0]
(29)x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_word[31:0]
(30)x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_word[31:0]
(31)x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_word[31:0]
@1401200
-group_end
@28
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.cmd_fetch
[color] 2
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_nop
@22
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.pause_len[9:0]
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.pause_cntr[9:0]
@28
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.pause
@800200
-phy_cmd
@22
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.pause_len[9:0]
@28
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.sequence_done
@22
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_addr_in[14:0]
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_bank_in[2:0]
@800028
[color] 3
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_rcw_pos[2:0]
@28
[color] 3
(0)x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_rcw_pos[2:0]
[color] 3
(1)x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_rcw_pos[2:0]
[color] 3
(2)x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_rcw_pos[2:0]
@1001200
-group_end
@28
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_odt_in
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_cke_dis
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.add_pause
@200
-
@1000200
-phy_cmd
@22
x393_dut.x393_i.mcntrl393_i.memctrl16_i.mcontr_sequencer_i.phy_cmd_i.phy_addr_in[14:0]
@200
-
@1000200
-mseq
@22
[color] 6
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.cmprs_frame_sync_i.line_unfinished_src[15:0]
......@@ -4204,11 +4635,36 @@ x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuf
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.stuffer_dv
@28
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.trailer
@22
@c00022
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.imgsz4[21:0]
@28
(0)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.imgsz4[21:0]
(1)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.imgsz4[21:0]
(2)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.imgsz4[21:0]
(3)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.imgsz4[21:0]
(4)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.imgsz4[21:0]
(5)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.imgsz4[21:0]
(6)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.imgsz4[21:0]
(7)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.imgsz4[21:0]
(8)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.imgsz4[21:0]
(9)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.imgsz4[21:0]
(10)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.imgsz4[21:0]
(11)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.imgsz4[21:0]
(12)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.imgsz4[21:0]
(13)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.imgsz4[21:0]
(14)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.imgsz4[21:0]
(15)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.imgsz4[21:0]
(16)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.imgsz4[21:0]
(17)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.imgsz4[21:0]
(18)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.imgsz4[21:0]
(19)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.imgsz4[21:0]
(20)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.imgsz4[21:0]
(21)x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_metadata_i.imgsz4[21:0]
@1401200
-group_end
@1000200
-stuffer_raw0
@c00200
@800200
-bit_stuffer
@22
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_27_32_i.xclk
......@@ -4237,9 +4693,8 @@ x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuf
x393_dut.x393_i.compressor393_i.cmprs_channel_block[0].jp_channel_i.huffman_stuffer_meta_i.bit_stuffer_27_32_i.stage[1:0]
@200
-
@1401200
-bit_stuffer
@1000200
-bit_stuffer
-jpeg0
[pattern_trace] 1
[pattern_trace] 0
cocotb/x393_dut.v
View file @ 5cc1817c
......@@ -418,14 +418,16 @@ module x393_dut#(
parameter PF_STRIPES=WOI_HEIGHT/PF_HEIGHT;
`else
parameter PF_HEIGHT=0; // SuppressThisWarning VEditor - not used
parameter FULL_HEIGHT=WOI_HEIGHT+4;
parameter PF_STRIPES=0; // SuppressThisWarning VEditor - not used
`endif
parameter WOI_MARGINS = 0; // 4;
parameter VIRTUAL_WIDTH= FULL_WIDTH + HBLANK;
parameter VIRTUAL_HEIGHT= FULL_HEIGHT + BLANK_ROWS_BEFORE + BLANK_ROWS_AFTER; //SuppressThisWarning Veditor UNUSED
parameter TRIG_INTERFRAME= 100; /// extra 100 clock cycles between frames //SuppressThisWarning Veditor UNUSED
parameter TRIG_DELAY= 200; /// delay in sensor clock cycles // SuppressThisWarning VEditor - not used
parameter FULL_WIDTH= WOI_WIDTH+4;
parameter FULL_WIDTH= WOI_WIDTH + WOI_MARGINS;
parameter FULL_HEIGHT= WOI_HEIGHT + WOI_MARGINS;
// localparam SENSOR_MEMORY_WIDTH_BURSTS = (FULL_WIDTH + 15) >> 4;
// localparam SENSOR_MEMORY_MASK = (1 << (FRAME_WIDTH_ROUND_BITS-4)) -1;
// localparam SENSOR_MEMORY_FULL_WIDTH_BURSTS = (SENSOR_MEMORY_WIDTH_BURSTS + SENSOR_MEMORY_MASK) & (~SENSOR_MEMORY_MASK);
......@@ -670,22 +672,35 @@ module x393_dut#(
`else
//connect parallel12 sensor to sensor port 2 (all data rotated left by 1 bit)
assign sns2_dp[6:1] = {PX2_D[9], PX2_D[7], PX2_D[5], PX2_D[3], PX2_D[1], PX2_HACT};
assign sns2_dn[6:0] = {PX2_D[10], PX2_D[8], PX2_D[6], PX2_D[4], PX2_D[2], PX2_VACT, PX2_DCLK};
assign sns2_clkn = PX2_D[11]; // inout CNVSYNC/TDI
assign sns2_clkp = PX2_D[0]; // CNVCLK/TDO
/// assign sns2_dp[6:1] = {PX2_D[9], PX2_D[7], PX2_D[5], PX2_D[3], PX2_D[1], PX2_HACT};
/// assign sns2_dn[6:0] = {PX2_D[10], PX2_D[8], PX2_D[6], PX2_D[4], PX2_D[2], PX2_VACT, PX2_DCLK};
/// assign sns2_clkn = PX2_D[11]; // inout CNVSYNC/TDI
/// assign sns2_clkp = PX2_D[0]; // CNVCLK/TDO
assign sns2_dp[6:1] = {PX2_D[10], PX2_D[8], PX2_D[6], PX2_D[4], PX2_D[2], PX2_HACT};
assign sns2_dn[6:0] = {PX2_D[11], PX2_D[9], PX2_D[7], PX2_D[5], PX2_D[3], PX2_VACT, PX2_DCLK};
assign sns2_clkn = PX2_D[0]; // inout CNVSYNC/TDI
assign sns2_clkp = PX2_D[1]; // CNVCLK/TDO
//connect parallel12 sensor to sensor port 3 (all data rotated left by 2 bits
assign sns3_dp[6:1] = {PX3_D[8], PX3_D[6], PX3_D[4], PX3_D[2], PX3_D[0], PX3_HACT};
assign sns3_dn[6:0] = {PX3_D[9], PX3_D[7], PX3_D[5], PX3_D[3], PX3_D[1], PX3_VACT, PX3_DCLK};
assign sns3_clkn = PX3_D[10]; // inout CNVSYNC/TDI
assign sns3_clkp = PX3_D[11]; // CNVCLK/TDO
/// assign sns3_dp[6:1] = {PX3_D[8], PX3_D[6], PX3_D[4], PX3_D[2], PX3_D[0], PX3_HACT};
/// assign sns3_dn[6:0] = {PX3_D[9], PX3_D[7], PX3_D[5], PX3_D[3], PX3_D[1], PX3_VACT, PX3_DCLK};
/// assign sns3_clkn = PX3_D[10]; // inout CNVSYNC/TDI
/// assign sns3_clkp = PX3_D[11]; // CNVCLK/TDO
assign sns3_dp[6:1] = {PX3_D[10], PX3_D[8], PX3_D[6], PX3_D[4], PX3_D[2], PX3_HACT};
assign sns3_dn[6:0] = {PX3_D[11], PX3_D[9], PX3_D[7], PX3_D[5], PX3_D[3], PX3_VACT, PX3_DCLK};
assign sns3_clkn = PX3_D[0]; // inout CNVSYNC/TDI
assign sns3_clkp = PX3_D[1]; // CNVCLK/TDO
//connect parallel12 sensor to sensor port 4 (all data rotated left by 3 bits
assign sns4_dp[6:1] = {PX4_D[5], PX4_D[3], PX4_D[1], PX4_D[11], PX4_D[9], PX4_HACT};
assign sns4_dn[6:0] = {PX4_D[6], PX4_D[4], PX4_D[2], PX4_D[0], PX4_D[10], PX4_VACT, PX4_DCLK};
assign sns4_clkn = PX4_D[7]; // inout CNVSYNC/TDI
assign sns4_clkp = PX4_D[8]; // CNVCLK/TDO
/// assign sns4_dp[6:1] = {PX4_D[5], PX4_D[3], PX4_D[1], PX4_D[11], PX4_D[9], PX4_HACT};
/// assign sns4_dn[6:0] = {PX4_D[6], PX4_D[4], PX4_D[2], PX4_D[0], PX4_D[10], PX4_VACT, PX4_DCLK};
/// assign sns4_clkn = PX4_D[7]; // inout CNVSYNC/TDI
/// assign sns4_clkp = PX4_D[8]; // CNVCLK/TDO
assign sns4_dp[6:1] = {PX4_D[10], PX4_D[8], PX4_D[6], PX4_D[4], PX4_D[2], PX4_HACT};
assign sns4_dn[6:0] = {PX4_D[11], PX4_D[9], PX4_D[7], PX4_D[5], PX4_D[3], PX4_VACT, PX4_DCLK};
assign sns4_clkn = PX4_D[0]; // inout CNVSYNC/TDI
assign sns4_clkp = PX4_D[1]; // CNVCLK/TDO
`endif
`endif
......@@ -1552,6 +1567,40 @@ simul_axi_hp_wr #(
.clk_out (PX4_MCLK) // output
);
/* Instance template for module simul_lwir160x120_vospi */
wire lwir1_miso;
simul_lwir160x120_vospi #(
.DATA_FILE ("/data_ssd/nc393/elphel393/fpga-elphel/x393/input_data/pattern_160_120_14.dat"),
.WINDOW_WIDTH (160),
.WINDOW_HEIGHT (120),
.TELEMETRY (2), // 1),
.FRAME_PERIOD (946969),
.FRAME_DELAY (100),
.MS_PERIOD (25) // 1us instead of 1 ms
) simul_lwir160x120_vospi_i (
.mclk (x393_i.ps7_i.SAXIHP0ACLK), // PX1_MCLK), // input temporarily made faster
.nrst ( PX1_MRST), // input
.sck ( 1'b0), // input
.ncs ( 1'b0), // inout
.miso ( lwir1_miso), // output
.telemetry_rev ( 16'h7654), // input[15:0]
.telemetry_status ( 32'h137f1248), // input[31:0]
.telemetry_srev (64'h0123456789abcdef), // input[63:0]
.telemetry_temp_counts ( 16'd59000), // input[15:0]
.telemetry_temp_kelvin ( 16'd29500), // input[15:0]
.telemetry_temp_last_kelvin ( 16'd29300), // input[15:0]
.telemetry_time_last_ms ( 32'h12345678), // input[31:0]
.telemetry_agc_roi_top ( 16'd0), // input[15:0]
.telemetry_agc_roi_left ( 16'd0), // input[15:0]
.telemetry_agc_roi_bottom ( 16'd119), // input[15:0]
.telemetry_agc_roi_right ( 16'd159), // input[15:0]
.telemetry_agc_high (16'd19200), // input[15:0]
.telemetry_agc_low ( 16'd200), // input[15:0]
.telemetry_video_format (32'haaaa5555) // input[31:0]
);
simul_sensor12bits #(
.SENSOR_IMAGE_TYPE (SENSOR_IMAGE_TYPE0),
.lline (VIRTUAL_WIDTH), // SENSOR12BITS_LLINE),
......@@ -1572,7 +1621,8 @@ simul_axi_hp_wr #(
.tDDO1 (SENSOR12BITS_TDDO1),
.trigdly (TRIG_LINES), // SENSOR12BITS_TRIGDLY),
.ramp (0), //SENSOR12BITS_RAMP),
.new_bayer (0) // was 1 SENSOR12BITS_NEW_BAYER)
.new_bayer (0), // was 1 SENSOR12BITS_NEW_BAYER)
.EXTRA_PERIOD(0)
) simul_sensor12bits_i (
.MCLK (PX1_MCLK), // input
.MRST (PX1_MRST), // input
......@@ -1611,7 +1661,9 @@ simul_axi_hp_wr #(
.tDDO1 (SENSOR12BITS_TDDO1),
.trigdly (TRIG_LINES), // SENSOR12BITS_TRIGDLY),
.ramp (0), //SENSOR12BITS_RAMP),
.new_bayer (0) //SENSOR12BITS_NEW_BAYER) was 1
.new_bayer (0), //SENSOR12BITS_NEW_BAYER) was 1
.EXTRA_PERIOD (50)
) simul_sensor12bits_2_i (
.MCLK (PX2_MCLK), // input
`ifdef DISABLE_SENSOR_2
......@@ -1653,7 +1705,8 @@ simul_axi_hp_wr #(
.tDDO1 (SENSOR12BITS_TDDO1),
.trigdly (TRIG_LINES), // SENSOR12BITS_TRIGDLY),
.ramp (0), // SENSOR12BITS_RAMP),
.new_bayer (0) // was 1SENSOR12BITS_NEW_BAYER)
.new_bayer (0), // was 1SENSOR12BITS_NEW_BAYER)
.EXTRA_PERIOD(100)
) simul_sensor12bits_3_i (
.MCLK (PX3_MCLK), // input
.MRST (PX3_MRST), // input
......@@ -1691,7 +1744,8 @@ simul_axi_hp_wr #(
.tDDO1 (SENSOR12BITS_TDDO1),
.trigdly (TRIG_LINES), // SENSOR12BITS_TRIGDLY),
.ramp (0),// SENSOR12BITS_RAMP),
.new_bayer (0) // was 1SENSOR12BITS_NEW_BAYER)
.new_bayer (0), // was 1SENSOR12BITS_NEW_BAYER)
.EXTRA_PERIOD(120)
) simul_sensor12bits_4_i (
.MCLK (PX4_MCLK), // input
.MRST (PX4_MRST), // input
......
fpga_version.vh
View file @ 5cc1817c
......@@ -35,8 +35,12 @@
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
parameter FPGA_VERSION = 32'h03930105; // parallel - 17.4 - fixing wide raw frames
parameter FPGA_VERSION = 32'h03930107; // parallel - 17.4 - restored delay after linear, foxed bug, all met
// parameter FPGA_VERSION = 32'h03930110; //A serial - 17.4 - restored delay after linear, foxed bug, timing met
// parameter FPGA_VERSION = 32'h03930110; // serial - 17.4 - restored delay after linear, foxed bug, timing failed
// parameter FPGA_VERSION = 32'h03930107; // parallel - 17.4 - restored delay after linear, foxed bug, all met
// parameter FPGA_VERSION = 32'h03930106; // parallel - 17.4 - increased delay after linear read all met
// parameter FPGA_VERSION = 32'h03930105; // parallel - 17.4 - fixed wide raw frames all met
// parameter FPGA_VERSION = 32'h03930104; // parallel - 17.4 - added RAW mode (for tiff files) timing met
// parameter FPGA_VERSION = 32'h03930103; // serial - 17.4 - trigger polarity on GP1 inverted
// parameter FPGA_VERSION = 32'h03930102; // serial - 17.4 - disabling SOF when setting interface, bug fix
......
includes/x393_simulation_parameters.vh
View file @ 5cc1817c
......@@ -79,17 +79,43 @@
// parameter SENSOR_IMAGE_TYPE2 = "NORM11", // 4",
// parameter SENSOR_IMAGE_TYPE3 = "NORM12",
parameter SENSOR_IMAGE_TYPE0 = "TEST01-1044X36", // "NORM13",
parameter SENSOR_IMAGE_TYPE1 = "TEST01-1044X36", // "NORM13",
parameter SENSOR_IMAGE_TYPE2 = "TEST01-1044X36", // "NORM14", // 4",
parameter SENSOR_IMAGE_TYPE3 = "TEST01-1044X36", // "NORM15",
// parameter SENSOR_IMAGE_TYPE0 = "TEST01-1044X36", // "NORM13",
// parameter SENSOR_IMAGE_TYPE1 = "TEST01-1044X36", // "NORM13",
// parameter SENSOR_IMAGE_TYPE2 = "TEST01-1044X36", // "NORM14", // 4",
// parameter SENSOR_IMAGE_TYPE3 = "TEST01-1044X36", // "NORM15",
// parameter SENSOR_IMAGE_TYPE0 = "TEST01-260X36", // "NORM13",
// parameter SENSOR_IMAGE_TYPE1 = "TEST01-260X36", // "NORM13",
// parameter SENSOR_IMAGE_TYPE2 = "TEST01-260X36", // "NORM14", // 4",
// parameter SENSOR_IMAGE_TYPE3 = "TEST01-260X36", // "NORM15",
parameter SIMULATE_CMPRS_CMODE0 = CMPRS_CBIT_CMODE_JPEG18,
parameter SIMULATE_CMPRS_CMODE1 = CMPRS_CBIT_CMODE_JPEG18,
parameter SIMULATE_CMPRS_CMODE2 = CMPRS_CBIT_CMODE_JP4,
parameter SIMULATE_CMPRS_CMODE3 = CMPRS_CBIT_CMODE_JP4,
// parameter SENSOR_IMAGE_TYPE0 = "TEST01-260X68", // "NORM13",
// parameter SENSOR_IMAGE_TYPE1 = "TEST01-260X68", // "NORM13",
// parameter SENSOR_IMAGE_TYPE2 = "TEST01-260X68", // "NORM14", // 4",
// parameter SENSOR_IMAGE_TYPE3 = "TEST01-260X68", // "NORM15",
// parameter SENSOR_IMAGE_TYPE0 = "260X260A", // "NORM13",
// parameter SENSOR_IMAGE_TYPE1 = "260X260A", // "NORM13",
// parameter SENSOR_IMAGE_TYPE2 = "260X260A", // "NORM14", // 4",
// parameter SENSOR_IMAGE_TYPE3 = "260X260A", // "NORM15",
parameter SENSOR_IMAGE_TYPE0 = "256X256A", // "NORM13",
parameter SENSOR_IMAGE_TYPE1 = "256X256A", // "NORM13",
parameter SENSOR_IMAGE_TYPE2 = "256X256A", // "NORM14", // 4",
parameter SENSOR_IMAGE_TYPE3 = "256X256A", // "NORM15",
// parameter SENSOR_IMAGE_TYPE0 = "512X512A", // "NORM13",
// parameter SENSOR_IMAGE_TYPE1 = "512X512A", // "NORM13",
// parameter SENSOR_IMAGE_TYPE2 = "512X512A", // "NORM14", // 4",
// parameter SENSOR_IMAGE_TYPE3 = "512X512A", // "NORM15",
//
parameter SIMULATE_CMPRS_CMODE0 = CMPRS_CBIT_CMODE_JP4, // CMPRS_CBIT_CMODE_JPEG18,
parameter SIMULATE_CMPRS_CMODE1 = CMPRS_CBIT_CMODE_JP4, // CMPRS_CBIT_CMODE_JPEG18,
parameter SIMULATE_CMPRS_CMODE2 = CMPRS_CBIT_CMODE_JP4, // CMPRS_CBIT_CMODE_JPEG18, // CMPRS_CBIT_CMODE_JP4,
parameter SIMULATE_CMPRS_CMODE3 = CMPRS_CBIT_CMODE_JP4, // CMPRS_CBIT_CMODE_JPEG18, // CMPRS_CBIT_CMODE_JP4,
// parameter SIMULATE_CMPRS_CMODE2 = CMPRS_CBIT_CMODE_JPEG18,
// parameter SIMULATE_CMPRS_CMODE3 = CMPRS_CBIT_CMODE_JPEG18,
// CMPRS_CBIT_CMODE_JPEG18, //input [31:0] cmode; // [13:9] color mode:
......@@ -134,8 +160,8 @@
parameter HISTOGRAM_START_PAGE = 20'h12345,
parameter FRAME_WIDTH_ROUND_BITS = 9, // multiple of 512 pixels (32 16-byte bursts) (11 - ful SDRAM page)
parameter WOI_WIDTH= 1040, // 64,
parameter WOI_HEIGHT= 32,
parameter WOI_WIDTH= 256, // 512, // 256, //1040, // 64,
parameter WOI_HEIGHT= 256, // 512, // 256, // 64, // 32,
parameter QUADRANTS_PXD_HACT_VACT = 6'h01, // 2 bits each: data-0, hact - 1, vact - 2
// 90-degree shifts for data [1:0], hact [3:2] and vact [5:4]
......
input_data/img256x256-12b.dat 0 → 100644
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input_data/img260x260-12b.dat 0 → 100644
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input_data/img260x260x12b.dat 0 → 100644
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input_data/img516x516-12b.dat 0 → 100644
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input_data/marching1_12b_260x36.dat 0 → 100644
View file @ 5cc1817c
//
// autogenerated from /data_ssd/nc393/elphel393/fpga-elphel/x393/attic/marching1_12b_260x36.tiff
//
000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000
000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000 000
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input_data/marching1_12b_260x68.dat 0 → 100644
View file @ 5cc1817c
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// autogenerated from /data_ssd/nc393/elphel393/fpga-elphel/x393/attic/marching1_12b_260x36.tiff
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input_data/pattern_160_120_14.dat 0 → 100644
View file @ 5cc1817c
//
// autogenerated from /data_ssd/nc393/elphel393/fpga-elphel/x393/input_data/pattern_160_120_14.tiff
//
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3478 34e9 350d 354d 35f4 3703 3799 398b 3255 20eb 15aa 1cf9 3b91 37ec 3607 3628 3651 3645 3678 3674 363a 35f6 366c 36e2 38e9 3001 117c 1333 147a 151b 144d 1463 1548 1661 165e 1667 17fd 172d 23f1 3c31 3a12 3be1 3c64 2669 14e2 1697 1787 1729 1683 1506 1427 14a8 14d1 12b6 2783 3af3 39a4 3799 3783 3823 3886 38e6 3b1e 3852 1c37 1638 1857 194e 1965 18ad 1709 1e0f 3b72 3a4c 3a03 3a32 39b9 398b 39ba 396f 39f0 3a5c 3b1f 3cf2 3dee 3e6e 3e94 3e21 3c9c 3aaa 3a11 395f 3977 3926 3856 3885 3970 3acf 3761 1736 15fc 15c2 1670 159c 1649 1649 156e 1458 14c7 1629 165d 1484 14ef 16e1 17a4 15fe 1418 1472 151a 168a 16c5 159b 15b1 168c 30af 3aab 3883 38e7 384c 3810 3843 377c 3734 3813 38ba 38cb 38e0 379d 372b 3768 3773 37a3 3875 38b1 3812 3831 397e 3b54 29a7 12f3 139b 120e 135a 15f8 167e 1622 15ce 1597 161a 14e3
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361d 3656 36f8 3743 3702 3979 1d68 12e4 156e 167a 1641 1488 17a6 2efd 3ad9 365a 3593 358f 35b6 35e2 36f2 37d8 3983 3bba 22e6 139e 151c 150a 155f 1568 149e 150e 15bb 1548 122a 226e 386b 3cb4 3dcd 2669 147a 1919 1944 1906 1820 1879 1731 168b 14ae 1515 170a 167a 2645 3c84 3922 38ef 3833 3863 3879 38ad 38a4 3951 3979 3989 3b19 36f4 15b7 159b 16a2 2563 3aa8 3a20 3941 387f 3837 38b7 38ef 3915 398a 3b2e 3b20 22b0 18e9 1a76 19b7 1998 19c6 199c 1a35 193b 2699 3c36 39a2 3834 375c 3747 384e 3c1a 2098 1514 1586 159e 16a8 164b 16e8 16dc 1617 151d 1457 1234 1428 182d 19c0 1724 1269 1341 164d 15b7 1536 14c9 1698 1785 18cf 181c 201b 3bdc 3af9 3a0d 3944 38f6 3831 37f5 37fe 3876 3889 3901 392a 38e1 38e6 38af 381e 3770 37cd 3812 37e7 377f 3741 3716 37b1 3b7e 263e 1199 13f1 155a 1742 1775 164e 155f 162e 1601
3642 374e 37e8 3768 38c0 30d2 1234 13d4 141c 15e3 1625 15de 1641 180c 2d85 3ad9 38f5 379d 3702 37b1 3960 3b96 3b0e 252c 1402 1530 154b 14ea 15ac 1619 1539 155c 1509 12e9 23b5 3a9b 398a 389b 3a73 3386 151c 18ca 19b9 194a 180b 180b 186f 176c 159a 16cb 1869 180a 3358 3b85 391b 38d7 38a3 3897 38a7 38dc 395f 3a25 3a95 3c39 3de7 3b2b 2043 2419 33c5 3c35 3a0d 38f9 389e 3887 37e8 37fe 3881 3839 38d8 3bf7 2525 16ed 17dc 185f 1a57 19cd 1a0f 1996 1897 194b 1904 2e8b 3c04 3875 37f6 3873 3bc8 3138 1461 14e9 1580 155c 165e 16d6 1786 18bf 1600 137e 17d5 2903 3578 38ef 393e 37c8 2fb8 1df1 1227 158c 1534 1491 1640 1739 18b7 1845 243a 3d03 3a63 39f0 3956 38c4 3829 3808 37b6 3893 38d7 3920 396c 39dc 39a0 3972 3883 37c7 3788 3795 376f 3745 36f2 3643 3763 3acf 2f0a 1219 13a0 1420 163d 16ad 1672 1691 169f 15eb
36d8 37c3 374f 3756 39be 271f 0f7e 13dc 14c4 1586 1555 15a2 15b0 1524 1637 2365 3272 392f 39a7 3a28 37ff 2d9f 1cfc 1493 157c 158d 14f6 1450 15f7 162d 15df 1521 13f4 1d90 3a7e 386e 379f 3809 3873 3bd6 23d5 162e 1a9f 1a45 1981 187d 1882 17c0 1748 169c 1472 23ce 3b40 38d7 3840 3884 38b7 38ec 38a6 3902 398c 3a9f 3d8d 389b 2ab2 21d5 37ab 3de7 3bdc 39b0 38d9 38da 387c 3871 385b 37ec 3828 38b1 3b0b 33c9 175d 17d7 17f7 18c6 1a6e 19e7 18b7 18d4 1820 18e8 181c 1e2f 3a8b 3ad3 3a39 3d21 3689 1929 1443 1556 1747 169d 164b 15ff 16e9 173f 13fd 1f31 3730 3bd1 39b5 3844 378b 3815 3a91 3aa1 26ec 110e 14dd 15b7 1612 1766 1852 1814 2e2a 3cc9 3a65 3a30 39af 38bd 389e 3826 37e2 38db 3971 3a7b 3bed 3ca9 3cd9 3be9 3a01 385c 37ff 37cd 379d 3769 36cb 35f3 376f 3a08 313e 12f2 13a2 143e 14f0 16d1 1651 1606 15d5 15d8
371d 3746 36cd 3713 39f5 234e 0fa4 13a3 1668 1756 1569 168f 151c 14b6 1535 1522 17be 1ad2 1c45 1d85 1a0f 1683 15c0 15b2 15c2 1650 1513 14de 1528 1403 1392 1420 1435 2fe9 3b0c 3846 37f0 380a 38e0 3a9e 394b 1de8 14fe 18a6 18b0 1874 173b 1619 1482 1442 1eea 38be 3995 37c6 3796 3865 3919 394c 394e 39ff 3ada 3d1a 2d9f 1b80 17ea 17d3 3465 3c39 38b4 38f8 3914 3903 38e3 38e3 3863 37b6 3831 3969 3d3f 2653 15ec 17c7 18bf 1952 1974 1958 190d 18ca 1948 187b 183e 17fd 32ec 3fa0 3d47 32dd 1c0d 16c4 1779 18f8 18a4 1848 177e 170a 15d9 14d6 1dba 3a80 3aae 3872 3864 37e3 37ce 375d 3818 38bd 3bce 24ad 11ec 15d6 1795 1856 1840 1e0a 3b22 3c36 3abb 3a25 3981 38bd 38bd 388f 3857 3904 3bb3 3b70 3401 2ebd 2e9e 3385 3ae5 3c68 398e 3888 3811 3777 36ae 3666 3708 3a95 2fd1 1316 1387 1534 15e1 16fe 166b 1558 155d 168d
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362d 3656 3659 3696 3857 2e4a 0f12 1346 15b1 14d0 1553 1493 1471 13f4 138d 123f 12da 1260 128c 13c6 1453 13b6 1405 15c7 14fa 16e8 165f 154b 15ea 15fb 15f8 14f6 1f81 3b57 3882 380d 3750 3894 391b 39b9 3a58 3aab 3c30 3690 2b97 2684 26e0 2b23 359b 3b7d 3a29 3994 38be 3843 37fa 382d 38de 3957 3a67 3c84 3555 1951 1912 18e9 17cd 174a 194b 34cf 3c19 38a3 383f 3841 3845 383c 38cb 3893 39dd 3d7c 26dd 1604 16a6 1714 1862 18f6 18a2 18d1 1761 1617 155c 25cb 373e 3da8 30e0 13d6 166f 1848 174a 1693 1676 167a 162d 15a6 1538 1570 1614 21e6 3ce3 39f1 38e4 386b 388b 3881 3852 3831 3837 3888 3962 3d40 246c 11dc 1340 176a 2f5b 3c84 3994 3913 3930 390e 3926 390a 3913 39e8 3c56 2902 14b3 150c 1695 1710 16a3 1735 1718 1812 2c23 3c9a 38dc 37eb 374d 36d5 37d8 39dd 1995 11f1 12d4 1401 155f 161f 1570 152c 146a 13e1
3618 365f 3641 364e 36ce 371a 1642 1229 1591 1578 1591 14a8 13ae 13d5 14a1 1490 1445 1425 14e4 1554 1663 16d2 15db 153f 154d 1615 15b9 1615 15b2 169e 15d1 1580 22e1 3cac 38c1 385a 383c 38bf 38fc 39b0 39ee 3a06 3983 3a5c 3b65 3be8 3b91 3b61 3a24 3909 3920 3921 391b 3814 387e 388c 3915 397d 3a9f 3d33 2358 18f6 1a5e 19ac 19c0 1900 1825 1f4f 38c1 3d25 3a6d 3988 3907 38db 395c 3b05 3d25 2b13 1716 1756 1614 169a 175f 1768 1752 1744 16e2 160d 2e5b 3d55 3bab 3aa2 389e 175e 156d 18eb 18f5 182e 1745 1788 16f6 1606 1509 15d2 1636 2fe5 3d1f 39dd 392c 3936 3902 38ee 38f8 3934 38a3 38c0 3a90 3ed8 2dbc 1569 234c 357e 3bdf 3974 3921 3902 38e8 38da 3916 3917 398a 3cb0 2ee1 13dd 151a 165e 1698 1679 168b 186e 17dc 1720 187a 32cb 3adc 3774 36e3 3683 3ab5 2bf7 1187 1334 13d5 151e 16a0 15a3 15b7 1492 1486 12a6
35b9 35d2 35ec 3602 366f 3985 2bd6 10a0 14bd 15b3 1505 1459 14e3 1579 1630 1597 15ce 158d 156b 16da 1776 16f0 160b 15a2 161f 1784 17a2 1685 1656 16a2 1673 16c2 217b 3c27 38d8 388e 388d 38ec 38aa 38b3 3864 3852 3869 38cf 38dc 38d1 38cd 384c 3894 38c7 38fa 3964 38c8 389f 390a 38e3 3934 38ff 3a5d 38d3 19ee 199d 1a51 1ac0 19f1 19a7 1a23 19b2 1e90 30cc 3b97 3d50 3d2d 3d1a 3cd2 3761 2531 16d9 17fa 182b 1805 18a4 17cb 17ea 177a 171e 15b6 29a1 3da6 39e2 399f 393a 3c3e 263e 13fc 17e5 18b1 1947 18a6 18b9 1885 17fa 17f0 15bf 1fa9 3c42 3b4c 3a05 39b8 394c 3977 39f5 3a08 3a22 3a09 3c2e 362b 2946 2a1c 3a2f 3bda 3a76 38b9 3942 3951 3928 3928 3974 395b 3922 3a2e 390e 1983 1503 163b 16df 177c 179c 1779 1801 1796 173b 1658 2280 3b79 3751 3809 3b5d 32f2 1598 1387 14cc 14dc 16ac 171b 1709 1624 15d6 12dd 21c7
3558 360e 3633 3645 3711 37af 3a30 260a 11eb 142c 1493 1385 13f0 14b2 1620 1585 1570 14d5 159d 16cc 1690 15ed 15f2 15c4 16c8 1780 173e 16a9 1577 15f8 1639 1730 1b90 38b9 39d7 38ab 384e 384d 38b6 38e5 3860 382d 383c 37fd 37ed 380d 37f3 37fc 383b 3867 3990 398a 3906 38ae 388a 38d2 3985 39ce 3b87 3446 172a 1a2b 1a25 19b0 1905 196e 1899 19d0 1917 1a34 200b 272d 2ae6 28b0 22f6 1b32 17a0 173b 17b9 17f1 1869 185f 18cf 18dd 18c1 1816 1de0 3bb4 3b98 39b4 3959 39b1 3a98 398c 1cfd 15ba 1818 182c 17a5 1858 1898 183c 15b6 1941 35be 3cab 3b00 3a82 39b7 3964 39e6 3a47 3a99 3b07 3c21 2900 17d8 151b 22c0 3dba 39fc 38da 385b 3825 385c 38a8 3911 38e8 391d 3921 3c02 2c43 12ac 15cf 16a0 16ad 1738 161f 16c9 16ff 1653 166c 15cc 1758 370c 3c45 3ba2 2ff1 1719 12ca 15ed 14fb 148b 161c 17d0 16d2 170c 1536 23f4 3bef
3587 361f 3608 3642 36ad 376a 3813 39f2 2995 151c 108e 1140 138e 13c7 14ed 1572 15c8 1453 156c 1682 16ad 157c 15b7 1689 16c9 1718 16ec 16a9 155f 1613 163b 1720 17a0 2e2b 3c41 389c 3865 3890 38da 38c1 385f 38b1 383c 37d0 381e 380b 37e9 37ef 37e0 3895 397a 3943 3915 38bd 38d9 3983 399a 3a69 3c14 3446 16d3 19ae 1a83 197f 197b 194e 189c 1989 18de 192d 1969 184c 17b8 183e 1874 18b3 172c 16bf 178c 16d6 166e 1729 1779 17e0 177a 1757 2bc9 3d5f 3a0a 3a78 39df 3a43 3a2b 3bfc 389a 210b 169c 1637 16bf 171c 1562 14f7 1d44 3422 3c56 3a2c 3a54 3a5a 3a5d 39c5 39ec 3a4c 3b57 3cb8 25e2 15cf 167f 17f8 1ccc 396c 3b49 3923 383e 3831 37c5 37fe 385d 3866 38fa 3a44 3bf5 1c64 1346 1582 16bc 1701 1881 164f 1546 1476 13fc 127d 15d0 1f51 3014 2b2f 1e1a 146f 1429 154c 15ef 1552 1445 1557 1667 1729 168c 1d0c 3b0f 3ab5
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3543 3546 3573 3605 363e 3690 3708 3744 36c0 379a 3916 399d 2bea 1430 1295 14c2 1500 1572 160f 1607 160d 154a 15c8 15ca 167a 1591 164b 1652 15d3 16e7 1665 1588 16d6 16d2 20d1 391c 3bda 3917 37e5 3821 37ce 36e1 3683 368d 3715 374e 375b 375b 376d 37d5 37ce 37e1 3795 37a9 3800 3898 38ca 3971 39e4 3bfc 1f84 15fc 18d9 1957 1880 1826 1881 17f6 1785 171a 1693 17b2 1759 15d2 156e 174e 181c 178f 17b4 176c 170c 15a7 1581 15b2 1775 1956 368a 3ab7 38f4 38c0 38bb 38a4 389c 38f6 3935 3a36 3aef 3bb8 3b4b 3b1d 3c0d 3be0 3a66 3904 37e9 379b 37d8 37fd 3825 382f 38ff 3ae5 38c4 1a36 16f4 1738 1966 18e3 18e9 1b78 31df 3e47 3b12 38ea 38fe 3944 38e2 3a5c 3d12 3022 15c6 139f 13cb 1589 162d 1686 175b 173e 1641 17bd 31e5 3d5a 3a56 3bca 328b 146b 154c 169a 15f6 16a5 1788 1783 1751 172f 1680 164b 1ae8 39d4 3af7 391e
343e 34d4 34f3 3531 35c4 3648 3671 35c6 3607 3604 35f5 36d1 3a97 3151 13e3 145b 146a 1465 150b 1793 17d8 1547 1575 14bc 153e 1587 162c 1614 15dc 1651 1699 1610 15c0 168a 15c4 1d3b 2fe0 39f8 3b62 3990 37a1 3685 35e9 3689 36bb 3677 3650 3649 36a1 36cf 377b 3743 3701 3772 37f9 37ea 3844 38cd 397b 3bd7 30b2 15c9 16a7 17a4 1686 1663 1715 1808 1824 17ae 16ff 1682 1651 155a 15ab 15b6 1707 16c7 16f0 16e3 16ef 1590 14fe 154f 1602 1797 356f 3aa2 3909 38a8 3853 380d 3809 37cb 37fb 3870 385b 387b 3932 3985 3935 38dc 3846 37b9 374e 3721 3775 3772 378a 376c 3867 3b80 2d16 16ba 1811 16f8 1846 181d 175c 17ed 1af3 2d16 3b11 3d7f 3c9a 3c70 3c6b 390a 2817 156a 13e3 1452 1471 1597 15fa 165e 1617 1656 1549 306f 3d2c 396b 3886 397b 3afe 1de3 132b 161e 180e 1816 1751 17dc 1737 1787 1774 15e1 2a59 3cfc 3953 38de
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33dc 3448 348a 3484 3450 3538 34ec 350d 3546 352d 34e5 34d4 3587 3610 3a44 2396 1206 14c0 1502 1612 14e9 15fb 1695 161c 155f 13d8 1308 1345 141d 1462 1488 1501 1670 1647 155c 1506 1606 163d 1780 1690 1afc 36f3 3a3b 3898 380f 37d9 3839 388e 3854 3853 3864 383e 387f 3854 37f4 385b 38bf 3938 3956 3951 3996 39b6 3bd5 352f 278b 1993 12fc 1482 1586 162b 178b 189d 180f 1707 166d 1660 16b1 174c 170e 16af 167d 1623 16ac 1791 168f 16af 1860 3521 3c48 38ca 38c2 3920 38f1 38bc 391e 38c1 38eb 3903 395a 38ff 38f5 38ca 3904 38dc 381b 37cd 37ff 38ab 38c8 3912 3975 3c7e 26b9 15f7 17ca 175b 1630 169a 17c4 179e 17ce 16ca 15d0 16e4 165f 15fc 15dd 16a0 1615 1533 1561 153a 1503 15b6 160a 16ca 178c 19b7 38b2 39ab 3825 381e 37d9 380a 3875 3949 3bd0 39a5 2c38 219e 1f00 21c3 2a4b 36cf 3d9f 3ad8 39a0 38dd 388d 3862
33c9 3490 3535 34b4 3520 35b5 35a9 3540 35a7 356f 357e 35aa 364a 3663 39a0 2af7 129e 156c 169c 166c 1597 162e 1632 15dc 16ca 1682 15dd 1433 149f 15b3 15e6 173d 1742 176b 16ea 176e 189a 180c 1821 17d3 1753 2449 3c48 39e5 39b2 399c 3934 396b 3935 3916 38fa 38dc 3930 395f 3912 38eb 3938 3986 38e2 38cc 38d5 38bc 38fa 3aaf 3cbd 3a85 28f8 1548 1559 1602 16c0 17a8 1828 1778 16d7 178b 17ec 1883 182c 17c3 172d 1731 16ff 165e 1646 157b 1698 1e47 38bf 3ca5 3a4c 3a1f 3a50 39c7 39fb 395e 392b 3921 3984 3936 394e 3920 390a 3916 38b4 384d 386f 38b8 38d8 392b 39d0 3b94 3114 1596 174b 17a7 166b 15a5 1663 160b 1731 16d7 1600 17ad 1730 1601 1631 1622 1609 15b9 15e4 1592 15bb 15ee 15cf 167a 176a 1db0 3b07 396f 3857 387e 38b7 38e7 395e 395a 39a4 3a77 3c8a 3cc1 3cd6 3d68 3dbc 3c85 3b3a 3b03 3a6f 39bf 3944 393d
367f 3567 3596 37ad 3916 37ab 3699 3676 35e5 363a 36ac 369d 36fa 374a 3a5c 2d79 138a 1662 16d4 157c 1508 154a 150a 1499 1581 15a6 14fe 1489 15dd 1745 176d 186b 1808 17d6 176f 16e1 180f 17f5 1815 1786 18a0 1a7d 366b 3bc3 3a87 3a9d 3a09 39b9 3975 396c 39a3 39d3 39fe 3a51 39f2 39cf 3986 3981 395a 3907 386c 38b2 394f 399d 3a2e 3b3a 3e6a 2d5a 17b3 1799 1664 1603 16ff 176f 1831 1881 183a 1802 17d8 178a 173e 1758 178d 183f 18b9 1810 1756 17c5 1df9 3206 3c98 3e64 3cc7 3ae9 3a29 39fd 399b 39cc 399e 395f 399e 39b8 39ed 396a 397d 393a 38e6 38c2 38cf 390b 3a0f 3aaa 3b40 1dcc 1613 182b 1746 16c0 16f2 1728 16b1 1704 15f6 1736 16d3 160e 1652 16bc 158c 1524 1569 15c6 154a 1573 1585 16fc 16b7 1d75 3b64 3a4e 38d9 38a5 3881 38d2 38e6 38f2 396f 39b8 3a1a 3a69 3ad4 3ae2 3b20 3b16 3b5c 3b2f 3acd 3a0f 3a1e 3a3b
1895 1509 1596 1af6 2659 34cd 39e3 3733 370f 3670 362b 363f 36e4 36b1 3adc 299f 13c5 155e 1480 1484 1449 1482 1461 13f0 142e 1469 14d0 15b7 1663 175f 15cb 15db 15b2 1563 1640 16a6 16d0 1754 17d6 18b2 196f 1849 2e81 3c7f 3a84 3a5b 39fe 39af 3970 399b 39f1 3a56 3a97 3ab9 3a09 3a53 3a35 3989 3926 394a 3929 3962 397f 39ca 3a2e 3a13 3b02 3e15 25b7 17db 1883 17b1 1724 17ae 186b 1866 1840 17c8 180d 17e5 1730 1792 16d0 1768 1890 1918 188a 17f7 181d 1acc 211e 2c36 3aca 3dfd 3b72 3ae7 3a87 3afe 3aa2 3a4c 3a32 39b1 39e2 39e0 39a5 39fd 39d2 394b 397d 392e 39c8 3a69 3bff 3411 16f0 15dc 17c0 181e 182b 1847 1742 17a0 1663 16b3 173f 1659 1636 1712 15e2 157f 1515 14cb 1536 153f 1572 16af 16a6 1aa0 37f7 3b1e 38d5 3907 390d 38e0 38ed 38d8 38ba 38f1 38ec 39ce 39ca 3a3b 3aab 3ab9 3a77 3ab6 3ac3 3a05 39be 3a3b
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0f27 0f48 0ff5 123b 13de 1646 16bb 17a6 32e5 38dd 368e 3775 392c 3be8 21f3 151b 170d 17ac 1825 18b1 1938 1983 18c8 169f 146f 23a6 3720 3c08 3b82 3b14 3bc8 3c43 3801 2496 13e5 16ea 182d 19b2 193e 1936 1a40 19b0 343d 3c49 3ac1 3a54 3a19 39ee 3a37 3a33 3a66 3adc 3b70 3c26 3c23 3cd2 3d09 3cc5 3c31 3be7 3bc4 3b22 3a74 3a5f 39cb 3966 3a07 3a2a 3d73 21e7 16f8 198a 18dc 1877 186c 192c 19f9 191b 193d 1a9c 1a25 19d6 1af5 1a5b 1aa1 1a0a 19df 1a61 1b12 1bed 1c60 1c81 1b43 1a9d 2767 3e6d 3be8 3ba4 3ae1 3a8b 3aa1 39f3 3993 39b6 39b7 3999 39a0 39b7 39ec 39a2 39e5 3a2a 3a34 3a71 3b18 3b4a 3c79 3d33 30b2 1a86 168b 17f6 16b3 1567 167d 1728 1729 1723 185f 18b3 17b5 158f 1492 14ef 156c 175e 1866 18f5 1929 2418 3b90 3d5b 3ac2 39a2 3960 38f0 38d1 3927 3987 39c9 39b4 39a5 39bb 399e 398c 3993 39b3 3a2e 3a0e 3a5f
0fa2 0f99 10b2 1222 135b 149b 16cd 1688 23f3 3ad2 3878 3b10 3c30 26ef 15f7 1732 17f7 180e 18d5 183a 1879 17d5 1690 1452 2905 3c39 3ab0 38c3 3852 387c 38a2 3873 39d4 3ca8 2898 13fa 1888 1a2a 198c 19fa 18ef 1f72 3b8d 3a58 39f1 3a0c 3a28 3aac 3a15 3a79 3baa 3c31 3c9c 3edd 3e80 3cbf 3c6a 3d0d 3ee7 3e64 3cd4 3c52 3ba8 3ad0 3a32 394c 39fe 39e8 3cda 229f 17fa 1982 1965 18e5 18ef 19fc 1a49 18e1 1836 186f 18aa 17f4 1875 1851 1839 19e1 19e6 18e8 1aa2 1add 1adc 1c09 1c49 1c05 1dd5 3961 3ce9 3af8 3ae2 3ad9 3a4c 3a0d 39ff 3a05 3a68 3a55 3a21 3a7e 3a8a 3a32 3a6b 3a6b 3aa9 3ac3 3a5c 39e8 39e8 3a0a 3d3a 343d 17bf 1713 184b 165c 1698 17bd 18c9 1842 18a0 18e2 17c4 1648 150c 15ca 15fa 15a6 1730 17f1 18d5 1957 2193 332f 3c4d 3d2c 3a8d 39aa 39aa 39d1 3a0f 39fc 3a02 39e4 39d1 39cb 397d 3949 39ea 3a57 3a83 3a59
0e6b 1026 1062 10fe 12c8 148a 14b8 14bb 1887 39e7 3cf0 34e3 2223 1600 17dd 18b5 191b 190d 18b4 188c 1726 15fd 1552 2470 3c5b 399a 3893 3871 38ab 383d 3893 38f7 38da 3a3e 3c8e 2036 151d 19a6 19e8 19a4 17f5 31c8 3cae 3a39 3a3e 3a2c 39ee 39fe 3a28 3b96 3be5 3ddb 3d51 31e6 25c6 21a1 214d 2241 2968 36f1 3ec5 3d1d 3c20 3aef 3a11 39d7 3a9e 3af1 3cf3 1fea 184c 1905 1906 1895 186b 192b 19ec 1a31 1a02 19e9 1881 187f 1803 1833 1816 186b 195b 1908 1933 1b3e 1b09 1bbc 1c0a 1b8e 1b2c 3244 3d92 3b05 3a7d 3a25 3a7c 3a98 3a54 3a79 3a75 3a4d 3a9a 3a8f 3b15 3ae8 3b01 3aa1 3ac6 3acf 3a04 39ff 39e2 39c0 39f1 3df9 29e7 1557 18e2 17aa 1673 175e 1914 19cb 197d 1867 1798 15f5 1581 15d3 15dd 14ca 15e9 1651 1739 18d1 186c 1a0d 1f40 2c66 3b83 3ba9 3a8f 3a35 3a05 3a0b 3a40 3a59 3a4b 3a3d 3a22 3991 39c6 3a47 3a45 3aa8
0dec 0f09 0f8f 11b3 138b 12c4 15fb 213d 2d1a 2a72 1fb5 19c0 1756 17d6 1953 1a55 19c5 1980 18c9 17f5 17d7 169f 1930 3711 3a59 3814 37d8 3835 3881 3876 38b8 3921 38e4 38f8 3bcc 3359 1596 1930 1987 17de 2b4e 3d74 3b38 3a82 3a31 3a24 3a6a 3a2b 3a79 3be8 3e05 381c 22f8 1ae1 1af6 1bb5 1c69 1bce 1b5f 1d19 2e1f 3e64 3c47 3afc 3a33 39f4 3a43 3ca2 3811 18be 196b 193d 1941 1940 19cb 1a53 1a21 1ab0 1b73 1af9 183a 164b 15f9 151e 15b5 1770 1918 19bf 19c6 1b58 1c0e 1c58 1bb2 1c5c 1b87 2f24 3da5 3acc 3a37 3a54 3a7b 3a83 3ad5 3acb 3a1f 3a73 3a9b 3ad4 3b3a 3b43 3b0f 3aa4 3a71 3a7c 3a80 3a17 3977 3a0c 3a1c 3c40 380f 184f 17f9 16a2 164d 1801 18c5 1941 195b 189a 189d 171c 16ee 1769 171c 172b 176a 1848 1850 1887 18a1 1868 17af 17fc 2321 3aa4 3bb6 3a56 3a31 3a4d 3aa0 3ae9 3ac3 3a88 3a70 3a08 3a19 3a60 3a3a 3ac6
0d56 0e44 1035 11d7 108f 1f2a 349d 3b9b 3dd0 289d 1444 17a1 1814 1959 19ea 18cd 174f 1787 17fa 1784 176d 15e0 22e9 3bf9 38eb 387b 3879 38a4 3889 3899 38e7 3949 39be 393d 3aa9 3cb5 1c19 1449 1c64 30d0 3d70 3aca 3a84 39ed 39b2 39d0 39c6 39fe 3ac4 3cf0 39af 1e7b 19af 1bac 1c32 1d74 1d04 1bfb 1b91 1b35 1b69 2f2c 3db5 3ae3 3a4a 3a1a 3a9c 3ea8 28b2 170d 1946 1989 18d9 1910 18c0 1965 18c0 18c3 177a 1937 2540 2dda 3230 3121 29d0 1d89 163a 1779 1877 1993 1a98 1aad 1bb4 1b4e 1b67 326d 3e18 3bb3 3abc 3a9c 3a3e 3a61 3af6 3aa9 3ab1 3abe 3a77 3aed 3ade 3b4f 3b0b 3ac8 3a5b 3a65 3ac7 3a2f 3949 39b0 3a6f 3a83 3c56 1eb5 165e 166b 164d 1887 195f 1985 19dd 17c3 1747 1792 178f 173c 1703 1693 17c5 1837 1808 1814 18d5 183b 1737 17db 18a3 2608 3cbf 3a8f 3a19 3a78 3ab6 3a8b 3a6d 3a5a 3a2b 3a37 3a79 3a81 3aaa 3a8e
0d81 0ee7 10a3 0f3b 204f 39cc 3964 3783 3949 34c7 169a 182e 1932 1a14 1a08 1906 1863 18ed 19fb 19d6 1910 17aa 3195 3c2a 398e 3958 3963 3918 389e 392d 3956 399a 3a34 3ca6 3d44 391f 2c11 2e79 3a0a 3caf 3a95 39f1 3a09 3a1b 3a43 39c1 398f 39f1 3acd 3dbd 25b1 17d8 1b69 1d4a 1c51 1c69 1ca8 1bea 1c38 1b91 1b29 1d48 3840 3b8c 39ad 3a5b 3e00 3460 1989 1823 197c 1a35 1956 196c 194f 1963 1a50 1812 24ea 391d 3ea3 3dc4 3d29 3d9b 3e42 3c0c 2b1f 1658 1824 1a0a 1aa5 1b5d 1b5e 1aec 1c98 3962 3dad 3c44 3b73 3b1b 3aee 3b88 3be7 3b8e 3bc3 3b72 3b63 3b81 3cad 3d52 3c2a 3ae9 3aea 3ab5 3aaf 3a72 39b5 3990 39af 39ec 3d30 215d 14ac 160e 1712 1882 1983 19a8 1931 178f 159d 15eb 1617 168a 16e1 172d 16f4 177a 1764 17cf 1964 186b 17a5 17f0 1911 1ab7 345a 3c53 3ad5 3abe 3a6c 3a26 3a2e 3a68 3a08 3a29 3a4e 3ac7 3af2 3aab
0ce6 0de8 0e9b 185a 384c 37c5 3686 3706 378b 3c10 2656 14c0 1925 1993 1a73 1a50 19bc 18e5 1881 1948 15ff 242c 3c9d 3ab5 3a14 3a50 39ad 3957 3986 39b3 39ea 3ab0 3d37 3405 22e6 1a43 33a4 3e0f 3a94 39be 39ad 39c7 3aba 3aec 39ae 398a 39da 39ce 3bf0 371d 1917 1961 1a85 1af9 1ae9 1adc 1a29 1a8b 1a7a 1aa2 1bc2 197f 2b21 3e2a 3c7f 3e75 346e 1abd 18d1 1a3f 1a7a 1a2f 1aa4 1afd 1abb 1a08 187b 2722 3dbb 3dae 3b8b 3b48 3b65 3b75 3b81 3bec 3e8a 2e32 16b5 18bf 1948 1b33 1ca0 19c1 26cc 3ef8 3d4f 3c93 3c1c 3c6a 3bbf 3c39 3cc1 3c95 3cd7 3e00 3d8a 3927 35d1 36d7 3b7e 3dcf 3c25 3b10 3aa7 39df 3971 38ae 38c1 3998 3cb8 20f4 13fd 1575 1660 17d5 1939 1948 194b 185f 16db 15e4 14d8 14c9 1551 1702 1798 17a9 1752 17f3 18a9 194d 18f0 1944 1942 19dd 2944 3dd5 3b7f 3b1c 3a5c 3a43 3a92 3ab3 3a71 3a89 3ad6 3b44 3b56 3b4a
0beb 0d11 0eba 2bbf 3925 35e1 35ce 368a 37a4 3a32 3aba 208d 157f 19ae 1afc 1b29 1944 17cd 15fe 1436 2048 3a16 3b47 39f4 39ac 39e5 398c 3a2a 3a4f 3a2d 3b23 3d83 2adc 1928 1866 179b 2903 3d28 39aa 3966 39a9 3a73 3a36 3a17 3a0f 3a76 3a92 3af3 3e6f 2b02 17bf 1a87 1a3b 1a1d 19b6 1917 19ac 1a7a 1ad8 19fb 193e 16ed 2242 3d56 3800 291e 19bd 178b 19bb 1ac6 1a9d 1af4 1a98 19ac 19b9 1908 1fa5 3bfd 3bee 3a8b 3a15 3a57 3aa0 3a48 3ab6 3aee 3c0b 3ee1 2510 179b 1a48 1b58 1b06 1cad 387a 3e06 3d29 3cb4 3c23 3bf1 3c5b 3c93 3cbb 3d43 3e8d 3445 2438 1c0b 1aaa 1b0d 1ed3 2b75 3b38 3cc8 3aa5 39a7 38f6 38b5 3978 3a10 3ad7 1bea 157a 16bc 1736 18c7 1946 1915 17df 1749 165c 1641 15b7 1575 1470 1561 16a2 16a7 1659 1738 17de 188c 1939 19df 197a 192e 2317 3cf8 3a8a 3ab1 3afd 3a9b 3acd 3b18 3ab8 3b08 3b07 3b4d 3b34 3b0f
0bdd 0c78 13d4 35e2 36ae 3604 3628 36cc 37d3 390e 3b04 3b73 2950 1a4b 1742 16d7 1556 1477 1746 26c9 3a41 3b34 39fb 39ae 39ab 39d1 39f1 3a80 3aba 3b16 3e0f 2d87 1892 1a48 189e 1761 1c41 3954 3b6e 3964 38d6 3941 3916 3961 39dd 39ff 3a4f 3c77 3a91 1c4c 190e 1a52 1ae5 1ae0 1a83 19ba 1a38 19e1 192a 18ba 21e6 301f 3665 21ad 1ad0 1893 19eb 1a6d 1b11 1afd 1ae3 1b94 1b40 1a8c 1abb 1966 3208 3df3 3af9 3a7c 3a5d 3ab0 3ab5 3b0e 3af4 3b35 3b96 3e25 3669 17b2 193a 17db 1c61 354e 3e15 3ca2 3ca8 3bc1 3b8e 3be0 3c87 3d2d 3d97 3d92 294d 1b18 1a9d 19c6 19cb 19a8 194d 18fc 2284 3a2d 3be1 3a38 3986 3917 39e6 3d42 3390 15b5 16de 1768 17fc 18cf 19f8 195c 1877 17b0 156d 13d0 1454 16b4 1627 1560 1370 1402 1672 1710 1825 17e7 1a08 1b60 19a3 19ef 2386 3d31 3a62 3a56 3adb 3ade 3a9e 3aec 3acc 3b0f 3b37 3b3d 3b32 3b67
0c05 0b5e 1a88 38b7 3619 3642 3633 372f 37ae 38dd 397d 3b08 3d5a 390e 3002 29f2 290d 2d48 372e 3c69 3a46 3959 390e 3916 39d0 39bc 39f5 3a3a 3b4f 3cae 380b 1b17 1957 1985 18c4 17c9 173d 2572 3d11 3bab 397f 387f 384a 389b 3944 396d 3b66 3cfc 2513 1734 187c 198c 1aeb 1b97 1b69 1b17 1a63 1900 1956 2f6e 3d5c 3d87 3e67 213a 16e3 19cb 19f1 1986 1965 19de 1aa6 1aa7 1a94 1a69 1a2d 1e97 3bf7 3c79 3ba6 3bec 3c0c 3b87 3bb6 3be8 3b88 3bea 3c2c 3d84 3e20 1b36 1766 25e3 38b1 3e76 3c78 3c4d 3c27 3bd2 3be4 3c1e 3cac 3d76 3e58 28be 1935 1c74 1c28 1b1b 1a38 1999 19f6 1a03 18c1 2406 3cca 3b95 3ac4 3a3e 3bb5 3e1d 220f 1622 185b 16e6 1818 1885 19e2 1a85 1943 1764 1631 2427 326a 387a 396a 37a3 2ebd 1d57 12f2 165e 1788 1787 19bd 1c09 1afd 1a58 27c5 3e5f 3baa 3ad4 3a52 3ad9 3ad0 3b09 3b1e 3b8a 3bd5 3c3d 3c1a 3bd4
0c2c 0cc2 1daf 391e 3635 3638 3606 36e2 37a1 38c5 39be 3a63 3aea 3c61 3ca9 3d17 3c54 3b62 3a3e 3979 3908 392d 3928 392a 3957 393d 398e 3a0e 3ac1 3d83 292a 17c1 19ef 1a02 1a34 1948 183c 17c1 26c3 3b14 3d2d 3b2e 3a64 3abc 3be9 3dcb 3aab 250c 1764 194e 1a86 1aae 1b40 1b49 1a40 1b77 1a40 188a 3212 3ea2 3b3a 3af4 3d33 2fd6 1663 1999 1be4 1b45 1b26 1a7d 1be7 1c28 1c25 1b83 18ed 2b88 3ed8 3c8f 3c1e 3bc0 3beb 3bc7 3b25 3b7e 3c19 3cff 3ead 3b25 327e 30fe 37c6 3dcc 3d5b 3bf7 3b4e 3b87 3b9f 3b4c 3b5f 3bb3 3c72 3e92 32b7 1a42 1b2b 1ca7 1c40 1b06 1a82 1a89 1a1b 195a 1a14 19f7 3169 3dd0 3b6a 3c55 3f06 2ab0 1672 1808 19b4 18c7 193b 192a 1a00 1a2f 190b 1be6 33d1 3e41 3c5e 3b2f 3a5d 3b4a 3c99 3c56 2828 12c0 1624 180b 1900 1a38 1b68 19e5 32e1 3e7a 3bb3 3ab8 3a33 3aa6 3ad9 3b64 3b9c 3be2 3cb6 3cf7 3d87 3e63
0ce3 0d44 1af4 3965 36c0 370c 3690 373a 3833 3920 395e 398f 39ce 39a9 39d4 3970 391d 38f1 38b8 38c5 387d 38b5 392a 3965 3966 3994 39bb 3a14 3ad0 3c6d 1fe6 18af 1a38 1a80 1aa4 1a42 1925 1825 172c 1ebf 2dd1 3733 3ac9 3aec 36e5 2beb 1d14 1681 17bc 1802 17e7 17be 1887 1805 1795 17c7 16b1 2804 3e36 3b10 3a4d 3a5c 3b13 3c43 20f8 166c 1a2f 1b01 1aed 1afa 1aa1 1ad6 1a87 1802 2037 3b9c 3cbf 3bec 3b46 3b3d 3bc6 3c48 3bfc 3c13 3dbe 3db5 2c8b 1df9 199c 35ea 3ea0 3b73 3b4a 3b34 3a57 3a40 3a7e 3a84 3aea 3b49 3c57 3e0d 22e1 1a60 1af5 1b5a 1bba 1a96 1a98 1ab8 19f7 18db 1986 1999 2483 3f45 3f00 3c93 2969 1719 1771 17b7 1857 182c 16af 1768 1804 1831 1c33 3693 3e10 3a88 39fe 39a8 394b 398f 3991 3ab2 3d55 24d5 12de 169b 17e4 1961 197e 224b 3d5f 3c94 3bca 3b96 3b59 3a98 3afa 3b82 3bd9 3cd4 3f21 3d28 3662 30a5
0da7 0e24 14f7 3636 383b 36f1 36fa 37b0 3839 3885 38cc 3931 39aa 398f 39f6 39b1 3937 38e7 38ea 38ec 38f8 38b9 394a 391a 390e 396a 39c9 3a17 3b14 3ad0 1c32 1941 1b1f 1ab3 1a6d 19f2 1911 17f9 1774 17b0 18bf 1c09 1e5d 1cf6 1a22 181d 17d2 17f1 185c 18e5 18b7 181b 180f 17dd 16ad 16a0 1919 3782 3ba7 39aa 397e 3a48 3a9e 3bc4 396e 1f44 16cd 1a06 1a69 1b51 1a2e 186a 1711 1f3c 3783 3db2 3bce 3b55 3b5d 3b9c 3bc6 3ca4 3cd9 3d8b 3c79 25a6 19f4 1a89 1976 2c4c 3ef1 3b23 3ad7 3ad4 3ab9 3ac8 3a5c 39df 3aa1 3aec 3dcd 3620 1a19 1aa4 1b91 1acf 1b49 1b80 19c5 1a91 1abf 194d 176c 1b8e 2744 3612 2d53 1ef5 172d 183c 1965 191d 18b9 18ab 1669 16f6 190b 1896 3169 3ed7 3adc 39e4 39be 39f0 39de 3997 39d3 3a07 3b7a 38e3 17f5 1558 16ec 1691 1b8c 36d4 3ded 3c58 3c01 3c10 3b9c 3b10 3b9a 3bdc 3ca6 3dc3 306f 2132 1aa6 18d6
0df2 1035 114e 2af0 3b55 376c 376d 37f7 38d4 38ec 3954 39a9 39c4 395c 393c 3914 393a 38e6 393c 3937 3912 3924 397c 3962 3936 39c0 39ff 39ca 3a73 3b5e 1d6c 18cb 188f 1851 18d7 18e4 183c 1849 185d 17d1 17ab 188f 1846 180b 18c6 1849 17f1 189c 19c6 19ba 19ba 1959 1978 18ce 17f9 1892 2166 3d0d 3ada 3a3c 39e4 3a65 3aca 3b66 3d54 3c60 2c62 1d60 18aa 18f2 1873 1cb8 2ad6 3b68 3d65 3ba5 3b0a 3ae6 3b2e 3b98 3bf5 3c54 3ce8 3e2a 26a2 19c6 1bf3 1b4c 1a0c 1f3a 3b68 3dde 3b70 3b80 3b42 3b25 3a98 3a86 3ad8 3c1a 3dd3 23c5 1903 1b16 1bb9 1aff 1b11 1a68 19dd 1954 18bb 1bdb 2f02 3b5f 3da9 1f05 183e 196d 19bc 1a76 1b07 1ac2 1a41 19e9 1843 1685 17f4 204c 3d6e 3c9e 3a5c 39dc 3a38 3a39 3a00 39e9 3a6f 3a74 3aa6 3dec 2368 1219 14e9 1cac 354f 3e09 3bd6 3bc2 3b98 3b80 3b62 3b7e 3c88 3d73 3da2 2772 1870 18d7 1947 1873
0e38 107e 1268 1a11 379c 3ac8 37d1 38ad 38bf 38fb 3967 392f 393c 391f 3953 38fb 393f 38fd 3921 38d1 3884 38f6 3985 3949 3936 39a6 39b5 3977 3a05 3cb4 225d 1629 19bd 1906 19c1 1a23 196b 1945 193d 18b3 1818 17d5 1814 185d 1a1b 1b2e 1b1f 1aa3 1aae 1a9f 1a24 1a29 1adf 1984 1994 19d4 26fe 3df0 3b5e 3a8b 3a6b 3a5a 3a42 3b84 3be0 3c8f 3e23 3b71 3620 3451 365d 3bed 3e95 3ca9 3bef 3b57 3af6 3a71 3aaa 3ad4 3b93 3c07 3e64 32eb 1ab7 1d84 1cc6 1cdc 1aec 1921 26b0 3db2 3dde 3c37 3bb5 3b3d 3b4f 3bb8 3d38 3e47 289a 177b 199c 1a33 1c14 1c3d 1a9d 19da 19f1 18f5 1fcf 3974 3f37 3d6d 3eeb 25a8 17f8 1a67 1af7 1b6b 1b7f 1c48 1ba2 1a4e 1989 17b0 17e8 2db9 3ec4 3bd7 3abb 3aac 3a89 3aa4 3a40 3a59 3ac4 3b15 3cc5 3fbe 2ce5 1b8e 2b70 3b05 3d72 3bad 3b6c 3ab8 3acf 3b2a 3b2a 3b58 3c7f 3eaa 2903 17c4 195d 186b 1854 1796
0e18 101f 1345 15a1 2004 38c1 3c3d 3a9e 3965 3a09 3a3c 39c0 3900 38db 391d 38b6 38c3 38c7 38b7 3890 38d0 38ed 38f8 38ba 38f3 3940 3943 38f6 396d 3b6d 3031 15a2 1945 18d3 1883 18ff 1936 18f0 19c2 1910 18d9 18e5 1984 1996 1a3e 1ab4 1b18 1b39 1aa5 1a0e 197f 19d8 19c2 18fb 1af2 1a57 27ca 3e27 3b65 3a7c 3a38 3a9e 3aff 3b1d 3af8 3b28 3b55 3c29 3d36 3d71 3ceb 3c80 3c50 3ba2 3b04 3a5f 3a94 3a1a 3a61 3ac9 3b2b 3bc8 3e83 2540 1a1b 1cd3 1d63 1d4c 1b24 18d3 1941 25e9 3964 3ebb 3e64 3dd5 3e54 3f00 3a3d 26a0 17e1 19a1 1944 1975 1a55 1b9b 1a9f 19e9 195c 1bf0 38b9 3dca 3ae1 3b52 3d51 34b0 17c9 1a52 1a07 19f6 1a38 1b09 1bae 1b4f 194f 1876 1df0 3b11 3c47 3b6a 3ad3 3b19 3afc 3b35 3b12 3b15 3c4b 3d7d 357f 2748 2d52 3db2 3dfe 3bb6 3a8d 3a95 3a9b 3a0a 3a1e 3a4c 3a81 3aab 3cfd 3558 194e 1aaa 1974 16f5 1794 1841
0e15 1076 1414 1690 15df 1dca 3069 3b00 3d00 3c44 3aa0 39ea 3897 38f1 394e 38ba 386b 384e 385a 3838 3881 38cb 38cf 38c7 38d9 390b 38fa 3901 3949 39e3 3be0 2081 15d1 195a 18f7 199a 19a5 1a24 1938 1898 18df 18f7 1826 1985 1a1f 19b9 1a17 1a14 19f6 190a 1969 1913 1896 1961 1ae1 19fa 254f 3e3f 3b77 3abb 3afa 3b2a 3b2c 3ae2 3ab6 3ac0 3aa6 3af4 3b57 3bc5 3bc9 3bd2 3bd0 3b67 3ae0 3a0b 3a49 39d8 39d6 3a69 3aaf 3bb0 3bfa 1d65 19f4 1b3d 1b12 1b93 1abf 1925 1917 18ba 1d31 2753 2f6d 31ec 3007 27cd 1c92 187a 18f9 18fd 189e 17e3 18dc 193a 1a41 19fc 185f 2de5 3ead 3aeb 398d 3a4f 3b6b 3e5b 2adf 17c0 19be 1abf 1b06 19d2 1a59 19e2 17c7 19ef 34ac 3d2e 3b43 3a41 3a28 3a8e 3b26 3b69 3bb2 3d02 3c51 27d2 1819 150a 247f 3ed8 3b9b 3a32 39c4 3a15 3a12 39c1 39fa 3a10 3a87 3b1b 3e12 2595 17fb 198d 184c 17fe 18ad 17e1
0f0e 11a5 149e 1661 1762 183c 19fc 1ee3 280a 365a 3cbb 39f1 3984 38f0 38d7 385b 3823 3857 38a1 387b 38ad 38a9 3889 38ee 38cf 38be 388d 394c 3a06 3ac2 3c0d 38de 1d6c 170f 196d 1997 19c8 19a3 19fa 19c8 1989 194f 18e8 19c9 1928 1911 192b 1995 1906 1905 1927 1911 1944 1981 1a24 1a5b 1e83 3a73 3c89 3b3e 3c08 3be4 3b25 3b24 3aa3 3a80 3a72 3ab1 3b1f 3b48 3b74 3b71 3b9f 3b44 3b2e 3ad3 3a3d 39e0 39ff 3a53 3afe 3bd2 3b18 1c17 1aaf 1b20 1c6b 1b33 1a2e 19f3 1960 1968 195c 1936 1a15 1af7 1981 1a0b 19b8 1964 193c 18cc 1961 1870 1889 1865 18b2 18cf 1ce9 3a74 3cac 3acb 3a98 3a3a 3b1e 3cdc 3e2f 2d0d 1a4e 193a 1991 1909 1850 174a 1ecc 34b1 3da9 3af5 3a8e 3a43 3a23 3a83 3abf 3b2c 3ca4 3cf9 23b5 16d4 188e 1836 1c3e 3a44 3c58 3a19 39e6 3a2e 3a26 39f2 3a5e 3a3e 3af7 3d66 37fe 18f9 184c 1813 17a1 17f8 16f3 1621
0fed 1134 14f4 1750 17ff 188d 19a3 1a23 1974 1bb7 2ebf 3d05 39b1 3908 387a 37fb 3820 3808 38ae 387e 3877 388a 38b0 3896 389d 3903 3920 39a1 3a25 3ac1 3acb 3c57 39a0 267c 17f0 14dd 178a 18e2 18f9 196b 1931 192b 1847 18b9 1924 19c9 19b0 19d3 199a 199e 1ab8 1932 1964 1988 197d 1aa2 1a7e 2e30 3f35 3caa 3c40 3c40 3b16 3ad6 3af8 3ac2 3a8f 3a94 3ace 3b19 3b9e 3b59 3b6d 3b2c 3ad4 3a8b 3a69 3a50 3a37 3a42 3b02 3ba7 3bf5 1d45 19b6 1acd 1c80 1b5f 19c5 19d8 1a4a 1933 18ad 18b4 187f 194f 19ba 1ae6 1ae3 1a9d 198c 1962 197e 186e 1846 185f 185d 18b4 23c7 3e35 3b56 3aa7 3ab4 3a51 3a97 3b52 3cb6 3ec3 390a 2c27 2378 21e4 255e 30ac 3c72 3d53 3b39 3a72 3a03 3a5a 3a20 3a54 3a7c 3b38 3e1d 2948 16f4 19b9 19bb 18cb 17d6 2a68 3e30 3afc 3a46 3a3c 3a91 3aea 3a8a 3aad 3cae 3d8d 2284 16ab 195d 189c 176e 16c8 15db 14db
109d 11b4 157c 1721 170b 17cd 18fa 194a 18cf 18e1 19cc 304a 3bdf 3935 37e7 380b 3830 382a 3854 384c 3851 3889 38a1 3897 38f7 3953 3968 39d6 3a7e 3a75 3a2d 3a75 3b88 3cdd 37cf 2ce5 1ca3 149d 17a7 1866 1834 197e 192d 18c7 19af 1a95 19ed 1a7c 1a11 1a6c 1a09 184f 199a 196c 199c 1a6d 1b00 1f2b 36ea 3fcf 3cdc 3b7e 3b91 3b33 3b1d 3b13 3aff 3b23 3b54 3bb8 3bbb 3b5a 3ba7 3aeb 3a50 3a2c 3a5d 3a7c 3a76 3a52 3a99 3af9 3ddf 2482 17ad 1ad5 1c06 1ab4 1940 1a62 1a1d 19a5 191e 1950 1823 18c3 19dc 1a99 1a1d 19ee 1997 1a42 1995 1933 18c0 183e 18ab 18e3 2681 3e50 3af5 3a68 3a5b 3a99 3ae1 3b14 3bae 3c7c 3da4 3ec0 3e33 3dfe 3ecd 3e95 3cdb 3b83 3b1c 3a99 39f4 3a25 3a02 3a7c 3afc 3c4c 3823 19af 18a9 197a 186a 179f 17bd 1930 2e78 3e37 3cd7 3b53 3b4d 3bc5 3ce0 3e46 3b97 250a 15d9 1856 18ae 18c1 1761 163b 1586 145c
1114 1283 1598 16e3 1738 184e 19e4 1986 190c 19b2 1979 1d0f 387a 3999 382b 3857 3883 3872 3844 3870 38a7 3875 38f1 38f1 3944 395a 3980 39c6 39fb 39d9 391f 396b 3990 39a5 3af9 3cc8 3ac6 2661 14bb 17d6 1859 1897 190e 18d4 19d8 1b53 1b60 1c70 1b44 1b16 1af5 1a17 1a94 1a32 1a16 19fc 1a41 1b4c 2036 342b 3ed6 3e2e 3ced 3bc9 3ba9 3bb9 3ba6 3b7a 3b8e 3c31 3c02 3bc0 3bc0 3ae0 3ae0 3aae 3a65 3adb 3b18 3b0f 3b64 3b78 3d8d 33e0 17bd 1a18 1c23 1bd9 198e 1a7a 1a78 19a7 199b 1a4e 189a 1907 1a11 1a7d 19b9 19d2 1984 1a17 19c2 1a66 19b6 1906 189f 189f 25d3 3dea 3ac9 3a68 3a55 3a16 3a24 3a77 3aa6 3b38 3b8c 3c06 3c50 3c88 3c78 3c2b 3c22 3bad 3b2a 3ad3 3a53 3a55 3a3f 39ec 3aba 3d87 2e15 1726 1910 198d 1942 17c9 16ab 1644 1900 2607 3602 3c28 3d6b 3d57 3a5c 2fcd 1e15 1720 1887 170a 17b8 1780 174c 16d7 14e9 1441
1174 1368 15bf 1712 17a4 18a1 1a91 19b1 1a12 1a0f 190d 16f9 2c92 3c10 398d 38f8 38fa 391a 38cd 389f 38b8 3932 3998 39c2 3a05 396c 39bb 39fb 39ce 397f 3935 38d7 3996 39a8 3969 39c8 3acd 3d2a 25f3 14a1 1803 1967 1a3c 1a20 1a70 1c13 1d0e 1c52 1bb0 1ad1 1af1 1a79 1a19 1abb 1bed 1a85 1a4b 1aa3 1b42 1d0b 26a4 3287 3c58 3ef6 3cd7 3c6b 3c30 3bfb 3b89 3c0f 3c64 3c79 3bff 3b60 3b44 3b0a 3b43 3b92 3b61 3b03 3b70 3baa 3bc8 3dc6 27f3 16e3 1a37 1ae0 1973 198e 1993 1924 19b7 1b5b 19c2 1978 1a52 19f2 1980 19ac 19d8 19b6 194f 197c 19da 193d 190a 193e 20f0 3cf1 3baf 3adf 3a52 3a51 3a6f 3a90 3a5f 3a60 3b49 3bc1 3bff 3c46 3c1d 3bb7 3bd0 3bcd 3b41 3b4c 3ae5 3a92 3a70 3a42 3af0 3de9 2962 1808 19c0 1a06 19ac 18f0 174c 15ba 1749 17d9 1a79 1f1d 216b 2113 1cfc 188e 1830 18cf 1912 188f 1898 175f 182c 1672 169f 1679
1048 132d 1602 1673 165d 1921 1a44 1928 19fc 1a3a 1965 172b 238a 3c68 3a10 3981 3964 3941 38eb 391f 3970 39b6 3a75 3af3 3ad2 3a37 3a75 3a64 3a2e 39be 39bd 3931 3964 39df 39f4 3a2f 3a12 3b65 3ad3 1b26 1739 1896 192e 1a02 19c4 1a8a 1a8a 1a67 19f1 1a60 1a15 1a63 19d2 19a0 1ab6 1b0c 1b82 1bee 1c4b 1c5a 1b1e 1c37 21f9 32f3 3ec2 3d28 3c9f 3c84 3c1a 3c3a 3cad 3c62 3c60 3c24 3bfd 3bf9 3c2f 3bc0 3bb9 3c0a 3bc6 3bc7 3beb 3ce1 3cc7 274d 170f 1746 1893 190c 1807 1859 1844 19e4 18d2 197c 1a98 1a5b 19cd 18be 1916 1996 18ad 17ef 1886 1806 17d4 1860 1a26 3618 3dca 3ac6 3a3b 39f9 3a74 3a2d 3a17 3a86 3ae4 3b04 3b2d 3ba5 3c31 3b57 3b1d 3ae9 3aef 3b10 3af6 3b03 3aab 3a54 3b19 3de9 28cd 1698 1985 1913 1853 181b 178c 1611 1624 17e9 18c7 1969 18c7 180a 1990 1985 18ba 1925 192d 175c 180c 1766 1754 15fb 15a3 1c3d
0d17 109a 14d6 1601 16c3 18e1 1928 18f6 19de 1aae 19c9 182f 20ba 3c1f 3a73 3a0b 3a37 39ae 3977 397e 3a23 3a52 3b13 3b5a 3b31 3ac2 3b3f 3ac8 3a57 3a63 3a53 3a44 3a01 3aa0 39e2 3a1c 3abf 3ad7 3dbd 2b39 166a 1781 182f 1964 18bd 1964 19f4 19c0 19d0 19d1 1996 193b 1975 1951 1a56 1b30 1bd4 1bb3 1bb6 1bcb 1bd1 1b66 1bb6 1c86 3039 3ec6 3ca5 3c45 3bc4 3bcb 3bd1 3b62 3b56 3ba8 3b74 3ba7 3bbe 3b21 3b6c 3bea 3be2 3bc9 3c04 3bcc 3c95 3db3 3346 2436 1904 15df 1853 17b6 1857 183a 1692 180c 1a1c 1a21 19ab 193b 1949 18bc 18b4 1884 17ba 178c 179c 17bb 17a8 2475 3d62 3bfb 3a25 3a6c 3a8f 3a80 3a32 3a77 3abf 3aa0 3aa5 3b16 3b53 3b6a 3b1a 3aa1 3a3b 3a76 3a57 3ad9 3a7d 3a62 3acc 3cf0 2da8 14f3 1738 17a7 1720 1706 17b7 170d 1756 1719 188e 1927 18bd 1711 1877 19ba 192c 1926 1894 1708 1789 17a2 16ab 15a6 152f 24bb
28e2 220b 1849 12f5 15be 18d0 192b 1967 19b8 1a17 1992 17cf 21db 3c5e 3a4d 39d7 39bd 3975 3971 39a3 3a63 3abf 3ac8 3b1a 3b38 3afd 3b07 3b33 3acd 3a42 3a55 3ace 3aa5 3a65 39bf 3a06 3ae9 3ac9 3cd1 342f 180d 1a4d 1910 199e 19bb 1981 1a33 19a8 19a3 1a42 1999 1986 1902 1984 1a3b 1b73 1ba6 1b3e 1b91 1c24 1baf 1af4 1c40 1c90 1dc8 3726 3d7b 3c3b 3b38 3b2f 3b13 3aec 3aef 3ae0 3af1 3b29 3afb 3b13 3b73 3bae 3c02 3bee 3b8d 3b81 3b86 3bd1 3d45 3e00 3908 260a 1534 170e 183f 17e5 1586 16f5 18c0 194b 198e 1a21 1983 18b0 182b 18a1 18c7 189c 18cc 17fe 17c7 19b2 2aca 3da4 3dd8 3c17 3afe 3ac6 3aa9 3a6c 3a26 3a62 3a56 3a82 3aa6 3ac3 3a6f 3a7d 3a1e 3a1d 39cf 3a0e 3a37 3a5a 3abf 3bb1 378f 16d9 1642 1703 1770 16f2 1685 1695 16d3 1755 177d 1835 1756 16ec 1788 1930 184f 1724 183e 17f0 16f9 1795 1698 14ee 14ae 27f4
38e2 3a8c 3866 2808 14ae 1730 1861 18a4 1947 19a5 1969 1634 287e 3c2b 394a 395a 396a 3964 3966 3985 3a0b 3a6e 3a61 3ae5 3ba2 3c59 3cb4 3d49 3c9a 3bee 3b7f 3b44 3ab0 3a15 3a2f 3a2d 3a35 3a62 3c56 3640 1890 1a15 1941 1978 191d 1915 1a1f 19d1 18b0 186b 17f6 184e 1901 19fd 1b1b 1ad4 1b1f 1b6e 1ba7 1b8b 1b73 1b39 1b44 1b4f 1b1b 28af 3e2d 3c52 3b36 3af8 3af6 3a8d 3a5c 3a4e 3aad 3b09 3b5d 3b76 3b9d 3b9f 3c02 3b97 3ac3 3b24 3b27 3b11 3b33 3ae4 3c2f 3e23 2a31 13ce 16b6 1764 15e4 1617 1700 176e 183e 1926 18e8 188e 16d4 16cd 1760 17c3 18b8 179d 1662 17f1 1a30 2586 3563 3cbf 3e1f 3bdd 3ad8 3ac5 3a6a 39ce 39bd 39da 3a39 3a49 3a41 3a62 3a50 39c2 3967 39ab 3a0c 3a17 3a1f 3a98 3d42 260b 1220 162d 16a3 15b8 14ab 14d3 154b 16c4 16b3 16f5 1696 16a7 1664 162f 16ae 15b8 1770 17a2 158f 1693 14f9 132f 13cf 254b
35e1 3688 3879 3c2d 2ede 1525 16ed 1698 1841 192e 17b6 174f 34bc 3af0 394e 391c 38de 3896 3896 38f1 39a6 3a5d 3a9e 3d02 3bfe 370f 341a 34f2 38fe 3d85 3d7a 3b20 3af6 3a2b 3a2f 39c8 39ea 3a24 3c00 358d 17c6 193b 187b 1911 18e4 184e 18a0 18e5 182d 18a4 181a 1805 1882 1949 1949 18a0 1823 17fd 18cd 19a3 1a2f 1ae0 1a88 1aa1 1b42 202d 3baa 3bf0 3b25 3aef 3a87 3a89 3a73 3aea 3b00 3b32 3b4c 3ba1 3bae 3b5b 3b73 3b56 3ad5 3b0b 3ab7 3aad 3ab6 3a57 3ab7 3b19 3d8f 2216 14a5 1738 16cc 161c 17b6 18ae 196d 19d3 1939 190d 18eb 1828 1792 18d5 1905 1856 1747 17d1 18a8 1901 1b85 21e1 2f7a 3d4b 3d28 3b74 3aa8 3a5f 3a83 39f4 3a5d 3a59 3a8c 3a7f 3a76 3a0c 398a 3965 39da 39b0 39f9 3a61 3b4d 3a45 1e29 127c 14ad 153d 13e7 1454 153f 1672 164a 16a0 160f 1699 16f6 1680 16b3 16ba 1749 1706 155d 1633 13d8 12ea 12d4 1c05
3570 3617 369b 371e 3bf3 291a 1420 17ec 18bd 18c7 1653 2697 3c51 39d1 395f 3932 3927 393f 3976 39b2 39d5 3bb7 3c6d 2e33 2044 1afb 1a95 1b5b 1d2b 2567 357c 3dac 3b77 3a83 3a11 39b5 39d4 39ec 3d39 3008 1769 1966 1a84 19d7 198f 18a6 1899 18eb 19b7 1a15 1961 188f 1745 17eb 1836 1834 18d3 1777 187b 1abd 1aec 1b0f 1a9e 1aae 1b3f 1d97 3994 3ca9 3b76 3b2c 3ae1 3a95 3ad3 3ba3 3b82 3b27 3b8b 3baa 3bec 3b91 3b0e 3acb 3aca 3ad9 3ab8 3a71 3ac7 3a7d 3adf 3afc 3ccc 342b 16c8 17ca 1756 15e8 17bd 19b6 1aa7 1ad8 1a70 1a46 1b1a 1abb 1979 1a56 1aa3 19ac 1a58 1b88 1b23 19f1 1963 19d1 1ad8 26e2 3cd6 3d1b 3bd2 3bfb 3bf7 3b41 3b31 3aaf 3ac9 3a7d 3a34 3a1f 39f3 39b5 3a08 3a34 39e8 3a05 3a83 3ba9 3abc 28af 16d4 11de 132e 147e 1503 1550 155d 15b6 16ad 1702 17a2 17a8 1824 186d 172c 16d6 1625 15c3 1477 12d4 1262 1578
35ae 35d0 3668 3748 38db 3944 1a27 17a1 1775 15bc 22c8 3a6e 3a32 395a 3945 3940 3968 39f4 3a0f 3a15 3b60 3c20 2523 18f3 1a3a 1ac5 1b85 1bdd 1cd9 1a9d 1c7d 3088 3d8c 3b5a 39d7 39af 39dc 3ad2 3df9 2333 189d 1a51 1b43 1b12 19e7 19d1 19e3 19c7 1a54 1884 1886 1dcb 22f7 247c 2195 1bd5 170d 1880 19eb 1a7d 1c4a 1c4e 1bae 1bf6 1c2d 1dca 3a27 3d12 3c25 3bce 3b21 3b45 3b96 3b95 3b97 3b74 3bdc 3c4a 3c94 3c65 3bf1 3bc2 3ba9 3b34 3b1f 3bab 3b95 3b12 3b5c 3b44 3c16 3c63 1d06 18bd 1787 16e1 1812 19d3 1ab1 1a31 1a37 1a24 1a4c 1b85 1a9f 19f3 19a5 19ad 1a2a 1ab7 1b12 1acd 1b6f 1b64 1c0c 1ba1 2a88 3ee6 3d49 3ccf 3c46 3c3c 3bba 3b3f 3b35 3b3f 3b86 3b00 3aba 3ad6 3aab 3af3 3a5b 3a80 3acb 3b0f 3bb1 3d05 39a9 2eb6 19c7 1131 1431 14bf 159a 1587 169b 173f 179e 1830 1862 18de 170a 165d 1615 162f 1528 12e0 11d0 144d
3673 36d1 37db 37ce 38a2 3e19 25bd 12eb 186a 296f 3aec 3ac1 398e 39b3 3986 396b 3984 3a39 3abb 3b14 3d2c 2554 17f7 1b17 19e2 1a26 1a68 1acb 1ae4 19db 1b7a 1b66 3432 3c80 3988 3a08 3abf 3e47 33a3 18b0 1a61 1af5 1c27 1b66 1ab9 1a78 19f4 1a0d 16e8 1fb4 32a5 3c41 3df0 3da6 3d2a 3a6d 2d94 1a00 177e 1a0f 1af3 1bc0 1b6e 1bbf 1b37 1fb7 3c6c 3c4c 3bb2 3b45 3b05 3b65 3b78 3b4e 3c58 3cb0 3cca 3cb5 3d2e 3d46 3d05 3cd4 3c40 3c2d 3bdb 3b90 3b31 3b47 3ba3 3bad 3c65 3e77 2117 1910 17aa 16bc 18a1 195c 1968 1969 18e6 189d 1885 1a86 1963 187d 18e2 199b 19f1 196b 1aa4 1a62 1b54 1be9 1b24 1b83 1e10 37db 3eab 3d30 3c7c 3c0c 3b60 3bc4 3b83 3bc7 3be8 3bd2 3c02 3be0 3b72 3b63 3af9 3aaa 3a9b 3b45 3abb 3a9a 3ac9 3c6f 3a52 212a 1218 1596 14d5 1606 16fa 16cc 1729 18b3 1935 18fd 1859 17aa 1693 1678 1543 1353 11cb 1240
3817 384b 3868 3acf 3bd2 37de 2f39 2eae 384c 3b70 39e5 398a 3953 3941 392a 394f 3975 3a09 3a90 3d23 30bd 180f 1a2c 1964 18c4 18e0 198e 1a4a 1a33 1a8b 1ac2 196b 21d1 3c10 3a54 3aad 3dfe 381d 1be0 1872 1abc 1c37 1b00 1ad7 1a78 1a51 1a3a 1727 2454 3bfd 3c9e 3a76 3a58 39e8 3a3d 3bb9 3e15 3807 1c8c 18dd 1a1f 1c0a 1c52 1b67 1982 2a58 3e17 3bcc 3b30 3aa9 3ac2 3af2 3b46 3bc7 3cbf 3d61 3e78 3eab 3cc8 3c1b 3cd2 3e9e 3e39 3cc2 3c6d 3b6a 3acd 3ad2 3b06 3b24 3c76 3e03 1fc3 1997 18aa 18ea 19e4 1a7d 1a3d 1961 197c 1902 1981 19f5 18f8 1890 1875 19f9 1b0e 1afc 1b16 1b91 1ae4 1cc0 1bce 1acf 1bb1 2ccc 3f5f 3d56 3c9c 3c4c 3bc2 3bea 3b91 3c13 3c64 3c3a 3c73 3c6f 3c59 3be9 3b76 3af3 3ad3 3b1b 3b64 3a99 3a42 39f8 3bc9 3b47 1be2 14cc 14e3 1609 177a 1789 17c3 1945 1a5c 19aa 1944 17de 16e3 16ad 167c 148d 1392 1279
38f8 3978 3c3c 3377 2204 17f6 28b2 3eaa 3a09 38ad 38dd 38e9 38ce 3945 3964 391b 395a 3988 3ac5 3d2c 21a7 18de 19b9 1a7d 1980 19c9 19c0 1a20 1ac7 1b64 1ab0 1a2f 1830 3584 3e93 3d75 33ac 1cab 17a5 1a0d 1adf 1bdb 1a9c 1994 196f 1a4d 17ff 2118 3c3c 3b82 39ea 3919 38f6 38ef 3960 3a6a 3b54 3da7 3670 199f 1b1c 1cc5 1c54 1a35 1d9d 399d 3d68 3c13 3b88 3add 3aea 3b21 3bc7 3c7b 3ce9 3ed9 35a9 2874 215e 204a 21fe 289b 34fd 3e93 3d80 3c49 3bde 3b25 3ad9 3ae6 3cef 3b6a 1c89 1a0d 180b 1991 1a06 1b04 1a2e 1a79 1a64 1976 19ad 19ce 198c 1839 1874 1aba 1a8b 1aa7 1b8e 1be6 1be9 1c28 1c7a 1c0e 1b85 268f 3eea 3d03 3c30 3baf 3b67 3b80 3b98 3c0f 3c7c 3c81 3c9c 3cae 3c91 3c31 3baf 3ad3 3b15 3aaf 3aef 3ab7 3a0e 3978 3a28 3d15 30a7 1344 1501 1600 16fa 168f 17b8 1a30 19c7 18e4 183e 181c 1754 176b 1698 151d 139d 131b
3967 3c71 2ab1 17fb 1720 1768 1fa0 3ba7 3a37 38e6 38be 3915 38bb 388f 390c 38e6 3943 3981 3c8c 367c 1963 1929 19e6 1b2c 19da 19f3 1956 1913 195f 18df 1713 182b 1f2e 2eeb 3042 2479 19dc 18f6 19ea 196c 1b47 1c0e 1b06 1abb 19d9 192f 191b 34c2 3d8c 3abe 3a28 39c2 395b 39bf 3a33 3a67 3b47 3bc6 3ec8 2734 1859 1b4a 1939 1b4b 3401 3e14 3cb7 3c2a 3bb2 3bc4 3baf 3bb7 3c99 3d79 3dfd 29d2 1be1 1b38 1c4c 1d0c 1d09 1d9a 1da9 29ac 3d1b 3d58 3c4a 3ba3 3b2a 3b82 3e6b 31eb 18f3 19db 1965 1a77 1a89 198d 1a02 18cb 1906 18be 16dd 174d 1a24 1a64 18ac 1586 17df 1a30 1aeb 1b84 1b87 1c07 1c12 1cdd 1b51 2592 3ed4 3d0f 3c21 3b83 3b5d 3b2a 3b18 3ba0 3c75 3c9c 3caa 3c94 3cb8 3c4a 3c0e 3bce 3b5c 3acc 3a86 3a79 3a31 39b6 3a01 3b92 3a49 1830 1485 14f0 1664 1738 1866 1a4d 19f2 17a6 1743 1797 175e 1673 15e0 1501 142d 12ec
3d00 2dce 1661 187c 189e 175a 1873 3047 3cf9 392d 38a4 3926 3950 392d 3968 39a5 3952 3aa9 3d58 240b 17a8 1954 1a22 1aca 19e2 1890 189d 179a 1781 176d 2557 36c3 3e69 3158 174e 1a11 1b59 1b0b 1ab5 1ab9 1be1 1c7f 1b72 1b9f 1a94 1905 228e 3dd0 3bfe 3b45 3b36 3ac1 3b0e 3b9d 3b83 3b24 3baa 3bcd 3e37 34cd 159a 17aa 20fe 3597 3dd6 3c5d 3cab 3c53 3c39 3c27 3c5e 3ce5 3d8d 3e94 2933 194a 1bb7 1c0f 1cc7 1e30 1d36 1d9d 1d8c 1ad5 2a81 3ece 3cc3 3bc7 3b4d 3cee 3d71 20a6 186f 1a71 1a20 1ace 1b01 1a89 1add 1a0f 18f1 19be 285d 3575 3a1b 3a90 3901 300a 1eee 163a 19ab 1a2b 1a4b 1bb2 1cac 1c2b 1bce 2931 3e8c 3cc4 3bdf 3bc6 3b87 3b1f 3aed 3b5a 3c86 3ce5 3d24 3cb1 3ca8 3cb1 3c74 3c00 3ba2 3b6d 3af6 3a87 3a18 3a3e 3a5e 3ac9 3cdc 1d00 1408 1565 169f 180f 18bf 1941 1ab7 18ae 1732 16ca 16cc 1614 1555 1526 1489 13e0
390a 1a58 18d8 1966 1968 1790 1712 1c87 3606 3d18 3a8d 3991 3983 39f5 39e8 3a7f 3c10 3e2b 2a2c 186a 19a4 1991 1a1f 1ac9 1944 17f8 1826 18fb 19ae 3073 3d90 3c24 3beb 3969 1b72 1ad5 1b87 1b2d 1b36 1c18 1c25 1bd7 1c26 1bdc 1bee 1aad 2fcd 3e6b 3bd5 3b30 3af2 3ab6 3b38 3bd5 3bd2 3c1c 3cfb 3ebf 3dfa 3690 280c 3287 3d3b 3dd1 3c89 3c5f 3c99 3c58 3c8a 3c58 3cd6 3d6c 3f5e 3313 1abf 1d55 1beb 1c10 1d42 1ce8 1dda 1ece 1e97 1b6f 1bdf 35d4 3e43 3bf6 3d37 3ef1 29b7 18b1 1ab1 1b90 1b14 1b90 1b79 1a5e 1adc 1987 1f16 3614 3ee8 3d5e 3c15 3bd7 3c47 3d67 3d01 2a13 168c 19f8 1a5e 1be0 1c5a 1c00 1bc9 3384 3e92 3c83 3c00 3bc5 3ba7 3b21 3ac6 3b3a 3c2b 3d18 3ee4 3f4f 3ee1 3f12 3f1d 3dc6 3c9a 3c1d 3adf 3a33 3a50 3a49 3ae9 3af7 3d20 1e5f 148d 1654 177a 18c9 1944 18f8 196b 17d5 16c8 1644 15d8 1682 1605 154a 1441 140d
2bf4 177a 1a0d 1a0c 1959 17b4 1750 1872 1dab 31a3 3ca1 3d49 3c08 3c1a 3ca5 3dae 3a0e 26a1 177f 1974 19bf 19df 1a0d 1a07 18e5 169e 1776 1784 2d46 3dde 39fd 39c6 39d4 3d6f 29a9 1763 1a77 1b53 1d43 1d1e 1c84 1c3f 1aa8 1a99 1a00 207e 3bc3 3bed 3b13 3aaa 3ae2 3b5e 3b6f 3c34 3ca8 3df5 3e57 31c5 2300 2112 3d2a 3efc 3cb8 3be7 3c3a 3c50 3c02 3c27 3ca3 3c8c 3cbb 3dcd 3edc 234a 1be1 1cdb 1c05 1d03 1e13 1d96 1d10 1d8c 1d8a 1d00 1a8e 2884 3f71 3f06 3d3e 296e 18ea 1aab 1b5b 1b78 1ba1 1c13 1b3e 1b18 1aa7 1e0a 390d 3e9a 3b61 3aee 3a8f 3a5d 3a7f 3aee 3b91 3e4e 28e2 174d 1a5e 1c0f 1bb6 1b01 22f1 3da9 3d28 3be8 3bb4 3bb6 3bae 3bc2 3b4f 3b89 3d93 3e49 3516 2b95 2790 28b3 2f8c 39da 3f20 3d40 3b62 3a78 3a82 3a32 3a7f 3ba5 3b3d 1a36 15c8 16de 18b9 18d1 18d1 19be 18ef 1719 15ad 16c7 173e 15ef 1568 1574 143f 13c3
217c 17f1 196b 18a0 18a6 1784 171f 1857 1900 1a9b 22f3 2da4 32eb 33e8 309a 27de 1cd6 17ae 1821 19b6 1a57 1948 1938 1927 17b8 15cf 175d 2067 3c20 3a1e 387d 388d 38a4 3a81 3aa8 2041 17f0 1bdf 1c2a 1ca8 1c8d 1b19 1a1d 1917 1ca3 369e 3d8f 3b8c 3abd 3abd 3b58 3bd5 3c48 3cbd 3dc8 3d81 27fd 1aba 1aeb 1c3b 3747 3e24 3c23 3bbe 3b90 3ba8 3b8b 3bab 3c69 3ca9 3c6f 3ec6 37f4 1bb6 1c99 1c43 1c43 1d12 1d8c 1d40 1d76 1d01 1cab 19ea 1ac4 2565 38d1 2fce 2059 198a 1a46 1ac0 1c2e 1bb8 1bf2 1cc3 1bff 1b2f 1abb 3206 3e70 3b74 3ac4 3b1f 3ae8 3ad9 3b53 3b48 3b62 3d33 3bb1 1aa8 17f1 1a01 1979 1d59 3750 3e8a 3c7a 3c12 3bb1 3b97 3be3 3c4e 3c2c 3e46 394d 24ae 19e1 1a1f 1b9d 1c13 1b13 1efe 2f56 3e78 3c50 3b1c 3a4b 3a42 3aa3 3dcb 3306 1591 16d5 16d2 185a 19e0 18d9 189f 1831 164e 15b7 15da 1424 138e 1390 115c 11e0 1308
1e34 17b8 1856 1869 179a 161a 1636 1951 19c8 1a00 1928 1965 1a2f 19cc 1919 188a 189f 1820 1862 1945 18fb 1917 1922 1883 16d4 178e 16c6 2dc4 3c87 38d0 37e6 37b6 3897 3a01 3bef 3ad8 275d 1954 191c 1a61 1a7c 18af 195c 23ac 37a2 3e30 3c72 3be2 3b7d 3b87 3bc7 3c9a 3cd8 3da6 3e35 27b7 1a5b 1d24 1d9f 1ade 29c4 3f3a 3ca5 3bd0 3bbc 3be7 3c1a 3c77 3ccb 3c87 3d73 3f7b 2748 1a2c 1bca 1bd6 1be4 1cf1 1c46 1cc5 1d12 1aea 1bd0 2995 37ce 3bc6 1ff7 19a0 1a60 1a7b 1b5e 1c90 1dca 1d08 1cf6 1da8 1cf0 1bc2 22b3 3d74 3ce5 3ba5 3a9d 3aca 3aeb 3b29 3b5a 3b96 3b97 3c08 3ed8 2723 1527 186f 1f2d 3626 3efc 3cca 3c5c 3c07 3b91 3ba3 3c7c 3cc6 3e1e 3904 1e0f 1921 1a5a 1b8e 1b99 1c14 1bae 1b3b 1b4d 2ded 3e23 3b33 3a67 3a77 3b6f 3de7 2143 166d 183c 184a 1947 19f3 1923 18a4 187e 15e8 1713 23a2 2f7c 3525 34b2 2f2b 20ff 119f
2096 16c5 1902 1828 174d 1609 1724 189f 198f 1a9e 19ab 1a3c 1a2f 19dc 198a 192e 191b 18d1 18cd 1998 1954 1a5e 19b2 17f6 179f 17d1 1863 3491 3a68 3821 37d2 3897 38f2 39cb 3b2f 3c1c 3e08 36cf 2c49 26c4 263f 2bc9 35ab 3df4 3dba 3c5b 3c36 3c48 3c26 3c57 3c82 3d0c 3cf9 3f15 324f 1b2b 1de7 1e83 1d3b 1b90 1cfb 339b 3e7f 3c99 3be1 3c0e 3c92 3ca9 3ce0 3d6c 3f87 30f8 1984 1ba1 1bf0 1be0 1bc3 1c90 1b6d 1b08 1b72 1e07 3557 4011 3eb8 3f23 250a 1a7c 1bd7 1c2a 1cd5 1dc3 1cd8 1d17 1c5d 1ca9 1c91 1ab2 2dc6 3f4d 3cf7 3c0a 3b01 3b46 3b61 3b1c 3bae 3c50 3cbd 3d17 3f03 312d 1f7f 2da3 3b92 3e50 3c6f 3c50 3c0b 3c25 3b96 3b79 3c86 3d9c 3d8a 2287 1925 1b4b 1afc 1a92 1af8 1afe 1a76 19f4 1984 1af9 3771 3ce6 3b14 3bac 3e37 2e64 160f 1823 1809 1900 1969 1826 1802 17a2 1735 1e16 3500 3e93 3d42 3c3d 3cda 3d86 3d7c 308a
memctrl/mcntrl_tiled_linear_rw.v
View file @ 5cc1817c
......@@ -595,7 +595,8 @@ module mcntrl_tiled_linear_rw#(
row_left[NUM_XFER_BITS:0]; // 7 bits, max 'h40
*/
lim_by_tile_width <= (|row_left[FRAME_WIDTH_BITS:MAX_TILE_WIDTH] || (!linear_mode && (row_left[MAX_TILE_WIDTH:0] >= tile_cols)))?
(linear_mode ? (1<< NUM_XFER_BITS) : tile_cols):
// (linear_mode ? (1<< NUM_XFER_BITS) : tile_cols):
(linear_mode ? {1'b1,{NUM_XFER_BITS{1'b0}}} : tile_cols):
row_left[MAX_TILE_WIDTH:0]; // 7 bits, max 'h40
end
......@@ -668,16 +669,16 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
// LINEAR matched
// TILED and TILED_LIN only:
if (mrst) xfer_start_rd_r <= 0;
else xfer_start_rd_r <= xfer_grant && !chn_rst && !cmd_wrmem && !byte32;
else xfer_start_rd_r <= xfer_grant && !chn_rst && !cmd_wrmem && !byte32 && !linear_mode;
if (mrst) xfer_start_wr_r <= 0;
else xfer_start_wr_r <= xfer_grant && !chn_rst && cmd_wrmem && !byte32;
else xfer_start_wr_r <= xfer_grant && !chn_rst && cmd_wrmem && !byte32 && !linear_mode;
if (mrst) xfer_start32_rd_r <= 0;
else xfer_start32_rd_r <= xfer_grant && !chn_rst && !cmd_wrmem && byte32;
else xfer_start32_rd_r <= xfer_grant && !chn_rst && !cmd_wrmem && byte32 && !linear_mode;
if (mrst) xfer_start32_wr_r <= 0;
else xfer_start32_wr_r <= xfer_grant && !chn_rst && cmd_wrmem && byte32;
else xfer_start32_wr_r <= xfer_grant && !chn_rst && cmd_wrmem && byte32 && !linear_mode;
if (mrst) xfer_start_lin_rd_r <= 0;
else xfer_start_lin_rd_r <= xfer_grant && !chn_rst && !cmd_wrmem && linear_mode;
......
py393/.project
View file @ 5cc1817c
......@@ -14,4 +14,11 @@
<natures>
<nature>org.python.pydev.pythonNature</nature>
</natures>
<linkedResources>
<link>
<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
<location>/data_ssd/nc393/elphel393/fpga-elphel/x393/py393/vivado_logs/VivadoSynthesis-20190404120819591.log</location>
</link>
</linkedResources>
</projectDescription>
py393/x393_sens_cmprs.py
View file @ 5cc1817c
......@@ -155,7 +155,7 @@ class X393SensCmprs(object):
x393Rtc = None
x393Membridge = None
def __init__(self, debug_mode=1,dry_mode=True, saveFileName=None):
def __init__(self, debug_mode=1,dry_mode=True, saveFileName=None, nomargins = True): # False):
# global BUFFER_ADDRESS, BUFFER_LEN
global BUFFER_ADDRESS, BUFFER_LEN, COMMAND_ADDRESS, DATAIN_ADDRESS, DATAOUT_ADDRESS
global BUFFER_ADDRESS_H2D, BUFFER_LEN_H2D, BUFFER_ADDRESS_D2H, BUFFER_LEN_D2H, BUFFER_ADDRESS_BIDIR, BUFFER_LEN_BIDIR
......@@ -173,6 +173,13 @@ class X393SensCmprs(object):
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_HISPI]["height"]= vrlg.WOI_HEIGHT + 4
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_HISPI]["top"]= 0
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_HISPI]["left"]= 0
if nomargins:
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_PARALLEL]["width"]= vrlg.WOI_WIDTH + 0 # 4
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_PARALLEL]["height"]= vrlg.WOI_HEIGHT + 0
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_HISPI]["width"]= vrlg.WOI_WIDTH + 0 #4
SENSOR_DEFAULTS[x393_sensor.SENSOR_INTERFACE_HISPI]["height"]= vrlg.WOI_HEIGHT + 0
print ("Using simulation size sensor defaults ",SENSOR_DEFAULTS)
except:
......@@ -628,12 +635,15 @@ class X393SensCmprs(object):
# moved before camsync to have a valid timestamo w/o special waiting
if verbose >0 :
print ("===================== MEMORY_SENSOR =========================")
print ("===================== MEMORY_SENSOR =========================, mode= %d"%(cmode))
window_height_memory = window_height
if cmode==vrlg.CMPRS_CBIT_CMODE_JP4:
if (cmode==vrlg.CMPRS_CBIT_CMODE_JP4) or (cmode==15): # vrlg.CMPRS_CBIT_CMODE_RAW):
window_height_memory &= 0xfff0 # do not need extra margins
num_burst_in_line &= 0xfffe # make even (assuming left=0)
print ("===================== Mode is JP4 or raw =========================")
else:
print ("===================== Mode is neither JP4 nor raw =========================")
self.x393Sensor.setup_sensor_memory (
num_sensor = num_sensor, # input [1:0] num_sensor;
......
py393/x393_tiff_verilog.py 100644 → 100755
View file @ 5cc1817c
#!/usr/bin/env python
# encoding: utf-8
from __future__ import division
from __future__ import print_function
......@@ -47,7 +49,7 @@ except:
try:
outname = sys.argv[3]
except IndexError:
outname = fname.replace(".tiff",".vh")
outname = fname.replace(".tiff",".dat")
tif = Image.open(fname)
......
simulation_modules/simul_lwir160x120_telemetry.v 0 → 100644
View file @ 5cc1817c
/*!
* <b>Module:</b> simul_lwir160x120_telemetry
* @file simul_lwir160x120_telemetry.v
* @date 2019-04-01
* @author Andrey Filippov
*
* @brief Combine telemetry data into vospi packet payload
*
* @copyright Copyright (c) 2019 Elphel, Inc.
*
* <b>License </b>
*
* simul_lwir160x120_telemetry.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* simul_lwir160x120_telemetry.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module simul_lwir160x120_telemetry(
input clk,
input en, // write all telemetry, but average
input en_avg, // write frame average (may be simultaneous)
// telemetry data
input [15:0] telemetry_rev,
input [31:0] telemetry_time,
input [31:0] telemetry_status,
input [63:0] telemetry_srev,
input [31:0] telemetry_frame,
input [15:0] telemetry_mean,
input [15:0] telemetry_temp_counts,
input [15:0] telemetry_temp_kelvin,
input [15:0] telemetry_temp_last_kelvin,
input [31:0] telemetry_time_last_ms,
input [15:0] telemetry_agc_roi_top,
input [15:0] telemetry_agc_roi_left,
input [15:0] telemetry_agc_roi_bottom,
input [15:0] telemetry_agc_roi_right,
input [15:0] telemetry_agc_high,
input [15:0] telemetry_agc_low,
input [31:0] telemetry_video_format, //???
output reg [160*16-1:0] telemetry_a,
output reg [160*16-1:0] telemetry_b
);
always @(posedge clk) if (en) begin
telemetry_a <= {
telemetry_rev [15:0], // word 0
telemetry_time [31:0], // words 1.. 2
telemetry_status [31:0], // words 3.. 4
{8{16'b0}}, // words 5..12
telemetry_srev [63:0], // words 13..16
{3{16'b0}}, // words 17..19
telemetry_frame [31:0], // words 20..21
en_avg?telemetry_mean[15:0]:telemetry_a[(159-22)*16 +: 16], // words 22
telemetry_temp_counts [15:0], // words 23
telemetry_temp_kelvin [15:0], // words 24
{4{16'b0}}, // words 25..28
telemetry_temp_last_kelvin[15:0], // words 29
telemetry_time_last_ms [31:0], // words 30..31
{2{16'b0}}, // words 32..33
telemetry_agc_roi_top [15:0], // words 34
telemetry_agc_roi_left [15:0], // words 35
telemetry_agc_roi_bottom [15:0], // words 36
telemetry_agc_roi_right [15:0], // words 37
telemetry_agc_high [15:0], // words 38
telemetry_agc_low [15:0], // words 39
{32{16'b0}}, // words 40..71
telemetry_video_format [31:0], // words 72..73
{86{16'b0}} // words 74..159
};
telemetry_b <= 0;
end else if (en_avg) begin
telemetry_a[(159-22)*16 +: 16] <= telemetry_mean[15:0];
end
endmodule
simulation_modules/simul_lwir160x120_vospi.v 0 → 100644
View file @ 5cc1817c
/*!
* <b>Module:</b> simul_lwir160x120_vospi
* @file simul_lwir160x120_vospi.v
* @date 2019-03-30
* @author Andrey FIlippov
*
* @brief simulates FLIR Lepton 3.0 output over VoSPI
*
* @copyright Copyright (c) 2019 Elphel, Inc .
*
* <b>License </b>
*
* simul_lwir160x120_vospi.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* simul_lwir160x120_vospi.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module simul_lwir160x120_vospi # (
parameter DATA_FILE = "/data_ssd/nc393/elphel393/fpga-elphel/x393/input_data/pattern_160_120_14.dat", //
parameter WINDOW_WIDTH = 160, //
parameter WINDOW_HEIGHT = 120, //
parameter TELEMETRY = 1, // 0 - disabled, 1 - as header, 2 - as footer
parameter FRAME_PERIOD = 946969, // 26.4 fps @25 MHz
parameter FRAME_DELAY = 100, // mclk period to start first frame 1
parameter MS_PERIOD = 25 // ahould actually be 25000
)(
input mclk,
input nrst,
input sck,
input ncs,
output miso,
// telemetry data
input [15:0] telemetry_rev,
input [31:0] telemetry_status,
input [63:0] telemetry_srev,
input [15:0] telemetry_temp_counts,
input [15:0] telemetry_temp_kelvin,
input [15:0] telemetry_temp_last_kelvin,
input [31:0] telemetry_time_last_ms,
input [15:0] telemetry_agc_roi_top,
input [15:0] telemetry_agc_roi_left,
input [15:0] telemetry_agc_roi_bottom,
input [15:0] telemetry_agc_roi_right,
input [15:0] telemetry_agc_high,
input [15:0] telemetry_agc_low,
input [31:0] telemetry_video_format //???
);
localparam OUT_BITS = 16;
localparam PACKET_PIXELS = 80;
localparam PACKET_HEADER = 2;
localparam PACKET_WORDS = PACKET_PIXELS + PACKET_HEADER;
localparam SEGMENT_PACKETS = 60; // w/o telemetry
localparam SEGMENT_PACKETS_TELEMETRY = SEGMENT_PACKETS + ((TELEMETRY > 0)? 1 : 0);
localparam FRAME_SEGMENTS = 4;
localparam FRAME_PACKETS = SEGMENT_PACKETS * FRAME_SEGMENTS;
localparam FRAME_PACKETS_FULL = FRAME_PACKETS + ((TELEMETRY==0) ? 0 : 4);
localparam FRAMES = 2; // 2 frames in a ping-pong buffer
localparam FRAME_WORDS = FRAME_SEGMENTS * (SEGMENT_PACKETS + ((TELEMETRY>0)?1 : 0)) * PACKET_WORDS;
wire mrst = !nrst;
reg [OUT_BITS-1:0] sensor_data[0 : WINDOW_WIDTH * WINDOW_HEIGHT - 1]; // SuppressThisWarning VEditor - Will be assigned by $readmem
reg [OUT_BITS-1:0] packed_data[0: FRAMES * FRAME_WORDS -1];
wire [160*16-1:0] telemetry_a;
wire [160*16-1:0] telemetry_b;
// registers for copiing data to packet array
//'0xe7319'
reg [19:0] frame_dly_cntr; // delay till next frame start
reg frame_start;
reg copy_page;
reg copy_run;
wire copy_done;
// reg [2:0] copy_segment; // 4 - copy average and telemetry
reg [7:0] copy_packet; // 240 image packets, then telemetry
reg [6:0] copy_word; // word number to copy in a packet (0..82), last one copies CRC to word 1
reg copy_crc;
wire [7:0] copy_packet_full;
wire [7:0] copy_telemetry_packet; // only 2 LSB
wire [7:0] copy_packet_segment;
wire [11:0] copy_packet_indx; // high bits are always 0
wire [7:0] copy_packet_ttt;
reg [15:0] copy_pxd;
reg [30:0] frame_sum;
wire [31:0] frame_average32;
wire [15:0] frame_average;
reg [15:0] copy_telemetry_d;
reg [15:0] copy_d;
wire copy_pix_or_tel;
wire copy_pix_only;
wire copy_tel_only;
// reg copy_pixels_r;
reg copy_pixels_pix;
// reg copy_pixels_tel;
wire [15:0] copy_din;
wire [ 6:0] copy_wa; // address in a packet where to write data
wire [15:0] copy_wa_full;
wire [15:0] crc_in;
wire [15:0] crc_out;
reg en_avg; // write frame average value to telemetry
reg [31:0] frame_num;
reg [31:0] time_ms;
reg [31:0] ms_cntr;
// wire [ 2:0] copy_segment;
//946,969 '0xe7319'
// assign copy_done = copy_run && copy_crc &&((TELEMETRY==0) ? (copy_packet== (FRAME_PACKETS -1)) : (FRAME_PACKETS + 3));
assign copy_done = copy_run && copy_crc && (copy_packet== (FRAME_PACKETS_FULL -1));
assign copy_packet_full = (copy_packet < FRAME_PACKETS)?(copy_packet + ((TELEMETRY == 1) ? 4 : 0)):(copy_packet - ((TELEMETRY == 1)?FRAME_PACKETS: 0)) ;
assign copy_telemetry_packet = copy_packet - FRAME_PACKETS;
assign copy_pix_or_tel = copy_run && (copy_word < PACKET_PIXELS); // && (copy_packet < FRAME_PACKETS);
assign copy_pix_only = copy_pix_or_tel && (copy_packet < FRAME_PACKETS);
assign copy_tel_only = copy_pix_or_tel && (copy_packet >= FRAME_PACKETS);
assign copy_packet_segment = copy_packet_full / SEGMENT_PACKETS_TELEMETRY;
assign copy_packet_indx = copy_packet_full % SEGMENT_PACKETS_TELEMETRY;
assign copy_packet_ttt = (copy_packet_indx == 20) ? (copy_packet_segment + 1): 8'b0;
assign crc_in = (copy_word == 0) ? {4'b0,copy_packet_indx[11:0]}:(
(copy_word == 1) ?16'b0:copy_d[15:0]);
assign copy_din = (copy_word == 0) ? {1'b0,copy_packet_ttt[2:0], copy_packet_indx[11:0]}:(
(copy_word == 1) ?16'bxx:(copy_crc? (crc_out): copy_d[15:0]));
assign copy_wa = copy_crc? 7'h01 : copy_word;
assign copy_wa_full = copy_wa + (PACKET_WORDS * copy_packet_full) + (FRAME_WORDS * copy_page);
assign frame_average32 = (frame_sum / (WINDOW_WIDTH * WINDOW_HEIGHT));
assign frame_average = frame_average32[15:0];
`ifndef ROOTPATH
`include "IVERILOG_INCLUDE.v"// SuppressThisWarning VEditor - maybe not used
`ifndef ROOTPATH
`define ROOTPATH "."
`endif
`endif
initial begin
// $readmemh({`ROOTPATH,"/input_data/sensor_16.dat"},sensor_data);
$readmemh(DATA_FILE,sensor_data,0);
end
always @ (posedge mclk) begin
if (mrst || (ms_cntr == 0)) ms_cntr <= MS_PERIOD -1;
else ms_cntr <= ms_cntr - 1;
if (mrst) time_ms <= 0;
else if ((ms_cntr == 0)) time_ms <= time_ms + 1;
//restarting frames
if (mrst) frame_dly_cntr <= FRAME_DELAY;
else if (frame_start) frame_dly_cntr <= FRAME_PERIOD;
else frame_dly_cntr <= frame_dly_cntr - 1;
frame_start <= !mrst && (frame_dly_cntr == 0);
if (mrst) frame_num <= 0;
else if (frame_start) frame_num <= frame_num + 1;
if (mrst) copy_page <= 0;
else if (frame_start) copy_page <= !copy_page;
if (mrst || copy_done) copy_run <= 0;
else if (frame_start) copy_run <= 1;
copy_crc <= copy_word == (PACKET_WORDS - 1);
if (!copy_run || copy_crc) copy_word <= 0;
else copy_word <= copy_word + 1;
if (!copy_run) copy_packet <= 0;
else if (copy_crc) copy_packet <= copy_packet + 1;
if (copy_pix_only) copy_pxd <= sensor_data[copy_packet * PACKET_PIXELS + copy_word];
else copy_pxd <= 'bx;
if (copy_tel_only) copy_telemetry_d <= copy_telemetry_packet[1]?
telemetry_b[(PACKET_PIXELS * (2 - copy_telemetry_packet[0])-copy_word - 1)*16 +: 16]:
telemetry_a[(PACKET_PIXELS * (2 - copy_telemetry_packet[0])-copy_word - 1)*16 +: 16];
else copy_telemetry_d <= 'bx;
copy_d <= (copy_packet < FRAME_PACKETS) ? copy_pxd : copy_telemetry_d;
// copy_pixels_r <= copy_pix_or_tel;
copy_pixels_pix <= copy_pix_or_tel && (copy_packet < FRAME_PACKETS);
// copy_pixels_tel <= copy_pix_or_tel && (copy_packet >= FRAME_PACKETS);
if (frame_start) frame_sum <= 0;
else if (copy_pixels_pix) frame_sum <= frame_sum + copy_pxd;
if (copy_run) packed_data[copy_wa_full] <= copy_din; // copy_d;
en_avg <= copy_crc && (copy_packet == (FRAME_PACKETS - 1)); // 1 cycle after last pixel written
end
/* Instance template for module crc16_x16x12x5x0 */
crc16_x16x12x5x0 crc16_x16x12x5x0_i (
.clk (mclk), // input
.srst (!copy_run || copy_crc), // input
.en (1'b1), // input
.din (crc_in), // input[15:0]
.dout (crc_out) // output[15:0]
);
/* Instance template for module simul_lwir160x120_telemetry */
simul_lwir160x120_telemetry simul_lwir160x120_telemetry_i (
.clk (mclk), // input
.en (frame_start), // input
.en_avg (en_avg), // input
.telemetry_rev (telemetry_rev), // input[15:0]
.telemetry_time (time_ms), // input[31:0]
.telemetry_status (telemetry_status), // input[31:0]
.telemetry_srev (telemetry_srev), // input[63:0]
.telemetry_frame (frame_num), // input[31:0]
.telemetry_mean (frame_average), // input[15:0]
.telemetry_temp_counts (telemetry_temp_counts), // input[15:0]
.telemetry_temp_kelvin (telemetry_temp_kelvin), // input[15:0]
.telemetry_temp_last_kelvin(telemetry_temp_last_kelvin), // input[15:0]
.telemetry_time_last_ms (telemetry_time_last_ms), // input[31:0]
.telemetry_agc_roi_top (telemetry_agc_roi_top), // input[15:0]
.telemetry_agc_roi_left (telemetry_agc_roi_left), // input[15:0]
.telemetry_agc_roi_bottom (telemetry_agc_roi_bottom), // input[15:0]
.telemetry_agc_roi_right (telemetry_agc_roi_right), // input[15:0]
.telemetry_agc_high (telemetry_agc_high), // input[15:0]
.telemetry_agc_low (telemetry_agc_low), // input[15:0]
.telemetry_video_format (telemetry_video_format), // input[31:0]
.telemetry_a (telemetry_a), // output[2559:0] reg
.telemetry_b (telemetry_b) // output[2559:0] reg
);
endmodule
/*
// Most significant bit first (big-endian)
// x^16+x^12+x^5+1 = (1) 0001 0000 0010 0001 = 0x1021
function crc(byte array string[1..len], int len) {
rem := 0
// A popular variant complements rem here
for i from 1 to len {
rem := rem xor (string[i] leftShift (n-8)) // n = 16 in this example
for j from 1 to 8 { // Assuming 8 bits per byte
if rem and 0x8000 { // if leftmost (most significant) bit is set
rem := (rem leftShift 1) xor 0x1021
} else {
rem := rem leftShift 1
}
rem := rem and 0xffff // Trim remainder to 16 bits
}
}
// A popular variant complements rem here
return rem
}
*/
simulation_modules/simul_sensor12bits.v
View file @ 5cc1817c
......@@ -55,7 +55,8 @@ module simul_sensor12bits # (
parameter tDDO1 = 5, //
parameter trigdly = 8, // delay between trigger input and start of output (VACT) in lines
parameter ramp = 1, // 1 - ramp, 0 - random (now - sensor.dat)
parameter new_bayer = 0 // 0 - old (16x16), 1 - new (18x18)
parameter new_bayer = 0, // 0 - old (16x16), 1 - new (18x18)
parameter EXTRA_PERIOD = 0 // add these clockc before VACT
) (
input MCLK, // Master clock
input MRST, // Master Reset - active low
......@@ -83,7 +84,7 @@ module simul_sensor12bits # (
localparam s_lastline= 7;
localparam s_frame_done=8;
localparam t_preVACT= lline* trigdly;
localparam t_preVACT= lline* trigdly + EXTRA_PERIOD;
localparam t_firstline=nrowb*lline+1; // 1664
localparam t_BPF= nbpf; // 16
localparam t_preHACT= ngp1; // 8
......@@ -92,7 +93,9 @@ module simul_sensor12bits # (
localparam t_lastline= nrowa*lline+1; // 1664
//reg [15:0] sensor_data[0:4095]; // up to 64 x 64 pixels // SuppressThisWarning VEditor - Will be assigned by $readmem
reg [15:0] sensor_data[0:65535]; // up to 1024 x 64 pixels // SuppressThisWarning VEditor - Will be assigned by $readmem
///reg [15:0] sensor_data[0:65535]; // up to 1024 x 64 pixels // SuppressThisWarning VEditor - Will be assigned by $readmem
reg [15:0] sensor_data[0: nrows * ncols -1]; // up to 1024 x 64 pixels // SuppressThisWarning VEditor - Will be assigned by $readmem
// $readmemh("sensor.dat",sensor_data);
......@@ -192,6 +195,11 @@ initial begin
else if (SENSOR_IMAGE_TYPE == "NORM15") $readmemh({`ROOTPATH,"/input_data/sensor_15.dat"},sensor_data);
else if (SENSOR_IMAGE_TYPE == "NORM16") $readmemh({`ROOTPATH,"/input_data/sensor_16.dat"},sensor_data);
else if (SENSOR_IMAGE_TYPE == "TEST01-1044X36") $readmemh({`ROOTPATH,"/input_data/test01-1044x36.dat"},sensor_data);
else if (SENSOR_IMAGE_TYPE == "TEST01-260X36") $readmemh({`ROOTPATH,"/input_data/marching1_12b_260x36.dat"},sensor_data);
else if (SENSOR_IMAGE_TYPE == "TEST01-260X68") $readmemh({`ROOTPATH,"/input_data/marching1_12b_260x68.dat"},sensor_data);
else if (SENSOR_IMAGE_TYPE == "260X260A") $readmemh({`ROOTPATH,"/input_data/img260x260x12b.dat"},sensor_data);
else if (SENSOR_IMAGE_TYPE == "256X256A") $readmemh({`ROOTPATH,"/input_data/img256x256-12b.dat"},sensor_data);
else if (SENSOR_IMAGE_TYPE == "512X512A") $readmemh({`ROOTPATH,"/input_data/img516x516-12b.dat"},sensor_data);
else begin
$display ("WARNING: Unrecognized sensor image :'%s', using default 'NORM': input_data/sensor.dat",SENSOR_IMAGE_TYPE);
$readmemh({`ROOTPATH,"/input_data/sensor.dat"},sensor_data);
......
simulation_modules/vospi.v 0 → 100644
View file @ 5cc1817c
/*!
* <b>Module:</b> vospi
* @file vospi.v
* @date 2019-03-31
* @author Andrey Filippov
*
* @brief single packet ;processing with a ping-pong buffer
*
* @copyright Copyright (c) 2019 Elphel, Inc.
*
* <b>License </b>
*
* vospi.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* vospi.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module vospi(
input clk,
input srst,
input [15:0] data_in,
output packet_rdy, // @clk
input sck, // SPI clk
input ncs, // SPI active-low CS
output miso // SPI data out
);
endmodule
util_modules/crc16_x16x12x5x0.v 0 → 100644
View file @ 5cc1817c
/*!
* <b>Module:</b> crc16_x16x12x5x0
* @file crc16_x16x12x5x0.v
* @date 2019-03-31
* @author Andrey Filippov
*
* @brief calculates CRC x^16+x^12+x^5+x^0 16-bit parallel
*
* @copyright Copyright (c) 2019 Elphel, Inc.
*
* <b>License </b>
*
* crc16_x16x12x5x0.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* crc16_x16x12x5x0.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module crc16_x16x12x5x0(
input clk,
input srst,
input en,
input [15:0] din,
output [15:0] dout
);
reg [15:0] crc;
assign dout = crc;
always@ (posedge clk) begin
if (srst) crc <= 0;
else if (en) crc <= din ^ {
crc[10]^crc[3]^crc[7]^crc[11],
crc[14]^crc[9]^crc[2],
crc[1]^crc[12]^crc[6]^crc[10]^crc[14]^crc[5]^crc[9],
crc[12]^crc[7]^crc[0]^crc[4]^crc[15],
crc[11]^crc[15]^crc[6]^crc[10]^crc[14],
crc[10]^crc[14]^crc[5]^crc[9]^crc[13],
crc[9]^crc[13]^crc[4]^crc[15]^crc[8]^crc[12],
crc[8]^crc[12]^crc[3]^crc[14]^crc[7]^crc[11]^crc[15],
crc[7]^crc[11]^crc[15]^crc[2]^crc[13],
crc[1]^crc[12]^crc[5]^crc[9]^crc[13],
crc[5]^crc[9]^crc[13]^crc[0]^crc[11]^crc[4]^crc[8]^crc[12],
crc[4]^crc[15]^crc[8]^crc[12],
crc[3]^crc[14]^crc[7]^crc[11]^crc[15],
crc[2]^crc[13],
crc[1]^crc[12]^crc[6]^crc[10]^crc[14]^crc[5]^crc[9]^crc[13],
crc[0]^crc[11]^crc[4]^crc[8]^crc[12]
};
end
endmodule
x393_hispi.bit
View file @ 5cc1817c
No preview for this file type
x393_hispi.timing_summary_impl 0 → 100644
View file @ 5cc1817c
This source diff could not be displayed because it is too large. You can view the blob instead.
x393_hispi_utilization.report 0 → 100644
View file @ 5cc1817c
------------------------------------------------------------------------------------
| Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
| Date : Thu Apr 4 15:35:18 2019
| Host : elphel-desktop running 64-bit Ubuntu 14.04.5 LTS
| Command : report_utilization
| Design : x393
| Device : 7z030fbg484-1
| Design State : Routed
------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Slice Logic Distribution
3. Memory
4. DSP
5. IO and GT Specific
6. Clocking
7. Specific Feature
8. Primitives
9. Black Boxes
10. Instantiated Netlists
1. Slice Logic
--------------
+----------------------------+-------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------------------+-------+-------+-----------+-------+
| Slice LUTs | 42671 | 0 | 78600 | 54.29 |
| LUT as Logic | 39126 | 0 | 78600 | 49.78 |
| LUT as Memory | 3545 | 0 | 26600 | 13.33 |
| LUT as Distributed RAM | 2930 | 0 | | |
| LUT as Shift Register | 615 | 0 | | |
| Slice Registers | 55453 | 0 | 157200 | 35.28 |
| Register as Flip Flop | 55453 | 0 | 157200 | 35.28 |
| Register as Latch | 0 | 0 | 157200 | 0.00 |
| F7 Muxes | 30 | 0 | 39300 | 0.08 |
| F8 Muxes | 0 | 0 | 19650 | 0.00 |
+----------------------------+-------+-------+-----------+-------+
1.1 Summary of Registers by Type
--------------------------------
+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 36 | Yes | - | Set |
| 680 | Yes | - | Reset |
| 962 | Yes | Set | - |
| 53775 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. Slice Logic Distribution
---------------------------
+-------------------------------------------+-------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------------------------+-------+-------+-----------+-------+
| Slice | 16846 | 0 | 19650 | 85.73 |
| SLICEL | 11074 | 0 | | |
| SLICEM | 5772 | 0 | | |
| LUT as Logic | 39126 | 0 | 78600 | 49.78 |
| using O5 output only | 1 | | | |
| using O6 output only | 30311 | | | |
| using O5 and O6 | 8814 | | | |
| LUT as Memory | 3545 | 0 | 26600 | 13.33 |
| LUT as Distributed RAM | 2930 | 0 | | |
| using O5 output only | 2 | | | |
| using O6 output only | 84 | | | |
| using O5 and O6 | 2844 | | | |
| LUT as Shift Register | 615 | 0 | | |
| using O5 output only | 341 | | | |
| using O6 output only | 221 | | | |
| using O5 and O6 | 53 | | | |
| LUT Flip Flop Pairs | 25047 | 0 | 78600 | 31.87 |
| fully used LUT-FF pairs | 4757 | | | |
| LUT-FF pairs with one unused LUT output | 18217 | | | |
| LUT-FF pairs with one unused Flip Flop | 17858 | | | |
| Unique Control Sets | 4700 | | | |
+-------------------------------------------+-------+-------+-----------+-------+
* Note: Review the Control Sets Report for more information regarding control sets.
3. Memory
---------
+-------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------+------+-------+-----------+-------+
| Block RAM Tile | 85 | 0 | 265 | 32.08 |
| RAMB36/FIFO* | 54 | 0 | 265 | 20.38 |
| RAMB36E1 only | 54 | | | |
| RAMB18 | 62 | 0 | 530 | 11.70 |
| RAMB18E1 only | 62 | | | |
+-------------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
4. DSP
------
+----------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------+------+-------+-----------+-------+
| DSPs | 76 | 0 | 400 | 19.00 |
| DSP48E1 only | 76 | | | |
+----------------+------+-------+-----------+-------+
5. IO and GT Specific
---------------------
+-----------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------------------------+------+-------+-----------+-------+
| Bonded IOB | 151 | 151 | 163 | 92.64 |
| IOB Master Pads | 73 | | | |
| IOB Slave Pads | 76 | | | |
| Bonded IPADs | 4 | 4 | 14 | 28.57 |
| Bonded OPADs | 2 | 2 | 8 | 25.00 |
| Bonded IOPADs | 0 | 0 | 130 | 0.00 |
| PHY_CONTROL | 0 | 0 | 5 | 0.00 |
| PHASER_REF | 0 | 0 | 5 | 0.00 |
| OUT_FIFO | 0 | 0 | 20 | 0.00 |
| IN_FIFO | 0 | 0 | 20 | 0.00 |
| IDELAYCTRL | 3 | 0 | 5 | 60.00 |
| IBUFDS | 22 | 22 | 155 | 14.19 |
| GTXE2_COMMON | 0 | 0 | 1 | 0.00 |
| GTXE2_CHANNEL | 1 | 1 | 4 | 25.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 38 | 38 | 250 | 15.20 |
| IDELAYE2 only | 20 | 20 | | |
| IDELAYE2_FINEDELAY only | 18 | 18 | | |
| ODELAYE2/ODELAYE2_FINEDELAY | 43 | 43 | 150 | 28.67 |
| ODELAYE2_FINEDELAY only | 43 | 43 | | |
| IBUFDS_GTE2 | 1 | 1 | 2 | 50.00 |
| ILOGIC | 32 | 32 | 163 | 19.63 |
| ISERDES | 32 | 32 | | |
| OLOGIC | 44 | 44 | 163 | 26.99 |
| OUTFF_ODDR_Register | 1 | 1 | | |
| OSERDES | 43 | 43 | | |
+-----------------------------+------+-------+-----------+-------+
6. Clocking
-----------
+--------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+--------------+------+-------+-----------+-------+
| BUFGCTRL | 14 | 0 | 32 | 43.75 |
| BUFIO | 3 | 0 | 20 | 15.00 |
| BUFIO only | 3 | 0 | | |
| MMCME2_ADV | 3 | 0 | 5 | 60.00 |
| PLLE2_ADV | 4 | 0 | 5 | 80.00 |
| BUFMRCE | 0 | 0 | 10 | 0.00 |
| BUFHCE | 0 | 0 | 96 | 0.00 |
| BUFR | 6 | 0 | 20 | 30.00 |
+--------------+------+-------+-----------+-------+
7. Specific Feature
-------------------
+-------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------+------+-------+-----------+-------+
| BSCANE2 | 0 | 0 | 4 | 0.00 |
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
| DNA_PORT | 0 | 0 | 1 | 0.00 |
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
| ICAPE2 | 0 | 0 | 2 | 0.00 |
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
| XADC | 0 | 0 | 1 | 0.00 |
+-------------+------+-------+-----------+-------+
8. Primitives
-------------
+------------------------+-------+----------------------+
| Ref Name | Used | Functional Category |
+------------------------+-------+----------------------+
| FDRE | 53775 | Flop & Latch |
| LUT3 | 11502 | LUT |
| LUT6 | 10432 | LUT |
| LUT2 | 8513 | LUT |
| LUT4 | 8148 | LUT |
| LUT5 | 7749 | LUT |
| RAMD32 | 4318 | Distributed Memory |
| CARRY4 | 2771 | CarryLogic |
| LUT1 | 1596 | LUT |
| RAMS32 | 1456 | Distributed Memory |
| FDSE | 962 | Flop & Latch |
| FDCE | 680 | Flop & Latch |
| SRL16E | 564 | Distributed Memory |
| SRLC32E | 104 | Distributed Memory |
| DSP48E1 | 76 | Block Arithmetic |
| RAMB18E1 | 62 | Block Memory |
| RAMB36E1 | 54 | Block Memory |
| OBUFT | 53 | IO |
| OSERDESE2 | 43 | IO |
| ODELAYE2_FINEDELAY | 43 | IO |
| FDPE | 36 | Flop & Latch |
| IBUF | 35 | IO |
| ISERDESE2 | 32 | IO |
| MUXF7 | 30 | MuxFx |
| OBUF | 23 | IO |
| IBUFDS | 22 | IO |
| IDELAYE2 | 20 | IO |
| OBUFT_DCIEN | 18 | IO |
| IDELAYE2_FINEDELAY | 18 | IO |
| IBUF_IBUFDISABLE | 18 | IO |
| PULLUP | 16 | I/O |
| BUFG | 14 | Clock |
| BUFR | 6 | Clock |
| PLLE2_ADV | 4 | Clock |
| OBUFTDS_DCIEN | 4 | IO |
| IBUFDS_IBUFDISABLE_INT | 4 | IO |
| MMCME2_ADV | 3 | Clock |
| INV | 3 | LUT |
| IDELAYCTRL | 3 | IO |
| BUFIO | 3 | Clock |
| OBUFTDS | 2 | IO |
| PS7 | 1 | Specialized Resource |
| ODDR | 1 | IO |
| IBUFDS_GTE2 | 1 | IO |
| GTXE2_CHANNEL | 1 | IO |
| DCIRESET | 1 | Others |
+------------------------+-------+----------------------+
9. Black Boxes
--------------
+----------+------+
| Ref Name | Used |
+----------+------+
10. Instantiated Netlists
-------------------------
+----------+------+
| Ref Name | Used |
+----------+------+
report_utilization: Time (s): cpu = 00:00:01 ; elapsed = 00:00:01 . Memory (MB): peak = 3495.180 ; gain = 0.000 ; free physical = 27077 ; free virtual = 29422
x393_parallel.bit
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Copyright 1986-2017 Xilinx, Inc. All Rights Reserved.
----------------------------------------------------------------------------------------
| Tool Version : Vivado v.2017.4 (lin64) Build 2086221 Fri Dec 15 20:54:30 MST 2017
| Date : Thu Apr 4 18:08:08 2019
| Host : elphel-desktop running 64-bit Ubuntu 14.04.5 LTS
| Command : report_utilization -file vivado_build/x393_parallel_utilization.report
| Design : x393
| Device : 7z030fbg484-1
| Design State : Routed
----------------------------------------------------------------------------------------
Utilization Design Information
Table of Contents
-----------------
1. Slice Logic
1.1 Summary of Registers by Type
2. Slice Logic Distribution
3. Memory
4. DSP
5. IO and GT Specific
6. Clocking
7. Specific Feature
8. Primitives
9. Black Boxes
10. Instantiated Netlists
1. Slice Logic
--------------
+----------------------------+-------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------------------+-------+-------+-----------+-------+
| Slice LUTs | 41675 | 0 | 78600 | 53.02 |
| LUT as Logic | 38288 | 0 | 78600 | 48.71 |
| LUT as Memory | 3387 | 0 | 26600 | 12.73 |
| LUT as Distributed RAM | 2850 | 0 | | |
| LUT as Shift Register | 537 | 0 | | |
| Slice Registers | 53972 | 0 | 157200 | 34.33 |
| Register as Flip Flop | 53972 | 0 | 157200 | 34.33 |
| Register as Latch | 0 | 0 | 157200 | 0.00 |
| F7 Muxes | 30 | 0 | 39300 | 0.08 |
| F8 Muxes | 0 | 0 | 19650 | 0.00 |
+----------------------------+-------+-------+-----------+-------+
1.1 Summary of Registers by Type
--------------------------------
+-------+--------------+-------------+--------------+
| Total | Clock Enable | Synchronous | Asynchronous |
+-------+--------------+-------------+--------------+
| 0 | _ | - | - |
| 0 | _ | - | Set |
| 0 | _ | - | Reset |
| 0 | _ | Set | - |
| 0 | _ | Reset | - |
| 0 | Yes | - | - |
| 16 | Yes | - | Set |
| 688 | Yes | - | Reset |
| 934 | Yes | Set | - |
| 52334 | Yes | Reset | - |
+-------+--------------+-------------+--------------+
2. Slice Logic Distribution
---------------------------
+-------------------------------------------+-------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------------------------------+-------+-------+-----------+-------+
| Slice | 16426 | 0 | 19650 | 83.59 |
| SLICEL | 10819 | 0 | | |
| SLICEM | 5607 | 0 | | |
| LUT as Logic | 38288 | 0 | 78600 | 48.71 |
| using O5 output only | 6 | | | |
| using O6 output only | 29749 | | | |
| using O5 and O6 | 8533 | | | |
| LUT as Memory | 3387 | 0 | 26600 | 12.73 |
| LUT as Distributed RAM | 2850 | 0 | | |
| using O5 output only | 2 | | | |
| using O6 output only | 84 | | | |
| using O5 and O6 | 2764 | | | |
| LUT as Shift Register | 537 | 0 | | |
| using O5 output only | 258 | | | |
| using O6 output only | 228 | | | |
| using O5 and O6 | 51 | | | |
| LUT Flip Flop Pairs | 24311 | 0 | 78600 | 30.93 |
| fully used LUT-FF pairs | 4601 | | | |
| LUT-FF pairs with one unused LUT output | 17639 | | | |
| LUT-FF pairs with one unused Flip Flop | 17425 | | | |
| Unique Control Sets | 4703 | | | |
+-------------------------------------------+-------+-------+-----------+-------+
* Note: Review the Control Sets Report for more information regarding control sets.
3. Memory
---------
+-------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------------+------+-------+-----------+-------+
| Block RAM Tile | 85 | 0 | 265 | 32.08 |
| RAMB36/FIFO* | 54 | 0 | 265 | 20.38 |
| RAMB36E1 only | 54 | | | |
| RAMB18 | 62 | 0 | 530 | 11.70 |
| RAMB18E1 only | 62 | | | |
+-------------------+------+-------+-----------+-------+
* Note: Each Block RAM Tile only has one FIFO logic available and therefore can accommodate only one FIFO36E1 or one FIFO18E1. However, if a FIFO18E1 occupies a Block RAM Tile, that tile can still accommodate a RAMB18E1
4. DSP
------
+----------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+----------------+------+-------+-----------+-------+
| DSPs | 76 | 0 | 400 | 19.00 |
| DSP48E1 only | 76 | | | |
+----------------+------+-------+-----------+-------+
5. IO and GT Specific
---------------------
+-----------------------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-----------------------------+------+-------+-----------+-------+
| Bonded IOB | 151 | 151 | 163 | 92.64 |
| IOB Master Pads | 73 | | | |
| IOB Slave Pads | 76 | | | |
| Bonded IPADs | 4 | 4 | 14 | 28.57 |
| Bonded OPADs | 2 | 2 | 8 | 25.00 |
| Bonded IOPADs | 0 | 0 | 130 | 0.00 |
| PHY_CONTROL | 0 | 0 | 5 | 0.00 |
| PHASER_REF | 0 | 0 | 5 | 0.00 |
| OUT_FIFO | 0 | 0 | 20 | 0.00 |
| IN_FIFO | 0 | 0 | 20 | 0.00 |
| IDELAYCTRL | 3 | 0 | 5 | 60.00 |
| IBUFDS | 2 | 2 | 155 | 1.29 |
| GTXE2_COMMON | 0 | 0 | 1 | 0.00 |
| GTXE2_CHANNEL | 1 | 1 | 4 | 25.00 |
| PHASER_OUT/PHASER_OUT_PHY | 0 | 0 | 20 | 0.00 |
| PHASER_IN/PHASER_IN_PHY | 0 | 0 | 20 | 0.00 |
| IDELAYE2/IDELAYE2_FINEDELAY | 78 | 78 | 250 | 31.20 |
| IDELAYE2 only | 60 | 60 | | |
| IDELAYE2_FINEDELAY only | 18 | 18 | | |
| ODELAYE2/ODELAYE2_FINEDELAY | 43 | 43 | 150 | 28.67 |
| ODELAYE2_FINEDELAY only | 43 | 43 | | |
| IBUFDS_GTE2 | 1 | 1 | 2 | 50.00 |
| ILOGIC | 72 | 72 | 163 | 44.17 |
| ISERDES | 72 | 72 | | |
| OLOGIC | 48 | 48 | 163 | 29.45 |
| OUTFF_ODDR_Register | 5 | 5 | | |
| OSERDES | 43 | 43 | | |
+-----------------------------+------+-------+-----------+-------+
6. Clocking
-----------
+--------------+------+-------+-----------+--------+
| Site Type | Used | Fixed | Available | Util% |
+--------------+------+-------+-----------+--------+
| BUFGCTRL | 14 | 0 | 32 | 43.75 |
| BUFIO | 3 | 0 | 20 | 15.00 |
| BUFIO only | 3 | 0 | | |
| MMCME2_ADV | 5 | 0 | 5 | 100.00 |
| PLLE2_ADV | 2 | 0 | 5 | 40.00 |
| BUFMRCE | 0 | 0 | 10 | 0.00 |
| BUFHCE | 0 | 0 | 96 | 0.00 |
| BUFR | 6 | 0 | 20 | 30.00 |
+--------------+------+-------+-----------+--------+
7. Specific Feature
-------------------
+-------------+------+-------+-----------+-------+
| Site Type | Used | Fixed | Available | Util% |
+-------------+------+-------+-----------+-------+
| BSCANE2 | 0 | 0 | 4 | 0.00 |
| CAPTUREE2 | 0 | 0 | 1 | 0.00 |
| DNA_PORT | 0 | 0 | 1 | 0.00 |
| EFUSE_USR | 0 | 0 | 1 | 0.00 |
| FRAME_ECCE2 | 0 | 0 | 1 | 0.00 |
| ICAPE2 | 0 | 0 | 2 | 0.00 |
| PCIE_2_1 | 0 | 0 | 1 | 0.00 |
| STARTUPE2 | 0 | 0 | 1 | 0.00 |
| XADC | 0 | 0 | 1 | 0.00 |
+-------------+------+-------+-----------+-------+
8. Primitives
-------------
+------------------------+-------+----------------------+
| Ref Name | Used | Functional Category |
+------------------------+-------+----------------------+
| FDRE | 52334 | Flop & Latch |
| LUT3 | 11303 | LUT |
| LUT6 | 10124 | LUT |
| LUT2 | 8405 | LUT |
| LUT4 | 7788 | LUT |
| LUT5 | 7581 | LUT |
| RAMD32 | 4198 | Distributed Memory |
| CARRY4 | 2793 | CarryLogic |
| LUT1 | 1620 | LUT |
| RAMS32 | 1416 | Distributed Memory |
| FDSE | 934 | Flop & Latch |
| FDCE | 688 | Flop & Latch |
| SRL16E | 484 | Distributed Memory |
| OBUFT | 121 | IO |
| SRLC32E | 104 | Distributed Memory |
| IBUF | 99 | IO |
| DSP48E1 | 76 | Block Arithmetic |
| ISERDESE2 | 72 | IO |
| RAMB18E1 | 62 | Block Memory |
| IDELAYE2 | 60 | IO |
| RAMB36E1 | 54 | Block Memory |
| OSERDESE2 | 43 | IO |
| ODELAYE2_FINEDELAY | 43 | IO |
| MUXF7 | 30 | MuxFx |
| OBUFT_DCIEN | 18 | IO |
| IDELAYE2_FINEDELAY | 18 | IO |
| IBUF_IBUFDISABLE | 18 | IO |
| PULLUP | 16 | I/O |
| FDPE | 16 | Flop & Latch |
| BUFG | 14 | Clock |
| BUFR | 6 | Clock |
| ODDR | 5 | IO |
| MMCME2_ADV | 5 | Clock |
| OBUFTDS_DCIEN | 4 | IO |
| IBUFDS_IBUFDISABLE_INT | 4 | IO |
| OBUF | 3 | IO |
| INV | 3 | LUT |
| IDELAYCTRL | 3 | IO |
| BUFIO | 3 | Clock |
| PLLE2_ADV | 2 | Clock |
| OBUFTDS | 2 | IO |
| IBUFDS | 2 | IO |
| PS7 | 1 | Specialized Resource |
| IBUFDS_GTE2 | 1 | IO |
| GTXE2_CHANNEL | 1 | IO |
| DCIRESET | 1 | Others |
+------------------------+-------+----------------------+
9. Black Boxes
--------------
+----------+------+
| Ref Name | Used |
+----------+------+
10. Instantiated Netlists
-------------------------
+----------+------+
| Ref Name | Used |
+----------+------+
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