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Elphel
x393
Commits
5a9ad21f
Commit
5a9ad21f
authored
Aug 06, 2016
by
Andrey Filippov
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combined histogram window settings to double-index
parent
0631243b
Changes
3
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3 changed files
with
14 additions
and
12 deletions
+14
-12
x393_parameters.vh
includes/x393_parameters.vh
+4
-3
vrlg.py
py393/vrlg.py
+4
-1
x393_export_c.py
py393/x393_export_c.py
+6
-8
No files found.
includes/x393_parameters.vh
View file @
5a9ad21f
...
@@ -493,10 +493,11 @@
...
@@ -493,10 +493,11 @@
parameter SENSI2C_ADDR_MASK = 'h7f0, // both for SENSI2C_ABS_ADDR and SENSI2C_REL_ADDR
parameter SENSI2C_ADDR_MASK = 'h7f0, // both for SENSI2C_ABS_ADDR and SENSI2C_REL_ADDR
// sens_hist registers (relative to SENSOR_GROUP_ADDR)
// sens_hist registers (relative to SENSOR_GROUP_ADDR)
parameter HISTOGRAM_RADDR_INC = 'h2, //
parameter HISTOGRAM_RADDR0 = 'h30, //
parameter HISTOGRAM_RADDR0 = 'h30, //
parameter HISTOGRAM_RADDR1 = 'h32, //
parameter HISTOGRAM_RADDR1 =
HISTOGRAM_RADDR0+ HISTOGRAM_RADDR_INC * 1, //
'h32, //
parameter HISTOGRAM_RADDR2 = 'h34, //
parameter HISTOGRAM_RADDR2 =
HISTOGRAM_RADDR0+ HISTOGRAM_RADDR_INC * 2, //
'h34, //
parameter HISTOGRAM_RADDR3 = 'h36, //
parameter HISTOGRAM_RADDR3 =
HISTOGRAM_RADDR0+ HISTOGRAM_RADDR_INC * 3, //
'h36, //
parameter HISTOGRAM_ADDR_MASK = 'h7fe, // for each channel
parameter HISTOGRAM_ADDR_MASK = 'h7fe, // for each channel
// sens_hist registers
// sens_hist registers
parameter HISTOGRAM_LEFT_TOP = 'h0,
parameter HISTOGRAM_LEFT_TOP = 'h0,
...
...
py393/vrlg.py
View file @
5a9ad21f
...
@@ -682,6 +682,7 @@ REFRESH_OFFSET__TYPE = str
...
@@ -682,6 +682,7 @@ REFRESH_OFFSET__TYPE = str
SENS_CTRL_ARST__RAW
=
str
SENS_CTRL_ARST__RAW
=
str
CMPRS_CBIT_DCSUB__TYPE
=
str
CMPRS_CBIT_DCSUB__TYPE
=
str
DFLT_INV_CLK_DIV__TYPE
=
str
DFLT_INV_CLK_DIV__TYPE
=
str
HISTOGRAM_RADDR_INC__RAW
=
str
MEMBRIDGE_WIDTH64__TYPE
=
str
MEMBRIDGE_WIDTH64__TYPE
=
str
SENS_GAMMA_MODE_BAYER__RAW
=
str
SENS_GAMMA_MODE_BAYER__RAW
=
str
MCNTRL_PS_STATUS_REG_ADDR__TYPE
=
str
MCNTRL_PS_STATUS_REG_ADDR__TYPE
=
str
...
@@ -782,6 +783,7 @@ DFLT_REFRESH_ADDR__RAW = str
...
@@ -782,6 +783,7 @@ DFLT_REFRESH_ADDR__RAW = str
GPIO_N
=
int
GPIO_N
=
int
MCONTR_ARBIT_ADDR_MASK__TYPE
=
str
MCONTR_ARBIT_ADDR_MASK__TYPE
=
str
SENS_CTRL_MRST__TYPE
=
str
SENS_CTRL_MRST__TYPE
=
str
HISTOGRAM_RADDR_INC__TYPE
=
str
SENS_CTRL_GP0
=
int
SENS_CTRL_GP0
=
int
SENS_CTRL_GP1
=
int
SENS_CTRL_GP1
=
int
FFCLK0_IBUF_LOW_PWR__TYPE
=
str
FFCLK0_IBUF_LOW_PWR__TYPE
=
str
...
@@ -998,6 +1000,7 @@ CMPRS_FRMT_MBCM1_BITS = int
...
@@ -998,6 +1000,7 @@ CMPRS_FRMT_MBCM1_BITS = int
SENS_GAMMA_MODE_REPET_SET__TYPE
=
str
SENS_GAMMA_MODE_REPET_SET__TYPE
=
str
HISTOGRAM_RAM_MODE__TYPE
=
str
HISTOGRAM_RAM_MODE__TYPE
=
str
AFI_LO_ADDR64
=
int
AFI_LO_ADDR64
=
int
NUM_CYCLES_28__TYPE
=
str
NUM_CYCLES_07__TYPE
=
str
NUM_CYCLES_07__TYPE
=
str
SENS_LENS_FAT0_IN
=
int
SENS_LENS_FAT0_IN
=
int
CMPRS_FRMT_LMARG_BITS__TYPE
=
str
CMPRS_FRMT_LMARG_BITS__TYPE
=
str
...
@@ -2111,7 +2114,7 @@ TILED_STARTX = int
...
@@ -2111,7 +2114,7 @@ TILED_STARTX = int
MEMBRIDGE_MASK__TYPE
=
str
MEMBRIDGE_MASK__TYPE
=
str
SENS_GAMMA_MODE_EN
=
int
SENS_GAMMA_MODE_EN
=
int
MCONTR_BUF3_RD_ADDR
=
int
MCONTR_BUF3_RD_ADDR
=
int
NUM_CYCLES_28__TYPE
=
str
HISTOGRAM_RADDR_INC
=
int
NUM_CYCLES_31__TYPE
=
str
NUM_CYCLES_31__TYPE
=
str
HISPI_CAPACITANCE__RAW
=
str
HISPI_CAPACITANCE__RAW
=
str
CMPRS_CBIT_FRAMES_SINGLE__TYPE
=
str
CMPRS_CBIT_FRAMES_SINGLE__TYPE
=
str
...
...
py393/x393_export_c.py
View file @
5a9ad21f
...
@@ -887,16 +887,14 @@ class X393ExportC(object):
...
@@ -887,16 +887,14 @@ class X393ExportC(object):
ba
=
vrlg
.
SENSOR_GROUP_ADDR
ba
=
vrlg
.
SENSOR_GROUP_ADDR
ia
=
vrlg
.
SENSOR_BASE_INC
ia
=
vrlg
.
SENSOR_BASE_INC
c
=
"sens_num"
c
=
"sens_num"
cs
=
(
"sens_num"
,
"sub_chn"
)
iam
=
(
vrlg
.
SENSOR_BASE_INC
,
vrlg
.
HISTOGRAM_RADDR_INC
)
z3z3
=
(
z3
,
z3
)
sdefines
+=
[
sdefines
+=
[
((
'Windows for histogram subchannels'
,)),
((
'Windows for histogram subchannels'
,)),
((
"X393_HISTOGRAM_LT0"
,
c
,
vrlg
.
HISTOGRAM_RADDR0
+
ba
,
ia
,
z3
,
"x393_hist_left_top"
,
"rw"
,
"Specify histogram 0 left/top"
)),
((
"X393_HISTOGRAM_LT"
,
cs
,
vrlg
.
HISTOGRAM_RADDR0
+
ba
,
iam
,
z3z3
,
"x393_hist_left_top"
,
"rw"
,
"Specify histograms left/top"
)),
((
"X393_HISTOGRAM_WH0"
,
c
,
vrlg
.
HISTOGRAM_RADDR0
+
1
+
ba
,
ia
,
z3
,
"x393_hist_width_height_m1"
,
"rw"
,
"Specify histogram 0 width/height"
)),
((
"X393_HISTOGRAM_WH"
,
cs
,
vrlg
.
HISTOGRAM_RADDR0
+
1
+
ba
,
iam
,
z3z3
,
"x393_hist_width_height_m1"
,
"rw"
,
"Specify histograms width/height"
)),
((
"X393_HISTOGRAM_LT1"
,
c
,
vrlg
.
HISTOGRAM_RADDR1
+
ba
,
ia
,
z3
,
"x393_hist_left_top"
,
"rw"
,
"Specify histogram 1 left/top"
)),
]
((
"X393_HISTOGRAM_WH1"
,
c
,
vrlg
.
HISTOGRAM_RADDR1
+
1
+
ba
,
ia
,
z3
,
"x393_hist_width_height_m1"
,
"rw"
,
"Specify histogram 1 width/height"
)),
((
"X393_HISTOGRAM_LT2"
,
c
,
vrlg
.
HISTOGRAM_RADDR2
+
ba
,
ia
,
z3
,
"x393_hist_left_top"
,
"rw"
,
"Specify histogram 2 left/top"
)),
((
"X393_HISTOGRAM_WH2"
,
c
,
vrlg
.
HISTOGRAM_RADDR2
+
1
+
ba
,
ia
,
z3
,
"x393_hist_width_height_m1"
,
"rw"
,
"Specify histogram 2 width/height"
)),
((
"X393_HISTOGRAM_LT3"
,
c
,
vrlg
.
HISTOGRAM_RADDR3
+
ba
,
ia
,
z3
,
"x393_hist_left_top"
,
"rw"
,
"Specify histogram 3 left/top"
)),
((
"X393_HISTOGRAM_WH3"
,
c
,
vrlg
.
HISTOGRAM_RADDR3
+
1
+
ba
,
ia
,
z3
,
"x393_hist_width_height_m1"
,
"rw"
,
"Specify histogram 3 width/height"
))]
ba
=
vrlg
.
SENSOR_GROUP_ADDR
ba
=
vrlg
.
SENSOR_GROUP_ADDR
ia
=
vrlg
.
SENSOR_BASE_INC
ia
=
vrlg
.
SENSOR_BASE_INC
c
=
"subchannel"
c
=
"subchannel"
...
...
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