Skip to content

X
x393
Commit 59774283 authored by Andrey Filippov's avatar Andrey Filippov
Browse files
Options

processing frame syn before previous frame is finished (fast forward, skipping memory transactions)

parent 2b1975c3
Show whitespace changes
Inline Side-by-side
Showing with 95 additions and 61 deletions
includes/x393_simulation_parameters.vh
View file @ 59774283
...@@ -67,7 +67,7 @@ ...@@ -67,7 +67,7 @@
parameter FRAME_WIDTH_ROUND_BITS = 9, // multiple of 512 pixels (32 16-byte bursts) (11 - ful SDRAM page) parameter FRAME_WIDTH_ROUND_BITS = 9, // multiple of 512 pixels (32 16-byte bursts) (11 - ful SDRAM page)
parameter WOI_WIDTH= 64, parameter WOI_WIDTH= 64,
parameter QUADRANTS_PXD_HACT_VACT = 6'h01 // 2 bits each: data-0, hact - 1, vact - 2 parameter QUADRANTS_PXD_HACT_VACT = 6'h01, // 2 bits each: data-0, hact - 1, vact - 2
// 90-degree shifts for data [1:0], hact [3:2] and vact [5:4] // 90-degree shifts for data [1:0], hact [3:2] and vact [5:4]
parameter SENSOR_PRIORITY = 0 // 1000 // 1000 - works OK, testing recover from too early Frame Sync // 5 usec for 200MHz mclk
\ No newline at end of file
memctrl/mcntrl393.v
View file @ 59774283
...@@ -300,6 +300,7 @@ module mcntrl393 #( ...@@ -300,6 +300,7 @@ module mcntrl393 #(
output [3:0] sens_buf_rd, // (), // input output [3:0] sens_buf_rd, // (), // input
input [255:0] sens_buf_dout, // (), // output[63:0] input [255:0] sens_buf_dout, // (), // output[63:0]
input [3:0] sens_page_written, // single mclk pulse: buffer page (full or partial) is written to the memory buffer input [3:0] sens_page_written, // single mclk pulse: buffer page (full or partial) is written to the memory buffer
output [3:0] sens_xfer_skipped, // single mclk pulse on each bit indicating one skipped (not written) block.
// compressor subsystem interface // compressor subsystem interface
// Buffer interfaces, combined for 4 channels // Buffer interfaces, combined for 4 channels
output [3:0] cmprs_xfer_reset_page_rd, // from mcntrl_tiled_rw ( output [3:0] cmprs_xfer_reset_page_rd, // from mcntrl_tiled_rw (
...@@ -1098,6 +1099,7 @@ module mcntrl393 #( ...@@ -1098,6 +1099,7 @@ module mcntrl393 #(
.xfer_done (sens_seq_done[i]), // input : page sequence over .xfer_done (sens_seq_done[i]), // input : page sequence over
.xfer_page_rst_wr (sens_rpage_set[i]), // output @ posedge mclk .xfer_page_rst_wr (sens_rpage_set[i]), // output @ posedge mclk
.xfer_page_rst_rd (), // output @ negedge mclk .xfer_page_rst_rd (), // output @ negedge mclk
.xfer_skipped (sens_xfer_skipped[i]), // output reg
.cmd_wrmem () // output .cmd_wrmem () // output
); );
...@@ -1237,6 +1239,7 @@ module mcntrl393 #( ...@@ -1237,6 +1239,7 @@ module mcntrl393 #(
.xfer_done (seq_done1), // input : sequence over .xfer_done (seq_done1), // input : sequence over
.xfer_page_rst_wr (xfer_reset_page1_wr), // output .xfer_page_rst_wr (xfer_reset_page1_wr), // output
.xfer_page_rst_rd (xfer_reset_page1_rd), // output .xfer_page_rst_rd (xfer_reset_page1_rd), // output
.xfer_skipped (), // output reg
.cmd_wrmem (cmd_wrmem_chn1) // output .cmd_wrmem (cmd_wrmem_chn1) // output
); );
...@@ -1300,6 +1303,7 @@ module mcntrl393 #( ...@@ -1300,6 +1303,7 @@ module mcntrl393 #(
.xfer_done (seq_done3), // input : sequence over .xfer_done (seq_done3), // input : sequence over
.xfer_page_rst_wr (xfer_reset_page3_wr), // output .xfer_page_rst_wr (xfer_reset_page3_wr), // output
.xfer_page_rst_rd (xfer_reset_page3_rd), // output .xfer_page_rst_rd (xfer_reset_page3_rd), // output
.xfer_skipped (), // output reg
.cmd_wrmem () // output .cmd_wrmem () // output
); );
......
memctrl/mcntrl_linear_rw.v
View file @ 59774283
...@@ -94,6 +94,7 @@ module mcntrl_linear_rw #( ...@@ -94,6 +94,7 @@ module mcntrl_linear_rw #(
input xfer_done, // transfer to/from the buffer finished input xfer_done, // transfer to/from the buffer finished
output xfer_page_rst_wr, // reset buffer internal page - at each frame start or when specifically reset (write to memory channel), @posedge output xfer_page_rst_wr, // reset buffer internal page - at each frame start or when specifically reset (write to memory channel), @posedge
output xfer_page_rst_rd, // reset buffer internal page - at each frame start or when specifically reset (read memory channel), @negedge output xfer_page_rst_rd, // reset buffer internal page - at each frame start or when specifically reset (read memory channel), @negedge
output reg xfer_skipped,
output cmd_wrmem output cmd_wrmem
); );
localparam NUM_RC_BURST_BITS=ADDRESS_NUMBER+COLADDR_NUMBER-3; //to spcify row and col8 == 22 localparam NUM_RC_BURST_BITS=ADDRESS_NUMBER+COLADDR_NUMBER-3; //to spcify row and col8 == 22
...@@ -217,7 +218,7 @@ module mcntrl_linear_rw #( ...@@ -217,7 +218,7 @@ module mcntrl_linear_rw #(
reg [FRAME_HEIGHT_BITS-1:0] window_y0; // (programmed) window top reg [FRAME_HEIGHT_BITS-1:0] window_y0; // (programmed) window top
reg [FRAME_WIDTH_BITS-1:0] start_x; // (programmed) normally 0, copied to curr_x on frame_start reg [FRAME_WIDTH_BITS-1:0] start_x; // (programmed) normally 0, copied to curr_x on frame_start
reg [FRAME_HEIGHT_BITS-1:0] start_y; // (programmed) normally 0, copied to curr_y on frame_start reg [FRAME_HEIGHT_BITS-1:0] start_y; // (programmed) normally 0, copied to curr_y on frame_start
reg xfer_done_d; // xfer_done delayed by 1 cycle; reg xfer_done_d; // xfer_done delayed by 1 cycle (also includes xfer_skipped)
assign frame_number = frame_number_current; assign frame_number = frame_number_current;
assign set_mode_w = cmd_we && (cmd_a== MCNTRL_SCANLINE_MODE); assign set_mode_w = cmd_we && (cmd_a== MCNTRL_SCANLINE_MODE);
...@@ -264,8 +265,8 @@ module mcntrl_linear_rw #( ...@@ -264,8 +265,8 @@ module mcntrl_linear_rw #(
if (mrst) is_last_frame <= 0; if (mrst) is_last_frame <= 0;
else is_last_frame <= frame_number_cntr == last_frame_number; else is_last_frame <= frame_number_cntr == last_frame_number;
if (mrst) frame_start_r <= 0; // if (mrst) frame_start_r <= 0;
else frame_start_r <= {frame_start_r[3:0], frame_start & frame_en}; // else frame_start_r <= {frame_start_r[3:0], frame_start & frame_en};
if (mrst) frame_en <= 0; if (mrst) frame_en <= 0;
else if (single_frame_r || repeat_frames) frame_en <= 1; else if (single_frame_r || repeat_frames) frame_en <= 1;
...@@ -354,12 +355,19 @@ module mcntrl_linear_rw #( ...@@ -354,12 +355,19 @@ module mcntrl_linear_rw #(
// Now skip if write and >=4 or read and >=5 (read starts with 4 and may end with 4) // Now skip if write and >=4 or read and >=5 (read starts with 4 and may end with 4)
// Also if the next page signal is used by the source/dest of data, it should use reject pulse to advance external // Also if the next page signal is used by the source/dest of data, it should use reject pulse to advance external
// page counter // page counter
wire start_skip_w = skip_too_late && want_r && (page_cntr >= 4) && !xfer_grant && (cmd_wrmem || page_cntr[0]); //&& busy_r && skip_run; wire start_skip_w;
reg start_skip_r; reg start_skip_r;
reg skip_run = 0; // run "skip" - advance addresses, but no actual read/write reg skip_run = 0; // run "skip" - advance addresses, but no actual read/write
reg xfer_reject_r; reg xfer_reject_r;
assign xfer_reject = xfer_reject_r; reg frame_start_pending; // frame_start came before previous one was finished
reg [1:0] frame_start_pending_long;
wire xfer_done_skipped = xfer_skipped || xfer_done;
wire frame_start_delayed = frame_start_pending_long[1] && !frame_start_pending_long[0];
wire frame_start_mod = (frame_start && !busy_r) || frame_start_delayed; // when frame_start_delayed it will completely miss a frame_start
assign xfer_reject = xfer_reject_r;
assign start_skip_w = skip_too_late && want_r && !xfer_grant && !skip_run &&
(((|page_cntr) && frame_start_pending) || ((page_cntr >= 4) && (cmd_wrmem || page_cntr[0]))); //&& busy_r && skip_run;
always @(posedge mclk) begin // Handling skip/reject always @(posedge mclk) begin // Handling skip/reject
if (mrst) xfer_reject_r <= 0; if (mrst) xfer_reject_r <= 0;
else xfer_reject_r <= xfer_grant && !chn_rst && skip_run; else xfer_reject_r <= xfer_grant && !chn_rst && skip_run;
...@@ -380,6 +388,28 @@ module mcntrl_linear_rw #( ...@@ -380,6 +388,28 @@ module mcntrl_linear_rw #(
if (mrst) start_skip_r <= 0; if (mrst) start_skip_r <= 0;
else start_skip_r <= start_skip_w; else start_skip_r <= start_skip_w;
if (mrst) xfer_skipped <= 0;
else xfer_skipped <= start_not_partial && skip_run;
// if (mrst || frame_start_delayed) frame_start_pending <= 0;
if (mrst) frame_start_pending <= 0;
// else frame_start_pending <= {frame_start_pending[0], busy_r && (frame_start_pending[0] | frame_start)};
else frame_start_pending <= busy_r && (frame_start_pending | frame_start);
if (mrst) frame_start_pending_long <= 0;
else frame_start_pending_long <= {frame_start_pending_long[0], (busy_r || skip_run) && (frame_start_pending_long[0] | frame_start)};
if (mrst) frame_start_r <= 0;
// else frame_start_r <= {frame_start_r[3:0], frame_start & frame_en};
else frame_start_r <= {frame_start_r[3:0], frame_start_mod & frame_en};
if (mrst || disable_need) need_r <= 0;
else if (chn_rst || xfer_grant || start_skip_r) need_r <= 0;
else if ((pre_want || want_r) && (page_cntr>=3)) need_r <= 1; // may raise need if want was already set
if (mrst) want_r <= 0;
else if (chn_rst || xfer_grant || start_skip_r) want_r <= 0;
else if (pre_want && (page_cntr>{1'b0,cmd_extra_pages})) want_r <= 1;
end end
...@@ -460,7 +490,7 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r; ...@@ -460,7 +490,7 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
else if (frame_done_r) busy_r <= 0; else if (frame_done_r) busy_r <= 0;
if (mrst) xfer_done_d <= 0; if (mrst) xfer_done_d <= 0;
else xfer_done_d <= xfer_done; else xfer_done_d <= xfer_done_skipped;
if (mrst) continued_xfer <= 1'b0; if (mrst) continued_xfer <= 1'b0;
...@@ -478,13 +508,13 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r; ...@@ -478,13 +508,13 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
else if (frame_done_r) frame_finished_r <= 1; else if (frame_done_r) frame_finished_r <= 1;
if (mrst || disable_need) need_r <= 0; // if (mrst || disable_need) need_r <= 0;
else if (chn_rst || xfer_grant) need_r <= 0; // else if (chn_rst || xfer_grant || start_skip_r) need_r <= 0;
else if ((pre_want || want_r) && (page_cntr>=3)) need_r <= 1; // may raise need if want was already set // else if ((pre_want || want_r) && (page_cntr>=3)) need_r <= 1; // may raise need if want was already set
if (mrst) want_r <= 0; // if (mrst) want_r <= 0;
else if (chn_rst || xfer_grant) want_r <= 0; // else if (chn_rst || xfer_grant || start_skip_r) want_r <= 0;
else if (pre_want && (page_cntr>{1'b0,cmd_extra_pages})) want_r <= 1; // else if (pre_want && (page_cntr>{1'b0,cmd_extra_pages})) want_r <= 1;
if (mrst) page_cntr <= 0; if (mrst) page_cntr <= 0;
else if (frame_start_r[0]) page_cntr <= cmd_wrmem?0:4; // What about last pages (like if only 1 page is needed)? Early frame end? else if (frame_start_r[0]) page_cntr <= cmd_wrmem?0:4; // What about last pages (like if only 1 page is needed)? Early frame end?
...@@ -513,35 +543,13 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r; ...@@ -513,35 +543,13 @@ wire start_not_partial= xfer_start_r[0] && !xfer_limited_by_mem_page_r;
if (mrst) pending_xfers <= 0; if (mrst) pending_xfers <= 0;
else if (chn_rst || !busy_r) pending_xfers <= 0; else if (chn_rst || !busy_r) pending_xfers <= 0;
else if ( xfer_start_r[0] && !xfer_done) pending_xfers <= pending_xfers + 1; else if ( xfer_start_r[0] && !xfer_done_skipped) pending_xfers <= pending_xfers + 1;
else if (!xfer_start_r[0] && xfer_done) pending_xfers <= pending_xfers - 1; else if (!xfer_start_r[0] && xfer_done_skipped) pending_xfers <= pending_xfers - 1;
/*
//line_unfinished_r cmd_wrmem
if (mrst) line_unfinished_r[0 +: FRAME_HEIGHT_BITS] <= 0; //{FRAME_HEIGHT_BITS{1'b0}};
else if (chn_rst || frame_start_r[0]) line_unfinished_r[0 +: FRAME_HEIGHT_BITS] <= window_y0+start_y;
else if (xfer_start_r[2]) line_unfinished_r[0 +: FRAME_HEIGHT_BITS] <= window_y0+next_y[FRAME_HEIGHT_BITS-1:0]; // latency 2 from xfer_start
if (mrst) line_unfinished_r[FRAME_HEIGHT_BITS +: FRAME_HEIGHT_BITS] <= 0; //{FRAME_HEIGHT_BITS{1'b0}};
// else if (chn_rst || frame_start_r[0]) line_unfinished_r[1] <= window_y0+start_y;
else if (chn_rst || frame_start_r[2]) line_unfinished_r[FRAME_HEIGHT_BITS +: FRAME_HEIGHT_BITS] <= window_y0+start_y; // _r[0] -> _r[2] to make it simultaneous with frame_number
// in read mode advance line number ASAP
else if (xfer_start_r[2] && !cmd_wrmem) line_unfinished_r[FRAME_HEIGHT_BITS +: FRAME_HEIGHT_BITS] <= window_y0+next_y[FRAME_HEIGHT_BITS-1:0]; // latency 2 from xfer_start
// in write mode advance line number only when it is guaranteed it will be the first to actually access memory
else if (xfer_grant && cmd_wrmem) line_unfinished_r[FRAME_HEIGHT_BITS +: FRAME_HEIGHT_BITS] <= line_unfinished_r[0 +: FRAME_HEIGHT_BITS];
*/
/*
if (mrst) line_unfinished_relw_r <= 0;
else if (cmd_wrmem && (frame_start_r[1] || !chn_en)) line_unfinished_relw_r <= start_y;
else if ((!cmd_wrmem && recalc_r[1]) || xfer_start_r[2]) line_unfinished_relw_r <= next_y[FRAME_HEIGHT_BITS-1:0];
// xfer_start_r[2] and recalc_r[1] are at the same time
if (mrst || (frame_start || !chn_en)) line_unfinished_r <= {FRAME_HEIGHT_BITS{~cmd_wrmem}}; // lowest/highest value until valid
else if (recalc_r[2]) line_unfinished_r <= line_unfinished_relw_r + window_y0;
*/
if (recalc_r[0]) line_unfinished_relw_r <= curr_y + (cmd_wrmem ? 0: 1); if (recalc_r[0]) line_unfinished_relw_r <= curr_y + (cmd_wrmem ? 0: 1);
if (mrst || (frame_start || !chn_en)) line_unfinished_r <= {FRAME_HEIGHT_BITS{~cmd_wrmem}}; // lowest/highest value until valid // if (mrst || (frame_start || !chn_en)) line_unfinished_r <= {FRAME_HEIGHT_BITS{~cmd_wrmem}}; // lowest/highest value until valid
if (mrst || (frame_start_mod || !chn_en)) line_unfinished_r <= {FRAME_HEIGHT_BITS{~cmd_wrmem}}; // lowest/highest value until valid
else if (recalc_r[2]) line_unfinished_r <= line_unfinished_relw_r + window_y0; else if (recalc_r[2]) line_unfinished_r <= line_unfinished_relw_r + window_y0;
......
x393.v
View file @ 59774283
...@@ -413,6 +413,7 @@ module x393 #( ...@@ -413,6 +413,7 @@ module x393 #(
wire [3:0] sens_buf_rd; // (), // input wire [3:0] sens_buf_rd; // (), // input
wire [255:0] sens_buf_dout; // (), // output[63:0] wire [255:0] sens_buf_dout; // (), // output[63:0]
wire [3:0] sens_page_written; // single mclk pulse: buffer page (full or partial) is written to the memory buffer wire [3:0] sens_page_written; // single mclk pulse: buffer page (full or partial) is written to the memory buffer
wire [3:0] sens_xfer_skipped; // single mclk pulse on every skipped (not written) block to record error statistics
wire trigger_mode; // (), // input wire trigger_mode; // (), // input
wire [3:0] trig_in; // input[3:0] wire [3:0] trig_in; // input[3:0]
...@@ -1131,7 +1132,7 @@ assign axi_grst = axi_rst_pre; ...@@ -1131,7 +1132,7 @@ assign axi_grst = axi_rst_pre;
.sens_buf_rd (sens_buf_rd), // output[3:0] .sens_buf_rd (sens_buf_rd), // output[3:0]
.sens_buf_dout (sens_buf_dout), // input[255:0] .sens_buf_dout (sens_buf_dout), // input[255:0]
.sens_page_written (sens_page_written), // input [3:0] single mclk pulse: buffer page (full or partial) is written to the memory buffer .sens_page_written (sens_page_written), // input [3:0] single mclk pulse: buffer page (full or partial) is written to the memory buffer
.sens_xfer_skipped (sens_xfer_skipped), // output reg
// compressor interface // compressor interface
.cmprs_xfer_reset_page_rd (cmprs_xfer_reset_page_rd), // output[3:0] .cmprs_xfer_reset_page_rd (cmprs_xfer_reset_page_rd), // output[3:0]
.cmprs_buf_wpage_nxt (cmprs_buf_wpage_nxt), // output[3:0] .cmprs_buf_wpage_nxt (cmprs_buf_wpage_nxt), // output[3:0]
......
x393_testbench03.sav
View file @ 59774283
[*] [*]
[*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI [*] GTKWave Analyzer v3.3.66 (w)1999-2015 BSI
[*] Tue Oct 20 00:35:32 2015 [*] Wed Oct 21 03:45:23 2015
[*] [*]
[dumpfile] "/home/andrey/git/x393/simulation/x393_testbench03-20151019173150201.fst" [dumpfile] "/home/andrey/git/x393/simulation/x393_testbench03-20151020195643294.fst"
[dumpfile_mtime] "Tue Oct 20 00:11:59 2015" [dumpfile_mtime] "Wed Oct 21 02:34:57 2015"
[dumpfile_size] 246875731 [dumpfile_size] 269754303
[savefile] "/home/andrey/git/x393/x393_testbench03.sav" [savefile] "/home/andrey/git/x393/x393_testbench03.sav"
[timestart] 0 [timestart] 93798600
[size] 1823 1180 [size] 1823 1180
[pos] 1917 0 [pos] 1917 0
*-25.380077 116922388 99347388 99907388 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 *-16.380077 94047388 178682388 184032388 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] x393_testbench03. [treeopen] x393_testbench03.
[treeopen] x393_testbench03.par12_hispi_psp4l0_i. [treeopen] x393_testbench03.par12_hispi_psp4l0_i.
[treeopen] x393_testbench03.par12_hispi_psp4l0_i.cmprs_channel_block[0]. [treeopen] x393_testbench03.par12_hispi_psp4l0_i.cmprs_channel_block[0].
...@@ -49,11 +49,11 @@ ...@@ -49,11 +49,11 @@
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1. [treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[2].sensor_channel_i.genblk1.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i. [treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.
[treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.genblk1. [treeopen] x393_testbench03.x393_i.sensors393_i.sensor_channel_block[3].sensor_channel_i.genblk1.
[sst_width] 512 [sst_width] 280
[signals_width] 347 [signals_width] 262
[sst_expanded] 1 [sst_expanded] 1
[sst_vpaned_height] 670 [sst_vpaned_height] 670
@821 @820
x393_testbench03.TEST_TITLE[639:0] x393_testbench03.TEST_TITLE[639:0]
@800200 @800200
-x393_top -x393_top
...@@ -853,7 +853,7 @@ x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i ...@@ -853,7 +853,7 @@ x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i
(1)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.pending_xfers[1:0] (1)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.pending_xfers[1:0]
@1401200 @1401200
-group_end -group_end
@c00022 @800022
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.recalc_r[8:0] x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.recalc_r[8:0]
@28 @28
(0)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.recalc_r[8:0] (0)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.recalc_r[8:0]
...@@ -865,7 +865,7 @@ x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i ...@@ -865,7 +865,7 @@ x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i
(6)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.recalc_r[8:0] (6)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.recalc_r[8:0]
(7)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.recalc_r[8:0] (7)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.recalc_r[8:0]
(8)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.recalc_r[8:0] (8)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.recalc_r[8:0]
@1401200 @1001200
-group_end -group_end
@c00022 @c00022
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.par_mod_r[8:0] x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.par_mod_r[8:0]
...@@ -883,7 +883,26 @@ x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i ...@@ -883,7 +883,26 @@ x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i
-group_end -group_end
@28 @28
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.calc_valid x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.calc_valid
@29
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.skip_run x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.skip_run
@28
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.frame_start
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.frame_start_delayed
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.frame_start_mod
@22
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.page_cntr[2:0]
@28
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.busy_r
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.pre_want
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.want_r
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.frame_start_pending
@800028
x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.frame_start_pending_long[1:0]
@28
(0)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.frame_start_pending_long[1:0]
(1)x393_testbench03.x393_i.mcntrl393_i.sens_comp_block[0].mcntrl_linear_wr_sensor_i.frame_start_pending_long[1:0]
@1001200
-group_end
@200 @200
- -
@1000200 @1000200
......
x393_testbench03.tf
View file @ 59774283
...@@ -113,8 +113,8 @@ parameter EXTERNAL_TIMESTAMP = 0; // 1 ; // embed local timestamp, 1 - emb ...@@ -113,8 +113,8 @@ parameter EXTERNAL_TIMESTAMP = 0; // 1 ; // embed local timestamp, 1 - emb
parameter TRIG_PERIOD = 6000 ; parameter TRIG_PERIOD = 6000 ;
`ifdef HISPI `ifdef HISPI
parameter HBLANK= 90; // 12; /// 52; //********************* parameter HBLANK= 52; // 90; // 12; /// 52; //*********************
parameter BLANK_ROWS_BEFORE= 9; // 3; //8; ///2+2 - a little faster than compressor parameter BLANK_ROWS_BEFORE= 3; // 9; // 3; //8; ///2+2 - a little faster than compressor
parameter BLANK_ROWS_AFTER= 1; //8; parameter BLANK_ROWS_AFTER= 1; //8;
`else `else
...@@ -2648,6 +2648,8 @@ task setup_sensor_channel; ...@@ -2648,6 +2648,8 @@ task setup_sensor_channel;
// Enable arbitration of sensor-to-memory controller // Enable arbitration of sensor-to-memory controller
enable_memcntrl_en_dis(4'h8 + {2'b0,num_sensor}, 1); enable_memcntrl_en_dis(4'h8 + {2'b0,num_sensor}, 1);
// write_contol_register(MCONTR_TOP_16BIT_ADDR + MCONTR_TOP_16BIT_CHN_EN, {16'b0,ENABLED_CHANNELS}); // write_contol_register(MCONTR_TOP_16BIT_ADDR + MCONTR_TOP_16BIT_CHN_EN, {16'b0,ENABLED_CHANNELS});
// Set sesnor channel priority - 5 usec bonus to compressor/other channels
configure_channel_priority(4'h8 + {2'b0,num_sensor}, SENSOR_PRIORITY); // lowest priority channel 1
compressor_run (num_sensor, 0); // reset compressor compressor_run (num_sensor, 0); // reset compressor
......
Markdown is supported
0% or
You are about to add 0 people to the discussion. Proceed with caution.
Finish editing this message first!
Please register or to comment