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Commit 56a59c77 authored by Andrey Filippov's avatar Andrey Filippov
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more changes to convert project

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.project
View file @ 56a59c77
<?xml version="1.0" encoding="UTF-8"?> <?xml version="1.0" encoding="UTF-8"?>
<projectDescription> <projectDescription>
<name>eddr3</name> <name>x393</name>
<comment></comment> <comment></comment>
<projects> <projects>
</projects> </projects>
...@@ -52,87 +52,87 @@ ...@@ -52,87 +52,87 @@
<link> <link>
<name>ise_logs/ISExst.log</name> <name>ise_logs/ISExst.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/ise_logs/ISExst-20140607155721361.log</location> <location>ise_logs/ISExst-20140607155721361.log</location>
</link> </link>
<link> <link>
<name>ise_state/eddr3-synth.tgz</name> <name>ise_state/x393-synth.tgz</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/ise_state/eddr3-synth-20140607155721361.tgz</location> <location>ise_state/x393-synth-20140607155721361.tgz</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoBitstream.log</name> <name>vivado_logs/VivadoBitstream.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoBitstream-20140611174132808.log</location> <location>vivado_logs/VivadoBitstream-20140611174132808.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOpt.log</name> <name>vivado_logs/VivadoOpt.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOpt-20140611174132808.log</location> <location>vivado_logs/VivadoOpt-20140611174132808.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPhys.log</name> <name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPhys-20140611174132808.log</location> <location>vivado_logs/VivadoOptPhys-20140611174132808.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPower.log</name> <name>vivado_logs/VivadoOptPower.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPower-20140611174132808.log</location> <location>vivado_logs/VivadoOptPower-20140611174132808.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoPlace.log</name> <name>vivado_logs/VivadoPlace.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoPlace-20140611174132808.log</location> <location>vivado_logs/VivadoPlace-20140611174132808.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoRoute.log</name> <name>vivado_logs/VivadoRoute.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoRoute-20140611174132808.log</location> <location>vivado_logs/VivadoRoute-20140611174132808.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoSynthesis.log</name> <name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140611174056482.log</location> <location>vivado_logs/VivadoSynthesis-20140611174056482.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name> <name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportImplemented-20140611174132808.log</location> <location>vivado_logs/VivadoTimimgSummaryReportImplemented-20140611174132808.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name> <name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140611174132808.log</location> <location>vivado_logs/VivadoTimimgSummaryReportSynthesis-20140611174132808.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimingReportImplemented.log</name> <name>vivado_logs/VivadoTimingReportImplemented.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportImplemented-20140611174132808.log</location> <location>vivado_logs/VivadoTimingReportImplemented-20140611174132808.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name> <name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140611174132808.log</location> <location>vivado_logs/VivadoTimingReportSynthesis-20140611174132808.log</location>
</link> </link>
<link> <link>
<name>vivado_state/eddr3-opt-phys.dcp</name> <name>vivado_state/x393-opt-phys.dcp</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-opt-phys-20140611174132808.dcp</location> <location>vivado_state/x393-opt-phys-20140611174132808.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/eddr3-place.dcp</name> <name>vivado_state/x393-place.dcp</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-place-20140611174132808.dcp</location> <location>vivado_state/x393-place-20140611174132808.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/eddr3-route.dcp</name> <name>vivado_state/x393-route.dcp</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-route-20140611174132808.dcp</location> <location>vivado_state/x393-route-20140611174132808.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/eddr3-synth.dcp</name> <name>vivado_state/x393-synth.dcp</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-synth-20140610113942407.dcp</location> <location>vivado_state/x393-synth-20140610113942407.dcp</location>
</link> </link>
</linkedResources> </linkedResources>
</projectDescription> </projectDescription>
.settings/com.elphel.vdt.iverilog.prefs
View file @ 56a59c77
...@@ -4,6 +4,6 @@ iverilog_77_Param_Exe=/usr/local/bin/iverilog ...@@ -4,6 +4,6 @@ iverilog_77_Param_Exe=/usr/local/bin/iverilog
iverilog_78_VVP_Exe=/usr/local/bin/vvp iverilog_78_VVP_Exe=/usr/local/bin/vvp
iverilog_81_TopModulesOther=glbl<-@\#\#@-> iverilog_81_TopModulesOther=glbl<-@\#\#@->
iverilog_83_ExtraFiles=glbl.v<-@\#\#@-> iverilog_83_ExtraFiles=glbl.v<-@\#\#@->
iverilog_84_IncludeDir=/data/vdt/vdt-projects/eddr3/ddr3<-@\#\#@-> iverilog_84_IncludeDir=/home/andrey/git/x393/ddr3<-@\#\#@->
iverilog_88_ShowNoProblem=true iverilog_88_ShowNoProblem=true
iverilog_99_GrepFindErrWarn=error|warning|sorry iverilog_99_GrepFindErrWarn=error|warning|sorry
README.md
View file @ 56a59c77
eddr3 x393
===== =====
ddr3 subproject for Elphel 393 camera FPGA code for Elphel 393 camera
This subproject is started to create a DDR3 memory controller for Elphel camera that does not depend on any non-documented
features of Xilinx Zynq and can be simulated by Free Software tools (Icarus Verilog + GTKWave) without use of any encrypted
modules. Everything in plain Verilog and constraints.
Detailed description of the project is available in the blog post: http://blog.elphel.com/2014/06/ddr3-memory-interface-on-xilinx-zynq-soc-free-software-compatible/
ddrc_test01_testbench.sav
View file @ 56a59c77
...@@ -2,10 +2,10 @@ ...@@ -2,10 +2,10 @@
[*] GTKWave Analyzer v3.3.49 (w)1999-2013 BSI [*] GTKWave Analyzer v3.3.49 (w)1999-2013 BSI
[*] Sat Jun 14 07:10:23 2014 [*] Sat Jun 14 07:10:23 2014
[*] [*]
[dumpfile] "/data/vdt/vdt-projects/eddr3/simulation/ddrc_test01_testbench-20140610175433027.lxt" [dumpfile] "simulation/ddrc_test01_testbench-20140610175433027.lxt"
[dumpfile_mtime] "Tue Jun 10 23:58:40 2014" [dumpfile_mtime] "Tue Jun 10 23:58:40 2014"
[dumpfile_size] 75451369 [dumpfile_size] 75451369
[savefile] "/data/vdt/vdt-projects/eddr3/ddrc_test01_testbench.sav" [savefile] "ddrc_test01_testbench.sav"
[timestart] 137507870 [timestart] 137507870
[size] 1920 1180 [size] 1920 1180
[pos] -1 -1 [pos] -1 -1
......
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