Commit 547054f6 authored by Andrey Filippov's avatar Andrey Filippov
Browse files

ran some tests with TEST_SCANLINE_WRITE, fixed some bugs

parent 8f79e6f7
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+54 −2
Original line number Original line Diff line number Diff line
@@ -19,7 +19,60 @@
 * You should have received a copy of the GNU General Public License
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/> .
 * along with this program.  If not, see <http://www.gnu.org/licenses/> .
 *******************************************************************************/
 *******************************************************************************/
//MCONTR_BUF1_WR_ADDR
task write_block_scanline_chn;  // S uppressThisWarning VEditor : may be unused
    input integer chn; // buffer channel
    input   [1:0] page;
    input integer num_words; // number of words to write (will be rounded up to multiple of 16)
    input integer startX;
    input integer startY;
    reg    [29:0] start_addr;
    begin
        case (chn)
            1:  start_addr=MCONTR_BUF1_WR_ADDR + (page << 8);
            3:  start_addr=MCONTR_BUF3_WR_ADDR + (page << 8);
            default: begin
                $display("**** ERROR: Invalid channel for write_block_scanline_chn = %d @%t", chn, $time);
                start_addr = MCONTR_BUF1_WR_ADDR+ (page << 8);
            end
        endcase
        write_block_incremtal (start_addr, num_words, startX+startY<<16);
    end
endtask


task write_block_incremtal;
    input [29:0] start_word_address;
    input integer num_words; // number of words to write (will be rounded up to multiple of 16)
    input integer start_value;      
    integer i, j;
    begin
        $display("**** write_block_buf  @%t", $time);
        for (i = 0; i < num_words; i = i + 16) begin
            axi_write_addr_data(
                i,    // id
                {start_word_address,2'b0}+( i << 2),
                start_value+i,
                4'hf, // len
                1,    // burst type - increment
                1'b1, // data_en
                4'hf, // wstrb
                1'b0 // last
                );
//            $display("+Write block data (addr:data): 0x%x:0x%08x @%t", i, i | (((i + 7) & 'hff) << 8) | (((i + 23) & 'hff) << 16) | (((i + 31) & 'hff) << 24), $time);
            $display("+Write block incremental (addr:data): 0x%x:0x%08x @%t", i, start_value+i, $time);
            for (j = 1; j < 16; j = j + 1) begin
                axi_write_data(
                    i,        // id
                    start_value+i+j,
                    4'hf, // wstrb
                    (1 == 15) ? 1 : 0 // last
                    );
                $display(" Write block incremental (addr:data): 0x%08x:0x%x @%t", (i + j), start_value+i+j, $time);
            end
        end
    end
endtask

task write_block_buf_chn;  // S uppressThisWarning VEditor : may be unused
task write_block_buf_chn;  // S uppressThisWarning VEditor : may be unused
    input integer chn; // buffer channel
    input integer chn; // buffer channel
    input   [1:0] page;
    input   [1:0] page;
@@ -68,7 +121,6 @@ task write_block_buf;
                    (i + j) | ((((i + j) + 7) & 'hff) << 8) | ((((i + j) + 23) & 'hff) << 16) | ((((i + j) + 31) & 'hff) << 24), $time);
                    (i + j) | ((((i + j) + 7) & 'hff) << 8) | ((((i + j) + 23) & 'hff) << 16) | ((((i + j) + 31) & 'hff) << 24), $time);
            end
            end
        end
        end

    end
    end
endtask
endtask
   
   
+5 −4
Original line number Original line Diff line number Diff line
@@ -34,6 +34,7 @@ module cmd_encod_linear_rd #(
//    parameter BASEADDR = 0,
//    parameter BASEADDR = 0,
    parameter ADDRESS_NUMBER=       15,
    parameter ADDRESS_NUMBER=       15,
    parameter COLADDR_NUMBER=       10,
    parameter COLADDR_NUMBER=       10,
    parameter NUM_XFER_BITS=         6,    // number of bits to specify transfer length
    parameter CMD_PAUSE_BITS=       10,
    parameter CMD_PAUSE_BITS=       10,
    parameter CMD_DONE_BIT=         10 // VDT BUG: CMD_DONE_BIT is used in a function call parameter!
    parameter CMD_DONE_BIT=         10 // VDT BUG: CMD_DONE_BIT is used in a function call parameter!
) (
) (
@@ -45,7 +46,7 @@ module cmd_encod_linear_rd #(
    input                  [2:0] bank_in,     // bank address
    input                  [2:0] bank_in,     // bank address
    input   [ADDRESS_NUMBER-1:0] row_in,      // memory row
    input   [ADDRESS_NUMBER-1:0] row_in,      // memory row
    input   [COLADDR_NUMBER-4:0] start_col,   // start memory column in 8-bursts
    input   [COLADDR_NUMBER-4:0] start_col,   // start memory column in 8-bursts
    input                  [5:0] num128_in,   // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
    input    [NUM_XFER_BITS-1:0] num128_in,   // number of 128-bit words to transfer (8*16 bits) - full bursts of 8 ( 0 - maximal length, 64)
    input                        start,       // start generating commands
    input                        start,       // start generating commands
    output reg            [31:0] enc_cmd,     // encoded commnad
    output reg            [31:0] enc_cmd,     // encoded commnad
    output reg                   enc_wr,      // write encoded command
    output reg                   enc_wr,      // write encoded command
@@ -78,7 +79,7 @@ module cmd_encod_linear_rd #(
    reg   [ADDRESS_NUMBER-1:0] row;     // memory row
    reg   [ADDRESS_NUMBER-1:0] row;     // memory row
    reg   [COLADDR_NUMBER-4:0] col;     // start memory column (3 LSBs should be 0?) // VDT BUG: col is used as a function call parameter!
    reg   [COLADDR_NUMBER-4:0] col;     // start memory column (3 LSBs should be 0?) // VDT BUG: col is used as a function call parameter!
    reg                  [2:0] bank;    // memory bank;
    reg                  [2:0] bank;    // memory bank;
    reg                  [5:0] num128;  // number of 128-bit words to transfer
    reg    [NUM_XFER_BITS-1:0] num128;  // number of 128-bit words to transfer
    
    
    reg                        gen_run;
    reg                        gen_run;
    reg                        gen_run_d;
    reg                        gen_run_d;
@@ -106,8 +107,8 @@ module cmd_encod_linear_rd #(


        if (rst)                     gen_addr <= 0;
        if (rst)                     gen_addr <= 0;
        else if (!start && !gen_run) gen_addr <= 0;
        else if (!start && !gen_run) gen_addr <= 0;
        else if ((gen_addr==(REPEAT_ADDR-1)) && (num128[5:1]==0)) gen_addr <= REPEAT_ADDR+1; // skip loop alltogeter
        else if ((gen_addr==(REPEAT_ADDR-1)) && (num128[NUM_XFER_BITS-1:1]==0)) gen_addr <= REPEAT_ADDR+1; // skip loop alltogeter
        else if ((gen_addr !=REPEAT_ADDR) || (num128[5:1]==0)) gen_addr <= gen_addr+1; // not in a loop
        else if ((gen_addr !=REPEAT_ADDR) || (num128[NUM_XFER_BITS-1:1]==0)) gen_addr <= gen_addr+1; // not in a loop
//counting loops?        
//counting loops?        
        if      (rst)          num128 <= 0;
        if      (rst)          num128 <= 0;
        else if (start)        num128 <= num128_in;
        else if (start)        num128 <= num128_in;
+2 −0
Original line number Original line Diff line number Diff line
@@ -916,6 +916,7 @@ module mcntrl393 #(
    cmd_encod_linear_rd #(
    cmd_encod_linear_rd #(
        .ADDRESS_NUMBER  (ADDRESS_NUMBER),
        .ADDRESS_NUMBER  (ADDRESS_NUMBER),
        .COLADDR_NUMBER  (COLADDR_NUMBER),
        .COLADDR_NUMBER  (COLADDR_NUMBER),
        .NUM_XFER_BITS   (NUM_XFER_BITS),
        .CMD_PAUSE_BITS  (CMD_PAUSE_BITS),
        .CMD_PAUSE_BITS  (CMD_PAUSE_BITS),
        .CMD_DONE_BIT    (CMD_DONE_BIT)
        .CMD_DONE_BIT    (CMD_DONE_BIT)
    ) cmd_encod_linear_rd_i (
    ) cmd_encod_linear_rd_i (
@@ -935,6 +936,7 @@ module mcntrl393 #(
    cmd_encod_linear_wr #(
    cmd_encod_linear_wr #(
        .ADDRESS_NUMBER  (ADDRESS_NUMBER),
        .ADDRESS_NUMBER  (ADDRESS_NUMBER),
        .COLADDR_NUMBER  (COLADDR_NUMBER),
        .COLADDR_NUMBER  (COLADDR_NUMBER),
        .NUM_XFER_BITS   (NUM_XFER_BITS),
        .CMD_PAUSE_BITS  (CMD_PAUSE_BITS),
        .CMD_PAUSE_BITS  (CMD_PAUSE_BITS),
        .CMD_DONE_BIT  (CMD_DONE_BIT)
        .CMD_DONE_BIT  (CMD_DONE_BIT)
    ) cmd_encod_linear_wr_i (
    ) cmd_encod_linear_wr_i (
+28 −8
Original line number Original line Diff line number Diff line
@@ -152,8 +152,8 @@ module mcntrl_linear_rw #(
    reg   [FRAME_HEIGHT_BITS-1:0] window_y0;      // (programmed) window top
    reg   [FRAME_HEIGHT_BITS-1:0] window_y0;      // (programmed) window top
    reg    [FRAME_WIDTH_BITS-1:0] start_x;        // (programmed) normally 0, copied to curr_x on frame_start  
    reg    [FRAME_WIDTH_BITS-1:0] start_x;        // (programmed) normally 0, copied to curr_x on frame_start  
    reg   [FRAME_HEIGHT_BITS-1:0] start_y;        // (programmed) normally 0, copied to curr_y on frame_start 
    reg   [FRAME_HEIGHT_BITS-1:0] start_y;        // (programmed) normally 0, copied to curr_y on frame_start 
    
    reg                           xfer_done_d;    // xfer_done delayed by 1 cycle;
    
 //   reg                           no_more_needed; // frame finished, no more requests is needed
    assign set_mode_w =         cmd_we && (cmd_a== MCNTRL_SCANLINE_MODE);
    assign set_mode_w =         cmd_we && (cmd_a== MCNTRL_SCANLINE_MODE);
    assign set_status_w =       cmd_we && (cmd_a== MCNTRL_SCANLINE_STATUS_CNTRL);
    assign set_status_w =       cmd_we && (cmd_a== MCNTRL_SCANLINE_STATUS_CNTRL);
    assign set_start_addr_w =   cmd_we && (cmd_a== MCNTRL_SCANLINE_STARTADDR);
    assign set_start_addr_w =   cmd_we && (cmd_a== MCNTRL_SCANLINE_STARTADDR);
@@ -205,6 +205,8 @@ module mcntrl_linear_rw #(
    assign xfer_reset_page = xfer_reset_page_r;
    assign xfer_reset_page = xfer_reset_page_r;
    assign frame_done=  frame_done_r;
    assign frame_done=  frame_done_r;
    assign pre_want=    chn_en && busy_r && !want_r && !xfer_start_r[0] && calc_valid && !last_block && !suspend;
    assign pre_want=    chn_en && busy_r && !want_r && !xfer_start_r[0] && calc_valid && !last_block && !suspend;
//    assign pre_want=    chn_en && busy_r && !want_r && !xfer_start_r[0] && calc_valid && !no_more_needed && !suspend;
    //
    assign last_in_row_w=(row_left=={{(FRAME_WIDTH_BITS-NUM_XFER_BITS){1'b0}},xfer_num128_r});
    assign last_in_row_w=(row_left=={{(FRAME_WIDTH_BITS-NUM_XFER_BITS){1'b0}},xfer_num128_r});
    assign last_row_w=  next_y==window_height;
    assign last_row_w=  next_y==window_height;
    assign xfer_want=   want_r;
    assign xfer_want=   want_r;
@@ -261,6 +263,19 @@ module mcntrl_linear_rw #(
        else if (frame_start)  busy_r <= 1;
        else if (frame_start)  busy_r <= 1;
        else if (frame_done_r) busy_r <= 0;
        else if (frame_done_r) busy_r <= 0;
        
        
        if (rst)          xfer_done_d <= 0;
        else              xfer_done_d <= xfer_done;
        

        if      (rst)                                                       frame_done_r <= 0;
        else if (chn_rst || frame_start)                                    frame_done_r <= 0;
        else if (busy_r && last_block && xfer_done_d && (pending_xfers==0)) frame_done_r <= 1;

//        if (rst)          frame_done_r <= 0;
//        else              frame_done_r <= busy_r && last_block && xfer_done_d && (pending_xfers==0);
        
        
        
        if (rst) xfer_start_r <= 0;
        if (rst) xfer_start_r <= 0;
        else     xfer_start_r <= {xfer_start_r[1:0],xfer_grant && !chn_rst};
        else     xfer_start_r <= {xfer_start_r[1:0],xfer_grant && !chn_rst};
        
        
@@ -273,9 +288,9 @@ module mcntrl_linear_rw #(
        else if (pre_want && (page_cntr>{1'b0,cmd_extra_pages})) want_r <= 1;
        else if (pre_want && (page_cntr>{1'b0,cmd_extra_pages})) want_r <= 1;
        
        
        if (rst)                                 page_cntr <= 0;
        if (rst)                                 page_cntr <= 0;
        else if (frame_start)                    page_cntr <= cmd_wrmem?0:4;
        else if (frame_start)                    page_cntr <= cmd_wrmem?0:4; // What about last pages (like if only 1 page is needed)? Early frame end?
        else if ( xfer_start_r[0] && !next_page) page_cntr <= page_cntr + 1;     
        else if ( xfer_start_r[0] && !next_page) page_cntr <= page_cntr - 1;     
        else if (!xfer_start_r[0] &&  next_page) page_cntr <= page_cntr - 1;
        else if (!xfer_start_r[0] &&  next_page) page_cntr <= page_cntr + 1;
        
        
/*
/*
        if (rst)                         xfer_page_r <= 0;
        if (rst)                         xfer_page_r <= 0;
@@ -298,15 +313,20 @@ module mcntrl_linear_rw #(
               
               
        if      (rst)                         last_block <= 0;
        if      (rst)                         last_block <= 0;
        else if (chn_rst || !busy_r)          last_block <= 0;
        else if (chn_rst || !busy_r)          last_block <= 0;
        else if (last_row_w && last_in_row_w) last_block <= 1;
//        else if (last_row_w && last_in_row_w) last_block <= 1;
        else if (xfer_start_r[0])             last_block <= last_row_w && last_in_row_w;
        
        
        if      (rst)                            pending_xfers <= 0;
        if      (rst)                            pending_xfers <= 0;
        else if (chn_rst || !busy_r)             pending_xfers <= 0;
        else if (chn_rst || !busy_r)             pending_xfers <= 0;
        else if ( xfer_start_r[0] && !xfer_done) pending_xfers <= pending_xfers + 1;     
        else if ( xfer_start_r[0] && !xfer_done) pending_xfers <= pending_xfers + 1;     
        else if (!xfer_start_r[0] &&  xfer_done) pending_xfers <= pending_xfers - 1;
        else if (!xfer_start_r[0] &&  xfer_done) pending_xfers <= pending_xfers - 1;
        
        
        if (rst)          frame_done_r <= 0;
        
        else              frame_done_r <= busy_r && last_block && xfer_done && (pending_xfers==0);
//        else              frame_done_r <= busy_r && no_more_needed && xfer_done && (pending_xfers==0);
        
//       if (rst)                          no_more_needed <= 0;
//       else if (chn_rst || !busy_r)      no_more_needed <= 0;
//       else if (xfer_start_r[0])         no_more_needed <= last_block;
        
        
        //line_unfinished_r cmd_wrmem
        //line_unfinished_r cmd_wrmem
        if (rst)                         line_unfinished_r[0] <= 0; //{FRAME_HEIGHT_BITS{1'b0}};
        if (rst)                         line_unfinished_r[0] <= 0; //{FRAME_HEIGHT_BITS{1'b0}};
+1 −0
Original line number Original line Diff line number Diff line
@@ -24,6 +24,7 @@
module  mcntrl_tiled_rw#(
module  mcntrl_tiled_rw#(
   parameter ADDRESS_NUMBER=                   15,
   parameter ADDRESS_NUMBER=                   15,
    parameter COLADDR_NUMBER=                   10,
    parameter COLADDR_NUMBER=                   10,
    parameter NUM_XFER_BITS=                     6,    // number of bits to specify transfer length
    parameter FRAME_WIDTH_BITS=                 13,    // Maximal frame width - 8-word (16 bytes) bursts 
    parameter FRAME_WIDTH_BITS=                 13,    // Maximal frame width - 8-word (16 bytes) bursts 
    parameter FRAME_HEIGHT_BITS=                16,    // Maximal frame height 
    parameter FRAME_HEIGHT_BITS=                16,    // Maximal frame height 
    parameter MAX_TILE_WIDTH=                   6,     // number of bits to specify maximal tile (width-1) (6 -> 64)
    parameter MAX_TILE_WIDTH=                   6,     // number of bits to specify maximal tile (width-1) (6 -> 64)
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