Commit 5450474d authored by Andrey Filippov's avatar Andrey Filippov

debugging hardware

parent 393faaf1
...@@ -62,77 +62,77 @@ ...@@ -62,77 +62,77 @@
<link> <link>
<name>vivado_logs/VivadoBitstream.log</name> <name>vivado_logs/VivadoBitstream.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoBitstream-20140607175804607.log</location> <location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoBitstream-20140610171311514.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOpt.log</name> <name>vivado_logs/VivadoOpt.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOpt-20140607175804607.log</location> <location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOpt-20140610171311514.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPhys.log</name> <name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPhys-20140607175804607.log</location> <location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPhys-20140610171311514.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoOptPower.log</name> <name>vivado_logs/VivadoOptPower.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPower-20140607175804607.log</location> <location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPower-20140610171311514.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoPlace.log</name> <name>vivado_logs/VivadoPlace.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoPlace-20140607175804607.log</location> <location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoPlace-20140610171311514.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoRoute.log</name> <name>vivado_logs/VivadoRoute.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoRoute-20140607175804607.log</location> <location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoRoute-20140610171311514.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoSynthesis.log</name> <name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140607173533434.log</location> <location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140610171153284.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name> <name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
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<link> <link>
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<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140607173533434.log</location> <location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140610171311514.log</location>
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<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportImplemented-20140607175804607.log</location> <location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportImplemented-20140610171311514.log</location>
</link> </link>
<link> <link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name> <name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140607173533434.log</location> <location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140610171311514.log</location>
</link> </link>
<link> <link>
<name>vivado_state/eddr3-opt-phys.dcp</name> <name>vivado_state/eddr3-opt-phys.dcp</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-opt-phys-20140607175804607.dcp</location> <location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-opt-phys-20140610171311514.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/eddr3-place.dcp</name> <name>vivado_state/eddr3-place.dcp</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-place-20140607175804607.dcp</location> <location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-place-20140610171311514.dcp</location>
</link> </link>
<link> <link>
<name>vivado_state/eddr3-route.dcp</name> <name>vivado_state/eddr3-route.dcp</name>
<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-route-20140607175804607.dcp</location> <location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-route-20140610171311514.dcp</location>
</link> </link>
<link> <link>
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<type>1</type> <type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-synth-20140607173533434.dcp</location> <location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-synth-20140610113942407.dcp</location>
</link> </link>
</linkedResources> </linkedResources>
</projectDescription> </projectDescription>
...@@ -232,7 +232,6 @@ fifo_same_clock #( .DATA_WIDTH(ADDRESS_BITS+20),.DATA_DEPTH(4)) ...@@ -232,7 +232,6 @@ fifo_same_clock #( .DATA_WIDTH(ADDRESS_BITS+20),.DATA_DEPTH(4))
.data_in({arid[11:0], arburst[1:0],arsize[1:0],arlen[3:0],araddr[ADDRESS_BITS+1:2]}), .data_in({arid[11:0], arburst[1:0],arsize[1:0],arlen[3:0],araddr[ADDRESS_BITS+1:2]}),
.data_out({arid_out[11:0], arburst_out[1:0],arsize_out[1:0],arlen_out[3:0],araddr_out[ADDRESS_BITS-1:0]}), //SuppressThisWarning ISExst Assignment to arsize ignored, since the identifier is never used .data_out({arid_out[11:0], arburst_out[1:0],arsize_out[1:0],arlen_out[3:0],araddr_out[ADDRESS_BITS-1:0]}), //SuppressThisWarning ISExst Assignment to arsize ignored, since the identifier is never used
.nempty(ar_nempty), .nempty(ar_nempty),
.full(),
.half_full(ar_half_full) .half_full(ar_half_full)
); );
endmodule endmodule
...@@ -19,6 +19,7 @@ ...@@ -19,6 +19,7 @@
* You should have received a copy of the GNU General Public License * You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> . * along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/ *******************************************************************************/
`define DEBUG_FIFO 1
module axibram_write #( module axibram_write #(
parameter ADDRESS_BITS = 10 // number of memory address bits parameter ADDRESS_BITS = 10 // number of memory address bits
)( )(
...@@ -61,6 +62,33 @@ module axibram_write #( ...@@ -61,6 +62,33 @@ module axibram_write #(
output bram_wen, // external memory wreite enable, (internally combined with registered dev_ready output bram_wen, // external memory wreite enable, (internally combined with registered dev_ready
output [3:0] bram_wstb, output [3:0] bram_wstb,
output [31:0] bram_wdata output [31:0] bram_wdata
`ifdef DEBUG_FIFO
,
output waddr_under,
output wdata_under,
output wresp_under,
output waddr_over,
output wdata_over,
output wresp_over,
output [3:0] waddr_wcount,
output [3:0] waddr_rcount,
output [3:0] waddr_num_in_fifo,
output [3:0] wdata_wcount,
output [3:0] wdata_rcount,
output [3:0] wdata_num_in_fifo,
output [3:0] wresp_wcount,
output [3:0] wresp_rcount,
output [3:0] wresp_num_in_fifo,
output [3:0] wleft,
output [3:0] wlength,
output reg [3:0] wlen_in_dbg
`endif
); );
// wire rst=~aresetn; // wire rst=~aresetn;
// **** Write channel: **** // **** Write channel: ****
...@@ -84,7 +112,7 @@ module axibram_write #( ...@@ -84,7 +112,7 @@ module axibram_write #(
wire [11:0] wid_out; wire [11:0] wid_out;
reg write_in_progress=0; reg write_in_progress=0;
reg [ADDRESS_BITS-1:0] write_address; // transfer address (not including lower bits reg [ADDRESS_BITS-1:0] write_address; // transfer address (not including lower bits
reg [ 3:0] write_left; // number of read transfers reg [ 3:0] write_left; // number of write transfers
// will ignore arsize - assuming always 32 bits (a*size[2:0]==2) // will ignore arsize - assuming always 32 bits (a*size[2:0]==2)
reg [ 1:0] wburst; // registered burst type reg [ 1:0] wburst; // registered burst type
reg [ 3:0] wlen; // registered awlen type (for wrapped over transfers) reg [ 3:0] wlen; // registered awlen type (for wrapped over transfers)
...@@ -105,12 +133,9 @@ module axibram_write #( ...@@ -105,12 +133,9 @@ module axibram_write #(
(wburst[0]? (write_address[ADDRESS_BITS-1:0]+1):(write_address[ADDRESS_BITS-1:0])); (wburst[0]? (write_address[ADDRESS_BITS-1:0]+1):(write_address[ADDRESS_BITS-1:0]));
assign bram_we_w= w_nempty_ready && write_in_progress; assign bram_we_w= w_nempty_ready && write_in_progress;
// assign bram_we_nonmasked= w_nempty && write_in_progress;
// assign start_write_burst_w=aw_nempty && (!write_in_progress || (w_nempty && (write_left[3:0]==4'b0)));
// assign start_write_burst_w=aw_nempty_ready && (!write_in_progress || (w_nempty_ready && (write_left[3:0]==4'b0)));
assign start_write_burst_w=w_nempty_ready && aw_nempty_ready && (!write_in_progress || (w_nempty_ready && (write_left[3:0]==4'b0))); assign start_write_burst_w=w_nempty_ready && aw_nempty_ready && (!write_in_progress || (w_nempty_ready && (write_left[3:0]==4'b0)));
// assign write_in_progress_w=aw_nempty || (write_in_progress && !(w_nempty && (write_left[3:0]==4'b0))); // assign write_in_progress_w= aw_nempty_ready || (write_in_progress && !(w_nempty_ready && (write_left[3:0]==4'b0)));
assign write_in_progress_w=aw_nempty_ready || (write_in_progress && !(w_nempty_ready && (write_left[3:0]==4'b0))); assign write_in_progress_w=w_nempty_ready && aw_nempty_ready || (write_in_progress && !(w_nempty_ready && (write_left[3:0]==4'b0)));
always @ (posedge aclk or posedge rst) begin always @ (posedge aclk or posedge rst) begin
if (rst) wburst[1:0] <= 0; if (rst) wburst[1:0] <= 0;
...@@ -161,17 +186,31 @@ module axibram_write #( ...@@ -161,17 +186,31 @@ module axibram_write #(
assign bram_wstb = wstb_out[3:0]; assign bram_wstb = wstb_out[3:0];
assign bram_wdata = wdata_out[31:0]; assign bram_wdata = wdata_out[31:0];
fifo_same_clock #( .DATA_WIDTH(20+ADDRESS_BITS),.DATA_DEPTH(4)) `ifdef DEBUG_FIFO
assign wleft=write_left;
assign wlength[3:0]=wlen[3:0];
always @ (posedge aclk) begin
wlen_in_dbg <= awlen[3:0];
end
`endif
fifo_same_clock #( .DATA_WIDTH(20+ADDRESS_BITS),.DATA_DEPTH(4))
waddr_i ( waddr_i (
.rst(rst), .rst (rst),
.clk(aclk), .clk (aclk),
.we(awvalid && awready), .we (awvalid && awready),
.re(start_write_burst_w), .re (start_write_burst_w),
.data_in({awid[11:0], awburst[1:0],awsize[1:0],awlen[3:0],awaddr[ADDRESS_BITS+1:2]}), .data_in ({awid[11:0], awburst[1:0],awsize[1:0],awlen[3:0],awaddr[ADDRESS_BITS+1:2]}),
.data_out({awid_out[11:0], awburst_out[1:0],awsize_out[1:0],awlen_out[3:0],awaddr_out[ADDRESS_BITS-1:0]}), //SuppressThisWarning ISExst Assignment to awsize_out ignored, since the identifier is never used .data_out ({awid_out[11:0], awburst_out[1:0],awsize_out[1:0],awlen_out[3:0],awaddr_out[ADDRESS_BITS-1:0]}), //SuppressThisWarning ISExst Assignment to awsize_out ignored, since the identifier is never used
.nempty(aw_nempty), .nempty (aw_nempty),
.full(), .half_full (aw_half_full)
.half_full(aw_half_full) `ifdef DEBUG_FIFO
,
.under (waddr_under), // output reg
.over (waddr_over), // output reg
.wcount (waddr_wcount), // output[3:0] reg
.rcount (waddr_rcount), // output[3:0] reg
.num_in_fifo(waddr_num_in_fifo) // output[3:0]
`endif
); );
fifo_same_clock #( .DATA_WIDTH(49),.DATA_DEPTH(4)) fifo_same_clock #( .DATA_WIDTH(49),.DATA_DEPTH(4))
wdata_i ( wdata_i (
...@@ -182,20 +221,45 @@ fifo_same_clock #( .DATA_WIDTH(49),.DATA_DEPTH(4)) ...@@ -182,20 +221,45 @@ fifo_same_clock #( .DATA_WIDTH(49),.DATA_DEPTH(4))
.data_in({wid[11:0],wlast,wstb[3:0],wdata[31:0]}), .data_in({wid[11:0],wlast,wstb[3:0],wdata[31:0]}),
.data_out({wid_out[11:0],wlast_out,wstb_out[3:0],wdata_out[31:0]}), //SuppressThisWarning ISExst Assignment to wlast ignored, since the identifier is never used .data_out({wid_out[11:0],wlast_out,wstb_out[3:0],wdata_out[31:0]}), //SuppressThisWarning ISExst Assignment to wlast ignored, since the identifier is never used
.nempty(w_nempty), .nempty(w_nempty),
.full(),
.half_full(w_half_full) .half_full(w_half_full)
`ifdef DEBUG_FIFO
,
.under (wdata_under), // output reg
.over (wdata_over), // output reg
.wcount (wdata_wcount), // output[3:0] reg
.rcount (wdata_rcount), // output[3:0] reg
.num_in_fifo(wdata_num_in_fifo) // output[3:0]
`endif
); );
//debugging - slow down bresp
reg was_bresp_re=0;
wire bresp_re;
assign bresp_re=bready && bvalid && !was_bresp_re;
always @ (posedge rst or posedge aclk) begin
if (rst) was_bresp_re<=0;
else was_bresp_re <= bresp_re;
end
fifo_same_clock #( .DATA_WIDTH(14),.DATA_DEPTH(4)) fifo_same_clock #( .DATA_WIDTH(14),.DATA_DEPTH(4))
wresp_i ( wresp_i (
.rst(rst), .rst(rst),
.clk(aclk), .clk(aclk),
.we(bram_we_w), .we(bram_we_w),
.re(bready && bvalid), // .re(bready && bvalid),
.re(bresp_re), // not allowing RE next cycle after bvalid
.data_in({wid_out[11:0],bresp_in[1:0]}), .data_in({wid_out[11:0],bresp_in[1:0]}),
.data_out({bid[11:0],bresp[1:0]}), .data_out({bid[11:0],bresp[1:0]}),
.nempty(bvalid), .nempty(bvalid),
.full(),
.half_full() .half_full()
`ifdef DEBUG_FIFO
,
.under (wresp_under), // output reg
.over (wresp_over), // output reg
.wcount (wresp_wcount), // output[3:0] reg
.rcount (wresp_rcount), // output[3:0] reg
.num_in_fifo(wresp_num_in_fifo) // output[3:0]
`endif
); );
endmodule endmodule
...@@ -20,6 +20,7 @@ ...@@ -20,6 +20,7 @@
*******************************************************************************/ *******************************************************************************/
`timescale 1ns/1ps `timescale 1ns/1ps
`define use200Mhz 1 `define use200Mhz 1
`define DEBUG_FIFO 1
module ddrc_test01 #( module ddrc_test01 #(
parameter PHASE_WIDTH = 8, parameter PHASE_WIDTH = 8,
parameter SLEW_DQ = "SLOW", parameter SLEW_DQ = "SLOW",
...@@ -136,6 +137,7 @@ module ddrc_test01 #( ...@@ -136,6 +137,7 @@ module ddrc_test01 #(
// AXI write interface signals // AXI write interface signals
//(* keep = "true" *) //(* keep = "true" *)
wire axi_aclk; // clock - should be buffered wire axi_aclk; // clock - should be buffered
// wire axi_naclk; // debugging
// wire axi_aresetn; // reset, active low // wire axi_aresetn; // reset, active low
//(* dont_touch = "true" *) //(* dont_touch = "true" *)
wire axi_rst; // reset, active high wire axi_rst; // reset, active high
...@@ -312,8 +314,12 @@ module ddrc_test01 #( ...@@ -312,8 +314,12 @@ module ddrc_test01 #(
else axi_rst_pre <= 1'b0; else axi_rst_pre <= 1'b0;
end end
BUFG bufg_axi_rst_i (.O(axi_rst),.I(axi_rst_pre)); BUFG bufg_axi_rst_i (.O(axi_rst),.I(axi_rst_pre));
BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0])); BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
//BUFG bufg_axi_naclk_i (.O(axi_naclk),.I(~fclk[0]));
always @ (posedge axi_aclk) begin always @ (posedge axi_aclk) begin
port0_rd_match_r <= port0_rd_match; // rd address matched in previous cycle port0_rd_match_r <= port0_rd_match; // rd address matched in previous cycle
...@@ -326,6 +332,37 @@ always @ (posedge axi_rst or posedge axi_aclk) begin ...@@ -326,6 +332,37 @@ always @ (posedge axi_rst or posedge axi_aclk) begin
else if (axird_start_burst) select_status <= (((axird_pre_araddr^ STATUS_ADDR) & STATUS_ADDR_MASK)==0); else if (axird_start_burst) select_status <= (((axird_pre_araddr^ STATUS_ADDR) & STATUS_ADDR_MASK)==0);
end end
`ifdef DEBUG_FIFO
wire waddr_under, wdata_under, wresp_under;
wire waddr_over, wdata_over, wresp_over;
reg waddr_under_r, wdata_under_r, wresp_under_r;
reg waddr_over_r, wdata_over_r, wresp_over_r;
wire fifo_rst= frst[2];
wire [3:0] waddr_wcount;
wire [3:0] waddr_rcount;
wire [3:0] waddr_num_in_fifo;
wire [3:0] wdata_wcount;
wire [3:0] wdata_rcount;
wire [3:0] wdata_num_in_fifo;
wire [3:0] wresp_wcount;
wire [3:0] wresp_rcount;
wire [3:0] wresp_num_in_fifo;
wire [3:0] wleft;
wire [3:0] wlength; // output[3:0]
wire [3:0] wlen_in_dbg; // output[3:0] reg
always @(posedge fifo_rst or posedge axi_aclk) begin
if (fifo_rst) {waddr_under_r, wdata_under_r, wresp_under_r,waddr_over_r, wdata_over_r, wresp_over_r} <= 0;
else {waddr_under_r, wdata_under_r, wresp_under_r, waddr_over_r, wdata_over_r, wresp_over_r} <=
{waddr_under_r, wdata_under_r, wresp_under_r, waddr_over_r, wdata_over_r, wresp_over_r} |
{waddr_under, wdata_under, wresp_under, waddr_over, wdata_over, wresp_over};
end
`endif
/* /*
dly_addr[1], dly_addr[1],
...@@ -341,6 +378,7 @@ end ...@@ -341,6 +378,7 @@ end
//MEMCLK //MEMCLK
wire [63:0] gpio_in; wire [63:0] gpio_in;
assign gpio_in={ assign gpio_in={
frst[3]?{
16'b0, 16'b0,
1'b1, // 1 1'b1, // 1
MEMCLK, // 1/0? - external clock MEMCLK, // 1/0? - external clock
...@@ -360,13 +398,11 @@ assign gpio_in={ ...@@ -360,13 +398,11 @@ assign gpio_in={
// dly_addr[0], 0 // dly_addr[0], 0
// clkin_stopped_mmcm, 0 // clkin_stopped_mmcm, 0
// clkfb_stopped_mmcm, 0 // clkfb_stopped_mmcm, 0
tmp_debug[3:0], // 4'b1100 -> 4'bxx00
tmp_debug[3:0], // 4'b1100 -> 4'bxx00
// ddr_rst, 1 1 4000609c -> 0 , 40006098 -> 1 // ddr_rst, 1 1 4000609c -> 0 , 40006098 -> 1
// rst_in, 0 0 // rst_in, 0 0
// dci_rst, 0 1 // dci_rst, 0 1
// dly_rst 0 1 // dly_rst 0 1
phy_locked_mmcm, // 1 1 phy_locked_mmcm, // 1 1
phy_locked_pll, // 1 1 phy_locked_pll, // 1 1
phy_dci_ready, // 1 0 phy_dci_ready, // 1 0
...@@ -375,20 +411,47 @@ assign gpio_in={ ...@@ -375,20 +411,47 @@ assign gpio_in={
locked_mmcm, // 1 1 locked_mmcm, // 1 1
locked_pll, // 1 1 locked_pll, // 1 1
dci_ready, // 1 0 dci_ready, // 1 0
dly_ready, // 1 0 dly_ready // 1 0
}:{
waddr_wcount[3:0],
waddr_rcount[3:0],
waddr_num_in_fifo[3:0],
wdata_wcount[3:0],
wdata_rcount[3:0],
wdata_num_in_fifo[3:0],
wresp_wcount[3:0],
wresp_rcount[3:0],
wresp_num_in_fifo[3:0],
wleft[3:0],
wlength[3:0],
wlen_in_dbg[3:0]
},
//ps_out[7:4], // 4'b0 input[7:0] 4'b0
ps_out[7:4], // 4'b0 input[7:0] 4'b0 //ps_out[3:0], // 4'b0 input[7:0] 4'b0
1'b0,
waddr_under_r,
wdata_under_r,
wresp_under_r,
ps_out[3:0], // 4'b0 input[7:0] 4'b0 1'b0,
waddr_over_r,
wdata_over_r,
wresp_over_r, // ???
run_busy, // input // 0 run_busy, // input // 0
locked, // input // 1 locked, // input // 1
ps_rdy, // input // 1 ps_rdy, // input // 1
axi_arready, // 1 axi_arready, // 1
axi_awready, // 1 axi_awready, // 1
axi_wready, // 1 axi_wready, // 1 - sometimes gets stuck with 0 (axi_awready==1) ? TODO: Add timeout
fclk[0], // 0/1 fifo_rst, // fclk[0], // 0/1
axi_rst_pre //axi_rst // 0 axi_rst_pre //axi_rst // 0
}; };
...@@ -423,7 +486,29 @@ assign DUMMY_TO_KEEP = 1'b0; // dbg_toggle[0]; ...@@ -423,7 +486,29 @@ assign DUMMY_TO_KEEP = 1'b0; // dbg_toggle[0];
.bram_waddr (axiwr_bram_waddr[AXI_WR_ADDR_BITS-1:0]), // output[9:0] .bram_waddr (axiwr_bram_waddr[AXI_WR_ADDR_BITS-1:0]), // output[9:0]
.bram_wen (axiwr_bram_wen), // output .bram_wen (axiwr_bram_wen), // output
.bram_wstb (axiwr_bram_wstb[3:0]), // output[3:0] //SuppressThisWarning ISExst Assignment to axiwr_bram_wstb ignored, since the identifier is never used .bram_wstb (axiwr_bram_wstb[3:0]), // output[3:0] //SuppressThisWarning ISExst Assignment to axiwr_bram_wstb ignored, since the identifier is never used
.bram_wdata (axiwr_bram_wdata[31:0]) // output[31:0] .bram_wdata (axiwr_bram_wdata[31:0]) // output[31:0]
`ifdef DEBUG_FIFO
,
.waddr_under (waddr_under), // output
.wdata_under (wdata_under), // output
.wresp_under (wresp_under), // output
.waddr_over (waddr_over), // output
.wdata_over (wdata_over), // output
.wresp_over (wresp_over), // output
.waddr_wcount(waddr_wcount), // output[3:0]
.waddr_rcount(waddr_rcount), // output[3:0]
.waddr_num_in_fifo(waddr_num_in_fifo), // output[3:0]
.wdata_wcount(wdata_wcount), // output[3:0]
.wdata_rcount(wdata_rcount), // output[3:0]
.wdata_num_in_fifo(wdata_num_in_fifo), // output[3:0]
.wresp_wcount(wresp_wcount), // output[3:0]
.wresp_rcount(wresp_rcount), // output[3:0]
.wresp_num_in_fifo(wresp_num_in_fifo), // output[3:0]
.wleft (wleft[3:0]),
.wlength (wlength[3:0]), // output[3:0]
.wlen_in_dbg (wlen_in_dbg[3:0]) // output[3:0] reg
`endif
); );
/* Instance template for module axibram_read */ /* Instance template for module axibram_read */
...@@ -976,8 +1061,10 @@ run_busy ...@@ -976,8 +1061,10 @@ run_busy
.FPGAIDLEN(1'b1), //Idle PL AXI interfaces (active low), input .FPGAIDLEN(1'b1), //Idle PL AXI interfaces (active low), input
// AXI PS Master GP0 // AXI PS Master GP0
// AXI PS Master GP0: Clock, Reset // AXI PS Master GP0: Clock, Reset
// .MAXIGP0ACLK(axi_aclk), // AXI PS Master GP0 Clock , input .MAXIGP0ACLK(axi_aclk), // AXI PS Master GP0 Clock , input
.MAXIGP0ACLK(fclk[0]), // AXI PS Master GP0 Clock , input // .MAXIGP0ACLK(fclk[0]), // AXI PS Master GP0 Clock , input
// .MAXIGP0ACLK(~fclk[0]), // AXI PS Master GP0 Clock , input
// .MAXIGP0ACLK(axi_naclk), // AXI PS Master GP0 Clock , input
// //
.MAXIGP0ARESETN(), // AXI PS Master GP0 Reset, output .MAXIGP0ARESETN(), // AXI PS Master GP0 Reset, output
// AXI PS Master GP0: Read Address // AXI PS Master GP0: Read Address
......
[*] [*]
[*] GTKWave Analyzer v3.3.49 (w)1999-2013 BSI [*] GTKWave Analyzer v3.3.49 (w)1999-2013 BSI
[*] Sat Jun 7 21:41:06 2014 [*] Tue Jun 10 23:54:44 2014
[*] [*]
[dumpfile] "/data/vdt/vdt-projects/eddr3/simulation/ddrc_test01_testbench-latest.lxt" [dumpfile] "/data/vdt/vdt-projects/eddr3/simulation/ddrc_test01_testbench-20140610170704485.lxt"
[dumpfile_mtime] "Thu Jun 5 05:22:25 2014" [dumpfile_mtime] "Tue Jun 10 23:11:05 2014"
[dumpfile_size] 80462049 [dumpfile_size] 75451369
[savefile] "/data/vdt/vdt-projects/eddr3/ddrc_test01_testbench.sav" [savefile] "/data/vdt/vdt-projects/eddr3/ddrc_test01_testbench.sav"
[timestart] 99857000 [timestart] 137157300
[size] 1920 1180 [size] 1920 1180
[pos] -1921 -1 [pos] -1 -1
*-19.410349 101060000 114486875 114489375 114571875 114574375 115289323 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 *-15.445735 137359375 134765625 134912600 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] ddrc_test01_testbench. [treeopen] ddrc_test01_testbench.
[treeopen] ddrc_test01_testbench.ddrc_test01_i. [treeopen] ddrc_test01_testbench.ddrc_test01_i.
[treeopen] ddrc_test01_testbench.ddrc_test01_i.axibram_read_i. [treeopen] ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.
...@@ -33,11 +33,12 @@ ...@@ -33,11 +33,12 @@
[treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i. [treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.
[treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1. [treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.
[treeopen] ddrc_test01_testbench.simul_axi_master_rdaddr_i. [treeopen] ddrc_test01_testbench.simul_axi_master_rdaddr_i.
[treeopen] ddrc_test01_testbench.simul_axi_master_wdata_i.
[treeopen] ddrc_test01_testbench.simul_axi_master_wraddr_i. [treeopen] ddrc_test01_testbench.simul_axi_master_wraddr_i.
[sst_width] 219 [sst_width] 219
[signals_width] 367 [signals_width] 367
[sst_expanded] 1 [sst_expanded] 1
[sst_vpaned_height] 740 [sst_vpaned_height] 820
@c00200 @c00200
-PS7_AXI -PS7_AXI
@22 @22
...@@ -844,8 +845,6 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.set[0] ...@@ -844,8 +845,6 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.set[0]
@22 @22
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.tin_dq[7:0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.tin_dq[7:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.tin_dqs[7:0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.tin_dqs[7:0]
@28
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.dbg_reg1[0]
@200 @200
- -
@1401200 @1401200
...@@ -1098,7 +1097,7 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.wdata_fifo_out_r[31:0] ...@@ -1098,7 +1097,7 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.wdata_fifo_out_r[31:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.wr_en[0] ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.wr_en[0]
@1401200 @1401200
-ddrc_control_i -ddrc_control_i
@800200 @c00200
-ddrc_status -ddrc_status
@28 @28
ddrc_test01_testbench.ddrc_test01_i.ddrc_status_i.busy[0] ddrc_test01_testbench.ddrc_test01_i.ddrc_status_i.busy[0]
...@@ -1122,7 +1121,7 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_status_i.ps_rdy[0] ...@@ -1122,7 +1121,7 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_status_i.ps_rdy[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_status_i.rdata[31:0] ddrc_test01_testbench.ddrc_test01_i.ddrc_status_i.rdata[31:0]
@28 @28
ddrc_test01_testbench.ddrc_test01_i.ddrc_status_i.run_busy[0] ddrc_test01_testbench.ddrc_test01_i.ddrc_status_i.run_busy[0]
@1000200 @1401200
-ddrc_status -ddrc_status
@c00200 @c00200
-ddr_refresh -ddr_refresh
...@@ -1528,8 +1527,9 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.sequence_done[0] ...@@ -1528,8 +1527,9 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.sequence_done[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.set[0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.set[0]
@1401200 @1401200
-ddrc_sequencer -ddrc_sequencer
@c00200 @800200
-ddr_sequencer_i_selected -ddr_sequencer_i_selected
@c00200
-tristate_control -tristate_control
@28 @28
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.SDODT[0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.SDODT[0]
...@@ -1631,6 +1631,7 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.buf_wdata_negedge[63:0] ...@@ -1631,6 +1631,7 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.buf_wdata_negedge[63:0]
@28 @28
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.buf_wr[0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.buf_wr[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.buf_wr_negedge[0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.buf_wr_negedge[0]
@29
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.mclk[0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.mclk[0]
@22 @22
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.cmd0_addr[9:0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.cmd0_addr[9:0]
...@@ -1706,7 +1707,7 @@ ddrc_test01_testbench.ddrc_test01_i.en_port0_rd[0] ...@@ -1706,7 +1707,7 @@ ddrc_test01_testbench.ddrc_test01_i.en_port0_rd[0]
ddrc_test01_testbench.ddrc_test01_i.en_port0_regen[0] ddrc_test01_testbench.ddrc_test01_i.en_port0_regen[0]
@200 @200
- -
@1401200 @1000200
-ddr_sequencer_i_selected -ddr_sequencer_i_selected
@c00200 @c00200
-ddrc_test01 -ddrc_test01
...@@ -1846,6 +1847,42 @@ ddrc_test01_testbench.ddrc_test01_i.status_rdata[31:0] ...@@ -1846,6 +1847,42 @@ ddrc_test01_testbench.ddrc_test01_i.status_rdata[31:0]
@c00200 @c00200
-axibram_write_i -axibram_write_i
@28 @28
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.write_in_progress_w[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.write_in_progress[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.w_nempty[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.w_nempty_ready[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.bram_we_w[0]
@22
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.bram_waddr[12:0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.bram_wdata[31:0]
@200
-simul_wdata
@28
ddrc_test01_testbench.simul_axi_master_wdata_i.set_cmd[0]
ddrc_test01_testbench.simul_axi_master_wdata_i.wvalid[0]
@200
-simul_waddr
@28
ddrc_test01_testbench.simul_axi_master_wraddr_i.set_cmd[0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.awvalid[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.start_write_burst_w[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.awvalid[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wvalid[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.aw_nempty[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.aw_nempty_ready[0]
@22
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.awlen[3:0]
@28
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.w_nempty[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.w_nempty_ready[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.start_write_burst_w[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.bram_we_w[0]
@22
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.write_left[3:0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_num_in_fifo[3:0]
@200
-
@28
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.aclk[0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.aclk[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.aw_half_full[0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.aw_half_full[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.aw_nempty[0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.aw_nempty[0]
...@@ -1882,6 +1919,7 @@ ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.bram_wstb[3:0] ...@@ -1882,6 +1919,7 @@ ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.bram_wstb[3:0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.bready[0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.bready[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.bresp[1:0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.bresp[1:0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.bresp_in[1:0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.bresp_in[1:0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.bresp_re[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.bvalid[0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.bvalid[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.dev_ready[0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.dev_ready[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.dev_ready_r[0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.dev_ready_r[0]
...@@ -1895,6 +1933,9 @@ ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wburst[1:0] ...@@ -1895,6 +1933,9 @@ ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wburst[1:0]
@22 @22
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata[31:0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata[31:0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_out[31:0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_out[31:0]
@28
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.was_bresp_re[0]
@22
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wid[11:0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wid[11:0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wid_out[11:0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wid_out[11:0]
@28 @28
...@@ -1912,25 +1953,27 @@ ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wstb[3:0] ...@@ -1912,25 +1953,27 @@ ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wstb[3:0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wstb_out[3:0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wstb_out[3:0]
@28 @28
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wvalid[0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wvalid[0]
@c00200 @800200
-axibram_write_waddr -axibram_write_waddr
@28 @28
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.awvalid[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.awready[0]
@22
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.awaddr[31:0]
@200
-
@28
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.clk[0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.clk[0]
@22 @22
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.data_in[32:0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.data_in[32:0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.data_out[32:0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.data_out[32:0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.fill[4:0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.fill[3:0]
@28 @28
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.full[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.half_full[0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.half_full[0]
@22 @22
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.inreg[32:0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.inreg[32:0]
@28 @28
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.just_one[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.nempty[0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.nempty[0]
@22
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.next_fill[4:0]
@28
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.out_full[0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.out_full[0]
@22 @22
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.outreg[32:0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.outreg[32:0]
...@@ -1944,27 +1987,21 @@ ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.wa[3:0] ...@@ -1944,27 +1987,21 @@ ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.wa[3:0]
@28 @28
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.we[0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.we[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.wem[0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.wem[0]
@1401200 @1000200
-axibram_write_waddr -axibram_write_waddr
@c00200 @800200
-axibram_write_wdata -axibram_write_wdata
@28 @28
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.clk[0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.clk[0]
@22 @22
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.data_in[48:0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.data_in[48:0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.data_out[48:0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.data_out[48:0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.fill[4:0]
@28 @28
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.full[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.half_full[0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.half_full[0]
@22 @22
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.inreg[48:0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.inreg[48:0]
@28 @28
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.just_one[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.nempty[0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.nempty[0]
@22
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.next_fill[4:0]
@28
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.out_full[0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.out_full[0]
@22 @22
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.outreg[48:0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.outreg[48:0]
...@@ -1978,8 +2015,9 @@ ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.wa[3:0] ...@@ -1978,8 +2015,9 @@ ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.wa[3:0]
@28 @28
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.we[0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.we[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.wem[0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.wem[0]
@1401200 @1000200
-axibram_write_wdata -axibram_write_wdata
@1401200
-axibram_write_i -axibram_write_i
@c00200 @c00200
-wresp_i -wresp_i
...@@ -1991,12 +2029,8 @@ ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wresp_i.wem[0] ...@@ -1991,12 +2029,8 @@ ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wresp_i.wem[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wresp_i.wa[3:0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wresp_i.wa[3:0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wresp_i.data_in[13:0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wresp_i.data_in[13:0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wresp_i.inreg[13:0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wresp_i.inreg[13:0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wresp_i.fill[4:0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wresp_i.next_fill[4:0]
@28 @28
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wresp_i.full[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wresp_i.half_full[0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wresp_i.half_full[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wresp_i.just_one[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wresp_i.nempty[0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wresp_i.nempty[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wresp_i.re[0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wresp_i.re[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wresp_i.rem[0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wresp_i.rem[0]
...@@ -2013,16 +2047,8 @@ ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wresp_i.rst[0] ...@@ -2013,16 +2047,8 @@ ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wresp_i.rst[0]
-waddr_i -waddr_i
@28 @28
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.clk[0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.clk[0]
@22
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.fill[4:0]
@28
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.full[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.half_full[0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.half_full[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.just_one[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.nempty[0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.nempty[0]
@22
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.next_fill[4:0]
@28
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.out_full[0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.out_full[0]
@22 @22
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.ra[3:0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.ra[3:0]
...@@ -2044,18 +2070,12 @@ ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.clk[0] ...@@ -2044,18 +2070,12 @@ ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.clk[0]
@22 @22
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.data_in[48:0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.data_in[48:0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.data_out[48:0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.data_out[48:0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.fill[4:0]
@28 @28
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.full[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.half_full[0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.half_full[0]
@22 @22
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.inreg[48:0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.inreg[48:0]
@28 @28
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.just_one[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.nempty[0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.nempty[0]
@22
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.next_fill[4:0]
@28
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.out_full[0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.out_full[0]
@22 @22
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.outreg[48:0] ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.outreg[48:0]
...@@ -2592,7 +2612,7 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_la ...@@ -2592,7 +2612,7 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_la
-byte_lane0_selected -byte_lane0_selected
@200 @200
- -
@800200 @c00200
-cmd_addr_i -cmd_addr_i
@28 @28
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.cmd_addr_i.clk[0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.cmd_addr_i.clk[0]
...@@ -2607,7 +2627,6 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.cmd_add ...@@ -2607,7 +2627,6 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.cmd_add
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.cmd_addr_i.ddr3_ras[0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.cmd_addr_i.ddr3_ras[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.cmd_addr_i.ddr3_we[0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.cmd_addr_i.ddr3_we[0]
@22 @22
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.cmd_addr_i.decode_addr[14:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.cmd_addr_i.decode_sel[7:0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.cmd_addr_i.decode_sel[7:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.cmd_addr_i.dly_addr[4:0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.cmd_addr_i.dly_addr[4:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.cmd_addr_i.dly_data[7:0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.cmd_addr_i.dly_data[7:0]
...@@ -2650,9 +2669,9 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.cmd_add ...@@ -2650,9 +2669,9 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.cmd_add
(14)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.cmd_addr_i.ld_dly_addr[14:0] (14)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.cmd_addr_i.ld_dly_addr[14:0]
@1001200 @1001200
-group_end -group_end
@800023 @800022
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.cmd_addr_i.ld_dly_cmd[7:0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.cmd_addr_i.ld_dly_cmd[7:0]
@29 @28
(0)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.cmd_addr_i.ld_dly_cmd[7:0] (0)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.cmd_addr_i.ld_dly_cmd[7:0]
(1)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.cmd_addr_i.ld_dly_cmd[7:0] (1)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.cmd_addr_i.ld_dly_cmd[7:0]
(2)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.cmd_addr_i.ld_dly_cmd[7:0] (2)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.cmd_addr_i.ld_dly_cmd[7:0]
...@@ -2661,13 +2680,13 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.cmd_add ...@@ -2661,13 +2680,13 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.cmd_add
(5)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.cmd_addr_i.ld_dly_cmd[7:0] (5)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.cmd_addr_i.ld_dly_cmd[7:0]
(6)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.cmd_addr_i.ld_dly_cmd[7:0] (6)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.cmd_addr_i.ld_dly_cmd[7:0]
(7)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.cmd_addr_i.ld_dly_cmd[7:0] (7)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.cmd_addr_i.ld_dly_cmd[7:0]
@1001201 @1001200
-group_end -group_end
@28 @28
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.cmd_addr_i.rst[0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.cmd_addr_i.rst[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.cmd_addr_i.set[0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.cmd_addr_i.set[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.cmd_addr_i.set_r[0] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.cmd_addr_i.set_r[0]
@1000200 @1401200
-cmd_addr_i -cmd_addr_i
@c00200 @c00200
-dq1_idelay2 -dq1_idelay2
......
...@@ -103,9 +103,9 @@ module ddrc_test01_testbench #( ...@@ -103,9 +103,9 @@ module ddrc_test01_testbench #(
parameter REFRESH_ADDR_REL_MASK = 'h3ff, // address mask set refresh sequencer address parameter REFRESH_ADDR_REL_MASK = 'h3ff, // address mask set refresh sequencer address
// simulation-specific parameters // simulation-specific parameters
parameter integer AXI_RDADDR_LATENCY=2, parameter integer AXI_RDADDR_LATENCY= 2, // 2, //2, //2,
parameter integer AXI_WRADDR_LATENCY=4, parameter integer AXI_WRADDR_LATENCY= 1, // 1, //2, //4,
parameter integer AXI_WRDATA_LATENCY=1, parameter integer AXI_WRDATA_LATENCY= 2, // 1, //1, //1
parameter integer AXI_TASK_HOLD=1.0, parameter integer AXI_TASK_HOLD=1.0,
parameter integer ADDRESS_NUMBER=15 parameter integer ADDRESS_NUMBER=15
)(); )();
...@@ -172,6 +172,14 @@ module ddrc_test01_testbench #( ...@@ -172,6 +172,14 @@ module ddrc_test01_testbench #(
localparam DLY_LANE1_ODELAY= 80'h4c4c4b4a494844434241; // odelay dqm, odelay ddqs, odelay dq[7:0] localparam DLY_LANE1_ODELAY= 80'h4c4c4b4a494844434241; // odelay dqm, odelay ddqs, odelay dq[7:0]
localparam DLY_LANE1_IDELAY= 72'ha0636261605c5b5a59; // idelay dqs, idelay dq[7:0 localparam DLY_LANE1_IDELAY= 72'ha0636261605c5b5a59; // idelay dqs, idelay dq[7:0
localparam DLY_CMDA= 256'h3c3c3c3c3b3a39383434343433323130002c2c2c2b2a29282424242423222120; // odelay odt, cke, cas, ras, we, ba2,ba1,ba0, X, a14,..,a0 localparam DLY_CMDA= 256'h3c3c3c3c3b3a39383434343433323130002c2c2c2b2a29282424242423222120; // odelay odt, cke, cas, ras, we, ba2,ba1,ba0, X, a14,..,a0
// alternative to set same type delays to the same value
localparam DLY_DQ_IDELAY = 'h60;
localparam DLY_DQ_ODELAY = 'h48;
localparam DLY_DQS_IDELAY = 'ha0;
localparam DLY_DQS_ODELAY = 'h4c; // b0 for WLV
localparam DLY_DM_ODELAY = 'h48;
localparam DLY_CMDA_ODELAY ='h30;
`else `else
localparam DLY_LANE0_DQS_WLV_IDELAY = 8'he8; // idelay dqs localparam DLY_LANE0_DQS_WLV_IDELAY = 8'he8; // idelay dqs
localparam DLY_LANE1_DQS_WLV_IDELAY = 8'he8; // idelay dqs localparam DLY_LANE1_DQS_WLV_IDELAY = 8'he8; // idelay dqs
...@@ -180,6 +188,15 @@ module ddrc_test01_testbench #( ...@@ -180,6 +188,15 @@ module ddrc_test01_testbench #(
localparam DLY_LANE1_ODELAY= 80'h7474737271706c6b6a69; // odelay dqm, odelay ddqs, odelay dq[7:0] localparam DLY_LANE1_ODELAY= 80'h7474737271706c6b6a69; // odelay dqm, odelay ddqs, odelay dq[7:0]
localparam DLY_LANE1_IDELAY= 72'hd8737271706c6b6a69; // idelay dqs, idelay dq[7:0 localparam DLY_LANE1_IDELAY= 72'hd8737271706c6b6a69; // idelay dqs, idelay dq[7:0
localparam DLY_CMDA= 256'h5c5c5c5c5b5a59585454545453525150004c4c4c4b4a49484444444443424140; // odelay odt, cke, cas, ras, we, ba2,ba1,ba0, X, a14,..,a0 localparam DLY_CMDA= 256'h5c5c5c5c5b5a59585454545453525150004c4c4c4b4a49484444444443424140; // odelay odt, cke, cas, ras, we, ba2,ba1,ba0, X, a14,..,a0
// alternative to set same type delays to the same value
localparam DLY_DQ_IDELAY = 'h70;
localparam DLY_DQ_ODELAY = 'h68;
localparam DLY_DQS_IDELAY = 'hd8;
localparam DLY_DQS_ODELAY = 'h74; // b0 for WLV
localparam DLY_DM_ODELAY = 'h74;
localparam DLY_CMDA_ODELAY ='h50;
`endif `endif
localparam DLY_PHASE= 8'h1c; // mmcm fine phase shift, 1/4 tCK localparam DLY_PHASE= 8'h1c; // mmcm fine phase shift, 1/4 tCK
...@@ -365,40 +382,52 @@ always #(CLKIN_PERIOD/2) CLK <= ~CLK; ...@@ -365,40 +382,52 @@ always #(CLKIN_PERIOD/2) CLK <= ~CLK;
#99000; // same as glbl #99000; // same as glbl
repeat (20) @(posedge CLK) ; repeat (20) @(posedge CLK) ;
RST <=1'b0; RST <=1'b0;
//set simulation-only parameters
axi_set_b_lag(0); //(1); axi_set_b_lag(0); //(1);
axi_set_rd_lag(0); axi_set_rd_lag(0);
// set real hardware parameters
// set delays (same for the same group),patterns, sequences, write buffer
// use axi_set_delays task to set individual delays from tables
set_up;
/*
// set dq /dqs tristate on/off patterns
axi_set_tristate_patterns;
// set patterns for DM (always 0) and DQS - always the same (may try different for write lev.)
axi_set_dqs_dqm_patterns;
// prepare all sequences
set_all_sequences;
// prepare write buffer
write_block_buf; // fill block memory
// set all delays
axi_set_delays; axi_set_delays;
*/
read_status; // ps ready goes false with some delay read_status; // ps ready goes false with some delay
wait_phase_shifter_ready; wait_phase_shifter_ready;
// enable output for address/commands to DDR chip
enable_cmda(1); enable_cmda(1);
repeat (16) @(posedge CLK) ; repeat (16) @(posedge CLK) ;
// remove reset from DDR chip
activate_sdrst(0); // was enabled at system reset activate_sdrst(0); // was enabled at system reset
set_refresh(
50, // input [ 9:0] t_rfc; // =50 for tCK=2.5ns
16); //input [ 7:0] t_refi; // 48/97 for normal, 8 - for simulation
#5000; // actually 500 usec required #5000; // actually 500 usec required
repeat (16) @(posedge CLK) ; repeat (16) @(posedge CLK) ;
enable_cke(1); enable_cke(1);
repeat (16) @(posedge CLK) ; repeat (16) @(posedge CLK) ;
set_mrs(1);
run_sequence(0,INITIALIZE_OFFSET); run_mrs;
repeat (4) @(posedge CLK) ;
// wait_sequencer_ready(16);
repeat (4) @(posedge CLK) ;
// enable refresh // enable refresh
enable_refresh(1); enable_refresh(1);
set_write_lev(16); // write leveling, 16 times (full buffer - 128)
// set dq /dqs tristate on/off patterns
axi_write_single(BASEADDR_PATTERNS_TRI, {16'h0, DQSTRI_LAST, DQSTRI_FIRST, DQTRI_LAST, DQTRI_FIRST});
#100; #100;
// $finish; // $finish;
run_sequence(0,INITIALIZE_OFFSET); // run_sequence(0,INITIALIZE_OFFSET); // Why was it for the second time?
wait_sequencer_ready(16); // wait_sequencer_ready(16);
axi_write_single(BASEADDR_PATTERNS, 32'h0055); // set patterns for DM (always 0) and DQS - always the same (may try different for write lev.)
// Set special values for DQS idelay for write leveling // Set special values for DQS idelay for write leveling
axi_set_dqs_idelay_wlv; axi_set_dqs_idelay_wlv;
...@@ -406,10 +435,10 @@ always #(CLKIN_PERIOD/2) CLK <= ~CLK; ...@@ -406,10 +435,10 @@ always #(CLKIN_PERIOD/2) CLK <= ~CLK;
axi_write_single(BASEADDR_WBUF_DELAY, {28'h0, WBUF_DLY_WLV}); axi_write_single(BASEADDR_WBUF_DELAY, {28'h0, WBUF_DLY_WLV});
//axi_set_dqs_idelay_nominal; //axi_set_dqs_idelay_nominal;
run_sequence(0,WRITELEV_OFFSET); run_write_lev;
// trying multiple run_sequence // trying multiple run_sequence
run_sequence(0,WRITELEV_OFFSET); run_write_lev;
run_sequence(0,WRITELEV_OFFSET); run_write_lev;
wait_sequencer_ready(16); wait_sequencer_ready(16);
wait_sequencer_ready(16); wait_sequencer_ready(16);
...@@ -421,8 +450,7 @@ always #(CLKIN_PERIOD/2) CLK <= ~CLK; ...@@ -421,8 +450,7 @@ always #(CLKIN_PERIOD/2) CLK <= ~CLK;
axi_set_dly_single(0,8,'h80); // was 'h74 dqs lane 0, odelay axi_set_dly_single(0,8,'h80); // was 'h74 dqs lane 0, odelay
axi_set_dly_single(2,8,'hc0); // was 'h74 dqs lane 1, odelay axi_set_dly_single(2,8,'hc0); // was 'h74 dqs lane 1, odelay
`endif `endif
run_write_lev;
run_sequence(0,WRITELEV_OFFSET);
`ifdef use200Mhz `ifdef use200Mhz
#120; // 140 ns delay 30; // 30 ns delay #120; // 140 ns delay 30; // 30 ns delay
axi_set_dly_single(2,8,'h78); // was 'h74 dqs lane 1, odelay axi_set_dly_single(2,8,'h78); // was 'h74 dqs lane 1, odelay
...@@ -450,8 +478,8 @@ always #(CLKIN_PERIOD/2) CLK <= ~CLK; ...@@ -450,8 +478,8 @@ always #(CLKIN_PERIOD/2) CLK <= ~CLK;
axi_write_single(BASEADDR_WBUF_DELAY, {28'h0, WBUF_DLY_DFLT}); axi_write_single(BASEADDR_WBUF_DELAY, {28'h0, WBUF_DLY_DFLT});
// test reading pattern // test reading pattern
set_read_pattern(8); // 8x2*64 bits, 32x32 bits to read // set_read_pattern(8); // 8x2*64 bits, 32x32 bits to read
run_sequence(0,READ_PATTERN_OFFSET); run_read_pattern;
// TODO: add timing variation during read // TODO: add timing variation during read
wait_sequencer_ready(16); wait_sequencer_ready(16);
...@@ -468,23 +496,26 @@ always #(CLKIN_PERIOD/2) CLK <= ~CLK; ...@@ -468,23 +496,26 @@ always #(CLKIN_PERIOD/2) CLK <= ~CLK;
// test write block; // test write block;
/*
write_block_buf; // fill block memory write_block_buf; // fill block memory
set_write_block( set_write_block(
3'h5, // bank 3'h5, // bank
15'h1234, // row address 15'h1234, // row address
10'h100 // column address 10'h100 // column address
); );
run_sequence(1,WRITE_BLOCK_OFFSET); */
run_write_block;
wait_sequencer_ready(16); wait_sequencer_ready(16);
// test read block; // test read block;
/*
set_read_block( set_read_block(
3'h5, // bank 3'h5, // bank
15'h1234, // row address 15'h1234, // row address
10'h100 // column address 10'h100 // column address
); );
*/
run_sequence(0,READ_BLOCK_OFFSET); run_read_block;
// read block over AXI // read block over AXI
wait_sequencer_ready(16); wait_sequencer_ready(16);
...@@ -1003,6 +1034,43 @@ simul_axi_read simul_axi_read_i( ...@@ -1003,6 +1034,43 @@ simul_axi_read simul_axi_read_i(
// $display("run_sequence(%x,%x) 2 @ %t",channel,start_addr,$time); // $display("run_sequence(%x,%x) 2 @ %t",channel,start_addr,$time);
end end
endtask endtask
task run_mrs;
begin
$display("RUN MRS @ %t",$time);
run_sequence(0,INITIALIZE_OFFSET);
end
endtask
task run_write_lev;
begin
$display("RUN WRITE LEVELING @ %t",$time);
run_sequence(0,WRITELEV_OFFSET);
end
endtask
task run_read_pattern;
begin
$display("RUN READ PATTERN @ %t",$time);
run_sequence(0,READ_PATTERN_OFFSET);
end
endtask
task run_write_block;
begin
$display("RUN WRITE BLOCK @ %t",$time);
run_sequence(1,WRITE_BLOCK_OFFSET);
end
endtask
task run_read_block;
begin
$display("RUN WRITE BLOCK @ %t",$time);
run_sequence(0,READ_BLOCK_OFFSET);
end
endtask
task enable_cmda; task enable_cmda;
input en; input en;
begin begin
...@@ -1296,7 +1364,7 @@ simul_axi_read simul_axi_read_i( ...@@ -1296,7 +1364,7 @@ simul_axi_read simul_axi_read_i(
// Turn off DCI // Turn off DCI
data <= encode_seq_word( data <= encode_seq_word(
15'h0, // [14:0] phy_addr_in; 15'h0, // [14:0] phy_addr_in;
mr3_norm[17:15], // [ 2:0] phy_bank_in; //TODO: debug! 3'h0, //mr3_norm[17:15], // [ 2:0] phy_bank_in; //TODO: debug!
3'b000, // [ 2:0] phy_rcw_in; // {ras,cas,we}, positive 3'b000, // [ 2:0] phy_rcw_in; // {ras,cas,we}, positive
1'b0, // phy_odt_in; // may be optimized? 1'b0, // phy_odt_in; // may be optimized?
1'b0, // phy_cke_inv; // may be optimized? 1'b0, // phy_cke_inv; // may be optimized?
...@@ -1964,8 +2032,12 @@ simul_axi_read simul_axi_read_i( ...@@ -1964,8 +2032,12 @@ simul_axi_read simul_axi_read_i(
mr3 <= ddr3_mr3 ( mr3 <= ddr3_mr3 (
1'h0, // mpr; // MPR mode: 0 - normal, 1 - dataflow from MPR 1'h0, // mpr; // MPR mode: 0 - normal, 1 - dataflow from MPR
2'h0); // [1:0] mpr_rf; // MPR read function: 2'b00: predefined pattern 0101... 2'h0); // [1:0] mpr_rf; // MPR read function: 2'b00: predefined pattern 0101...
cmd_addr <= BASEADDR_CMD0; cmd_addr <= BASEADDR_CMD0 + (INITIALIZE_OFFSET << 2);
@(posedge CLK) @(posedge CLK)
$display("mr0=0x%x",mr0);
$display("mr1=0x%x",mr1);
$display("mr2=0x%x",mr2);
$display("mr3=0x%x",mr3);
data <= encode_seq_word( data <= encode_seq_word(
mr2[14:0], // [14:0] phy_addr_in; mr2[14:0], // [14:0] phy_addr_in;
mr2[17:15], // [ 2:0] phy_bank_in; //TODO: debug! mr2[17:15], // [ 2:0] phy_bank_in; //TODO: debug!
...@@ -2310,6 +2382,24 @@ simul_axi_read simul_axi_read_i( ...@@ -2310,6 +2382,24 @@ simul_axi_read simul_axi_read_i(
reg [7:0] target_phase=0; reg [7:0] target_phase=0;
// initialize delays // initialize delays
// set dq /dqs tristate on/off patterns
task axi_set_tristate_patterns;
begin
$display("SET TRISTATE PATTERNS @ %t",$time);
axi_write_single(BASEADDR_PATTERNS_TRI, {16'h0, DQSTRI_LAST, DQSTRI_FIRST, DQTRI_LAST, DQTRI_FIRST});
end
endtask
task axi_set_dqs_dqm_patterns;
begin
$display("SET DQS+DQM PATTERNS @ %t",$time);
// set patterns for DM (always 0) and DQS - always the same (may try different for write lev.)
axi_write_single(BASEADDR_PATTERNS, 32'h0055);
end
endtask
// use to set all different delays from tables, use axi_set_same_delays for same delays
task axi_set_delays; task axi_set_delays;
integer i; integer i;
begin begin
...@@ -2377,12 +2467,116 @@ simul_axi_read simul_axi_read_i( ...@@ -2377,12 +2467,116 @@ simul_axi_read simul_axi_read_i(
end end
endtask endtask
task axi_set_dq_idelay;
input [7:0] delay;
integer i, dly;
begin
dly=delay;
$display("SET DQ IDELAY=0x%x @ %t",delay,$time);
for (i=0;i<8;i=i+1) begin
axi_write_single(BASEADDRESS_LANE0_IDELAY + (i<<2), dly & 32'hff);
end
for (i=0;i<8;i=i+1) begin
axi_write_single(BASEADDRESS_LANE1_IDELAY + (i<<2), dly & 32'hff);
end
axi_write_single(BASEADDR_DLY_SET, 0); // set all delays
end
endtask
task axi_set_dq_odelay;
input [7:0] delay;
integer i, dly;
begin
dly=delay;
$display("SET DQ ODELAY=0x%x @ %t",delay,$time);
for (i=0;i<8;i=i+1) begin
axi_write_single(BASEADDRESS_LANE0_ODELAY + (i<<2), dly & 32'hff);
end
for (i=0;i<8;i=i+1) begin
axi_write_single(BASEADDRESS_LANE1_ODELAY + (i<<2), dly & 32'hff);
end
axi_write_single(BASEADDR_DLY_SET, 0); // set all delays
end
endtask
task axi_set_dqs_idelay;
input [7:0] delay;
integer i, dly;
begin
dly=delay;
i=8;
$display("SET DQS IDELAY=0x%x @ %t",delay,$time);
axi_write_single(BASEADDRESS_LANE0_IDELAY + (i<<2), dly & 32'hff);
axi_write_single(BASEADDRESS_LANE1_IDELAY + (i<<2), dly & 32'hff);
axi_write_single(BASEADDR_DLY_SET, 0); // set all delays
end
endtask
task axi_set_dqs_odelay;
input [7:0] delay;
integer i, dly;
begin
dly=delay;
i=8;
$display("SET DQS ODELAY=0x%x @ %t",delay,$time);
axi_write_single(BASEADDRESS_LANE0_ODELAY + (i<<2), dly & 32'hff);
axi_write_single(BASEADDRESS_LANE1_ODELAY + (i<<2), dly & 32'hff);
axi_write_single(BASEADDR_DLY_SET, 0); // set all delays
end
endtask
task axi_set_dm_odelay;
input [7:0] delay;
integer i, dly;
begin
dly=delay;
i=9;
$display("SET DQM IDELAY=0x%x @ %t",delay,$time);
axi_write_single(BASEADDRESS_LANE0_ODELAY + (i<<2), dly & 32'hff);
axi_write_single(BASEADDRESS_LANE1_ODELAY + (i<<2), dly & 32'hff);
axi_write_single(BASEADDR_DLY_SET, 0); // set all delays
end
endtask
task axi_set_cmda_odelay;
input [7:0] delay;
integer i, dly;
begin
dly=delay;
$display("SET COMMAND and ADDRESS ODELAY=0x%x @ %t",delay,$time);
for (i=0;i<32;i=i+1) begin
axi_write_single(BASEADDRESS_CMDA + (i<<2), dly & 32'hff);
end
axi_write_single(BASEADDR_DLY_SET, 0); // set all delays
end
endtask
task axi_set_same_delays;
input [7:0] dq_idelay;
input [7:0] dq_odelay;
input [7:0] dqs_idelay;
input [7:0] dqs_odelay;
input [7:0] dm_odelay;
input [7:0] cmda_odelay;
begin
$display("SET DELAYS(0x%x,0x%x,0x%x,0x%x,0x%x,0x%x) @ %t",
dq_idelay,dq_odelay,dqs_idelay,dqs_odelay,dm_odelay,cmda_odelay,$time);
axi_set_dq_idelay(dq_idelay);
axi_set_dq_odelay(dq_odelay);
axi_set_dqs_idelay(dqs_idelay);
axi_set_dqs_odelay(dqs_odelay);
axi_set_dm_odelay(dm_odelay);
axi_set_cmda_odelay(cmda_odelay);
end
endtask
task axi_set_phase; task axi_set_phase;
input [PHASE_WIDTH-1:0] phase; input [PHASE_WIDTH-1:0] phase;
begin begin
$display("SET CLOCK PHASE to 0x%x @ %t",phase,$time);
axi_write_single(BASEADDRESS_PHASE, {{(32-PHASE_WIDTH){1'b0}},phase}); axi_write_single(BASEADDRESS_PHASE, {{(32-PHASE_WIDTH){1'b0}},phase});
axi_write_single(BASEADDR_DLY_SET, 0); // set all delays
target_phase <= phase; target_phase <= phase;
end end
endtask endtask
...@@ -2600,5 +2794,61 @@ simul_axi_read simul_axi_read_i( ...@@ -2600,5 +2794,61 @@ simul_axi_read simul_axi_read_i(
end end
endtask endtask
task set_all_sequences;
begin
$display("SET MRS @ %t",$time);
set_mrs(1);
$display("SET REFRESH @ %t",$time);
set_refresh(
50, // input [ 9:0] t_rfc; // =50 for tCK=2.5ns
16); //input [ 7:0] t_refi; // 48/97 for normal, 8 - for simulation
$display("SET WRITE LEVELING @ %t",$time);
set_write_lev(16); // write leveling, 16 times (full buffer - 128)
$display("SET READ PATTERN @ %t",$time);
set_read_pattern(8); // 8x2*64 bits, 32x32 bits to read
$display("SET WRITE BLOCK @ %t",$time);
set_write_block(
3'h5, // bank
15'h1234, // row address
10'h100 // column address
);
$display("SET READ BLOCK @ %t",$time);
set_read_block(
3'h5, // bank
15'h1234, // row address
10'h100 // column address
);
end
endtask
/*
task set_same_delays;
input [7:0] dq_idelay;
input [7:0] dq_odelay;
input [7:0] dqs_idelay;
input [7:0] dqs_odelay;
input [7:0] dm_odelay;
input [7:0] cmda_odelay;
*/
task set_up;
begin
// set dq /dqs tristate on/off patterns
axi_set_tristate_patterns;
// set patterns for DM (always 0) and DQS - always the same (may try different for write lev.)
axi_set_dqs_dqm_patterns;
// prepare all sequences
set_all_sequences;
// prepare write buffer
write_block_buf; // fill block memory
// set all delays
//#axi_set_delays - from tables, per-pin
axi_set_same_delays(DLY_DQ_IDELAY,DLY_DQ_ODELAY,DLY_DQS_IDELAY,DLY_DQS_ODELAY,DLY_DM_ODELAY,DLY_CMDA_ODELAY);
// set clock phase relative to DDR clk
axi_set_phase(DLY_PHASE);
end
endtask
endmodule endmodule
#!/usr/bin/env python #!/usr/bin/env python
# -*- coding: utf-8 -*- # -*- coding: utf-8 -*-
from __future__ import print_function
# Copyright (C) 2013, Elphel.inc. # Copyright (C) 2013, Elphel.inc.
# Export range of GPIO (EMIO)registers # Export range of GPIO (EMIO)registers
# This program is free software: you can redistribute it and/or modify # This program is free software: you can redistribute it and/or modify
...@@ -23,7 +24,6 @@ __maintainer__ = "Andrey Filippov" ...@@ -23,7 +24,6 @@ __maintainer__ = "Andrey Filippov"
__email__ = "andrey@elphel.com" __email__ = "andrey@elphel.com"
__status__ = "Development" __status__ = "Development"
from __future__ import print_function
import sys import sys
if len(sys.argv) < 3 or (sys.argv[1] != "in" and sys.argv[1] != "out") : if len(sys.argv) < 3 or (sys.argv[1] != "in" and sys.argv[1] != "out") :
print ("Usage: ", sys.argv[0]+" <in|out> <gpio_number>[<gpio_max_number>]") print ("Usage: ", sys.argv[0]+" <in|out> <gpio_number>[<gpio_max_number>]")
......
#!/usr/bin/env python #!/usr/bin/env python
# -*- coding: utf-8 -*- # -*- coding: utf-8 -*-
from __future__ import print_function
# Copyright (C) 2013, Elphel.inc. # Copyright (C) 2013, Elphel.inc.
# Monitor a range of GPIO bits (should be exported first) # Monitor a range of GPIO bits (should be exported first)
# This program is free software: you can redistribute it and/or modify # This program is free software: you can redistribute it and/or modify
...@@ -22,7 +23,6 @@ __version__ = "3.0+" ...@@ -22,7 +23,6 @@ __version__ = "3.0+"
__maintainer__ = "Andrey Filippov" __maintainer__ = "Andrey Filippov"
__email__ = "andrey@elphel.com" __email__ = "andrey@elphel.com"
__status__ = "Development" __status__ = "Development"
from __future__ import print_function
import sys import sys
if len(sys.argv) < 2 : if len(sys.argv) < 2 :
print ("Usage: ", sys.argv[0]+" <gpio_number>[<gpio_max_number>]") print ("Usage: ", sys.argv[0]+" <gpio_number>[<gpio_max_number>]")
......
...@@ -19,7 +19,7 @@ ...@@ -19,7 +19,7 @@
* along with this program. If not, see <http://www.gnu.org/licenses/> . * along with this program. If not, see <http://www.gnu.org/licenses/> .
*******************************************************************************/ *******************************************************************************/
`timescale 1ns/1ps `timescale 1ns/1ps
`define DEBUG_FIFO 1
module fifo_same_clock module fifo_same_clock
#( #(
parameter integer DATA_WIDTH=16, parameter integer DATA_WIDTH=16,
...@@ -32,67 +32,80 @@ module fifo_same_clock ...@@ -32,67 +32,80 @@ module fifo_same_clock
input re, // read enable input re, // read enable
input [DATA_WIDTH-1:0] data_in, // input data input [DATA_WIDTH-1:0] data_in, // input data
output [DATA_WIDTH-1:0] data_out, // output data output [DATA_WIDTH-1:0] data_out, // output data
output reg nempty, // FIFO has some data output nempty, // FIFO has some data
output reg full, // FIFO full
output reg half_full // FIFO half full output reg half_full // FIFO half full
`ifdef DEBUG_FIFO
,output reg under, // debug outputs - under - attempt to read from empty
output reg over, // overwritten
output reg [DATA_DEPTH-1:0] wcount,
output reg [DATA_DEPTH-1:0] rcount,
output [DATA_DEPTH-1:0] num_in_fifo
`endif
); );
localparam integer DATA_2DEPTH=(1<<DATA_DEPTH)-1; localparam integer DATA_2DEPTH=(1<<DATA_DEPTH)-1;
//ISExst: FF/Latch ddrc_test01.axibram_write_i.waddr_i.fill[4] has a constant value of 0 in block <ddrc_test01>. This FF/Latch will be trimmed during the optimization process. //ISExst: FF/Latch ddrc_test01.axibram_write_i.waddr_i.fill[4] has a constant value of 0 in block <ddrc_test01>. This FF/Latch will be trimmed during the optimization process.
//ISExst: FF/Latch ddrc_test01.axibram_read_i.raddr_i.fill[4] has a constant value of 0 in block <ddrc_test01>. This FF/Latch will be trimmed during the optimization process. //ISExst: FF/Latch ddrc_test01.axibram_read_i.raddr_i.fill[4] has a constant value of 0 in block <ddrc_test01>. This FF/Latch will be trimmed during the optimization process.
//ISExst: FF/Latch ddrc_test01.axibram_write_i.wdata_i.fill[4] has a constant value of 0 in block <ddrc_test01>. This FF/Latch will be trimmed during the optimization process. //ISExst: FF/Latch ddrc_test01.axibram_write_i.wdata_i.fill[4] has a constant value of 0 in block <ddrc_test01>. This FF/Latch will be trimmed during the optimization process.
// Do not understand - why? // Do not understand - why?
reg [DATA_DEPTH :0] fill=0; reg [DATA_DEPTH-1:0] fill=0; // RAM fill
reg just_one,two_or_less;
reg [DATA_WIDTH-1:0] inreg; reg [DATA_WIDTH-1:0] inreg;
reg [DATA_WIDTH-1:0] outreg; reg [DATA_WIDTH-1:0] outreg;
reg [DATA_DEPTH-1:0] ra; reg [DATA_DEPTH-1:0] ra;
reg [DATA_DEPTH-1:0] wa; reg [DATA_DEPTH-1:0] wa;
wire [DATA_DEPTH :0] next_fill; wire [DATA_DEPTH-1:0] next_fill;
wire outreg_use_inreg;
reg wem; reg wem;
wire rem; wire rem;
reg out_full=0; //output register full reg out_full=0; //output register full
reg [DATA_WIDTH-1:0] ram [0:DATA_2DEPTH]; reg [DATA_WIDTH-1:0] ram [0:DATA_2DEPTH];
// assign next_fill = fill[4:0]+((we && ~re)?1:((~we && re)?5'b11111:5'b00000));
// assign data_out = just_one?inreg:outreg;
assign data_out = out_full?outreg:inreg;
assign rem = (!out_full || re)&& (just_one? wem : re);
assign outreg_use_inreg=(out_full && two_or_less) || just_one;
// assign next_fill = fill[4:0]+((we && ~rem)?1:((~we && rem)?5'b11111:5'b00000));
// TODO: verify rem is not needed instead of re
assign next_fill = fill[DATA_DEPTH:0]+((we && ~re)?1:((~we && re)?-1:0)); //S uppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 5-bit target.
reg ram_nempty;
assign next_fill = fill[DATA_DEPTH-1:0]+((wem && ~rem)?1:((~wem && rem && ram_nempty)?-1:0));
assign rem= ram_nempty && (re || !out_full);
assign data_out=outreg;
assign nempty=out_full;
`ifdef DEBUG_FIFO
assign num_in_fifo=fill[DATA_DEPTH-1:0];
`endif
always @ (posedge clk or posedge rst) begin always @ (posedge clk or posedge rst) begin
if (rst) fill <= 0; if (rst) fill <= 0;
else fill <= next_fill; else fill <= next_fill;
// else if (we && ~re) fill <= fill+1; //S uppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 5-bit target. if (rst) wem <= 0;
// else if (~we && re) fill <= fill-1; //S uppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 5-bit target. else wem <= we;
if (rst) ram_nempty <= 0;
else ram_nempty <= (next_fill != 0);
if (rst) wa <= 0; if (rst) wa <= 0;
else if (wem) wa <= wa+1; //S uppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 4-bit target. else if (wem) wa <= wa+1;
if (rst) ra <= 1; // 0; if (rst) ra <= 0;
else if (re) ra <= ra+1; //now ra is 1 ahead //SuppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 4-bit target. else if (rem) ra <= ra+1;
else if (!nempty) ra <= wa+1; // Just recover from bit errors TODO: fix //SuppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 4-bit target. else if (!ram_nempty) ra <= wa; // Just recover from bit errors
if (rst) nempty <= 0;
else nempty <= (next_fill != 0);
if (rst) out_full <= 0; if (rst) out_full <= 0;
else if (rem && ~re) out_full <= 1; else if (rem && ~re) out_full <= 1;
else if (re && ~rem) out_full <= 0; else if (re && ~rem) out_full <= 0;
`ifdef DEBUG_FIFO
if (rst) wcount <= 0;
else if (we) wcount <= wcount + 1;
if (rst) rcount <= 0;
else if (re) rcount <= rcount + 1;
`endif
end end
// no reset elements
always @ (posedge clk) begin always @ (posedge clk) begin
if (wem) ram[wa] <= inreg;
just_one <= (next_fill == 1);
two_or_less <= (next_fill == 1) | (next_fill == 2);
half_full <=(fill & (1<<(DATA_DEPTH-1)))!=0; half_full <=(fill & (1<<(DATA_DEPTH-1)))!=0;
full <= (fill & (1<< DATA_DEPTH ))!=0; if (wem) ram[wa] <= inreg;
if (we) inreg <= data_in; if (we) inreg <= data_in;
// if (rem) outreg <= just_one?inreg:ram[ra]; if (rem) outreg <= ram[ra];
if (rem) outreg <= outreg_use_inreg ? inreg : ram[ra]; `ifdef DEBUG_FIFO
wem <= we; under <= ~we & re & ~nempty; // underrun error
over <= we & ~re & (fill == (1<< (DATA_DEPTH-1))); // overrun error
`endif
end end
endmodule endmodule
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