.data_out({arid_out[11:0],arburst_out[1:0],arsize_out[1:0],arlen_out[3:0],araddr_out[ADDRESS_BITS-1:0]}),//SuppressThisWarning ISExst Assignment to arsize ignored, since the identifier is never used
.data_out({awid_out[11:0],awburst_out[1:0],awsize_out[1:0],awlen_out[3:0],awaddr_out[ADDRESS_BITS-1:0]}),//SuppressThisWarning ISExst Assignment to awsize_out ignored, since the identifier is never used
.data_out({awid_out[11:0],awburst_out[1:0],awsize_out[1:0],awlen_out[3:0],awaddr_out[ADDRESS_BITS-1:0]}),//SuppressThisWarning ISExst Assignment to awsize_out ignored, since the identifier is never used
.data_out({wid_out[11:0],wlast_out,wstb_out[3:0],wdata_out[31:0]}),//SuppressThisWarning ISExst Assignment to wlast ignored, since the identifier is never used
.nempty(w_nempty),
.full(),
.half_full(w_half_full)
`ifdefDEBUG_FIFO
,
.under(wdata_under),// output reg
.over(wdata_over),// output reg
.wcount(wdata_wcount),// output[3:0] reg
.rcount(wdata_rcount),// output[3:0] reg
.num_in_fifo(wdata_num_in_fifo)// output[3:0]
`endif
);
//debugging - slow down bresp
regwas_bresp_re=0;
wirebresp_re;
assignbresp_re=bready&&bvalid&&!was_bresp_re;
always@(posedgerstorposedgeaclk)begin
if(rst)was_bresp_re<=0;
elsewas_bresp_re<=bresp_re;
end
fifo_same_clock#(.DATA_WIDTH(14),.DATA_DEPTH(4))
wresp_i(
.rst(rst),
.clk(aclk),
.we(bram_we_w),
.re(bready&&bvalid),
// .re(bready && bvalid),
.re(bresp_re),// not allowing RE next cycle after bvalid
