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Commit 5449c194 authored by Andrey Filippov's avatar Andrey Filippov
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added measurement/adjustment of WE, RAS, CAS delays

parent 494d6c95
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Showing with 529 additions and 174 deletions
py393/get_test_dq_dqs_data.py
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...@@ -1400,99 +1400,112 @@ def get_addr_meas(): ...@@ -1400,99 +1400,112 @@ def get_addr_meas():
] ]
def get_addr_odly(): def get_addr_odly():
return { return {
'dlys':[[46, 49, 48, 47, 48, 49, 48, 45, 49, 50, 48, 48, 45, 48, 48, 46, 49, 48], [45, 48, 46, 45, 46, 48, 46, 44, 47, 49, 45, 46, 44, 46, 45, 45, 48, 46], 'dlys': [[46, 49, 48, 47, 48, 49, 48, 45, 49, 50, 48, 48, 45, 48, 48, 46, 49, 48, 50, 49, 49, 48], [45, 48, 46, 45, 46, 48, 45, 44, 47, 49, 45, 46, 44, 46, 45, 45, 48, 46, 49, 48, 48, 46],
[44, 45, 44, 44, 44, 46, 44, 43, 45, 48, 44, 44, 43, 44, 44, 44, 46, 44], [43, 44, 44, 43, 44, 44, 44, 41, 44, 45, 44, 44, 41, 44, 44, 43, 44, 44], [44, 45, 44, 44, 44, 46, 44, 43, 45, 48, 44, 44, 43, 44, 44, 44, 46, 44, 48, 46, 45, 45], [43, 44, 44, 43, 44, 44, 44, 41, 44, 45, 44, 44, 41, 44, 44, 43, 44, 44, 45, 44, 44, 44],
[40, 44, 43, 40, 43, 44, 42, 39, 43, 44, 42, 43, 39, 43, 42, 40, 44, 43], [39, 42, 40, 39, 40, 43, 40, 39, 41, 43, 40, 40, 39, 40, 40, 39, 43, 40], [40, 44, 43, 40, 43, 44, 42, 39, 43, 44, 42, 43, 39, 43, 42, 40, 44, 43, 44, 44, 43, 43], [39, 42, 40, 39, 40, 43, 40, 39, 41, 43, 40, 40, 39, 40, 40, 39, 43, 40, 44, 42, 42, 40],
[39, 40, 39, 39, 39, 40, 39, 38, 39, 42, 39, 39, 38, 39, 39, 39, 40, 39], [37, 39, 38, 37, 38, 39, 38, 35, 39, 40, 38, 38, 35, 38, 38, 37, 39, 38], [39, 40, 39, 39, 39, 40, 39, 38, 39, 42, 39, 39, 38, 39, 39, 39, 40, 39, 42, 40, 40, 39], [37, 39, 38, 37, 38, 39, 38, 35, 39, 40, 38, 38, 35, 38, 38, 37, 39, 38, 40, 39, 39, 38],
[35, 38, 37, 35, 37, 38, 36, 34, 38, 39, 36, 37, 34, 37, 36, 35, 38, 37], [34, 36, 35, 34, 35, 37, 34, 33, 35, 38, 34, 35, 33, 35, 34, 34, 36, 35], [35, 38, 37, 35, 37, 38, 36, 34, 38, 39, 36, 37, 34, 37, 36, 35, 38, 37, 39, 38, 38, 37], [34, 36, 35, 34, 35, 37, 34, 33, 35, 38, 34, 35, 33, 35, 34, 34, 36, 35, 38, 36, 36, 35],
[33, 34, 34, 33, 34, 35, 34, 32, 34, 35, 34, 34, 32, 34, 34, 33, 34, 34], [32, 34, 33, 31, 33, 34, 33, 30, 33, 34, 33, 33, 30, 33, 33, 32, 34, 33], [33, 34, 34, 33, 34, 35, 34, 32, 34, 35, 34, 34, 32, 34, 34, 33, 34, 34, 35, 34, 34, 34], [32, 34, 33, 31, 33, 34, 32, 30, 33, 34, 33, 33, 30, 33, 33, 32, 34, 33, 34, 34, 34, 33],
[30, 33, 31, 29, 30, 33, 30, 29, 31, 33, 30, 30, 29, 31, 30, 30, 33, 31], [29, 30, 29, 29, 29, 31, 29, 28, 29, 32, 29, 29, 28, 29, 29, 29, 30, 29], [30, 32, 31, 29, 30, 33, 30, 29, 31, 33, 30, 30, 29, 31, 30, 30, 33, 31, 33, 33, 33, 31], [29, 30, 29, 29, 29, 31, 29, 28, 29, 32, 29, 29, 28, 29, 29, 29, 30, 29, 32, 30, 30, 29],
[28, 29, 29, 28, 29, 29, 28, 26, 29, 30, 28, 29, 26, 29, 28, 28, 29, 29], [26, 28, 28, 25, 27, 29, 26, 24, 28, 29, 27, 27, 24, 28, 27, 26, 28, 28], [28, 29, 29, 28, 29, 29, 28, 26, 29, 30, 28, 29, 26, 29, 28, 28, 29, 29, 30, 29, 29, 29], [26, 28, 28, 25, 27, 29, 26, 24, 28, 29, 27, 27, 24, 28, 27, 26, 28, 28, 29, 28, 28, 28],
[24, 26, 25, 24, 25, 28, 24, 24, 25, 28, 25, 25, 24, 25, 25, 24, 27, 25], [24, 24, 24, 23, 24, 25, 24, 23, 24, 25, 24, 24, 23, 24, 24, 24, 25, 24], [24, 26, 25, 24, 25, 28, 24, 24, 25, 28, 25, 25, 24, 25, 25, 24, 27, 25, 28, 26, 27, 25], [24, 24, 24, 23, 24, 25, 24, 23, 24, 25, 24, 24, 23, 24, 24, 24, 25, 24, 25, 25, 25, 24],
[23, 24, 23, 22, 23, 24, 23, 20, 23, 24, 23, 23, 20, 23, 23, 23, 24, 23], [20, 23, 22, 20, 21, 23, 20, 19, 22, 23, 20, 21, 19, 22, 20, 20, 23, 22], [23, 24, 23, 22, 23, 24, 23, 20, 23, 24, 23, 23, 20, 23, 23, 23, 24, 23, 24, 24, 24, 23], [20, 23, 22, 20, 21, 23, 20, 19, 22, 23, 20, 21, 19, 22, 20, 20, 23, 22, 23, 23, 23, 21],
[19, 20, 20, 19, 19, 22, 19, 18, 20, 22, 19, 19, 19, 20, 19, 19, 20, 20], [18, 19, 19, 18, 19, 20, 18, 17, 19, 20, 19, 19, 17, 19, 18, 18, 19, 19], [19, 20, 20, 19, 19, 22, 19, 18, 20, 22, 19, 19, 19, 20, 19, 19, 20, 20, 22, 20, 21, 20], [18, 19, 19, 18, 19, 20, 18, 17, 19, 20, 19, 19, 17, 19, 18, 18, 19, 19, 20, 19, 19, 19],
[17, 18, 18, 16, 18, 19, 16, 15, 18, 19, 17, 18, 15, 18, 17, 17, 18, 18], [15, 16, 16, 14, 15, 18, 14, 14, 15, 18, 15, 15, 14, 15, 15, 15, 17, 16], [17, 18, 18, 15, 18, 19, 16, 15, 18, 19, 17, 18, 15, 18, 17, 17, 18, 18, 19, 18, 19, 18], [15, 16, 16, 14, 15, 18, 14, 14, 15, 18, 15, 15, 14, 15, 15, 15, 17, 16, 18, 17, 18, 15],
[14, 14, 14, 14, 14, 16, 14, 13, 14, 15, 14, 14, 13, 14, 14, 14, 15, 14], [13, 14, 14, 12, 13, 15, 13, 11, 13, 14, 13, 13, 11, 14, 13, 13, 14, 14], [14, 14, 14, 14, 14, 16, 14, 13, 14, 15, 14, 14, 13, 14, 14, 14, 15, 14, 15, 15, 15, 14], [13, 14, 14, 12, 13, 15, 13, 11, 13, 14, 13, 13, 11, 14, 13, 13, 14, 14, 14, 14, 14, 13],
[11, 13, 13, 10, 12, 14, 10, 9, 12, 13, 11, 12, 10, 12, 10, 11, 13, 13], [9, 10, 10, 9, 10, 13, 9, 9, 10, 12, 9, 10, 9, 10, 9, 9, 10, 10], [11, 13, 13, 10, 12, 14, 10, 9, 12, 13, 11, 12, 10, 12, 10, 11, 13, 13, 13, 13, 13, 12], [9, 10, 10, 9, 10, 13, 9, 9, 10, 12, 9, 10, 9, 10, 9, 9, 10, 10, 12, 10, 12, 10],
[9, 9, 9, 8, 9, 10, 8, 8, 9, 10, 9, 9, 8, 9, 9, 9, 9, 9], [8, 8, 8, 6, 8, 9, 7, 5, 8, 9, 8, 8, 5, 8, 7, 8, 8, 8], [9, 9, 9, 8, 9, 10, 8, 8, 9, 10, 9, 9, 8, 9, 9, 9, 9, 9, 10, 9, 10, 9], [8, 8, 8, 6, 8, 9, 7, 5, 8, 9, 8, 8, 5, 8, 7, 8, 8, 8, 9, 8, 9, 8],
[5, 7, 7, 5, 6, 9, 5, 4, 5, 8, 5, 5, 4, 6, 5, 5, 7, 7], [4, 5, 5, 4, 4, 7, 4, 3, 4, 5, 4, 4, 4, 4, 4, 4, 5, 5], [5, 7, 7, 5, 5, 9, 5, 4, 5, 8, 5, 5, 4, 6, 5, 5, 7, 7, 8, 7, 8, 6], [4, 5, 5, 4, 4, 7, 4, 3, 4, 5, 4, 4, 4, 4, 4, 4, 5, 5, 5, 5, 5, 4],
[3, 4, 4, 3, 4, 5, 3, 2, 4, 4, 3, 3, 2, 4, 3, 3, 4, 4], [2, 3, 3, 0, 2, 4, 0, 0, 2, 4, 2, 2, 0, 3, 1, 2, 3, 3], [3, 4, 4, 3, 4, 5, 3, 2, 3, 4, 3, 3, 2, 4, 3, 3, 4, 4, 4, 4, 4, 4], [2, 3, 3, 0, 2, 4, 0, 0, 2, 3, 2, 2, 0, 3, 1, 2, 3, 3, 3, 3, 4, 3],
[0, 0, 0, 0, 0, 3, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0], [150, 158, 154, 153, 154, 154, 157, 150, 157, 159, 154, 154, 149, 154, 155, 150, 158, 153], [0, 0, 0, 0, 0, 3, 0, 0, 0, 2, 0, 0, 0, 0, 0, 0, 0, 0, 1, 0, 2, 0], [150, 158, 154, 153, 154, 154, 157, 150, 157, 159, 154, 154, 149, 154, 155, 150, 158, 153, 159, 158, 154, 154],
[149, 156, 152, 152, 153, 152, 155, 149, 155, 159, 153, 154, 149, 153, 154, 149, 156, 152], [148, 154, 150, 150, 152, 150, 154, 148, 154, 157, 151, 153, 147, 151, 153, 148, 154, 150], [149, 156, 152, 152, 153, 152, 155, 149, 155, 159, 153, 154, 148, 153, 154, 149, 156, 152, 159, 156, 153, 154], [148, 154, 150, 150, 152, 150, 154, 148, 154, 157, 151, 153, 147, 151, 153, 148, 154, 150, 159, 154, 151, 152],
[147, 154, 149, 149, 150, 149, 153, 145, 153, 155, 149, 150, 145, 149, 151, 147, 154, 149], [145, 153, 148, 148, 149, 148, 150, 144, 151, 154, 149, 149, 144, 149, 149, 145, 152, 148], [147, 154, 149, 149, 150, 149, 153, 145, 153, 155, 149, 150, 145, 149, 151, 147, 154, 149, 158, 154, 149, 150], [145, 153, 148, 148, 149, 148, 150, 144, 151, 154, 149, 149, 144, 149, 149, 145, 152, 148, 155, 153, 149, 149],
[144, 150, 146, 145, 148, 147, 149, 144, 149, 153, 148, 148, 143, 148, 149, 144, 150, 146], [143, 149, 145, 144, 145, 145, 148, 142, 149, 150, 145, 147, 141, 145, 148, 143, 149, 144], [144, 150, 146, 145, 148, 147, 149, 144, 149, 153, 148, 148, 143, 148, 149, 144, 150, 146, 154, 150, 148, 148], [143, 149, 145, 144, 145, 145, 148, 142, 149, 150, 145, 147, 141, 145, 148, 143, 149, 144, 153, 149, 145, 146],
[141, 148, 144, 144, 144, 144, 147, 140, 148, 149, 144, 145, 140, 144, 145, 141, 148, 144], [139, 146, 143, 142, 144, 143, 145, 139, 145, 149, 143, 144, 139, 143, 144, 139, 146, 143], [141, 148, 144, 144, 144, 144, 147, 140, 148, 149, 144, 145, 140, 144, 145, 141, 148, 144, 151, 148, 144, 144], [139, 146, 143, 142, 144, 143, 145, 139, 145, 149, 143, 144, 139, 143, 144, 139, 146, 143, 149, 146, 143, 144],
[139, 144, 140, 140, 142, 141, 144, 138, 144, 147, 142, 143, 138, 142, 143, 139, 144, 140], [138, 144, 139, 139, 140, 139, 143, 137, 143, 145, 140, 140, 135, 140, 141, 138, 144, 139], [139, 144, 140, 140, 142, 141, 144, 138, 144, 147, 142, 143, 138, 142, 143, 139, 144, 140, 149, 144, 142, 143], [138, 144, 139, 139, 140, 139, 143, 137, 143, 145, 140, 140, 135, 140, 141, 138, 144, 139, 148, 144, 140, 140],
[135, 143, 138, 138, 139, 139, 140, 135, 141, 144, 139, 139, 134, 139, 139, 135, 143, 138], [134, 140, 137, 136, 138, 138, 139, 134, 139, 143, 138, 139, 134, 138, 139, 134, 140, 137], [135, 143, 138, 138, 139, 139, 140, 135, 141, 144, 139, 139, 134, 139, 139, 135, 143, 138, 145, 143, 139, 139], [134, 140, 137, 136, 138, 138, 139, 134, 139, 143, 138, 139, 134, 138, 139, 134, 140, 137, 144, 140, 138, 138],
[133, 139, 135, 134, 136, 135, 138, 133, 139, 141, 135, 137, 132, 135, 138, 133, 139, 135], [132, 138, 134, 134, 134, 134, 137, 130, 138, 139, 134, 135, 130, 134, 135, 132, 138, 134], [133, 139, 135, 134, 136, 135, 138, 133, 139, 140, 135, 137, 132, 135, 138, 133, 139, 135, 143, 139, 136, 137], [132, 138, 134, 134, 134, 134, 137, 130, 138, 139, 134, 135, 130, 134, 135, 132, 138, 134, 141, 138, 134, 135],
[130, 137, 133, 133, 134, 133, 135, 129, 135, 139, 134, 134, 129, 134, 134, 130, 136, 133], [129, 135, 131, 130, 133, 132, 134, 129, 134, 137, 132, 133, 128, 132, 133, 129, 134, 131], [130, 137, 133, 133, 134, 133, 135, 129, 135, 139, 134, 134, 129, 134, 134, 130, 136, 133, 139, 136, 134, 134], [129, 135, 131, 130, 133, 132, 134, 129, 134, 137, 132, 133, 128, 132, 133, 129, 134, 131, 139, 135, 133, 133],
[128, 134, 129, 129, 130, 130, 133, 128, 133, 135, 130, 131, 127, 130, 132, 128, 134, 129], [126, 133, 129, 128, 129, 129, 130, 125, 132, 134, 129, 129, 125, 129, 130, 126, 133, 129], [128, 134, 129, 129, 130, 130, 133, 128, 133, 135, 130, 131, 127, 130, 132, 128, 134, 129, 137, 134, 130, 130], [126, 133, 129, 128, 129, 129, 130, 125, 132, 134, 129, 129, 125, 129, 130, 126, 133, 129, 135, 133, 129, 129],
[125, 130, 128, 127, 128, 128, 129, 124, 130, 133, 128, 129, 124, 128, 129, 124, 130, 128], [124, 129, 125, 125, 127, 126, 129, 123, 129, 131, 126, 128, 123, 126, 128, 124, 129, 125], [125, 130, 128, 127, 128, 128, 129, 124, 130, 133, 128, 129, 124, 128, 129, 124, 130, 128, 134, 130, 128, 129], [124, 129, 125, 125, 127, 126, 129, 123, 129, 131, 126, 128, 123, 126, 128, 124, 129, 125, 133, 129, 127, 127],
[123, 128, 124, 124, 125, 124, 127, 122, 128, 129, 124, 125, 121, 125, 125, 123, 128, 124], [120, 127, 123, 123, 124, 124, 125, 120, 125, 129, 124, 124, 119, 124, 124, 120, 127, 123], [123, 128, 124, 124, 125, 124, 127, 122, 128, 129, 124, 125, 121, 125, 125, 123, 128, 124, 130, 128, 125, 125], [120, 127, 123, 123, 124, 124, 125, 120, 125, 129, 124, 124, 119, 124, 124, 120, 127, 123, 129, 127, 124, 124],
[119, 125, 122, 121, 123, 123, 124, 119, 124, 127, 123, 123, 119, 123, 124, 119, 125, 122], [119, 124, 120, 119, 120, 120, 123, 118, 123, 125, 120, 122, 118, 120, 122, 118, 124, 120], [119, 125, 122, 121, 123, 123, 124, 119, 124, 127, 123, 123, 119, 123, 124, 119, 125, 122, 129, 125, 123, 123], [119, 124, 120, 119, 120, 120, 123, 118, 123, 125, 120, 122, 118, 120, 122, 118, 124, 120, 127, 124, 121, 121],
[117, 123, 119, 119, 119, 119, 121, 116, 122, 124, 119, 120, 115, 119, 120, 117, 123, 119], [115, 120, 118, 118, 119, 118, 119, 114, 120, 123, 118, 119, 114, 118, 119, 115, 120, 118], [117, 123, 119, 119, 119, 119, 121, 115, 122, 124, 119, 120, 115, 119, 120, 117, 123, 119, 125, 123, 119, 119], [115, 120, 118, 118, 119, 118, 119, 114, 120, 123, 118, 119, 114, 118, 119, 115, 120, 118, 124, 120, 119, 119],
[114, 119, 116, 115, 117, 117, 119, 114, 119, 121, 117, 118, 113, 117, 118, 114, 119, 116], [113, 118, 114, 114, 115, 115, 117, 113, 118, 119, 115, 115, 112, 115, 116, 113, 118, 114], [114, 119, 116, 115, 117, 117, 119, 114, 119, 121, 117, 118, 113, 117, 118, 114, 119, 116, 123, 119, 118, 118], [113, 118, 114, 114, 115, 115, 117, 113, 118, 119, 115, 115, 112, 115, 116, 113, 118, 114, 120, 118, 115, 115],
[112, 117, 114, 113, 114, 114, 115, 110, 115, 119, 114, 114, 110, 114, 114, 111, 117, 114], [110, 115, 113, 112, 113, 113, 114, 109, 114, 117, 113, 114, 109, 113, 114, 110, 115, 113], [112, 117, 114, 113, 114, 114, 115, 110, 115, 119, 114, 114, 110, 114, 114, 111, 117, 114, 119, 117, 114, 114], [110, 115, 113, 112, 113, 113, 114, 109, 114, 117, 113, 113, 109, 113, 114, 110, 115, 113, 118, 115, 113, 113],
[109, 114, 110, 110, 111, 111, 113, 108, 114, 115, 111, 112, 108, 111, 113, 109, 114, 110], [108, 113, 109, 109, 109, 109, 111, 107, 112, 114, 109, 110, 106, 109, 110, 108, 113, 109], [109, 114, 110, 110, 111, 111, 113, 108, 114, 115, 111, 112, 108, 111, 113, 109, 114, 110, 117, 114, 112, 112], [108, 113, 109, 109, 109, 109, 111, 107, 112, 114, 109, 110, 106, 109, 110, 108, 113, 109, 115, 113, 110, 110],
[105, 110, 108, 108, 109, 109, 109, 105, 110, 113, 109, 109, 104, 109, 109, 105, 110, 108], [104, 109, 107, 105, 108, 108, 109, 104, 109, 111, 108, 108, 104, 108, 108, 104, 109, 107], [105, 110, 108, 108, 109, 109, 109, 105, 110, 113, 109, 109, 104, 109, 109, 105, 110, 108, 114, 110, 109, 109], [104, 109, 107, 105, 108, 108, 109, 104, 109, 111, 107, 108, 104, 108, 108, 104, 109, 107, 113, 109, 108, 108],
[104, 109, 105, 104, 105, 105, 108, 103, 108, 109, 105, 106, 103, 105, 106, 104, 109, 105], [103, 107, 104, 104, 104, 104, 105, 101, 106, 109, 104, 104, 100, 104, 104, 102, 107, 104], [104, 109, 105, 104, 105, 105, 108, 103, 108, 109, 105, 106, 103, 105, 106, 104, 109, 105, 110, 109, 105, 105], [103, 107, 104, 104, 104, 104, 105, 101, 106, 109, 104, 104, 100, 104, 104, 102, 107, 104, 109, 107, 104, 104],
[100, 105, 103, 102, 103, 103, 104, 99, 104, 108, 103, 104, 99, 103, 104, 100, 105, 103], [99, 104, 101, 100, 102, 102, 103, 99, 104, 105, 101, 103, 98, 102, 103, 99, 104, 100], [100, 105, 103, 102, 103, 103, 104, 99, 104, 108, 103, 104, 99, 103, 104, 100, 105, 103, 108, 105, 104, 104], [99, 104, 101, 100, 102, 102, 103, 99, 104, 105, 101, 103, 98, 102, 103, 99, 104, 100, 107, 104, 103, 102],
[98, 103, 99, 99, 100, 100, 101, 98, 102, 104, 100, 100, 97, 100, 100, 98, 103, 99], [97, 101, 99, 98, 99, 99, 99, 95, 100, 103, 99, 99, 95, 99, 99, 97, 101, 99], [98, 103, 99, 99, 100, 100, 101, 98, 102, 104, 100, 100, 97, 100, 100, 98, 103, 99, 105, 103, 100, 100], [97, 101, 99, 98, 99, 99, 99, 95, 100, 103, 99, 99, 95, 99, 99, 97, 101, 99, 104, 101, 99, 99],
[95, 99, 98, 96, 98, 98, 99, 94, 99, 101, 98, 98, 94, 98, 98, 95, 99, 98], [94, 99, 95, 94, 96, 96, 98, 93, 98, 99, 95, 97, 93, 95, 97, 94, 99, 95], [95, 99, 98, 96, 98, 98, 99, 94, 99, 101, 98, 98, 94, 98, 98, 95, 99, 98, 103, 99, 98, 98], [94, 99, 95, 94, 96, 96, 98, 93, 98, 99, 95, 96, 93, 95, 97, 94, 99, 95, 100, 99, 97, 96],
[93, 97, 94, 94, 94, 95, 95, 92, 96, 99, 94, 95, 91, 94, 95, 93, 98, 94], [91, 95, 93, 93, 94, 94, 94, 90, 94, 98, 93, 94, 89, 94, 94, 90, 95, 93], [93, 97, 94, 94, 94, 95, 95, 92, 96, 99, 94, 95, 91, 94, 95, 93, 97, 94, 99, 97, 95, 94], [91, 95, 93, 93, 94, 94, 94, 90, 94, 98, 93, 94, 89, 94, 94, 90, 95, 93, 98, 95, 94, 94],
[89, 94, 92, 90, 93, 93, 93, 89, 94, 95, 92, 93, 89, 92, 93, 89, 94, 92], [89, 93, 90, 89, 90, 90, 91, 88, 93, 94, 90, 90, 88, 90, 90, 89, 93, 90], [89, 94, 92, 90, 92, 93, 93, 89, 94, 95, 92, 93, 89, 92, 93, 89, 94, 92, 97, 94, 93, 93], [89, 93, 90, 89, 90, 90, 91, 88, 93, 94, 90, 90, 88, 90, 90, 89, 93, 90, 95, 93, 90, 90],
[88, 91, 89, 88, 89, 89, 89, 86, 90, 93, 89, 89, 85, 89, 89, 88, 91, 89], [85, 89, 88, 87, 88, 89, 89, 84, 89, 91, 88, 88, 84, 88, 88, 85, 89, 88], [88, 91, 89, 88, 89, 89, 89, 86, 90, 93, 89, 89, 85, 89, 89, 88, 91, 89, 94, 91, 89, 89], [85, 89, 88, 87, 88, 89, 89, 84, 89, 91, 88, 88, 84, 88, 88, 85, 89, 88, 93, 89, 89, 88],
[84, 89, 85, 85, 86, 87, 88, 84, 88, 89, 86, 87, 84, 86, 87, 84, 89, 85], [83, 88, 84, 84, 85, 85, 85, 83, 86, 89, 84, 85, 82, 85, 85, 83, 88, 84], [84, 89, 85, 85, 86, 87, 88, 84, 88, 89, 86, 87, 84, 86, 87, 84, 89, 85, 90, 89, 87, 87], [83, 88, 84, 84, 85, 85, 85, 83, 86, 89, 84, 85, 82, 85, 85, 83, 88, 84, 89, 88, 85, 85],
[82, 85, 84, 83, 84, 84, 84, 80, 84, 88, 84, 84, 80, 84, 84, 82, 85, 84], [80, 84, 82, 80, 83, 83, 83, 79, 84, 85, 83, 83, 79, 83, 83, 80, 84, 82], [82, 85, 84, 83, 84, 84, 84, 80, 84, 88, 84, 84, 80, 84, 84, 82, 85, 84, 88, 85, 84, 84], [80, 84, 82, 80, 83, 83, 83, 79, 84, 85, 83, 83, 79, 83, 83, 80, 84, 82, 86, 84, 83, 83],
[79, 83, 80, 79, 80, 82, 82, 78, 83, 84, 80, 81, 78, 80, 81, 79, 83, 80], [78, 81, 79, 79, 79, 80, 80, 77, 80, 83, 79, 79, 76, 79, 79, 78, 82, 79], [79, 83, 80, 79, 80, 81, 82, 78, 83, 84, 80, 81, 78, 80, 81, 79, 83, 80, 84, 83, 81, 80], [78, 81, 79, 79, 79, 80, 80, 77, 80, 83, 79, 79, 76, 79, 79, 78, 81, 79, 84, 81, 80, 79],
[76, 79, 78, 77, 78, 79, 79, 75, 79, 81, 78, 79, 75, 78, 79, 76, 80, 78], [74, 79, 77, 75, 77, 78, 78, 74, 78, 79, 77, 78, 74, 77, 77, 74, 79, 76], [76, 79, 78, 77, 78, 79, 79, 75, 79, 81, 78, 79, 75, 78, 79, 76, 80, 78, 83, 80, 79, 79], [74, 79, 76, 75, 77, 78, 78, 74, 78, 79, 77, 77, 74, 77, 77, 74, 79, 76, 80, 79, 78, 77],
[74, 78, 75, 74, 75, 75, 75, 73, 77, 79, 75, 75, 73, 75, 75, 74, 78, 75], [73, 75, 74, 73, 74, 74, 74, 71, 75, 78, 74, 74, 70, 74, 74, 73, 75, 74], [74, 78, 75, 74, 75, 75, 75, 73, 77, 79, 75, 75, 73, 75, 75, 74, 78, 75, 79, 78, 75, 75], [73, 75, 74, 73, 74, 74, 74, 71, 75, 78, 74, 74, 70, 74, 74, 73, 75, 74, 78, 75, 74, 74],
[70, 74, 73, 71, 73, 74, 73, 69, 74, 75, 73, 73, 69, 73, 73, 70, 74, 73], [69, 73, 70, 70, 71, 73, 72, 69, 73, 74, 70, 71, 69, 71, 71, 69, 73, 70], [70, 74, 73, 71, 73, 74, 73, 69, 74, 75, 73, 73, 69, 73, 73, 70, 74, 73, 76, 74, 74, 73], [69, 73, 70, 70, 71, 72, 72, 69, 73, 74, 70, 71, 69, 71, 71, 69, 73, 70, 74, 73, 72, 71],
[68, 72, 69, 69, 69, 70, 70, 68, 70, 73, 69, 69, 67, 69, 69, 68, 72, 69], [67, 70, 69, 68, 69, 69, 69, 65, 69, 71, 69, 69, 65, 69, 69, 67, 70, 69], [68, 72, 69, 69, 69, 70, 70, 68, 70, 73, 69, 69, 67, 69, 69, 68, 72, 69, 74, 72, 70, 69], [67, 70, 69, 68, 69, 69, 69, 65, 69, 71, 68, 69, 65, 69, 69, 67, 70, 69, 73, 70, 69, 69],
[65, 69, 67, 65, 68, 68, 68, 64, 68, 69, 67, 68, 64, 68, 68, 65, 69, 67], [64, 68, 65, 64, 65, 67, 65, 63, 67, 69, 65, 65, 63, 65, 65, 64, 68, 65], [65, 69, 67, 65, 68, 68, 68, 64, 68, 69, 67, 68, 64, 68, 68, 65, 69, 67, 70, 69, 68, 68], [64, 68, 65, 64, 65, 67, 65, 63, 67, 69, 65, 65, 63, 65, 65, 64, 68, 65, 69, 68, 66, 65],
[63, 65, 64, 63, 64, 65, 64, 62, 65, 68, 64, 64, 62, 64, 64, 63, 65, 64], [61, 64, 63, 62, 63, 64, 63, 60, 64, 65, 63, 63, 60, 63, 63, 61, 64, 63], [63, 65, 64, 63, 64, 65, 64, 62, 65, 68, 64, 64, 62, 64, 64, 63, 65, 64, 68, 65, 64, 64], [61, 64, 63, 62, 63, 64, 63, 60, 64, 65, 63, 63, 60, 63, 63, 61, 64, 63, 66, 64, 64, 63],
[59, 63, 61, 60, 62, 63, 62, 59, 63, 64, 61, 62, 59, 62, 62, 59, 63, 61], [59, 62, 60, 59, 60, 61, 60, 58, 60, 63, 59, 60, 58, 60, 60, 59, 62, 59], [59, 63, 61, 60, 62, 63, 62, 59, 63, 64, 61, 62, 59, 62, 62, 59, 63, 61, 64, 63, 63, 62], [59, 62, 60, 59, 60, 61, 60, 58, 60, 63, 59, 60, 58, 60, 60, 59, 62, 59, 64, 62, 60, 60],
[58, 60, 59, 58, 59, 59, 59, 56, 59, 62, 59, 59, 56, 59, 59, 58, 60, 59], [55, 59, 58, 56, 58, 59, 58, 54, 59, 60, 58, 58, 54, 58, 58, 55, 59, 58], [58, 60, 59, 58, 59, 59, 59, 56, 59, 62, 59, 59, 56, 59, 59, 58, 60, 59, 63, 60, 59, 59], [55, 59, 58, 56, 58, 59, 58, 54, 59, 60, 58, 58, 54, 58, 58, 55, 59, 58, 60, 59, 58, 58],
[54, 58, 55, 54, 55, 58, 55, 54, 57, 59, 55, 55, 54, 55, 55, 54, 58, 55], [54, 55, 54, 54, 54, 55, 54, 53, 55, 58, 54, 54, 53, 54, 54, 54, 55, 54], [54, 58, 55, 54, 55, 58, 55, 54, 57, 59, 55, 55, 54, 55, 55, 54, 58, 55, 59, 58, 57, 56], [54, 55, 54, 54, 54, 55, 54, 53, 55, 58, 54, 54, 53, 54, 54, 53, 55, 54, 58, 55, 55, 54],
[52, 54, 53, 53, 54, 54, 54, 50, 54, 55, 53, 54, 50, 54, 53, 52, 54, 53], [50, 53, 52, 50, 52, 53, 52, 49, 53, 54, 52, 52, 49, 52, 52, 50, 54, 52], [52, 54, 53, 53, 54, 54, 54, 50, 54, 55, 53, 54, 50, 54, 53, 52, 54, 53, 56, 54, 54, 54], [50, 53, 52, 50, 52, 53, 52, 49, 53, 54, 52, 52, 49, 52, 52, 50, 54, 52, 54, 54, 53, 52],
[49, 52, 50, 49, 50, 52, 50, 48, 51, 53, 50, 50, 48, 50, 50, 49, 52, 50], [48, 50, 49, 48, 49, 50, 49, 47, 49, 52, 49, 49, 47, 49, 49, 48, 50, 49]] , [49, 52, 50, 49, 50, 52, 50, 48, 51, 53, 50, 50, 48, 50, 50, 49, 52, 50, 54, 52, 51, 50], [48, 50, 49, 48, 49, 50, 49, 47, 49, 52, 49, 49, 47, 49, 49, 48, 50, 49, 52, 50, 49, 49]] ,
'err': [13.962964335319754, 14.46429395531473, 14.75460153980027, 13.475517581958847, 13.284416516290385, 11.663797035212177, 13.653748010915642, 13.26165170209461, 13.24815971580258, 'err': [13.591395033232551, 14.077950186440525, 14.774078403334137, 13.65934002629309, 13.12217675495582, 13.019427245957683, 13.849105164311265, 12.894135823661522, 12.754900417921139,
13.704740921594585, 13.721711458162027, 10.926952106844219, 13.867842460076481, 14.293172159036494, 14.579460380045766, 15.03997746648367, 14.201679362112287, 14.444065341711763, 13.520651123253504, 13.566283196977214, 11.102221842808046, 13.70305926105289, 14.133743371321646, 14.442648311199594, 14.877654872295, 13.770229522080776, 14.852989812289856,
11.902270769685195, 14.691612876379189, 14.370267185984012, 13.047294014283374, 12.169228459682493, 14.214054982108628, 14.937184479560138, 14.882721298587882, 14.130903608506884, 11.376691221268633, 14.20474659835418, 14.299090517163119, 12.673647866712496, 11.652108793615529, 14.059936820604538, 14.743231137066562, 14.46924040995092, 13.7489773744093,
14.691101466192158, 12.788451840377483, 14.27987313699716, 14.877840276142166, 14.177382339396281, 14.252554270784621, 14.153712070169313, 32.15463688611945, 14.375792433964307, 14.506343282833871, 13.625227561880969, 13.757078478579846, 14.544854433928698, 14.08105533364493, 13.967673510547232, 13.924628222954656, 31.71821283965111, 35.90962486984108,
14.47064949941523, 12.743269820884052, 13.631768130732326, 11.913216891477532, 12.919801879321767, 15.279078580885198, 14.464812795898979, 14.166895907396338, 14.231010953645637, 14.428814631557088, 12.396488849372417, 14.44349535612264, 11.697157053250066, 12.842605611074305, 14.900714216159486, 14.082168677064601, 14.027363975209937, 14.1585010535955,
12.060641939813195, 14.931975247365244, 14.894368450250568, 15.06971394322909, 13.460529401296299, 12.562129828223988, 14.936693256444869, 14.13972897214262, 13.260296600784386, 11.697571646731376, 14.724236662308158, 14.810319472047013, 14.919015572698754, 13.266331597123553, 12.743546086496735, 14.838014918763747, 13.972730312696967, 12.941672188816028,
15.151668447706925, 13.001226656316703, 14.699922303124367, 13.153026300941747, 14.022030075945622, 14.367512628437908, 13.321350576140958, 14.24115686407913, 11.60517732129847, 14.749046167095912, 13.161067590084258, 14.436445063049632, 12.633027392416352, 14.217286781247822, 13.893543448524724, 13.775412319535917, 13.714783382202313, 11.764520622695272,
13.907016890931118, 11.318156851370532, 14.99552948232531, 13.675968792989352, 14.628795379333951, 13.11746192259443, 10.453520400424622, 13.26883790741158, 14.336915207258699, 13.457606885271161, 11.202881280195925, 14.57657476175973, 13.752538732663197, 14.451908382473903, 12.955581103627992, 10.367973655306287, 13.381703725968691, 14.158301008296348,
14.433672210448094, 13.35445753477461, 14.946750782743038, 13.508349920166893, 13.155903701367151, 13.548932970055375, 15.14066196451904, 14.873022872787715, 12.050849264783665, 13.912709826521223, 12.839932165545179, 14.584749905688568, 13.350001883511595, 12.744474585038006, 13.379430901476553, 14.761277181783953, 14.711059220966945, 11.903560453478349,
13.367169640438078, 14.90439925518558, 14.237414094496671, 14.303694905719112, 15.277141503528128, 14.593770304643385, 11.316277920408083, 11.287929747718408, 13.904513352755657, 13.368661091197282, 14.74654885090058, 13.71950248348503, 14.465686168491175, 14.8841620175167, 14.472031421684278, 10.912374408315372, 14.674839328481085, 14.14521165448241,
14.891896781228297, 14.068586037783916, 14.519374974788207, 13.69447679097857, 12.20856370903175, 15.196749766163066, 14.898141003024193, 14.461878126555803, 14.769898671009742, 14.660294651886034, 13.907584129517545, 14.110105268596271, 13.27805697394706, 14.143264423486926, 14.833207914620289, 14.738966277840063, 14.06390559648571, 14.604843339088802,
11.630730056896027, 13.579206090805656, 13.604613044049984, 15.245506993501749, 15.226149353881738, 12.115686678627299, 14.664276968544982, 12.028151996881661, 14.520569557289946, 11.138417075612324, 14.78326284399327, 13.095445066808225, 15.093564054725448, 14.936375739520827, 11.722341587152187, 14.288654242804114, 11.839846230253897, 14.392168023843169,
14.509640286205013, 14.260103653888109, 12.974029693548346, 10.81030248279012] 14.189822689755147, 13.7499719270063, 12.613365586527834, 13.530196602357591]
} }
def get_cmd_meas():
return [
[130, 129, 124], [129, 126, 124], [128, 124, 123], [127, 124, 120], [124, 121, 119], [124, 119, 119], [124, 119, 116], [119, 119, 114], [119, 117, 114], [119, 114, 114],
[116, 114, 110], [114, 113, 109], [114, 109, 109], [113, 109, 109], [109, 109, 104], [109, 107, 104], [109, 104, 104], [106, 104, 102], [104, 100, 99], [104, 99, 99],
[103, 99, 99], [99, 99, 95], [99, 95, 94], [99, 94, 94], [97, 94, 94], [94, 93, 90], [94, 91, 89], [94, 89, 89], [89, 89, 87], [89, 86, 84],
[89, 84, 84], [87, 84, 83], [84, 82, 80], [84, 80, 79], [83, 79, 79], [79, 79, 75], [79, 78, 74], [78, 74, 74], [75, 74, 74], [74, 74, 70],
[74, 72, 69], [74, 69, 69], [72, 69, 69], [70, 69, 69], [69, 68, 65], [69, 65, 64], [65, 64, 64], [64, 64, 62], [64, 62, 60], [59, 59, 59],
[59, 59, 58], [59, 56, 55], [56, 54, 54], [54, 54, 54], [54, 54, 53], [53, 52, 50], [49, 49, 49], [49, 49, 49], [49, 49, 47], [47, 45, 45],
None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None, None,
None, None, None, None, None, None, None, None, None, None, None, None, None, None, None,
[147, 144, 139], [144, 144, 139], [143, 139, 135], [140, 139, 134], [139, 135, 134], [139, 134, 132], [136, 134, 130], [134, 131, 129], [134, 130, 129]]
def get_cmda_parameters():
return {
'tAFW': [2, 7, 12, 9, 68, 6, 11, 10, 8, 63, 10, 3, 8, 5, 72, 3, 4, 15, 4, 72, 9, 4, 14, 2, 69, 8, 5, 8, 6, 71, 5, 8, 8, 6, 71, 6, 5, 11, 8, 68, 9, 10, 11, 7, 61, 5, 7, 6, 9, 71,
5, 6, 5, 5, 77, 9, 4, 5, 7, 73, 2, 6, 5, 12, 73, 7, 7, 3, 10, 71, 9, 4, 13, 2, 70, 3, 8, 11, 10, 66, 7, 9, 9, 10, 63, 9, 5, 7, 10, 67, 5, 4, 6, 7, 47, 7, 6, 6, 4, 46, 14, 1, 5, 4, 45],
'tAF': [-14.304887292510024, -3.867559016949655, 6.415142195627467, 12.166160535835392, -14.304887292510024, -3.867559016949655, 6.415142195627467, 12.166160535835392,
-14.304887292510024, -3.867559016949655, 6.415142195627467, 12.166160535835392, -14.304887292510024, -3.867559016949655, 6.415142195627467, 12.166160535835392,
-14.304887292510024, -3.867559016949655, 6.415142195627467, 12.166160535835392, -14.304887292510024, -3.867559016949655, 6.415142195627467, 12.166160535835392,
-14.304887292510024, -3.867559016949655, 6.415142195627467, 12.166160535835392, -14.304887292510024, -3.867559016949655, 6.415142195627467, 12.166160535835392,
-14.304887292510024, -3.867559016949655, 6.415142195627467, 12.166160535835392, -14.304887292510024, -3.867559016949655, 6.415142195627467, 12.166160535835392,
-14.304887292510024, -3.867559016949655, 6.415142195627467, 12.166160535835392, -14.304887292510024, -3.867559016949655, 6.415142195627467, 12.166160535835392,
-14.304887292510024, -3.867559016949655, 6.415142195627467, 12.166160535835392, -14.304887292510024, -3.867559016949655, 6.415142195627467, 12.166160535835392,
-14.304887292510024, -3.867559016949655, 6.415142195627467, 12.166160535835392, -14.304887292510024, -3.867559016949655, 6.415142195627467, 12.166160535835392,
-14.304887292510024, -3.867559016949655, 6.415142195627467, 12.166160535835392, -14.304887292510024, -3.867559016949655, 6.415142195627467, 12.166160535835392,
-14.304887292510024, -3.867559016949655, 6.415142195627467, 12.166160535835392, -14.304887292510024, -3.867559016949655, 6.415142195627467, 12.166160535835392,
-14.304887292510024, -3.867559016949655, 6.415142195627467, 12.166160535835392, -14.304887292510024, -3.867559016949655, 6.415142195627467, 12.16616053583539],
'tSA': [16.47538107242251, 15.801201220422305, 16.282070496503987, 16.144546097505152, 16.118851642842586, 16.465704031076484, 15.764654696738909, 16.3924057265115,
15.8217713860973, 15.694725920957122, 16.110856257811786, 16.026978711007544, 16.48607949353691, 16.16928448917916, 15.927707960905796, 16.49118763082908,
15.83549696849642, 16.29288527645779, 15.49067904992473, 15.824418529551094, 16.285509869605203, 16.0905903108754],
'tAHL': [-86.13236607256961, -61.575444266310654, -25.73425695789149, -20.66639131034885, -5.467130255335034, 7.220450343481222, -90.82728716638456, -32.76326046923422,
-33.201181964458236, 25.409848911510508, -30.368390180628438, -39.36603091924407, 36.27996904412795, -15.396143352482966, -5.774471239675338, -83.3362924331818,
-62.61309437741333, -27.740006944954295, None, None, None, -30.669526645055175],
'tA': [2014.335618035371, 2022.0831903592677, 2025.482966498, 2000.1256204889644, 2017.3513081600333, 2054.856921634421, 1998.5668161398096, 1991.5152458814302, 2013.552541418718,
2035.4497883071335, 2012.5914774537146, 2013.8664966165068, 1995.7738477106127, 2021.1313354266506, 2005.8702139359314, 2014.6518090648067, 2025.5963222621444, 2025.7326063296766,
2030.5864502298764, 2024.5266464332833, 2039.6076080635871, 2018.250230021426]}
\ No newline at end of file
py393/x393_mcntrl_adjust.py
View file @ 5449c194
...@@ -224,6 +224,8 @@ class X393McntrlAdjust(object): ...@@ -224,6 +224,8 @@ class X393McntrlAdjust(object):
except: except:
print("No valid delay data for phase %d is available"%(phase)) print("No valid delay data for phase %d is available"%(phase))
return False return False
if quiet<1:
print ("delays=",delays)
try: try:
cmda_odly=delays['cmda'] cmda_odly=delays['cmda']
...@@ -284,9 +286,11 @@ class X393McntrlAdjust(object): ...@@ -284,9 +286,11 @@ class X393McntrlAdjust(object):
if isinstance(cmda_odly,(list,tuple)): if isinstance(cmda_odly,(list,tuple)):
self.x393_mcntrl_timing.axi_set_address_odelay(combine_delay(cmda_odly[:num_addr]),quiet=quiet) self.x393_mcntrl_timing.axi_set_address_odelay(combine_delay(cmda_odly[:num_addr]),quiet=quiet)
self.x393_mcntrl_timing.axi_set_bank_odelay (combine_delay(cmda_odly[num_addr:num_addr+num_banks]),quiet=quiet) self.x393_mcntrl_timing.axi_set_bank_odelay (combine_delay(cmda_odly[num_addr:num_addr+num_banks]),quiet=quiet)
self.x393_mcntrl_timing.axi_set_cmd_odelay (combine_delay(cmda_odly[num_addr+num_banks]),quiet=quiet) # for now - same delay TODO: upgrade! cmd_dly_data=cmda_odly[num_addr+num_banks:]
while len(cmd_dly_data) < 5:
self.x393_mcntrl_timing.axi_set_cmda_odelay(combine_delay(cmda_odly),quiet=quiet) cmd_dly_data.append(cmd_dly_data[-1]) # repeat last element (average address/command delay)
self.x393_mcntrl_timing.axi_set_cmd_odelay (combine_delay(cmd_dly_data),quiet=quiet) # for now - same delay TODO: upgrade!
# self.x393_mcntrl_timing.axi_set_cmda_odelay(combine_delay(cmda_odly),quiet=quiet)
else: else:
self.x393_mcntrl_timing.axi_set_cmda_odelay(combine_delay(cmda_odly),quiet=quiet) self.x393_mcntrl_timing.axi_set_cmda_odelay(combine_delay(cmda_odly),quiet=quiet)
if refresh: if refresh:
...@@ -299,8 +303,8 @@ class X393McntrlAdjust(object): ...@@ -299,8 +303,8 @@ class X393McntrlAdjust(object):
self.x393_mcntrl_timing.axi_set_dqs_odelay(combine_delay(dqs_odelays),quiet=quiet) self.x393_mcntrl_timing.axi_set_dqs_odelay(combine_delay(dqs_odelays),quiet=quiet)
if not dq_odelays is None: if not dq_odelays is None:
self.x393_mcntrl_timing.axi_set_dq_odelay(combine_delay(dq_odelays),quiet=quiet) self.x393_mcntrl_timing.axi_set_dq_odelay(combine_delay(dq_odelays),quiet=quiet)
if refresh: # if refresh: #already set
self.x393_axi_tasks.enable_refresh(1) # self.x393_axi_tasks.enable_refresh(1)
return True return True
def adjust_cmda_odelay(self, def adjust_cmda_odelay(self,
...@@ -320,6 +324,7 @@ class X393McntrlAdjust(object): ...@@ -320,6 +324,7 @@ class X393McntrlAdjust(object):
@param max_phase_err maximal phase error for command and address line as a fraction of SDCLK period to consider @param max_phase_err maximal phase error for command and address line as a fraction of SDCLK period to consider
@param quiet reduce output @param quiet reduce output
""" """
nbursts=16
start_phase &= 0xff start_phase &= 0xff
if start_phase >=128: if start_phase >=128:
start_phase -= 256 # -128..+127 start_phase -= 256 # -128..+127
...@@ -338,13 +343,13 @@ class X393McntrlAdjust(object): ...@@ -338,13 +343,13 @@ class X393McntrlAdjust(object):
cmda_dly_lin=split_delay(cmda_dly) cmda_dly_lin=split_delay(cmda_dly)
self.x393_mcntrl_timing.axi_set_phase(phase,quiet=quiet) self.x393_mcntrl_timing.axi_set_phase(phase,quiet=quiet)
self.x393_mcntrl_timing.axi_set_cmda_odelay(cmda_dly,quiet=quiet) self.x393_mcntrl_timing.axi_set_cmda_odelay(cmda_dly,quiet=quiet)
wlev_rslt=self.x393_pio_sequences.write_levelling(1, quiet+1) wlev_rslt=self.x393_pio_sequences.write_levelling(1, nbursts, quiet+1)
if wlev_rslt[2]>wlev_max_bad: # should be 0, if not - Try to recover if wlev_rslt[2]>wlev_max_bad: # should be 0, if not - Try to recover
if quiet <4: if quiet <4:
print("*** FAILED to read data in write levelling mode, restarting memory device") print("*** FAILED to read data in write levelling mode, restarting memory device")
print(" Retrying with the same cmda_odelay value = 0x%x"%cmda_dly) print(" Retrying with the same cmda_odelay value = 0x%x"%cmda_dly)
self.x393_pio_sequences.restart_ddr3() self.x393_pio_sequences.restart_ddr3()
wlev_rslt=self.x393_pio_sequences.write_levelling(1, quiet) wlev_rslt=self.x393_pio_sequences.write_levelling(1,nbursts, quiet)
if wlev_rslt[2]>wlev_max_bad: # should be 0, if not - change delay and restart memory if wlev_rslt[2]>wlev_max_bad: # should be 0, if not - change delay and restart memory
cmda_dly_old=cmda_dly cmda_dly_old=cmda_dly
if cmda_dly >=recover_cmda_dly_step: if cmda_dly >=recover_cmda_dly_step:
...@@ -356,7 +361,7 @@ class X393McntrlAdjust(object): ...@@ -356,7 +361,7 @@ class X393McntrlAdjust(object):
print(" old cmda_odelay= 0x%x, new cmda_odelay =0x%x"%(cmda_dly_old,cmda_dly)) print(" old cmda_odelay= 0x%x, new cmda_odelay =0x%x"%(cmda_dly_old,cmda_dly))
self.x393_mcntrl_timing.axi_set_cmda_odelay(cmda_dly,quiet=quiet) self.x393_mcntrl_timing.axi_set_cmda_odelay(cmda_dly,quiet=quiet)
self.x393_pio_sequences.restart_ddr3() self.x393_pio_sequences.restart_ddr3()
wlev_rslt=self.x393_pio_sequences.write_levelling(1, quiet) wlev_rslt=self.x393_pio_sequences.write_levelling(1, nbursts, quiet)
if wlev_rslt[2]>wlev_max_bad: # should be 0, if not - change delay and restart memory if wlev_rslt[2]>wlev_max_bad: # should be 0, if not - change delay and restart memory
raise Exception("Failed to read in write levelling mode after modifying cmda_odelay, aborting") raise Exception("Failed to read in write levelling mode after modifying cmda_odelay, aborting")
...@@ -366,7 +371,7 @@ class X393McntrlAdjust(object): ...@@ -366,7 +371,7 @@ class X393McntrlAdjust(object):
combine_delay(d_high), combine_delay(d_high),
wlev_address_bit, wlev_address_bit,
quiet=quiet) quiet=quiet)
wlev_rslt=self.x393_pio_sequences.write_levelling(1, quiet+1) wlev_rslt=self.x393_pio_sequences.write_levelling(1, nbursts, quiet+1)
if not wlev_rslt[2]>wlev_max_bad: if not wlev_rslt[2]>wlev_max_bad:
return (split_delay(cmda_dly),-1) # even maximal delay is not enough to make rising sdclk separate command from A7 return (split_delay(cmda_dly),-1) # even maximal delay is not enough to make rising sdclk separate command from A7
# find marginal value of a7 delay to spoil write levelling mode # find marginal value of a7 delay to spoil write levelling mode
...@@ -375,7 +380,7 @@ class X393McntrlAdjust(object): ...@@ -375,7 +380,7 @@ class X393McntrlAdjust(object):
while d_high > d_low: while d_high > d_low:
dly= (d_high + d_low)//2 dly= (d_high + d_low)//2
self.x393_mcntrl_timing.axi_set_address_odelay(combine_delay(dly),wlev_address_bit,quiet=quiet) self.x393_mcntrl_timing.axi_set_address_odelay(combine_delay(dly),wlev_address_bit,quiet=quiet)
wlev_rslt=self.x393_pio_sequences.write_levelling(1, quiet+1) wlev_rslt=self.x393_pio_sequences.write_levelling(1, nbursts, quiet+1)
if wlev_rslt[2] > wlev_max_bad: if wlev_rslt[2] > wlev_max_bad:
d_high=dly d_high=dly
else: else:
...@@ -402,6 +407,8 @@ class X393McntrlAdjust(object): ...@@ -402,6 +407,8 @@ class X393McntrlAdjust(object):
# print ("safe_early=%d(0x%x), recover_cmda_dly_step=%d(0x%x)"%(safe_early,safe_early,recover_cmda_dly_step,recover_cmda_dly_step)) # print ("safe_early=%d(0x%x), recover_cmda_dly_step=%d(0x%x)"%(safe_early,safe_early,recover_cmda_dly_step,recover_cmda_dly_step))
if reinits>0: if reinits>0:
self.x393_pio_sequences.restart_ddr3() self.x393_pio_sequences.restart_ddr3()
else:
self.x393_axi_tasks.enable_refresh(0) # if not init, at least turn refresh off!
for phase in range(start_phase,start_phase+numPhaseSteps): for phase in range(start_phase,start_phase+numPhaseSteps):
if quiet <3: if quiet <3:
...@@ -660,6 +667,7 @@ class X393McntrlAdjust(object): ...@@ -660,6 +667,7 @@ class X393McntrlAdjust(object):
Find DQS output delay for each phase value Find DQS output delay for each phase value
Depends on adjust_cmda_odelay results Depends on adjust_cmda_odelay results
""" """
nbursts=16
try: try:
self.adjustment_state['cmda_bspe'] self.adjustment_state['cmda_bspe']
except: except:
...@@ -673,6 +681,9 @@ class X393McntrlAdjust(object): ...@@ -673,6 +681,9 @@ class X393McntrlAdjust(object):
if quiet < 2: if quiet < 2:
print("cmda_bspe = %s"%str(self.adjustment_state['cmda_bspe'])) print("cmda_bspe = %s"%str(self.adjustment_state['cmda_bspe']))
print ("numPhaseSteps=%d"%(numPhaseSteps)) print ("numPhaseSteps=%d"%(numPhaseSteps))
self.x393_pio_sequences.set_write_lev(nbursts) # write leveling, 16 times (full buffer - 128)
def wlev_phase_step (phase): def wlev_phase_step (phase):
def norm_wlev(wlev): #change results to invert wlev data def norm_wlev(wlev): #change results to invert wlev data
if invert: if invert:
...@@ -689,7 +700,7 @@ class X393McntrlAdjust(object): ...@@ -689,7 +700,7 @@ class X393McntrlAdjust(object):
d_low=0 d_low=0
while d_low <= max_lin_dly: while d_low <= max_lin_dly:
self.x393_mcntrl_timing.axi_set_dqs_odelay(combine_delay(d_low),quiet=quiet) self.x393_mcntrl_timing.axi_set_dqs_odelay(combine_delay(d_low),quiet=quiet)
wlev_rslt=norm_wlev(self.x393_pio_sequences.write_levelling(1, quiet+1)) wlev_rslt=norm_wlev(self.x393_pio_sequences.write_levelling(1, nbursts, quiet+1))
if wlev_rslt[2]>wlev_max_bad: # should be 0 - otherwise wlev did not work (CMDA?) if wlev_rslt[2]>wlev_max_bad: # should be 0 - otherwise wlev did not work (CMDA?)
raise Exception("Write levelling gave unespected data, aborting (may be wrong command/address delay, incorrectly initializaed") raise Exception("Write levelling gave unespected data, aborting (may be wrong command/address delay, incorrectly initializaed")
if (wlev_rslt[0] <= wlev_max_bad) and (wlev_rslt[1] <= wlev_max_bad): if (wlev_rslt[0] <= wlev_max_bad) and (wlev_rslt[1] <= wlev_max_bad):
...@@ -703,7 +714,7 @@ class X393McntrlAdjust(object): ...@@ -703,7 +714,7 @@ class X393McntrlAdjust(object):
d_high= d_low+dly90 d_high= d_low+dly90
while d_high <= max_lin_dly: while d_high <= max_lin_dly:
self.x393_mcntrl_timing.axi_set_dqs_odelay(combine_delay(d_high),quiet=quiet) self.x393_mcntrl_timing.axi_set_dqs_odelay(combine_delay(d_high),quiet=quiet)
wlev_rslt=norm_wlev(self.x393_pio_sequences.write_levelling(1, quiet+1)) wlev_rslt=norm_wlev(self.x393_pio_sequences.write_levelling(1, nbursts, quiet+1))
if wlev_rslt[2]>wlev_max_bad: # should be 0 - otherwise wlev did not work (CMDA?) if wlev_rslt[2]>wlev_max_bad: # should be 0 - otherwise wlev did not work (CMDA?)
raise Exception("Write levelling gave unespected data, aborting (may be wrong command/address delay, incorrectly initializaed") raise Exception("Write levelling gave unespected data, aborting (may be wrong command/address delay, incorrectly initializaed")
if (wlev_rslt[0] >= (1.0 -wlev_max_bad)) and (wlev_rslt[1] >= (1.0-wlev_max_bad)): if (wlev_rslt[0] >= (1.0 -wlev_max_bad)) and (wlev_rslt[1] >= (1.0-wlev_max_bad)):
...@@ -720,7 +731,7 @@ class X393McntrlAdjust(object): ...@@ -720,7 +731,7 @@ class X393McntrlAdjust(object):
while d_high > d_low: while d_high > d_low:
dly= (d_high + d_low)//2 dly= (d_high + d_low)//2
self.x393_mcntrl_timing.axi_set_dqs_odelay(combine_delay(dly),quiet=quiet) self.x393_mcntrl_timing.axi_set_dqs_odelay(combine_delay(dly),quiet=quiet)
wlev_rslt=norm_wlev(self.x393_pio_sequences.write_levelling(1, quiet+1)) wlev_rslt=norm_wlev(self.x393_pio_sequences.write_levelling(1, nbursts, quiet+1))
if wlev_rslt[2]>wlev_max_bad: # should be 0 - otherwise wlev did not work (CMDA?) if wlev_rslt[2]>wlev_max_bad: # should be 0 - otherwise wlev did not work (CMDA?)
raise Exception("Write levelling gave unespected data, aborting (may be wrong command/address delay, incorrectly initializaed") raise Exception("Write levelling gave unespected data, aborting (may be wrong command/address delay, incorrectly initializaed")
if (wlev_rslt[0] <= wlev_max_bad) and (wlev_rslt[1] <= wlev_max_bad): if (wlev_rslt[0] <= wlev_max_bad) and (wlev_rslt[1] <= wlev_max_bad):
...@@ -744,7 +755,7 @@ class X393McntrlAdjust(object): ...@@ -744,7 +755,7 @@ class X393McntrlAdjust(object):
dly01=[d_low[0],d_low[1]] dly01=[d_low[0],d_low[1]]
dly01[i]=dly dly01[i]=dly
self.x393_mcntrl_timing.axi_set_dqs_odelay(combine_delay(dly01),quiet=quiet) self.x393_mcntrl_timing.axi_set_dqs_odelay(combine_delay(dly01),quiet=quiet)
wlev_rslt=norm_wlev(self.x393_pio_sequences.write_levelling(1, quiet+1)) wlev_rslt=norm_wlev(self.x393_pio_sequences.write_levelling(1, nbursts, quiet+1))
if wlev_rslt[2]>wlev_max_bad: # should be 0 - otherwise wlev did not work (CMDA?) if wlev_rslt[2]>wlev_max_bad: # should be 0 - otherwise wlev did not work (CMDA?)
raise Exception("Write levelling gave unespected data, aborting (may be wrong command/address delay, incorrectly initializaed") raise Exception("Write levelling gave unespected data, aborting (may be wrong command/address delay, incorrectly initializaed")
if wlev_rslt[i] <= wlev_max_bad: if wlev_rslt[i] <= wlev_max_bad:
...@@ -2286,7 +2297,7 @@ class X393McntrlAdjust(object): ...@@ -2286,7 +2297,7 @@ class X393McntrlAdjust(object):
print("%d %s %s"%(phase,str(dly),str(ldly))) print("%d %s %s"%(phase,str(dly),str(ldly)))
dly_try_step=NUM_FINE_STEPS # how far to step when looking for zero crossing (from predicted) dly_try_step=NUM_FINE_STEPS # how far to step when looking for zero crossing (from predicted)
phase_try_step=numPhaseSteps//8 # when searching for marginal delay, wry not optimal+perid/2 but smaller step to accommodate per-bit variations phase_try_step=numPhaseSteps//8 # when searching for marginal delay, try not optimal+perid/2 but smaller step to accommodate per-bit variations
good_patt=0xaaaa good_patt=0xaaaa
bad_patt = good_patt ^ 0xffff bad_patt = good_patt ^ 0xffff
# make sure delay data is available # make sure delay data is available
...@@ -2521,7 +2532,7 @@ class X393McntrlAdjust(object): ...@@ -2521,7 +2532,7 @@ class X393McntrlAdjust(object):
addr_odelay.append(addr_phase_step(phase)) addr_odelay.append(addr_phase_step(phase))
if quiet < 6: if quiet < 6:
print () print ()
self.adjustment_state['addr_odelay_meas']=addr_odelay # self.adjustment_state['addr_odelay_meas']=addr_odelay
if quiet < 3: if quiet < 3:
for phase, adly in enumerate(addr_odelay): for phase, adly in enumerate(addr_odelay):
print("%d"%(phase),end=" ") print("%d"%(phase),end=" ")
...@@ -2534,7 +2545,297 @@ class X393McntrlAdjust(object): ...@@ -2534,7 +2545,297 @@ class X393McntrlAdjust(object):
print("?",end=" ") print("?",end=" ")
print() print()
return addr_odelay return addr_odelay
def measure_cmd_odelay(self,
safe_phase=0.25, # 0 strictly follow cmda_odelay, >0 -program with this fraction of clk period from the margin
reinits=1,
tryWrongWlev=1, # try wrong write levelling mode to make sure device is not stuck in write levelling mode
quiet=0):
"""
Measure output delay on 3 command lines - WE, RAS and CAS, only for high-low transitions as controller
keeps these lines at high (inactive) level all the time but the command itself.
Scanning is performed with refresh off, one bit at a time in write levelling mode and DQS output delay set
1/4 later than nominal, so 0x01010101 pattern is supposed to be read on all bits. If it is not (usually just 0xffffffff-s)
the command bit is wrong. After each test one read with normal delay is done to make sure the write levelling mode is
turned off - during write levelling mode it is turned on first, then off and marginal command bit delay may cause
write levelling to turn on, but not off
"""
# self.load_hardcoded_data() # TODO: ******** TEMPORARY - remove later
nrep=4 #16 # number of 8-bursts in write levelling mode
margin_error=0.1 # put 0.0? - how high wlev error can be to accept
cmd_bits=(0,1,2) # WE, RAS, CAS
if not "cmda_bspe" in self.adjustment_state:
raise Exception ("No cmda_odelay data is available. 'adjust_cmda_odelay 0 1 0.1 3' command should run first.")
dly_steps=self.x393_mcntrl_timing.get_dly_steps()
numPhaseSteps= int(dly_steps['SDCLK_PERIOD']/dly_steps['PHASE_STEP']+0.5)
#create a list of None/optimal cmda determined earlier
cmda_odly= [None if (self.adjustment_state['cmda_bspe'][phase] is None) else self.adjustment_state['cmda_bspe'][phase]['ldly'] for phase in range(numPhaseSteps)]
if safe_phase:
cmda_odly_zerr=[None if (self.adjustment_state['cmda_bspe'][phase] is None) else self.adjustment_state['cmda_bspe'][phase]['zerr'] for phase in range(numPhaseSteps)]
cmda_odly_early=[]
for phase,zerr in enumerate (cmda_odly_zerr):
if (not zerr is None) and (zerr < 0.5-safe_phase):
cmda_odly_early.append(0)
else:
cmda_odly_early.append(cmda_odly[phase])
else:
cmda_odly_early=cmda_odly
#get write levellimg data
if not "wlev_dqs_bspe" in self.adjustment_state:
raise Exception ("No wlev_dqs_bspe data is available, this method should run after write levelling")
wlev_odly=[]
for wlev_data in self.adjustment_state['wlev_dqs_bspe']:
wlev_odly.append([None if (wlev_data[phase] is None) else wlev_data[phase]['ldly'] for phase in range(numPhaseSteps)])
if quiet <1:
print("wlev_odly=",wlev_odly)
#fill gaps (if any - currently none
if quiet <1:
#simulate
wlev_odly[0][5]=None
wlev_odly[1][3]=None
print("wlev_odly=",wlev_odly)
for wlev_lane in wlev_odly:
for phase in range(numPhaseSteps):
if wlev_lane[phase] is None:
otherPhase=None
for p in range(phase-numPhaseSteps/8,phase+numPhaseSteps/8+1):
if not wlev_lane[p % numPhaseSteps] is None:
if (otherPhase is None) or (abs(phase-p) < abs(phase-otherPhase)):
otherPhase=p
if not otherPhase is None:
print ("phase=",phase,", otherPhase=",otherPhase)
wlev_lane[phase]=wlev_lane[otherPhase % numPhaseSteps]
if quiet <1:
print("wlev_odly=",wlev_odly)
#shift by 90 degrees
wlev_odly_late=[]
for wlev_lane in wlev_odly:
wlev_odly_late.append(wlev_lane[3*numPhaseSteps//4:]+wlev_lane[:3*numPhaseSteps//4])
if quiet <1:
print("wlev_odly_late=",wlev_odly_late)
if quiet <1:
for phase,dly in enumerate(cmda_odly):
ldly=None
if not self.adjustment_state['cmda_bspe'][phase] is None:
ldly=self.adjustment_state['cmda_bspe'][phase]['ldly']
print("%d %s %s"%(phase,str(dly),str(ldly)))
dly_try_step=NUM_FINE_STEPS # how far to step when looking for zero crossing (from predicted)
phase_try_step=numPhaseSteps//8 # when searching for marginal delay, try not optimal+perid/2 but smaller step to accommodate per-bit variations
#turn off refresh - it will not be needed in this test
if reinits > 0:
self.x393_pio_sequences.restart_ddr3()
else:
self.x393_axi_tasks.enable_refresh(0) # if not init, at least turn refresh off!
self.x393_pio_sequences.set_write_lev(nrep,False) # write leveling - 'good' mode
def set_delays_with_reinit(phase,
restart=False):
"""
Re-initialize memory device if it stopped responding
"""
if restart:
if quiet < 2:
print ('Re-initializing memory device after failure, phase=%d'%(phase))
self.x393_pio_sequences.restart_ddr3()
if cmda_odly_early[phase] is None:
if quiet < 2:
print ('No good cmda_odly_early delays for phase = %d'%(phase))
return None
dly_wlev=(wlev_odly_late[0][phase],wlev_odly_late[1][phase])
if None in dly_wlev:
if quiet < 2:
print ('No good late write levellilng DQS output delays for phase = %d'%(phase))
return None
# no need to set any other delays but cmda and dqs odelay?
#just set phase!
self.x393_mcntrl_timing.axi_set_phase(phase,quiet=quiet)
self.x393_mcntrl_timing.axi_set_cmda_odelay(combine_delay(cmda_odly_early[phase]),None, quiet=quiet)
# set DQS odelays to get write levelling pattern
self.x393_mcntrl_timing.axi_set_dqs_odelay(combine_delay(dly_wlev), quiet=quiet)
#Verify wlev is OK
wl_rslt=self.x393_pio_sequences.write_levelling(1, nrep, quiet)
if wl_rslt[2] > margin_error:
self.x393_pio_sequences.set_write_lev(nrep,False) # write leveling - 'good' mode (if it was not set so)
wl_rslt=self.x393_pio_sequences.write_levelling(1, nrep, quiet)
if wl_rslt[2] > margin_error:
if not restart:
set_delays_with_reinit(phase=phase,restart=True) # try with reinitialization
else:
raise Exception ("set_delays_with_reinit failed to read with safe delays for phase=%d after re-initializing device, wl_rslt=%s"%
(phase,str(wl_rslt)))
return cmda_odly_early[phase] # safe command/adderss delay
def cmd_phase_step(phase):
def measure_block(dly,
cmd_bit,
force_meas=False):
if (meas_cache[dly] is None) or force_meas:
#set same delays for all cmda bits (should be already done with 'set_phase_with_refresh'
self.x393_mcntrl_timing.axi_set_cmd_odelay(combine_delay(cmda_odly_early[phase]),None, quiet=quiet)
self.x393_mcntrl_timing.axi_set_cmd_odelay(combine_delay(dly), cmd_bit,quiet=quiet)
if quiet < 1:
print ('measure_block(%d,%d,%d,%d,%s) - new measurement'%(dly,cmda_odly_early[phase],cmd_bit,phase,str(force_meas)))
self.x393_pio_sequences.manual_refresh() # run refresh that sets address bit to opposite values to the required row+bank address
wl_rslt=self.x393_pio_sequences.write_levelling(1, nrep, quiet)
meas= not (wl_rslt[2] > margin_error) # not so many errors (normally should be just 0
meas_cache[dly]=meas
# now reset command bit delay and make sure it worked
self.x393_mcntrl_timing.axi_set_cmd_odelay(combine_delay(cmda_odly_early[phase]),None, quiet=quiet)
wl_rslt=self.x393_pio_sequences.write_levelling(1, nrep, quiet)
if wl_rslt[2] > margin_error:
if quiet < 2:
print ("measure_block failed to re-read with safe delays for phase=%d, cmd_bit=%d. Resetting memory device, wl_rslt=%s"%(phase,cmd_bit,str(wl_rslt)))
set_delays_with_reinit(phase=phase, restart=True)
#retry after re-initialization
wl_rslt=self.x393_pio_sequences.write_levelling(1,nrep, quiet)
if wl_rslt[2] > margin_error:
raise Exception ("measure_block failed to re-read with safe delays for phase=%d even after re-initializing device, wl_rslt=%s"%(phase,str(wl_rslt)))
# Now make sure device responds - setup read "wrong" write levelling (no actually turning on wlev mode)
if tryWrongWlev:
self.x393_pio_sequences.set_write_lev(nrep, True) # 'wrong' write leveling - should not work
wl_rslt=self.x393_pio_sequences.write_levelling(1, nrep, quiet)
#restore normal write levelling mode:
self.x393_pio_sequences.set_write_lev(nrep, False) # 'wrong' write leveling - should not work
if not (wl_rslt[2] > margin_error):
if quiet < 2:
print ("!!! Write levelling mode is stuck (not turning off) for phase=%d, wl_rslt=%s"%(phase,str(wl_rslt)))
set_delays_with_reinit(phase=phase, restart=True) # just do it, no testimng here (wlev mode is already restored
else:
meas=meas_cache[dly]
if quiet < 1:
print ('measure_block(%d,%s) - using cache'%(dly,str(force_meas)))
return meas
#cmd_phase_step(phase) body
if quiet < 1:
print ("****** phase=%d ******"%(phase),end=" ")
# if delays_phase[phase] is None:
# if quiet < 1:
# print ("delays_phase[%d] is None"%(phase))
# return None
dly_optimal= cmda_odly[phase]
if dly_optimal is None:
if quiet < 1:
print ("dly_optimal is None")
return None
# may increase range by using dly_optimal=0 until it is not dangerously late (say only 1/4 period off)
phase_marg= (phase+ (numPhaseSteps//2)-phase_try_step) % numPhaseSteps
if cmda_odly[phase_marg] is None:
phase_marg_traget=phase_marg
phase_marg=None
for p in range(numPhaseSteps):
if not cmda_odly[p is None]:
if (phase_marg is None) or (min(abs(p-phase_marg_traget),
abs(p-phase_marg_traget+numPhaseSteps),
abs(p-phase_marg_traget-numPhaseSteps)) < min(abs(phase_marg-phase_marg_traget),
abs(phase_marg-phase_marg_traget+numPhaseSteps),
abs(phase_marg-phase_marg_traget-numPhaseSteps))):
phase_marg=p
else:
print("BUG: could to find a valid marginal phase")
return None
# may increase range by using dly_optimal=0 until it is not dangerously late (say only 1/4 period off)
dly_marg = cmda_odly[phase_marg]# - dly_try_step
if dly_marg < dly_optimal:
if cmda_odly_early[phase] < dly_marg:
dly_optimal=cmda_odly_early[phase]
else:
if quiet < 1:
print ("dly_marg (==%d) < dly_optimal (==%d)"%(dly_marg,dly_optimal))
return None # It is not possble to try delay lower than optimal with this method
#set phase and all optimal delays for that phase
# Maybe it is not needed at all?
# self.set_phase_delays(phase=phase,
# refresh=True,
# delays_phase=delays_phase,
# quiet=quiet) # all the rest are defaults
dlyOK=set_delays_with_reinit(phase=phase, restart=False) # will check wlev and re-init if required
if dlyOK is None:
if quiet < 1:
print ("set_delays_with_reinit(%d) failed"%(phase))
return None
# Now try
rslt=[]
for cmd_bit in cmd_bits:
if quiet < 1 :
print("\n===== phase=%d, dly_optimal=%d, cmd_bit=%d"%(phase, dly_optimal,cmd_bit))
set_delays_with_reinit(phase=phase, restart=False) # no need to check results? Maybe remove completely?
# set_delays_with_reinit(phase=phase, restart=True) # no need to check results? Maybe remove completely?
meas_cache=[None]*NUM_DLY_STEPS # cache for holding results of already measured delays, new cach for each address bit
dly=dly_marg
dly_low=None #dly
dly_high=None# dly
while ((dly_low is None) or (dly_high is None)) and (dly > dly_optimal) and (dly < NUM_DLY_STEPS):
meas=measure_block(dly,
cmd_bit)
if meas :
if dly==(NUM_DLY_STEPS-1):
dly = None
break
dly_low=dly
dly=min(NUM_DLY_STEPS-1,dly+dly_try_step)
else:
dly_high=dly
dly=max(dly_optimal,dly-dly_try_step)
if quiet < 1 :
print ("dly_low=%s, dly_high=%s, dly=%s"%(str(dly_low),str(dly_high),str(dly)))
if (dly_low is None) or (dly_high is None): # dly is None:
rslt.append(None)
continue
#find highest delay that is lower than margin (here delay monotonicity is assumed!)
while dly_low < (dly_high-1):
dly=(dly_low+dly_high)//2
meas=measure_block(dly,
cmd_bit)
if meas:
dly_low=dly
else:
dly_high=dly
rslt.append(dly_low)
if quiet < 1 :
print ("rslt=",rslt)
if quiet < 1 :
print ("final rslt=",rslt)
return rslt
cmd_odelay=[]
for phase in range(numPhaseSteps):
if quiet < 6:
print (".",end="")
sys.stdout.flush()
cmd_odelay.append(cmd_phase_step(phase))
if quiet < 6:
print ()
self.adjustment_state['cmd_meas']=cmd_odelay
if quiet < 3:
for phase, cdly in enumerate(cmd_odelay):
print("%d"%(phase),end=" ")
print("%s"%(str(cmda_odly[phase])),end=" ")
if cdly:
for b in cdly:
if not b is None:
print("%d"%(b),end=" ")
else:
print("?",end=" ")
print()
if quiet < 3:
print("cmd_meas=",cmd_odelay)
# Keeps refresh off?
# Restore default write levelling sequence
self.x393_pio_sequences.set_write_lev(16,False) # write leveling - 'good' mode (if it was not set so)
return cmd_odelay
def measure_all(self, def measure_all(self,
tasks="CWRPOAZ", tasks="CWRPOAZ",
...@@ -2585,6 +2886,13 @@ class X393McntrlAdjust(object): ...@@ -2585,6 +2886,13 @@ class X393McntrlAdjust(object):
'invert':0, 'invert':0,
'max_phase_err':max_phase_err, 'max_phase_err':max_phase_err,
'quiet':quiet+1}}, 'quiet':quiet+1}},
{'key':'A',
'func':self.measure_cmd_odelay,
'comment':'Measuring command (WE, RAS, CAS) lines output delays',
'params':{'safe_phase':safe_phase,
'reinits': 1,
'tryWrongWlev': 1,
'quiet':quiet+1}},
{'key':'R', {'key':'R',
'func':self.measure_pattern, 'func':self.measure_pattern,
'comment':'Read levelling - measuring predefined pattern to determine DQ input delays relative to DQS ones', 'comment':'Read levelling - measuring predefined pattern to determine DQ input delays relative to DQS ones',
...@@ -2696,8 +3004,11 @@ class X393McntrlAdjust(object): ...@@ -2696,8 +3004,11 @@ class X393McntrlAdjust(object):
self.adjustment_state.update(get_test_dq_dqs_data.get_wlev_data()) self.adjustment_state.update(get_test_dq_dqs_data.get_wlev_data())
self.adjustment_state.update(get_test_dq_dqs_data.get_dqsi_phase()) self.adjustment_state.update(get_test_dq_dqs_data.get_dqsi_phase())
self.adjustment_state['addr_odelay_meas']= get_test_dq_dqs_data.get_addr_meas() # self.adjustment_state['addr_odelay_meas']= get_test_dq_dqs_data.get_addr_meas()
self.adjustment_state['addr_meas']= get_test_dq_dqs_data.get_addr_meas()
self.adjustment_state['addr_odelay']= get_test_dq_dqs_data.get_addr_odly() self.adjustment_state['addr_odelay']= get_test_dq_dqs_data.get_addr_odly()
self.adjustment_state['cmd_meas']= get_test_dq_dqs_data.get_cmd_meas()
def proc_dqi_dqsi(self, def proc_dqi_dqsi(self,
lane="all", lane="all",
...@@ -2931,8 +3242,8 @@ class X393McntrlAdjust(object): ...@@ -2931,8 +3242,8 @@ class X393McntrlAdjust(object):
print ("'%s':%s,"%(k,str(v))) print ("'%s':%s,"%(k,str(v)))
print ("}") print ("}")
self.adjustment_state["dqo_dqso"]=rslt self.adjustment_state["dqo_dqso"]=rslt
return rslt return rslt
def proc_addr_odelay(self, def proc_addr_odelay(self,
commonFine=True, # use same values for fine delay commonFine=True, # use same values for fine delay
max_err=0.125, # 1/8 period max_err=0.125, # 1/8 period
...@@ -2941,10 +3252,24 @@ class X393McntrlAdjust(object): ...@@ -2941,10 +3252,24 @@ class X393McntrlAdjust(object):
Process delay calibration data for address and bank line, calculate delay scales, shift and rise/fall differences. Process delay calibration data for address and bank line, calculate delay scales, shift and rise/fall differences.
Calculate finedelay corrections and finally optimal delay value for each line each phase Calculate finedelay corrections and finally optimal delay value for each line each phase
""" """
self.load_hardcoded_data() # TODO: TEMPORARY - remove later # self.load_hardcoded_data() # TODO: TEMPORARY - remove later
addr_odelay=self.adjustment_state['addr_odelay_meas'] try:
# addr_odelay=self.adjustment_state['addr_odelay_meas']
addr_odelay=self.adjustment_state['addr_meas']
except:
print("No measurement data for address and bank lines is available. Please run 'measure_addr_odelay' first or load 'load_hardcoded_data'")
return None
try:
cmd_odelay=self.adjustment_state['cmd_meas']
except:
print("No measurement data for command (WE,RAS,CAS) lines is available. Please run 'measure_cmd_odelay' first or load 'load_hardcoded_data'")
return None
numCmdLines=3
numABLines=vrlg.ADDRESS_NUMBER+3
numLines= numABLines+numCmdLines
# print('addr_odelay=','addr_odelay')
numLines=vrlg.ADDRESS_NUMBER+3
dly_steps=self.x393_mcntrl_timing.get_dly_steps() dly_steps=self.x393_mcntrl_timing.get_dly_steps()
numPhaseSteps= int(dly_steps['SDCLK_PERIOD']/dly_steps['PHASE_STEP']+0.5) numPhaseSteps= int(dly_steps['SDCLK_PERIOD']/dly_steps['PHASE_STEP']+0.5)
phase_step=1000.0*dly_steps['PHASE_STEP'] phase_step=1000.0*dly_steps['PHASE_STEP']
...@@ -2959,6 +3284,18 @@ class X393McntrlAdjust(object): ...@@ -2959,6 +3284,18 @@ class X393McntrlAdjust(object):
cmda_odly_b=self.adjustment_state["cmda_odly_b"] cmda_odly_b=self.adjustment_state["cmda_odly_b"]
except: except:
raise Exception ("No cmda_odly_b is available.") raise Exception ("No cmda_odly_b is available.")
#Combine measurements for address and command lines
# print ("cmd_odelay=",cmd_odelay)
for phase in range (numPhaseSteps):
if (not addr_odelay[0][phase] is None) or (not cmd_odelay[phase] is None):
if addr_odelay[0][phase] is None:
addr_odelay[0][phase]=[None]*numABLines
if cmd_odelay[phase] is None:
cmd_odelay[phase]=[None]*numCmdLines
addr_odelay[0][phase] += cmd_odelay[phase]
if not addr_odelay[1][phase] is None:
addr_odelay[1][phase] += [None]*numCmdLines
tSA=-clk_period/(numPhaseSteps*cmda_odly_a) # positive tSA=-clk_period/(numPhaseSteps*cmda_odly_a) # positive
variantStep=-cmda_odly_a*numPhaseSteps #how much b changes when moving over the full SDCLK period variantStep=-cmda_odly_a*numPhaseSteps #how much b changes when moving over the full SDCLK period
tA=cmda_odly_b*tSA-clk_period/2 tA=cmda_odly_b*tSA-clk_period/2
...@@ -3009,6 +3346,7 @@ class X393McntrlAdjust(object): ...@@ -3009,6 +3346,7 @@ class X393McntrlAdjust(object):
for edge,pol_data in enumerate(addr_odelay): for edge,pol_data in enumerate(addr_odelay):
for phase, phase_data in enumerate(pol_data): for phase, phase_data in enumerate(pol_data):
# print("##### ",phase,phase_data)
if (not phase_data is None) and (not phase_data[indx] is None): if (not phase_data is None) and (not phase_data[indx] is None):
dly=phase_data[indx] dly=phase_data[indx]
# y=-(phase_step*phase+tAF5C[dly %NUM_FINE_STEPS]) # y=-(phase_step*phase+tAF5C[dly %NUM_FINE_STEPS])
...@@ -3028,7 +3366,7 @@ class X393McntrlAdjust(object): ...@@ -3028,7 +3366,7 @@ class X393McntrlAdjust(object):
s01[edge]+=diff s01[edge]+=diff
n01[edge]+=1 n01[edge]+=1
if quiet <1: if quiet <1:
print("%d %d %f %f %f"%(phase,dly,y,diff0,diff)) print("%d %d %d %f %f %f"%(edge, phase,dly,y,diff0,diff))
avgF=0.0 avgF=0.0
for i in range (NUM_FINE_STEPS): for i in range (NUM_FINE_STEPS):
if nAF5[i]: if nAF5[i]:
...@@ -3038,6 +3376,8 @@ class X393McntrlAdjust(object): ...@@ -3038,6 +3376,8 @@ class X393McntrlAdjust(object):
for edge in range(len(addr_odelay)): for edge in range(len(addr_odelay)):
if n01[edge]: if n01[edge]:
s01[edge] /= n01[edge] s01[edge] /= n01[edge]
else:
s01[edge] = None # commands have onl;y one edge tested
if quiet <2: if quiet <2:
...@@ -3053,7 +3393,10 @@ class X393McntrlAdjust(object): ...@@ -3053,7 +3393,10 @@ class X393McntrlAdjust(object):
print ("tAF4=",parameters['tAF'][4*indx:4*(indx+1)], "(old)") print ("tAF4=",parameters['tAF'][4*indx:4*(indx+1)], "(old)")
parameters['tSA'][indx] = (SXY*S0 - SY*SX) / (SX2*S0 - SX*SX) parameters['tSA'][indx] = (SXY*S0 - SY*SX) / (SX2*S0 - SX*SX)
parameters['tA'][indx] = - (SY*SX2 - SXY*SX) / (SX2*S0 - SX*SX) parameters['tA'][indx] = - (SY*SX2 - SXY*SX) / (SX2*S0 - SX*SX)
parameters['tAHL'][indx] = 2*(s01[0]-s01[1]) try:
parameters['tAHL'][indx] = 2*(s01[0]-s01[1])
except:
parameters['tAHL'][indx] = None
if corrFine: if corrFine:
for i in range (NUM_FINE_STEPS-1): for i in range (NUM_FINE_STEPS-1):
# parameters['tAF'][(NUM_FINE_STEPS-1)*indx+i] += sAF5[i] - avgF # parameters['tAF'][(NUM_FINE_STEPS-1)*indx+i] += sAF5[i] - avgF
...@@ -3098,6 +3441,7 @@ class X393McntrlAdjust(object): ...@@ -3098,6 +3441,7 @@ class X393McntrlAdjust(object):
""" """
avg_index=numLines # len(parameters['tA'])-1 avg_index=numLines # len(parameters['tA'])-1
num_items=numLines+1
s_avg=parameters['tSA'][avg_index] s_avg=parameters['tSA'][avg_index]
t_avg= parameters['tA'][avg_index]-phase_step*phase - clk_period/2 t_avg= parameters['tA'][avg_index]-phase_step*phase - clk_period/2
periods=0 periods=0
...@@ -3117,8 +3461,13 @@ class X393McntrlAdjust(object): ...@@ -3117,8 +3461,13 @@ class X393McntrlAdjust(object):
worst_err=0 # worst_err=0 #
if quiet < 1: if quiet < 1:
print ("Phase=%d"%(phase)) print ("Phase=%d"%(phase))
# print("num_items=",num_items)
# print("len(parameters['tA'])=",len(parameters['tA']))
# print("len(parameters['tSA'])=",len(parameters['tSA']))
# print("len(parameters['tAF'])=",len(parameters['tAF']))
for line in range(numLines): #+1): for line in range(num_items): #+1):
tAF5=parameters['tAF'][(NUM_FINE_STEPS-1)*line:(NUM_FINE_STEPS-1)*(line+1)] tAF5=parameters['tAF'][(NUM_FINE_STEPS-1)*line:(NUM_FINE_STEPS-1)*(line+1)]
tAF5.append(-sum(tAF5)) tAF5.append(-sum(tAF5))
best_dly=None best_dly=None
...@@ -3127,7 +3476,15 @@ class X393McntrlAdjust(object): ...@@ -3127,7 +3476,15 @@ class X393McntrlAdjust(object):
dbg_dly=[] dbg_dly=[]
for dly in range (NUM_DLY_STEPS): for dly in range (NUM_DLY_STEPS):
#TODO: verify finedelay polarity #TODO: verify finedelay polarity
t_dly=parameters['tA'][line]-parameters['tSA'][line]*dly -phase_step*phase - clk_period/2 + tAF5[dly %NUM_FINE_STEPS] + periods*clk_period try:
t_dly=parameters['tA'][line]-parameters['tSA'][line]*dly -phase_step*phase - clk_period/2 + tAF5[dly %NUM_FINE_STEPS] + periods*clk_period
except:
print ("line=",line)
print ("parameters['tA']=",parameters['tA'])
print ("parameters['tSA']=",parameters['tSA'])
print ("tAF5=",tAF5)
raise Exception("That's all")
# t_dly=parameters['tA'][line]-parameters['tSA'][line]*dly -phase_step*phase - clk_period/2 - tAF5[dly %NUM_FINE_STEPS] + periods*clk_period # t_dly=parameters['tA'][line]-parameters['tSA'][line]*dly -phase_step*phase - clk_period/2 - tAF5[dly %NUM_FINE_STEPS] + periods*clk_period
if quiet < 1: if quiet < 1:
dbg_dly.append(t_dly) dbg_dly.append(t_dly)
...@@ -3169,9 +3526,25 @@ class X393McntrlAdjust(object): ...@@ -3169,9 +3526,25 @@ class X393McntrlAdjust(object):
for _ in range (2): for _ in range (2):
proc_addr_step(line,0,1) proc_addr_step(line,0,1)
# Calculate average parameters (to be used for command bits until found better measurement for them: # Calculate average parameters (to be used for command bits until found better measurement for them:
parameters['tAFW'] += average_finedelays()[:NUM_FINE_STEPS-1] # do only once - increases length of parameters items # print ("0:len(parameters['tAFW'])=",len(parameters['tAFW']))
parameters['tAF'] += average_finedelays()[:NUM_FINE_STEPS-1] # do only once - increases length of parameters items
# print ("1:len(parameters['tAFW'])=",len(parameters['tAFW']))
for k in ("tSA",'tA','tAHL'): for k in ("tSA",'tA','tAHL'):
parameters[k].append(sum(parameters[k])/numLines) try:
parameters[k].append(sum(parameters[k])/numLines)
except:
s=0.0
n=0
for d in parameters[k]:
if not d is None:
s+=d
n+=1
if n>0:
parameters[k].append(s/n)
else:
parameters[k].append(None)
tAF5A=average_finedelays()
if quiet<3: if quiet<3:
print ("parameters=",parameters) print ("parameters=",parameters)
...@@ -3201,24 +3574,11 @@ class X393McntrlAdjust(object): ...@@ -3201,24 +3574,11 @@ class X393McntrlAdjust(object):
print("'dlys': ",rslt['dlys'],",") print("'dlys': ",rslt['dlys'],",")
print("'err': ",rslt['err']) print("'err': ",rslt['err'])
print("}") print("}")
if quiet<3:
print ("parameters=",parameters)
self.adjustment_state['addr_odelay']= rslt self.adjustment_state['addr_odelay']= rslt
return rslt return rslt
"""
proc_addr_odelay 3
proc_addr_odelay 0
dt=phase_step*phase+tA+tSA*dly+tAF5[dly %NUM_FINE_STEPS]
tSA* dly +tA =-(phase_step*phase+tAF5[dly %NUM_FINE_STEPS])
a <-> tSA,
b <-> tA,
y <->-(phase_step*phase+tAF5C[dly %NUM_FINE_STEPS]) tAF5C should include 0.5 of the step between this and next
"""
def get_delays_vs_phase(self, def get_delays_vs_phase(self,
filter_dqo=2, filter_dqo=2,
filter_dqi=2, filter_dqi=2,
...@@ -3250,6 +3610,7 @@ class X393McntrlAdjust(object): ...@@ -3250,6 +3610,7 @@ class X393McntrlAdjust(object):
# self.load_hardcoded_data() # TODO: REMOVE LATER # self.load_hardcoded_data() # TODO: REMOVE LATER
num_addr=vrlg.ADDRESS_NUMBER num_addr=vrlg.ADDRESS_NUMBER
num_banks=3 num_banks=3
# num_cmd=3 # (we,ras,cas,cke,odt)
rslt_names=("early","nominal","late") rslt_names=("early","nominal","late")
timing=self.x393_mcntrl_timing.get_dly_steps() timing=self.x393_mcntrl_timing.get_dly_steps()
numPhaseSteps= int(timing['SDCLK_PERIOD']/timing['PHASE_STEP']+0.5) numPhaseSteps= int(timing['SDCLK_PERIOD']/timing['PHASE_STEP']+0.5)
...@@ -3389,15 +3750,6 @@ class X393McntrlAdjust(object): ...@@ -3389,15 +3750,6 @@ class X393McntrlAdjust(object):
elif not keep_all: elif not keep_all:
delays_phase[phase]=None delays_phase[phase]=None
continue # next phase continue # next phase
"""
delays_phase[phase]['in']=k # found solution
delays_phase[phase]['dqi']=dqi
break
else:
delays_phase[phase]=None # phase for at least one of the DQSI is invalid
continue # next phase
"""
if filter_dqo: if filter_dqo:
dqso=[None if wlev_lane[phase] is None else wlev_lane[phase]['ldly'] for wlev_lane in wlev_dqs_bspe] dqso=[None if wlev_lane[phase] is None else wlev_lane[phase]['ldly'] for wlev_lane in wlev_dqs_bspe]
if (None in dqso) and (not keep_all): if (None in dqso) and (not keep_all):
...@@ -3422,14 +3774,6 @@ class X393McntrlAdjust(object): ...@@ -3422,14 +3774,6 @@ class X393McntrlAdjust(object):
elif not keep_all: elif not keep_all:
delays_phase[phase]=None delays_phase[phase]=None
continue # next phase continue # next phase
"""
delays_phase[phase]['out']=k # found solution
delays_phase[phase]['dqo']=dqo
break
else:
delays_phase[phase]=None # phase for at least one of the DQSI is invalid
continue # next phase
"""
if quiet <1: if quiet <1:
print("delays_phase=",delays_phase) print("delays_phase=",delays_phase)
if quiet < 2: if quiet < 2:
...@@ -3502,7 +3846,8 @@ class X393McntrlAdjust(object): ...@@ -3502,7 +3846,8 @@ class X393McntrlAdjust(object):
print("A%d"%(i),end=" ") print("A%d"%(i),end=" ")
for i in range(num_banks): for i in range(num_banks):
print("BA%d"%(i),end=" ") print("BA%d"%(i),end=" ")
print("RCW",end=" ") # TODO - modify when separate command line data will be available print ("WE RAS CAS AVG", end=" ") # AVG - average for address, banks, RCW
# print("RCW",end=" ") # TODO - modify when separate command line data will be available
# num_addr=vrlg.ADDRESS_NUMBER # num_addr=vrlg.ADDRESS_NUMBER
# num_banks=3 # num_banks=3
for lane in range(numLanes): for lane in range(numLanes):
......
py393/x393_mcntrl_tests.py
View file @ 5449c194
...@@ -28,22 +28,12 @@ __version__ = "3.0+" ...@@ -28,22 +28,12 @@ __version__ = "3.0+"
__maintainer__ = "Andrey Filippov" __maintainer__ = "Andrey Filippov"
__email__ = "andrey@elphel.com" __email__ = "andrey@elphel.com"
__status__ = "Development" __status__ = "Development"
#import sys
#import x393_mem
#x393_pio_sequences
#from import_verilog_parameters import VerilogParameters
from x393_mem import X393Mem from x393_mem import X393Mem
#from x393_axi_control_status import X393AxiControlStatus
import x393_axi_control_status import x393_axi_control_status
from x393_pio_sequences import X393PIOSequences from x393_pio_sequences import X393PIOSequences
from x393_mcntrl_timing import X393McntrlTiming from x393_mcntrl_timing import X393McntrlTiming
from x393_mcntrl_buffers import X393McntrlBuffers from x393_mcntrl_buffers import X393McntrlBuffers
#from x393_mcntrl_adjust import X393McntrlAdjust
#from verilog_utils import * # concat, bits
#from verilog_utils import hx, concat, bits, getParWidth
from verilog_utils import concat,convert_w32_to_mem16 #, getParWidth from verilog_utils import concat,convert_w32_to_mem16 #, getParWidth
#from x393_axi_control_status import concat, bits
#from time import sleep
import vrlg import vrlg
class X393McntrlTests(object): class X393McntrlTests(object):
DRY_MODE= True # True DRY_MODE= True # True
...@@ -58,13 +48,11 @@ class X393McntrlTests(object): ...@@ -58,13 +48,11 @@ class X393McntrlTests(object):
self.DEBUG_MODE= debug_mode self.DEBUG_MODE= debug_mode
self.DRY_MODE= dry_mode self.DRY_MODE= dry_mode
self.x393_mem= X393Mem(debug_mode,dry_mode) self.x393_mem= X393Mem(debug_mode,dry_mode)
# self.x393_axi_tasks= X393AxiControlStatus(debug_mode,dry_mode)
self.x393_axi_tasks=x393_axi_control_status.X393AxiControlStatus(debug_mode,dry_mode) self.x393_axi_tasks=x393_axi_control_status.X393AxiControlStatus(debug_mode,dry_mode)
self.x393_pio_sequences= X393PIOSequences(debug_mode,dry_mode) self.x393_pio_sequences= X393PIOSequences(debug_mode,dry_mode)
self.x393_mcntrl_timing= X393McntrlTiming(debug_mode,dry_mode) self.x393_mcntrl_timing= X393McntrlTiming(debug_mode,dry_mode)
self.x393_mcntrl_buffers= X393McntrlBuffers(debug_mode,dry_mode) self.x393_mcntrl_buffers= X393McntrlBuffers(debug_mode,dry_mode)
# self.x393_mcntrl_adjust= X393McntrlAdjust(debug_mode,dry_mode) # self.x393_mcntrl_adjust= X393McntrlAdjust(debug_mode,dry_mode)
# self.__dict__.update(VerilogParameters.__dict__["_VerilogParameters__shared_state"]) # Add verilog parameters to the class namespace
try: try:
self.verbose=vrlg.VERBOSE self.verbose=vrlg.VERBOSE
except: except:
...@@ -231,6 +219,8 @@ class X393McntrlTests(object): ...@@ -231,6 +219,8 @@ class X393McntrlTests(object):
<quiet> reduce output <quiet> reduce output
returns a pair of ratios for getting "1" for 2 lanes and problem marker (should be 0) returns a pair of ratios for getting "1" for 2 lanes and problem marker (should be 0)
""" """
self.x393_pio_sequences.set_write_lev(16) # write leveling, 16 times (full buffer - 128)
if not dqs_odly is None: if not dqs_odly is None:
self.x393_mcntrl_timing.axi_set_dqs_odelay(dqs_odly) self.x393_mcntrl_timing.axi_set_dqs_odelay(dqs_odly)
# Set write buffer (from DDR3) WE signal delay for write leveling mode # Set write buffer (from DDR3) WE signal delay for write leveling mode
...@@ -239,6 +229,7 @@ class X393McntrlTests(object): ...@@ -239,6 +229,7 @@ class X393McntrlTests(object):
rslt= self.x393_pio_sequences.write_levelling( rslt= self.x393_pio_sequences.write_levelling(
wait_complete, wait_complete,
16, # number of 8-bursts
quiet) quiet)
#restore values to defaults (only if changed) #restore values to defaults (only if changed)
if not dqs_odly is None: if not dqs_odly is None:
......
py393/x393_mcntrl_timing.py
View file @ 5449c194
...@@ -438,9 +438,9 @@ class X393McntrlTiming(object): ...@@ -438,9 +438,9 @@ class X393McntrlTiming(object):
# print ("===axi_set_multiple_delays(0x%x,%d,%s"%(reg_addr,number,delay)) # print ("===axi_set_multiple_delays(0x%x,%d,%s"%(reg_addr,number,delay))
if delay is None: return # Do nothing, that's OK if delay is None: return # Do nothing, that's OK
if isinstance(delay,(int,long)): if isinstance(delay,(int,long)):
delay=(delay,)*number delay=[delay]*number
if len(delay) < number: if len(delay) < number:
delay= delay + (None,)*(number-len(delay)) # delay= delay + [None]*(number-len(delay)) #
for i, d in enumerate(delay): for i, d in enumerate(delay):
if not d is None: if not d is None:
self.x393_axi_tasks.write_contol_register(reg_addr + (offset + i), d) self.x393_axi_tasks.write_contol_register(reg_addr + (offset + i), d)
......
py393/x393_pio_sequences.py
View file @ 5449c194
...@@ -710,6 +710,7 @@ class X393PIOSequences(object): ...@@ -710,6 +710,7 @@ class X393PIOSequences(object):
def set_write_lev(self, def set_write_lev(self,
nrep, #input[CMD_PAUSE_BITS-1:0]nrep; nrep, #input[CMD_PAUSE_BITS-1:0]nrep;
make_bad=False, # do not turn write levelling mode on to test device is not stuck
verbose=0): verbose=0):
""" """
Setup write levelling sequence at parameter defined address in the sequencer memory Setup write levelling sequence at parameter defined address in the sequencer memory
...@@ -737,7 +738,10 @@ class X393PIOSequences(object): ...@@ -737,7 +738,10 @@ class X393PIOSequences(object):
cmd_addr = vrlg.MCONTR_CMD_WR_ADDR + vrlg.WRITELEV_OFFSET cmd_addr = vrlg.MCONTR_CMD_WR_ADDR + vrlg.WRITELEV_OFFSET
# Enter write leveling mode # Enter write leveling mode
# addr bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST # addr bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
data=self.func_encode_cmd(bits(mr1_wlev,(14,0)), bits(mr1_wlev,(17,15)), 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0) if make_bad:
data=self.func_encode_cmd(bits(mr1_norm,(14,0)),bits(mr1_norm,(17,15)),7,0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
else:
data=self.func_encode_cmd(bits(mr1_wlev,(14,0)),bits(mr1_wlev,(17,15)),7,0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
self.x393_mem.axi_write_single_w(cmd_addr, data, verbose) self.x393_mem.axi_write_single_w(cmd_addr, data, verbose)
cmd_addr += 1 cmd_addr += 1
# skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST # skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
...@@ -970,14 +974,16 @@ class X393PIOSequences(object): ...@@ -970,14 +974,16 @@ class X393PIOSequences(object):
def write_levelling(self, def write_levelling(self,
wait_complete=1, # Wait for operation to complete wait_complete=1, # Wait for operation to complete
nburst=16,
quiet=1): quiet=1):
""" """
Read data in write levelling mode Read data in write levelling mode
<wait_complete> wait write levelling operation to complete (0 - may initiate multiple PS PIO operations) @param wait_complete wait write levelling operation to complete (0 - may initiate multiple PS PIO operations)
<quiet> reduce output @param nburst number of 8-bursts written (should match sequence!)
returns a pair of ratios for getting "1" for 2 lanes and problem marker (should be 0) @param quiet reduce output
@eturn a pair of ratios for getting "1" for 2 lanes and problem marker (should be 0)
""" """
numBufWords=32 # twice nrep in set_write_lev numBufWords=2*nburst # twice nrep in set_write_lev
self.wait_ps_pio_done(vrlg.DEFAULT_STATUS_MODE,1); # not no interrupt running cycle - delays are changed immediately self.wait_ps_pio_done(vrlg.DEFAULT_STATUS_MODE,1); # not no interrupt running cycle - delays are changed immediately
self.schedule_ps_pio (# schedule software-control memory operation (may need to check FIFO status first) self.schedule_ps_pio (# schedule software-control memory operation (may need to check FIFO status first)
vrlg.WRITELEV_OFFSET, # input [9:0] seq_addr; # sequence start address vrlg.WRITELEV_OFFSET, # input [9:0] seq_addr; # sequence start address
...@@ -1088,10 +1094,10 @@ class X393PIOSequences(object): ...@@ -1088,10 +1094,10 @@ class X393PIOSequences(object):
# enable output for address/commands to DDR chip # enable output for address/commands to DDR chip
self.x393_axi_tasks.enable_cmda(1) self.x393_axi_tasks.enable_cmda(1)
self.x393_axi_tasks.activate_sdrst(1) # reset DDR3 self.x393_axi_tasks.activate_sdrst(1) # reset DDR3
sleep(0.1) sleep(0.001)
# remove reset from DDR3 chip # remove reset from DDR3 chip
self.x393_axi_tasks.activate_sdrst(0) # was enabled at system reset self.x393_axi_tasks.activate_sdrst(0) # was enabled at system reset
sleep(0.1) # actually 500 usec required sleep(0.001) # actually 500 usec required
self.x393_axi_tasks.enable_cke(1); self.x393_axi_tasks.enable_cke(1);
self.x393_axi_tasks.enable_memcntrl_channels(0x3) # only channel 0 and 1 are enabled self.x393_axi_tasks.enable_memcntrl_channels(0x3) # only channel 0 and 1 are enabled
......
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