Commit 5449c194 authored by Andrey Filippov's avatar Andrey Filippov

added measurement/adjustment of WE, RAS, CAS delays

parent 494d6c95
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......@@ -28,22 +28,12 @@ __version__ = "3.0+"
__maintainer__ = "Andrey Filippov"
__email__ = "andrey@elphel.com"
__status__ = "Development"
#import sys
#import x393_mem
#x393_pio_sequences
#from import_verilog_parameters import VerilogParameters
from x393_mem import X393Mem
#from x393_axi_control_status import X393AxiControlStatus
import x393_axi_control_status
from x393_pio_sequences import X393PIOSequences
from x393_mcntrl_timing import X393McntrlTiming
from x393_mcntrl_buffers import X393McntrlBuffers
#from x393_mcntrl_adjust import X393McntrlAdjust
#from verilog_utils import * # concat, bits
#from verilog_utils import hx, concat, bits, getParWidth
from verilog_utils import concat,convert_w32_to_mem16 #, getParWidth
#from x393_axi_control_status import concat, bits
#from time import sleep
import vrlg
class X393McntrlTests(object):
DRY_MODE= True # True
......@@ -58,13 +48,11 @@ class X393McntrlTests(object):
self.DEBUG_MODE= debug_mode
self.DRY_MODE= dry_mode
self.x393_mem= X393Mem(debug_mode,dry_mode)
# self.x393_axi_tasks= X393AxiControlStatus(debug_mode,dry_mode)
self.x393_axi_tasks=x393_axi_control_status.X393AxiControlStatus(debug_mode,dry_mode)
self.x393_pio_sequences= X393PIOSequences(debug_mode,dry_mode)
self.x393_mcntrl_timing= X393McntrlTiming(debug_mode,dry_mode)
self.x393_mcntrl_buffers= X393McntrlBuffers(debug_mode,dry_mode)
# self.x393_mcntrl_adjust= X393McntrlAdjust(debug_mode,dry_mode)
# self.__dict__.update(VerilogParameters.__dict__["_VerilogParameters__shared_state"]) # Add verilog parameters to the class namespace
try:
self.verbose=vrlg.VERBOSE
except:
......@@ -231,6 +219,8 @@ class X393McntrlTests(object):
<quiet> reduce output
returns a pair of ratios for getting "1" for 2 lanes and problem marker (should be 0)
"""
self.x393_pio_sequences.set_write_lev(16) # write leveling, 16 times (full buffer - 128)
if not dqs_odly is None:
self.x393_mcntrl_timing.axi_set_dqs_odelay(dqs_odly)
# Set write buffer (from DDR3) WE signal delay for write leveling mode
......@@ -239,6 +229,7 @@ class X393McntrlTests(object):
rslt= self.x393_pio_sequences.write_levelling(
wait_complete,
16, # number of 8-bursts
quiet)
#restore values to defaults (only if changed)
if not dqs_odly is None:
......
......@@ -438,9 +438,9 @@ class X393McntrlTiming(object):
# print ("===axi_set_multiple_delays(0x%x,%d,%s"%(reg_addr,number,delay))
if delay is None: return # Do nothing, that's OK
if isinstance(delay,(int,long)):
delay=(delay,)*number
delay=[delay]*number
if len(delay) < number:
delay= delay + (None,)*(number-len(delay)) #
delay= delay + [None]*(number-len(delay)) #
for i, d in enumerate(delay):
if not d is None:
self.x393_axi_tasks.write_contol_register(reg_addr + (offset + i), d)
......
......@@ -710,6 +710,7 @@ class X393PIOSequences(object):
def set_write_lev(self,
nrep, #input[CMD_PAUSE_BITS-1:0]nrep;
make_bad=False, # do not turn write levelling mode on to test device is not stuck
verbose=0):
"""
Setup write levelling sequence at parameter defined address in the sequencer memory
......@@ -737,7 +738,10 @@ class X393PIOSequences(object):
cmd_addr = vrlg.MCONTR_CMD_WR_ADDR + vrlg.WRITELEV_OFFSET
# Enter write leveling mode
# addr bank RCW ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD NOP, B_RST
data=self.func_encode_cmd(bits(mr1_wlev,(14,0)), bits(mr1_wlev,(17,15)), 7, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
if make_bad:
data=self.func_encode_cmd(bits(mr1_norm,(14,0)),bits(mr1_norm,(17,15)),7,0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
else:
data=self.func_encode_cmd(bits(mr1_wlev,(14,0)),bits(mr1_wlev,(17,15)),7,0, 0, 0, 0, 0, 0, 0, 0, 0, 0, 0)
self.x393_mem.axi_write_single_w(cmd_addr, data, verbose)
cmd_addr += 1
# skip done bank ODT CKE SEL DQEN DQSEN DQSTGL DCI B_WR B_RD B_RST
......@@ -970,14 +974,16 @@ class X393PIOSequences(object):
def write_levelling(self,
wait_complete=1, # Wait for operation to complete
nburst=16,
quiet=1):
"""
Read data in write levelling mode
<wait_complete> wait write levelling operation to complete (0 - may initiate multiple PS PIO operations)
<quiet> reduce output
returns a pair of ratios for getting "1" for 2 lanes and problem marker (should be 0)
@param wait_complete wait write levelling operation to complete (0 - may initiate multiple PS PIO operations)
@param nburst number of 8-bursts written (should match sequence!)
@param quiet reduce output
@eturn a pair of ratios for getting "1" for 2 lanes and problem marker (should be 0)
"""
numBufWords=32 # twice nrep in set_write_lev
numBufWords=2*nburst # twice nrep in set_write_lev
self.wait_ps_pio_done(vrlg.DEFAULT_STATUS_MODE,1); # not no interrupt running cycle - delays are changed immediately
self.schedule_ps_pio (# schedule software-control memory operation (may need to check FIFO status first)
vrlg.WRITELEV_OFFSET, # input [9:0] seq_addr; # sequence start address
......@@ -1088,10 +1094,10 @@ class X393PIOSequences(object):
# enable output for address/commands to DDR chip
self.x393_axi_tasks.enable_cmda(1)
self.x393_axi_tasks.activate_sdrst(1) # reset DDR3
sleep(0.1)
sleep(0.001)
# remove reset from DDR3 chip
self.x393_axi_tasks.activate_sdrst(0) # was enabled at system reset
sleep(0.1) # actually 500 usec required
sleep(0.001) # actually 500 usec required
self.x393_axi_tasks.enable_cke(1);
self.x393_axi_tasks.enable_memcntrl_channels(0x3) # only channel 0 and 1 are enabled
......
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