Commit 4bc39b80 authored by Andrey Filippov's avatar Andrey Filippov

CRC for LWIR sensor

parent 2d6880d4
/*!
* <b>Module:</b> crc16_x16x12x5x0
* @file crc16_x16x12x5x0.v
* @date 2019-03-31
* @author Andrey Filippov
*
* @brief calculates CRC x^16+x^12+x^5+x^0 16-bit parallel
*
* @copyright Copyright (c) 2019 Elphel, Inc.
*
* <b>License </b>
*
* crc16_x16x12x5x0.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* crc16_x16x12x5x0.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module crc16_x16x12x5x0(
input clk,
input srst,
input en,
input [15:0] din,
output [15:0] dout
);
reg [15:0] crc;
assign dout = crc;
always@ (posedge clk) begin
if (srst) crc <= 0;
else if (en) crc <= din ^ {
crc[10]^crc[3]^crc[7]^crc[11],
crc[14]^crc[9]^crc[2],
crc[1]^crc[12]^crc[6]^crc[10]^crc[14]^crc[5]^crc[9],
crc[12]^crc[7]^crc[0]^crc[4]^crc[15],
crc[11]^crc[15]^crc[6]^crc[10]^crc[14],
crc[10]^crc[14]^crc[5]^crc[9]^crc[13],
crc[9]^crc[13]^crc[4]^crc[15]^crc[8]^crc[12],
crc[8]^crc[12]^crc[3]^crc[14]^crc[7]^crc[11]^crc[15],
crc[7]^crc[11]^crc[15]^crc[2]^crc[13],
crc[1]^crc[12]^crc[5]^crc[9]^crc[13],
crc[5]^crc[9]^crc[13]^crc[0]^crc[11]^crc[4]^crc[8]^crc[12],
crc[4]^crc[15]^crc[8]^crc[12],
crc[3]^crc[14]^crc[7]^crc[11]^crc[15],
crc[2]^crc[13],
crc[1]^crc[12]^crc[6]^crc[10]^crc[14]^crc[5]^crc[9]^crc[13],
crc[0]^crc[11]^crc[4]^crc[8]^crc[12]
};
end
endmodule
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