Commit 4bacb90a authored by Andrey Filippov's avatar Andrey Filippov
Browse files

write leveling done, working on write buffer

parent 1b719ff1

.settings/com.elphel.vdt.iverilog.prefs

+2 −1
Original line number Diff line number Diff line 
com.elphel.store.context.iverilog=iverilog_81_TopModulesOther<-@\#\#@->iverilog_83_ExtraFiles<-@\#\#@->iverilog_88_ShowNoProblem<-@\#\#@->iverilog_77_Param_Exe<-@\#\#@->iverilog_78_VVP_Exe<-@\#\#@->iverilog_99_GrepFindErrWarn<-@\#\#@->

com.elphel.store.context.iverilog=iverilog_81_TopModulesOther<-@\#\#@->iverilog_83_ExtraFiles<-@\#\#@->iverilog_88_ShowNoProblem<-@\#\#@->iverilog_77_Param_Exe<-@\#\#@->iverilog_78_VVP_Exe<-@\#\#@->iverilog_99_GrepFindErrWarn<-@\#\#@->iverilog_84_IncludeDir<-@\#\#@->

eclipse.preferences.version=1

iverilog_77_Param_Exe=/usr/local/bin/iverilog

iverilog_78_VVP_Exe=/usr/local/bin/vvp

iverilog_81_TopModulesOther=glbl<-@\#\#@->

iverilog_83_ExtraFiles=glbl.v<-@\#\#@->

iverilog_84_IncludeDir=/data/vdt/vdt-projects/eddr3/ddr3<-@\#\#@->

iverilog_88_ShowNoProblem=true

iverilog_99_GrepFindErrWarn=error|warning|sorry

ddr3/ddr3.v

+3 −3
Original line number Diff line number Diff line
@@ -115,7 +115,7 @@ module ddr3 ( 
`elsif den2048Mb

    `include "2048Mb_ddr3_parameters.vh"

`elsif den4096Mb

    `include "ddr3/4096Mb_ddr3_parameters.vh"

    `include "4096Mb_ddr3_parameters.vh"

`else

    // NOTE: Intentionally cause a compile fail here to force the users

    //       to select the correct component density before continuing
@@ -606,11 +606,11 @@ module ddr3 ( 
            floor = number;

    endfunction



    function integer max( input integer a, b );

    function integer max( input integer a, input integer b );

        max = (a < b) ? b : a;

    endfunction



    function integer min( input integer a, b );

    function integer min( input integer a, input integer b );

        min = (a > b) ? b : a;

    endfunction

ddrc_test01.v

+4 −4
Original line number Diff line number Diff line
@@ -43,8 +43,8 @@ module ddrc_test01 #( 
    parameter SS_EN =              "FALSE",

    parameter SS_MODE =      "CENTER_HIGH",

    parameter SS_MOD_PERIOD =       10000,

    parameter CMD_PAUSE_BITS=       6,

    parameter CMD_DONE_BIT=         6,

    parameter CMD_PAUSE_BITS=       10,

    parameter CMD_DONE_BIT=         10,

    parameter AXI_WR_ADDR_BITS =    13,

    parameter AXI_RD_ADDR_BITS =    13,

    parameter CONTROL_ADDR =        'h1000, // AXI write address of control write registers
@@ -92,10 +92,10 @@ module ddrc_test01 #( 
    output                       SDODT, // output ODT port



    inout                 [15:0] SDD,   // DQ  I/O pads

    inout                        SDDML, // LDM  I/O pad (actually only output)

    output                       SDDML, // LDM  I/O pad (actually only output)

    inout                        DQSL,  // LDQS I/O pad

    inout                        NDQSL, // ~LDQS I/O pad

    inout                        SDDMU, // UDM  I/O pad (actually only output)

    output                       SDDMU, // UDM  I/O pad (actually only output)

    inout                        DQSU,  // UDQS I/O pad

    inout                        NDQSU // ~UDQS I/O pad

    // AXI write (ps -> pl)