Commit 4bacb90a authored by Andrey Filippov's avatar Andrey Filippov

write leveling done, working on write buffer

parent 1b719ff1
com.elphel.store.context.iverilog=iverilog_81_TopModulesOther<-@\#\#@->iverilog_83_ExtraFiles<-@\#\#@->iverilog_88_ShowNoProblem<-@\#\#@->iverilog_77_Param_Exe<-@\#\#@->iverilog_78_VVP_Exe<-@\#\#@->iverilog_99_GrepFindErrWarn<-@\#\#@->
com.elphel.store.context.iverilog=iverilog_81_TopModulesOther<-@\#\#@->iverilog_83_ExtraFiles<-@\#\#@->iverilog_88_ShowNoProblem<-@\#\#@->iverilog_77_Param_Exe<-@\#\#@->iverilog_78_VVP_Exe<-@\#\#@->iverilog_99_GrepFindErrWarn<-@\#\#@->iverilog_84_IncludeDir<-@\#\#@->
eclipse.preferences.version=1
iverilog_77_Param_Exe=/usr/local/bin/iverilog
iverilog_78_VVP_Exe=/usr/local/bin/vvp
iverilog_81_TopModulesOther=glbl<-@\#\#@->
iverilog_83_ExtraFiles=glbl.v<-@\#\#@->
iverilog_84_IncludeDir=/data/vdt/vdt-projects/eddr3/ddr3<-@\#\#@->
iverilog_88_ShowNoProblem=true
iverilog_99_GrepFindErrWarn=error|warning|sorry
......@@ -115,7 +115,7 @@ module ddr3 (
`elsif den2048Mb
`include "2048Mb_ddr3_parameters.vh"
`elsif den4096Mb
`include "ddr3/4096Mb_ddr3_parameters.vh"
`include "4096Mb_ddr3_parameters.vh"
`else
// NOTE: Intentionally cause a compile fail here to force the users
// to select the correct component density before continuing
......@@ -606,11 +606,11 @@ module ddr3 (
floor = number;
endfunction
function integer max( input integer a, b );
function integer max( input integer a, input integer b );
max = (a < b) ? b : a;
endfunction
function integer min( input integer a, b );
function integer min( input integer a, input integer b );
min = (a > b) ? b : a;
endfunction
......
......@@ -43,8 +43,8 @@ module ddrc_test01 #(
parameter SS_EN = "FALSE",
parameter SS_MODE = "CENTER_HIGH",
parameter SS_MOD_PERIOD = 10000,
parameter CMD_PAUSE_BITS= 6,
parameter CMD_DONE_BIT= 6,
parameter CMD_PAUSE_BITS= 10,
parameter CMD_DONE_BIT= 10,
parameter AXI_WR_ADDR_BITS = 13,
parameter AXI_RD_ADDR_BITS = 13,
parameter CONTROL_ADDR = 'h1000, // AXI write address of control write registers
......@@ -92,10 +92,10 @@ module ddrc_test01 #(
output SDODT, // output ODT port
inout [15:0] SDD, // DQ I/O pads
inout SDDML, // LDM I/O pad (actually only output)
output SDDML, // LDM I/O pad (actually only output)
inout DQSL, // LDQS I/O pad
inout NDQSL, // ~LDQS I/O pad
inout SDDMU, // UDM I/O pad (actually only output)
output SDDMU, // UDM I/O pad (actually only output)
inout DQSU, // UDQS I/O pad
inout NDQSU // ~UDQS I/O pad
// AXI write (ps -> pl)
......
[*]
[*] GTKWave Analyzer v3.3.49 (w)1999-2013 BSI
[*] Wed May 28 07:13:39 2014
[*] Fri May 30 07:35:38 2014
[*]
[dumpfile] "/data/vdt/vdt-projects/eddr3/simulation/ddrc_test01_testbench-20140528005647850.lxt"
[dumpfile_mtime] "Wed May 28 07:00:13 2014"
[dumpfile_size] 48289383
[dumpfile] "/data/vdt/vdt-projects/eddr3/simulation/ddrc_test01_testbench-20140530013238993.lxt"
[dumpfile_mtime] "Fri May 30 07:33:55 2014"
[dumpfile_size] 55044338
[savefile] "/data/vdt/vdt-projects/eddr3/ddrc_test01_testbench.sav"
[timestart] 109441730
[timestart] 117839420
[size] 1920 1180
[pos] -1920 108
*-13.962209 109532898 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
*-11.298908 117840830 117826250 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] ddrc_test01_testbench.
[treeopen] ddrc_test01_testbench.ddrc_test01_i.
[treeopen] ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.
......@@ -18,14 +18,19 @@
[treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.
[treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.
[treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.
[treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.
[treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.
[treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.
[treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.oserdes_i.
[treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.oserdes_i.oserdes_i.
[treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.idelay_ctrl_i.
[treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.
[treeopen] ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.pll_base_i.PLLE2_BASE_i.plle2_adv_1.
[treeopen] ddrc_test01_testbench.simul_axi_master_wdata_i.
[sst_width] 210
[signals_width] 368
[treeopen] ddrc_test01_testbench.simul_axi_master_wraddr_i.
[sst_width] 334
[signals_width] 427
[sst_expanded] 1
[sst_vpaned_height] 820
[sst_vpaned_height] 723
@28
ddrc_test01_testbench.RST[0]
ddrc_test01_testbench.CLK[0]
......@@ -786,6 +791,140 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.idelay_
@1401200
-idelay_ctrl_i
@c00200
-byte_lane0_i
@28
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.clk[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.clk_div[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dci_disable_dq[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dci_disable_dq_r[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dci_disable_dqs[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dci_disable_dqs_r[0]
@c00022
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.decode_sel[9:0]
@28
(0)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.decode_sel[9:0]
(1)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.decode_sel[9:0]
(2)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.decode_sel[9:0]
(3)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.decode_sel[9:0]
(4)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.decode_sel[9:0]
(5)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.decode_sel[9:0]
(6)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.decode_sel[9:0]
(7)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.decode_sel[9:0]
(8)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.decode_sel[9:0]
(9)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.decode_sel[9:0]
@1401200
-group_end
@22
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.din[31:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.din_dm[3:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.din_dm_r[3:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.din_dqs[3:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.din_dqs_r[3:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.din_r[31:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dly_addr[4:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dly_data[7:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dly_data_r[7:0]
@28
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dm[0]
@22
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dout[31:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dq[7:0]
@28
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_read[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.iclk[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.inv_clk_div[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.ld_delay[0]
@22
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.ld_idly[7:0]
@28
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@22
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.ld_odly[7:0]
@28
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.ld_odly_dm[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.ld_odly_dqs[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.ndqs[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.rst[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.set[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.set_r[0]
@22
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.tin_dq[3:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.tin_dq_r[3:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.tin_dqs[3:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.tin_dqs_r[3:0]
@1401200
-byte_lane0_i
@c00200
-lane0_dqs
@28
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.clk[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.clk_div[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.d_ser[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.dci_disable[0]
@22
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.din[3:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.dly_data[7:0]
@28
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.dqs[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.dqs_data_dly[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.dqs_di[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.dqs_received_dly[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.dqs_tri[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.ld_idelay[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.ld_odelay[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.ndqs[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.rst[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.set_idelay[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.set_odelay[0]
@22
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane0_i.dqs_i.tin[3:0]
@1401200
-lane0_dqs
@c00200
-lane1_dqs
@28
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.clk[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.clk_div[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.d_ser[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.dci_disable[0]
@22
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.din[3:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.dly_data[7:0]
@28
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.dqs[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.dqs_data_dly[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.dqs_di[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.dqs_received_dly[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.dqs_tri[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.ld_idelay[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.ld_odelay[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.ndqs[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.rst[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.set_idelay[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.set_odelay[0]
@22
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.tin[3:0]
@c00200
-oserdes_i
@28
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.oserdes_i.clk[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.oserdes_i.clk_div[0]
@22
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.oserdes_i.din[3:0]
@28
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.oserdes_i.dout_dly[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.oserdes_i.dout_iob[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.oserdes_i.rst[0]
@22
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.oserdes_i.tin[3:0]
@28
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.oserdes_i.tout_dly[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.byte_lane1_i.dqs_i.oserdes_i.tout_iob[0]
@1401200
-oserdes_i
-lane1_dqs
@c00200
-ddrc_control_i
@28
ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.busy[0]
......@@ -845,6 +984,21 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.wdata_fifo_out_r[31:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.wr_en[0]
@1401200
-ddrc_control_i
@800200
-ddrc_status
@28
ddrc_test01_testbench.ddrc_test01_i.ddrc_status_i.busy[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_status_i.locked[0]
@22
ddrc_test01_testbench.ddrc_test01_i.ddrc_status_i.ps_out[7:0]
@28
ddrc_test01_testbench.ddrc_test01_i.ddrc_status_i.ps_rdy[0]
@22
ddrc_test01_testbench.ddrc_test01_i.ddrc_status_i.rdata[31:0]
@28
ddrc_test01_testbench.ddrc_test01_i.ddrc_status_i.run_busy[0]
@1000200
-ddrc_status
@c00200
-fifo_cross_clocks
@22
......@@ -878,7 +1032,7 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.fifo_cross_clocks_i.wclk[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_control_i.fifo_cross_clocks_i.we[0]
@1401200
-fifo_cross_clocks
@800200
@c00200
-phy_cmd_i
@28
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.SDRST[0]
......@@ -886,9 +1040,27 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.DQSL[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.DQSU[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.NDQSL[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.NDQSU[0]
@22
@c00022
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.SDA[14:0]
@28
(0)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.SDA[14:0]
(1)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.SDA[14:0]
(2)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.SDA[14:0]
(3)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.SDA[14:0]
(4)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.SDA[14:0]
(5)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.SDA[14:0]
(6)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.SDA[14:0]
(7)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.SDA[14:0]
(8)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.SDA[14:0]
(9)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.SDA[14:0]
(10)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.SDA[14:0]
(11)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.SDA[14:0]
(12)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.SDA[14:0]
(13)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.SDA[14:0]
(14)ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.SDA[14:0]
@1401200
-group_end
@28
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.SDBA[2:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.SDCAS[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.SDCKE[0]
......@@ -934,7 +1106,6 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.locked_r1[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.locked_r2[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.mclk[0]
@22
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.pause_len[5:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_addr[29:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_addr_in[14:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_bank[5:0]
......@@ -943,9 +1114,7 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_bank_in[2:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_buf_rd[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_buf_wr[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_cke[1:0]
@29
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_cke_dis[0]
@28
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_cke_in[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_cmd_nop[0]
@22
......@@ -979,7 +1148,6 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_rdata[63:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_rdata_r[63:0]
@28
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_sel_in[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_spare[2:0]
@22
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.ps_out[7:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.ps_out_r1[7:0]
......@@ -992,7 +1160,7 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.rst_in[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.sequence_done[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.set[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.set_r[0]
@1000200
@1401200
-phy_cmd_i
@c00200
-ddrc_sequencer
......@@ -1077,8 +1245,6 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.locked[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.mclk[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.pause[0]
@22
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.pause_cntr[5:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.pause_len[5:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd0_word[31:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd1_word[31:0]
@28
......@@ -1130,9 +1296,11 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.sequence_done[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.set[0]
@1401200
-ddrc_sequencer
@800200
@c00200
-ddr_sequencer_i_selected
@28
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.clk[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_i.phy_top_i.sdclk[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.SDCLK[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.SDCKE[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.SDBA[2:0]
......@@ -1176,8 +1344,7 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.cmd_busy[2:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.cmd_fetch[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.pause[0]
@22
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.pause_cntr[5:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.pause_len[5:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.pause_cntr[9:0]
@28
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.phy_cmd_nop[0]
@22
......@@ -1192,7 +1359,7 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.run_done[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.run_seq[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.run_seq_d[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.sequence_done[0]
@1000200
@1401200
-ddr_sequencer_i_selected
@c00200
-ddrc_test01
......@@ -1338,6 +1505,7 @@ ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.aw_nempty[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.aw_nempty_ready[0]
@22
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.awaddr[31:0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.awaddr_out[12:0]
@28
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.awburst[1:0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.awburst_out[1:0]
......@@ -1397,7 +1565,74 @@ ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wstb[3:0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wstb_out[3:0]
@28
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wvalid[0]
@c00200
-axibram_write_waddr
@28
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.clk[0]
@22
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.data_in[32:0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.data_out[32:0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.fill[4:0]
@28
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.full[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.half_full[0]
@22
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.inreg[32:0]
@28
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.just_one[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.nempty[0]
@22
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.next_fill[4:0]
@28
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.out_full[0]
@22
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.outreg[32:0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.ra[3:0]
@28
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.re[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.rem[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.rst[0]
@22
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.wa[3:0]
@28
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.we[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.waddr_i.wem[0]
@1401200
-axibram_write_waddr
@c00200
-axibram_write_wdata
@28
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.clk[0]
@22
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.data_in[48:0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.data_out[48:0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.fill[4:0]
@28
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.full[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.half_full[0]
@22
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.inreg[48:0]
@28
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.just_one[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.nempty[0]
@22
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.next_fill[4:0]
@28
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.out_full[0]
@22
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.outreg[48:0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.ra[3:0]
@28
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.re[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.rem[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.rst[0]
@22
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.wa[3:0]
@28
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.we[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_write_i.wdata_i.wem[0]
@1401200
-axibram_write_wdata
-axibram_write_i
@c00200
-wresp_i
......@@ -1566,6 +1801,8 @@ ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.start_read_burst_1[0]
ddrc_test01_testbench.ddrc_test01_i.axibram_read_i.start_read_burst_w[0]
@1401200
-axibram_read_i
@c00200
-ddrc_status
@22
ddrc_test01_testbench.registered_rdata[31:0]
@28
......@@ -1587,6 +1824,8 @@ ddrc_test01_testbench.ddrc_test01_i.axird_pre_araddr[12:0]
ddrc_test01_testbench.ddrc_test01_i.axird_start_burst[0]
@22
ddrc_test01_testbench.GLOBAL_WRITE_ID[11:0]
@1401200
-ddrc_status
@c00200
-cmd0_buf_i
@22
......@@ -1606,15 +1845,187 @@ ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.cmd0_buf_i.we[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.cmd0_buf_i.web[3:0]
@1401200
-cmd0_buf_i
@c00200
-axi_set_dly_single
@22
ddrc_test01_testbench.axi_set_dly_single.delay[7:0]
ddrc_test01_testbench.axi_set_dly_single.dly[31:0]
@28
ddrc_test01_testbench.axi_set_dly_single.group[2:0]
@22
ddrc_test01_testbench.axi_set_dly_single.i[31:0]
ddrc_test01_testbench.axi_set_dly_single.index[4:0]
@1401200
-axi_set_dly_single
@c00200
-axi_write_single
@22
ddrc_test01_testbench.GLOBAL_WRITE_ID[11:0]
ddrc_test01_testbench.axi_write_single.address[31:0]
ddrc_test01_testbench.axi_write_single.data[31:0]
@1401200
-axi_write_single
@c00200
-axi_write_address_data
@28
ddrc_test01_testbench.DEBUG1[0]
ddrc_test01_testbench.AW_READY[0]
ddrc_test01_testbench.W_READY[0]
@22
ddrc_test01_testbench.WID_IN_r[11:0]
@28
ddrc_test01_testbench.CLK[0]
@22
ddrc_test01_testbench.axi_write_addr_data.addr[31:0]
@28
ddrc_test01_testbench.axi_write_addr_data.burst[1:0]
@22
ddrc_test01_testbench.axi_write_addr_data.data[31:0]
@28
ddrc_test01_testbench.axi_write_addr_data.data_en[0]
ddrc_test01_testbench.axi_write_addr_data.data_sent[0]
@22
ddrc_test01_testbench.axi_write_addr_data.id[11:0]
@28
ddrc_test01_testbench.axi_write_addr_data.last[0]
@22
ddrc_test01_testbench.axi_write_addr_data.len[3:0]
ddrc_test01_testbench.axi_write_addr_data.wstrb[3:0]
@1401200
-axi_write_address_data
@c00200
-simul_axi_master_wdata_i
@28
ddrc_test01_testbench.simul_axi_master_wdata_i.clk[0]
ddrc_test01_testbench.simul_axi_master_wdata_i.ready[0]
ddrc_test01_testbench.simul_axi_master_wdata_i.reset[0]
ddrc_test01_testbench.simul_axi_master_wdata_i.set_cmd[0]
@22
ddrc_test01_testbench.simul_axi_master_wdata_i.wdata[31:0]
ddrc_test01_testbench.simul_axi_master_wdata_i.wdata_in[31:0]
ddrc_test01_testbench.simul_axi_master_wdata_i.wdata_out[31:0]
ddrc_test01_testbench.simul_axi_master_wdata_i.wid[11:0]
ddrc_test01_testbench.simul_axi_master_wdata_i.wid_in[11:0]
ddrc_test01_testbench.simul_axi_master_wdata_i.wid_out[11:0]
@28
ddrc_test01_testbench.simul_axi_master_wdata_i.wlast[0]
ddrc_test01_testbench.simul_axi_master_wdata_i.wlast_in[0]
ddrc_test01_testbench.simul_axi_master_wdata_i.wlast_out[0]
ddrc_test01_testbench.simul_axi_master_wdata_i.wready[0]
@22
ddrc_test01_testbench.simul_axi_master_wdata_i.wstrb[3:0]
ddrc_test01_testbench.simul_axi_master_wdata_i.wstrb_in[3:0]
ddrc_test01_testbench.simul_axi_master_wdata_i.wstrb_out[3:0]
@28
ddrc_test01_testbench.simul_axi_master_wdata_i.wvalid[0]
ddrc_test01_testbench.simul_axi_master_wdata_i.wvalid_out[0]
@1401200
-simul_axi_master_wdata_i
@c00200
-simul_axi_master_wraddr_i
@22
ddrc_test01_testbench.simul_axi_master_wraddr_i.awaddr[31:0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.awaddr_in[31:0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.awaddr_out[31:0]
@28
ddrc_test01_testbench.simul_axi_master_wraddr_i.awburst[1:0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.awburst_in[1:0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.awburst_out[1:0]
@22
ddrc_test01_testbench.simul_axi_master_wraddr_i.awcache[3:0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.awcache_in[3:0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.awcache_out[3:0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.awid[11:0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.awid_in[11:0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.awid_out[11:0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.awlen[3:0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.awlen_in[3:0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.awlen_out[3:0]
@28
ddrc_test01_testbench.simul_axi_master_wraddr_i.awprot[2:0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.awprot_in[2:0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.awprot_out[2:0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.awready[0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.awsize[2:0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.awsize_in[2:0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.awsize_out[2:0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.awvalid[0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.awvalid_out[0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.clk[0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.ready[0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.reset[0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.set_cmd[0]
@1401200
-simul_axi_master_wraddr_i
@c00200
-simul_axi_master_wraddr_fifo
@28
ddrc_test01_testbench.simul_axi_master_wraddr_i.simul_axi_fifo_i.clk[0]
@22
ddrc_test01_testbench.simul_axi_master_wraddr_i.simul_axi_fifo_i.data_in[59:0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.simul_axi_fifo_i.data_out[59:0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.simul_axi_fifo_i.in_address[31:0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.simul_axi_fifo_i.in_count[31:0]
@28
ddrc_test01_testbench.simul_axi_master_wraddr_i.simul_axi_fifo_i.input_ready[0]
@22
ddrc_test01_testbench.simul_axi_master_wraddr_i.simul_axi_fifo_i.latency_delay[5:0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.simul_axi_fifo_i.latency_delay_r[4:0]
@28
ddrc_test01_testbench.simul_axi_master_wraddr_i.simul_axi_fifo_i.load[0]
@22
ddrc_test01_testbench.simul_axi_master_wraddr_i.simul_axi_fifo_i.out_address[31:0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.simul_axi_fifo_i.out_count[31:0]
@28
ddrc_test01_testbench.simul_axi_master_wraddr_i.simul_axi_fifo_i.out_inc[0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.simul_axi_fifo_i.ready[0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.simul_axi_fifo_i.reset[0]
ddrc_test01_testbench.simul_axi_master_wraddr_i.simul_axi_fifo_i.valid[0]
@1401200
-simul_axi_master_wraddr_fifo
@800200
-write_block
@28
ddrc_test01_testbench.SDCLK[0]
ddrc_test01_testbench.DQSL[0]
ddrc_test01_testbench.DQSU[0]
@22
ddrc_test01_testbench.SDA[14:0]
@28
ddrc_test01_testbench.SDBA[2:0]
ddrc_test01_testbench.SDRAS[0]
ddrc_test01_testbench.SDCAS[0]
ddrc_test01_testbench.SDWE[0]
ddrc_test01_testbench.SDCKE[0]
ddrc_test01_testbench.SDDML[0]
ddrc_test01_testbench.SDDMU[0]
@22
ddrc_test01_testbench.set_mrs.data[31:0]
ddrc_test01_testbench.set_mrs.cmd_addr[31:0]
ddrc_test01_testbench.set_mrs.data[31:0]
ddrc_test01_testbench.set_mrs.mr0[17:0]
ddrc_test01_testbench.set_mrs.mr1[17:0]
ddrc_test01_testbench.set_mrs.mr2[17:0]
ddrc_test01_testbench.set_mrs.mr3[17:0]
ddrc_test01_testbench.SDD[15:0]
@28
ddrc_test01_testbench.set_mrs.reset_dll[0]
ddrc_test01_testbench.SDODT[0]
ddrc_test01_testbench.SDRST[0]
@200
-
@28
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.run_seq[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.buf_rd[0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.buf_page[1:0]
@22
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.buf_raddr[8:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.buf_rdata[63:0]
@800200
-port1_wr
@28
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.port1_clk[0]
@22
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.port1_data[31:0]
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.port1_addr[7:0]
@28
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.port1_page[1:0]
@29
ddrc_test01_testbench.ddrc_test01_i.ddrc_sequencer_i.port1_we[0]
@1000200
-port1_wr
-write_block
[pattern_trace] 1
[pattern_trace] 0
......@@ -43,8 +43,8 @@ module ddrc_test01_testbench #(
parameter SS_EN = "FALSE",
parameter SS_MODE = "CENTER_HIGH",
parameter SS_MOD_PERIOD = 10000,
parameter CMD_PAUSE_BITS= 6,
parameter CMD_DONE_BIT= 6,
parameter CMD_PAUSE_BITS= 10,
parameter CMD_DONE_BIT= 10,
parameter AXI_WR_ADDR_BITS = 13,
parameter AXI_RD_ADDR_BITS = 13,
parameter CONTROL_ADDR = 'h1000, // AXI write address of control write registers
......@@ -94,6 +94,51 @@ module ddrc_test01_testbench #(
parameter lxtname = "x393.lxt";
`endif
`define DEBUG_WR_SINGLE 1
// SuppressWarnings VEditor
localparam BASEADDR_PORT0_RD = PORT0_RD_ADDR << 2; // 'h0000 << 2
// SuppressWarnings VEditor
localparam BASEADDR_PORT1_WR = PORT1_WR_ADDR << 2; // 'h0000 << 2 = 'h000
localparam BASEADDR_CMD0 = CMD0_ADDR << 2; // 'h0800 << 2 = 'h2000
// localparam BASEADDR_CTRL = CONTROL_ADDR << 2;
localparam BASEADDR_CTRL = (CONTROL_ADDR | BUSY_WR_ADDR) << 2; // with busy
localparam BASEADDR_STATUS = STATUS_ADDR << 2; // 'h0800 << 2 = 'h2000
localparam BASEADDR_DLY_LD = BASEADDR_CTRL | (DLY_LD_REL <<2); // 'h080, address to generate delay load
localparam BASEADDR_DLY_SET = BASEADDR_CTRL | (DLY_SET_REL<<2); // 'h070, address to generate delay set
localparam BASEADDR_RUN_CHN = BASEADDR_CTRL | (RUN_CHN_REL<<2); // 'h000, address to set sequnecer channel and run (4 LSB-s - channel)
// S uppressWarnings VEditor
localparam BASEADDR_PATTERNS =BASEADDR_CTRL | (PATTERNS_REL<<2); // 'h020, address to set DQM and DQS patterns (16'h0055)
// SuppressWarnings VEditor
localparam BASEADDR_PAGES = BASEADDR_CTRL | (PAGES_REL<<2); // 'h021, address to set buffer pages {port1_page[1:0],port1_int_page[1:0],port0_page[1:0],port0_int_page[1:0]}
localparam BASEADDR_CMDA_EN = BASEADDR_CTRL | (CMDA_EN_REL<<2); // 'h022, address to enable('h823)/disable('h822) command/address outputs
localparam BASEADDR_SDRST_ACT = BASEADDR_CTRL | (SDRST_ACT_REL<<2); // address to activate('h825)/deactivate('h824) active-low reset signal to DDR3 memory
localparam BASEADDR_CKE_EN = BASEADDR_CTRL | (CKE_EN_REL<<2); //
// SuppressWarnings VEditor
localparam BASEADDR_EXTRA = BASEADDR_CTRL | (EXTRA_REL<<2); // 'h028, address to set extra parameters (currently just inv_clk_div)
localparam BASEADDRESS_LANE0_ODELAY = BASEADDR_DLY_LD;
localparam BASEADDRESS_LANE0_IDELAY = BASEADDR_DLY_LD+('h10<<2);
localparam BASEADDRESS_LANE1_ODELAY = BASEADDR_DLY_LD+('h20<<2);
localparam BASEADDRESS_LANE1_IDELAY = BASEADDR_DLY_LD+('h30<<2);
localparam BASEADDRESS_CMDA = BASEADDR_DLY_LD+('h40<<2);
localparam BASEADDRESS_PHASE = BASEADDR_DLY_LD+('h60<<2);
localparam STATUS_PSHIFTER_RDY_MASK = 'h100;
// SuppressWarnings VEditor - not yet used
localparam STATUS_LOCKED_MASK = 'h200;
localparam STATUS_SEQ_BUSY_MASK = 'h400;
localparam DLY_LANE0_ODELAY= 80'h7574737271706f6e6d6c; // odelay dqm, odelay ddqs, odelay dq[7:0]
localparam DLY_LANE0_IDELAY= 72'h74737271706f6e6d6c; // idelay dqs, idelay dq[7:0
localparam DLY_LANE1_ODELAY= 80'h7574737271706f6e6d6c; // odelay dqm, odelay ddqs, odelay dq[7:0]
localparam DLY_LANE1_IDELAY= 72'h74737271706f6e6d6c; // idelay dqs, idelay dq[7:0
localparam DLY_CMDA= 256'h5f5e5d5c5b5a59585756555453525150004e4b4c4b4a49484746454443424140; // odelay odt, cke, cas, ras, we, ba2,ba1,ba0, X, a14,..,a0
localparam DLY_PHASE= 8'h1c; // mmcm fine phase shift, 1/4 tCK
// localparam DLY_PHASE= 8'hdb; // mmcm fine phase shift
localparam WRITELEV_OFFSET='h20; // write leveling start address (in words)
localparam WRITE_BLOCK_OFFSET='h100; // write block sequence start address (in words)
// DDR3 signals
wire SDRST;
wire SDCLK; // output
......@@ -253,16 +298,8 @@ always #(CLKIN_PERIOD/2) CLK <= ~CLK;
axi_set_b_lag(0); //(1);
axi_set_rd_lag(0);
axi_set_delays;
// write memory
// test_axi_1;
// read memory
// test_axi_2;
read_status; // ps ready goes false with some delay
// read_status;
wait_phase_shifter_ready;
// repeat (40) begin
// read_status;
// end
enable_cmda(1);
repeat (16) @(posedge CLK) ;
activate_sdrst(0); // was enabled at system reset
......@@ -271,10 +308,38 @@ always #(CLKIN_PERIOD/2) CLK <= ~CLK;
enable_cke(1);
repeat (16) @(posedge CLK) ;
set_mrs(1);
set_write_lev(16); // write leveling, 16 times
#100;
// $finish;
run_sequence(0);
//#100;
run_sequence(0,0);
wait_sequencer_ready(16);
axi_write_single(BASEADDR_PATTERNS, 32'h0055); // set patterns for DM (always 0) and DQS - always the same (may try different for write lev.)
run_sequence(0,WRITELEV_OFFSET);
wait_sequencer_ready(16);
axi_set_dly_single(0,8,'h80); // was 'h74 dqs lane 0, odelay
axi_set_dly_single(2,8,'hc0); // was 'h74 dqs lane 1, odelay
run_sequence(0,WRITELEV_OFFSET);
#140; // 140 ns delay 30; // 30 ns delay
axi_set_dly_single(2,8,'hb8); // was 'h74 dqs lane 1, odelay
#20