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Commit 47f19c8b authored by Andrey Filippov's avatar Andrey Filippov
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Debugging sequencer-based UART commands

parent da24e724
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Showing with 74 additions and 39 deletions
cocotb/x393_cocotb3_server.py
View file @ 47f19c8b
......@@ -24,19 +24,20 @@ to the simulator and sends back data from the model.
@license: GPLv3.0+
@contact: andrey@elphel.coml
"""
import asyncio
##import asyncio
import os
import cocotb
##import cocotb
import socket
import select
##import select
#import json
from socket_command import SocketCommand
from cocotb.triggers import Timer
from x393interfaces import MAXIGPMaster, PSBus, SAXIRdSim, SAXIWrSim
from cocotb.drivers import BitDriver
from cocotb.triggers import Timer, RisingEdge, ReadOnly
from cocotb.result import ReturnValue, TestFailure, TestError, TestSuccess
## from cocotb.drivers import BitDriver
from cocotb.triggers import RisingEdge ## Timer, ReadOnly
from cocotb.result import ReturnValue, TestFailure,TestSuccess ## TestError,
import cocotb.regression # added
import logging
import re
import struct
......
sensor/sens_103993_deser10.v
View file @ 47f19c8b
......@@ -61,13 +61,13 @@ module sens_103993_deser10(
reg [2:0] copy_r;
reg [11:0] sr;
reg [ 9:0] dout_pclk10;
always @(posedge pclk or posedge copy_r[2]) begin // re_simulate!
if (copy_r[2]) xclk_r <= 0;
always @(posedge pclk or posedge copy_r[1]) begin // re_simulate!
if (copy_r[1]) xclk_r <= 0;
else xclk_r <= 1;
end
always @ (negedge pclk10) begin
copy_r <= {copy_r[1] & ~copy_r[0], copy_r[0], xclk_r};
copy_r <= {copy_r[0] & ~copy_r[1], copy_r[0], xclk_r};
sr <= {sr[10:0], din};
if (copy_r[2]) dout_pclk10 <= sr[11:2];
end
......
sensor/sensor_i2c_prot.v
View file @ 47f19c8b
......@@ -125,16 +125,16 @@ module sensor_i2c_prot#(
reg [ 4:0] run_reg_ext_wr; // [4] - SA (attr), [3] - RA_msb (module) [2] - RA_lsb (func), [1] - DH, [0] - DL (DH, DL - optional)?
reg run_extra_wr_d; // any of run_extra_wr bits, delayed by 1
reg run_any_d; // any of command states, delayed by 1
reg [1:0] pre_cmd; // from i2c_start until run_any_d will be active
reg [1:0] pre_cmd; // from i2c_start until run_any_d will be active ** pre_cmd[1] never used?
reg first_mem_re;
reg [ 2:0] mem_re;
reg [ 3:0] mem_re;
reg mem_valid;
reg [ 2:0] table_re;
wire is_extif = (|tdout[SENSI2C_TBL_EXTIF +: SENSI2C_TBL_EXTIF_BITS]);
wire start_wr_seq_w = table_re[2] && !is_extif && !tdout[SENSI2C_TBL_RNWREG]; // [8]
wire start_rd_seq_w = table_re[2] && !is_extif && tdout[SENSI2C_TBL_RNWREG]; // [8]
wire start_extra_seq_w = i2c_start && (bytes_left_send !=0);
wire start_extra_seq_w = i2c_start && (bytes_left_send !=0) && !is_extif;
wire start_extif_w = table_re[2] && (is_extif);
reg snd_start;
......@@ -159,10 +159,10 @@ module sensor_i2c_prot#(
wire pre_next_cmd = (snd_start || snd_stop || snd9) && i2c_rdy;
wire next_byte_wr_w;
// reg next_byte_wr;
reg next_byte_wr_or_ext; // write byte or extrenal command
reg next_byte_wr_or_ext; // write byte or external command
reg extif_dav_r;
reg extif_run;
wire extif_next_w;
/// wire extif_next_w;
// reg extif_ackn;
wire pre_next_extif = extif_run && extif_ready && extif_dav && !next_cmd && !next_cmd_d; // TODO: Verify last terms
......@@ -179,19 +179,25 @@ module sensor_i2c_prot#(
reg [ 7:0] extif_byte_r;
reg [ 1:0] extif_sel_r;
wire extif_last;
reg extif_ackn_d;
wire extif_ackn;
wire extif_inc; // sent and acknowledged byte
assign seq_mem_re = mem_re[1:0];
assign next_byte_wr_w = snd9 && i2c_rdy && !run_reg_wr[5] && !rnw;
assign extif_dav = extif_dav_r;
assign extif_next_w = |run_reg_ext_wr[3:0];
/// assign extif_next_w = |run_reg_ext_wr[3:0];
// assign extif_sa = extif_sa_r;
assign extif_byte = extif_byte_r;
assign extif_sel = extif_sel_r;
// sequencer interface now always 5 bytes form the sequencer! (no need for extif_last - remove)
assign extif_last = bytes_left_send == 0;
// assign extif_last = extif_last_w;
assign extif_ackn = extif_dav && extif_ready;
assign extif_inc = extif_ackn && !extif_ackn_d && !extif_last;
always @ (posedge mclk) begin
extif_ackn_d <= extif_ackn;
if (mrst || i2c_rst || start_wr_seq_w) rnw <= 0;
else if (start_rd_seq_w) rnw <= 1;
run_extra_wr_d <= |run_extra_wr;
......@@ -228,13 +234,13 @@ module sensor_i2c_prot#(
if (table_re[2]) extif_byte_r <= {1'b0, tdout[SENSI2C_TBL_SA +: SENSI2C_TBL_SA_BITS]};
else if (next_cmd && extif_run) extif_byte_r <= run_reg_ext_wr[4]? reg_ah : seq_rd;
next_cmd <= pre_next_cmd || pre_next_extif;
// next_cmd <= pre_next_cmd || pre_next_extif;
next_cmd <= extif_run? pre_next_extif : pre_next_cmd;
next_cmd_d <= next_cmd;
// same time as next_cmd, no pulse when sending SA during write
// next_byte_wr <= next_byte_wr_w; // snd9 && i2c_rdy && !run_reg_wr[5] && !rnw; // (|run_reg_rd); // same time as next_cmd, no pulse when sending SA during write
next_byte_wr_or_ext <= next_byte_wr_w || extif_next_w;
next_byte_wr_or_ext <= next_byte_wr_w || extif_inc; // extif_next_w;
// counting bytes (and address) in extif mode also
if (mrst || i2c_rst) bytes_left_send <= 0;
......@@ -249,8 +255,9 @@ module sensor_i2c_prot#(
else if (extif_ready && extif_dav && extif_last) extif_run <= 0;
if (mrst || i2c_rst) extif_dav_r <= 0;
else if (start_extif_w || (extif_run && mem_re[2]) || (run_reg_ext_wr[3] && next_cmd_d)) extif_dav_r <= 1;
else if (next_cmd) extif_dav_r <= 0;
else if (start_extif_w || (extif_run && mem_re[3]) || (run_reg_ext_wr[3] && next_cmd_d)) extif_dav_r <= 1;
// else if (next_cmd) extif_dav_r <= 0;
else if (pre_next_extif) extif_dav_r <= 0;
// calculate stages for each type of commands
// start and write sa and some bytes, stop if number of bytes <= 4 at the end
......@@ -259,7 +266,9 @@ module sensor_i2c_prot#(
else if (next_cmd) run_reg_ext_wr <= {1'b0, // SA (attr)
run_reg_ext_wr[4], // RA_msb (module) - always after SA (attr)
run_reg_ext_wr[3], // RA_lsb (func)
run_reg_ext_wr[2] & (num_bytes_send == 4'h2), // DH
// normally always use num_bytes_send== 4, then it can be just a shift register (for variable
// need to modify consumer)
run_reg_ext_wr[2] & (num_bytes_send[1] | num_bytes_send[2]), // 2 or 4 bytes (num_bytes_send == 4'h2), // DH
run_reg_ext_wr[1] | (run_reg_ext_wr[2] & (num_bytes_send == 4'h1)) // DL
};
......@@ -310,7 +319,7 @@ module sensor_i2c_prot#(
run_reg_rd[1] & (read_data_bytes == 3'h1)
};
// read sequencer memory byte (for the current word)
mem_re <= {mem_re[1:0], i2c_start | next_cmd_d & (
mem_re <= {mem_re[2:0], i2c_start | next_cmd_d & (
(~extif_last & (|run_reg_ext_wr[3:0])) |
(|run_reg_wr[3:1]) |
(|run_extra_wr[4:1]) |
......@@ -318,7 +327,7 @@ module sensor_i2c_prot#(
initial_address <= initial_address_w[1:0]; // if bytes left to send is 0 mod 4 - will be 3 (read MSB)
seq_mem_ra <= i2c_start ? initial_address : { // run_extra_wr[4] is not needed - it will be read by i2c_start
run_reg_wr[3] | run_extra_wr[3] | run_reg_rd[6] | run_reg_ext_wr[3], //?
run_reg_wr[2] | run_extra_wr[2] | run_reg_rd[5] | run_reg_ext_wr[1] //?
run_reg_wr[2] | run_extra_wr[2] | run_reg_rd[5] | (run_reg_ext_wr[2] & (num_bytes_send[1] | num_bytes_send[2]))//?
};
if (mrst || i2c_rst || i2c_start || next_cmd ) mem_valid <= 0;
else if (mem_re[2]) mem_valid <= 1;
......
sensor/serial_103993.v
View file @ 47f19c8b
......@@ -103,6 +103,7 @@ module serial_103993#(
reg xmit_run; // runing soft xmit
reg xmit_run_d; // runing soft xmit, delayed
reg extif_run; // running xmit from the sequencer
reg extif_run_in; // receiving bytes from extif
reg extif_run_d; // running xmit from the sequencer
wire [ 7:0] xmit_extif_data; // data byte to transmit from the sequencer
reg xmit_stb_fifo;
......@@ -123,6 +124,7 @@ module serial_103993#(
wire xmit_start_out_seq;
wire xmit_start_out;
reg xmit_done; // any mode - soft or seq;
reg xmit_extif_done; // simultaneously with xmit_done, only it will increment sequence number
wire extif_rq_w;
wire [ 7:0] xmit_any_data;
wire xmit_stb_any;
......@@ -137,6 +139,7 @@ module serial_103993#(
wire packet_over_seq;
// wire recv_end; // Discard recv_data, this is packet end
wire recv_prgrs; // packet is being received (to distinguish eop from data byte)
wire xmit_run_any;
assign extif_rq_w = packet_ready_seq && !extif_run && !packet_over_seq;
assign xmit_any_data = extif_run ? xmit_extif_data : xmit_fifo_out;
......@@ -146,10 +149,12 @@ module serial_103993#(
assign xmit_start_out_seq = extif_run && !extif_run_d;
assign xmit_start_out = xmit_start_out_fifo || xmit_start_out_seq;
// TODO: is !xmit_stb_d needed?
assign pre_tx_stb = !xmit_stb_any && !xmit_stb_d && !xmit_over_d && !mrst && !xmit_rst && !extif_rst && xmit_run && tx_rdy;
/// assign pre_tx_stb = !xmit_stb_any && !xmit_stb_d && !xmit_over_d && !mrst && !xmit_rst && !extif_rst && xmit_run && tx_rdy;
assign pre_tx_stb = !xmit_stb_any && !xmit_stb_d && !xmit_over_d && !mrst && !xmit_rst && !extif_rst && xmit_run_any && tx_rdy;
assign xmit_busy = xmit_busy_r;
assign recv_fifo_wr = fslp_stb_or_done;
assign recv_pav = recv_pav_r;
assign xmit_run_any = xmit_run || extif_run;
// assign recv_eop = recv_end;
always @(posedge mclk) begin
fslp_stb_or_done <= fslp_rx_stb || fslp_rx_done;
......@@ -164,8 +169,10 @@ module serial_103993#(
xmit_busy_r <= uart_tx_busy || stuffer_busy_d || xmit_pend || xmit_run || extif_run;
if (mrst || xmit_rst) xmit_pend <= 0;
// else if (xmit_start) xmit_pend <= 1;
// else if (xmit_start_out_fifo) xmit_pend <= 0;
else if (xmit_start) xmit_pend <= 1;
else if (xmit_start_out_fifo) xmit_pend <= 0;
else if (xmit_start_out) xmit_pend <= 0;
if (mrst || xmit_rst) xmit_run <= 0;
else if (xmit_pend && !xmit_run && !extif_run) xmit_run <= 1;
......@@ -177,19 +184,27 @@ module serial_103993#(
else if (!xmit_run && !xmit_pend && extif_rq_w) extif_run <= 1;
else if (xmit_done) extif_run <= 0; // no need to condition with xmit_run
extif_run_d <= extif_run && !mrst && !extif_rst;
if (mrst || xmit_rst || !packet_ready_seq) extif_run_in <= 0;
else if (extif_rq_w) extif_run_in <= 1;
else if (packet_over_seq) extif_run_in <= 0;
xmit_stb_d <= xmit_stb_any;
xmit_over_d <= xmit_over;
stuffer_busy_d <= stuffer_busy;
xmit_done <= stuffer_busy_d && !stuffer_busy;
xmit_extif_done <= stuffer_busy_d && !stuffer_busy && extif_run;
// transmit soft (from fifo) (FIFO should always be not empty until last byte (should nit be replenished)
xmit_stb_fifo <= pre_tx_stb && xmit_fifo_nempty; // also advances FIFO read
xmit_over_fifo <= pre_tx_stb && !xmit_fifo_nempty;
// Generate sequencer packet and transmit it
xmit_stb_seq <= pre_tx_stb && packet_ready_seq;
/// xmit_stb_seq <= pre_tx_stb && packet_ready_seq;
xmit_stb_seq <= pre_tx_stb && extif_run_in;
xmit_over_seq <= pre_tx_stb && packet_over_seq;
end
......@@ -205,11 +220,11 @@ module serial_103993#(
.extif_byte (extif_byte), // input[7:0]
.extif_ready (extif_ready), // output
.extif_rst (extif_rst), // input
.packet_ready (packet_ready_seq), // output
.packet_ready (packet_ready_seq),// output
.packet_byte (xmit_extif_data), // output[7:0]
.packet_byte_stb (xmit_stb_seq), // input
.packet_over (packet_over_seq), // output
.packet_sent (xmit_done) // input
.packet_sent (xmit_extif_done) // input
);
......
sensor/serial_103993_extif.v
View file @ 47f19c8b
......@@ -58,7 +58,7 @@ module serial_103993_extif #(
input [7:0] extif_byte, // data to external interface (first - extif_sa)
output extif_ready, // acknowledges extif_dav
input extif_rst, // reset seq xmit and sequence number
output packet_ready,// packet ready, later next packet byte ready
output packet_ready,// packet ready, later next packet byte ready (just >=4 bytes got now?)
output [7:0] packet_byte,
input packet_byte_stb, // packet byte read out - should be >2(?) cycles apart
// output packet_byte_rdy, // packet byte ready
......@@ -86,22 +86,32 @@ module serial_103993_extif #(
reg [15:0] seq_num; // 16-bit sequence number
reg [7:0] packet_byte_r;
reg [1:0] packet_byte_stb_d;
assign packet_ready = in_bytes[2] && !packet_byte_stb_d[0] && !packet_byte_stb_d[1]; //
assign recv_start = !packet_nempty_r && extif_en && extif_dav && (extif_sel == EXTIF_MODE) && extif_ready_r;
assign recv_next = packet_nempty_r && extif_dav && !extif_ready_r;
assign reset_in_bytes = mrst || extif_rst || !packet_nempty_r;
/// reg packet_xmit_busy; // after packet got from the sequencer and until it is transmitted out
/// assign packet_ready = in_bytes[2] && !packet_byte_stb_d[0] && !packet_byte_stb_d[1]; //
assign packet_ready = in_bytes[2]; // && !packet_byte_stb_d[0] && !packet_byte_stb_d[1]; //
// recv_start needs extif_ready_r, extif_ready_r needs recv_start ??
assign recv_start = !packet_nempty_r && extif_en && extif_dav && (extif_sel == EXTIF_MODE); // && extif_ready_r;
/// assign recv_next = packet_nempty_r && extif_dav && !extif_ready_r; // should wait when extif_byte is used (1-st OK, it is not xmitted)
assign recv_next = packet_nempty_r && extif_dav && !extif_ready_r && !packet_ready; // should wait when extif_byte is used (1-st OK, it is not xmitted)
// assign reset_in_bytes = mrst || extif_rst || !packet_nempty_r;
assign reset_in_bytes = mrst || extif_rst || !packet_nempty_r || packet_sent;
assign packet_byte = packet_byte_r;
assign extif_ready = extif_ready_r;
/// assign extif_ready = extif_ready_r && !packet_ready;
assign packet_over = packet_gen_state[17];
always @(posedge mclk) begin
/// if (mrst || extif_rst) packet_xmit_busy <= 0;
/// else packet_byte_stb_d <= {packet_byte_stb_d[0], packet_byte_stb};
if (mrst || extif_rst) packet_byte_stb_d <= 0;
else packet_byte_stb_d <= {packet_byte_stb_d[0], packet_byte_stb};
if (mrst || extif_rst || !extif_dav) extif_ready_r <= 0;
else if (recv_start || recv_next) extif_ready_r <= 1;
// else if (recv_start || recv_next) extif_ready_r <= 1;
else if (recv_start || (recv_next && !packet_ready)) extif_ready_r <= 1;
if (mrst || extif_rst) packet_nempty_r <= 0;
......
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