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Commit 46f1a6c9 authored by Andrey Filippov's avatar Andrey Filippov
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Continue debugging 256-cycle Bayer MCLT

parent a5e4cd6e
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dsp/dtt_iv_8x8_ad.v
View file @ 46f1a6c9
...@@ -76,6 +76,7 @@ module dtt_iv_8x8_ad#( ...@@ -76,6 +76,7 @@ module dtt_iv_8x8_ad#(
output reg out_we, //!< output data valid (write to external buffer output reg out_we, //!< output data valid (write to external buffer
output reg sub16, //!< Subtract 16 from the full output address when true output reg sub16, //!< Subtract 16 from the full output address when true
output reg inc16, //!< increment full output address by 16 output reg inc16, //!< increment full output address by 16
output reg start16, //!< reset/copy page address
output reg start_out); //!< may start output readout, 1 entry per clock, vertically output reg start_out); //!< may start output readout, 1 entry per clock, vertically
// 1. Two 16xINPUT_WIDTH memories to feed two of the 'horizontal' 1-dct - they should provide outputs shifted by 1 clock // 1. Two 16xINPUT_WIDTH memories to feed two of the 'horizontal' 1-dct - they should provide outputs shifted by 1 clock
...@@ -383,7 +384,8 @@ module dtt_iv_8x8_ad#( ...@@ -383,7 +384,8 @@ module dtt_iv_8x8_ad#(
sub16 <= ~out_cntr[3] & ~out_cntr[0] & out_run; sub16 <= ~out_cntr[3] & ~out_cntr[0] & out_run;
inc16 <= out_cntr[3:0] == 'he; inc16 <= out_cntr[3:0] == 'he;
out_we <= dctv_out_we[1]; out_we <= dctv_out_we[1];
start_out <= start_out_w; start_out <= start_out_w;
start16 <= dctv_phin [6:0] == 'h11;
end end
always @ (posedge clk) begin always @ (posedge clk) begin
......
dsp/mclt16x16_bayer.v
View file @ 46f1a6c9
...@@ -292,7 +292,8 @@ module mclt16x16_bayer#( ...@@ -292,7 +292,8 @@ module mclt16x16_bayer#(
always @(posedge clk) begin always @(posedge clk) begin
if (rst) dtt_out_ram_cntr <= 0; if (rst) dtt_out_ram_cntr <= 0;
else if (dtt_inc16) dtt_out_ram_cntr <= dtt_out_ram_cntr + 1; else if (dtt_inc16) dtt_out_ram_cntr <= dtt_out_ram_cntr + 1; // make it copy input page?
dtt_out_ram_wah <= dtt_out_ram_cntr - dtt_sub16; dtt_out_ram_wah <= dtt_out_ram_cntr - dtt_sub16;
dtt_start_first_fill <= dtt_start_fill & dtt_first_quad_out; dtt_start_first_fill <= dtt_start_fill & dtt_first_quad_out;
...@@ -368,8 +369,6 @@ module mclt16x16_bayer#( ...@@ -368,8 +369,6 @@ module mclt16x16_bayer#(
.data_in ({{(36-DTT_IN_WIDTH){1'b0}}, data_dtt_in}) // input[35:0] .data_in ({{(36-DTT_IN_WIDTH){1'b0}}, data_dtt_in}) // input[35:0]
); );
dtt_iv_8x8_ad #( dtt_iv_8x8_ad #(
.INPUT_WIDTH (DTT_IN_WIDTH), .INPUT_WIDTH (DTT_IN_WIDTH),
.OUT_WIDTH (OUT_WIDTH), .OUT_WIDTH (OUT_WIDTH),
...@@ -393,7 +392,8 @@ module mclt16x16_bayer#( ...@@ -393,7 +392,8 @@ module mclt16x16_bayer#(
.out_wa (dtt_out_wa16), // output[3:0] reg .out_wa (dtt_out_wa16), // output[3:0] reg
.out_we (dtt_out_we), // output reg .out_we (dtt_out_we), // output reg
.sub16 (dtt_sub16), // output reg .sub16 (dtt_sub16), // output reg
.inc16 (dtt_inc16), // output reg .inc16 (dtt_inc16), // output reg
.start16 (), // output reg
.start_out (dtt_start_fill) // output[24:0] signed .start_out (dtt_start_fill) // output[24:0] signed
); );
//[DTT_IN_WIDTH-1:0 //[DTT_IN_WIDTH-1:0
......
dsp/mclt16x16_bayer3.v
View file @ 46f1a6c9
...@@ -48,7 +48,7 @@ module mclt16x16_bayer3#( ...@@ -48,7 +48,7 @@ module mclt16x16_bayer3#(
parameter OUT_WIDTH = 25, // bits in dtt output parameter OUT_WIDTH = 25, // bits in dtt output
parameter DTT_IN_WIDTH = 25, // bits in DTT input parameter DTT_IN_WIDTH = 25, // bits in DTT input
parameter TRANSPOSE_WIDTH = 25, // width of the transpose memory (intermediate results) parameter TRANSPOSE_WIDTH = 25, // width of the transpose memory (intermediate results)
parameter OUT_RSHIFT = 2, // overall right shift of the result from input, aligned by MSB (>=3 will never cause saturation) parameter OUT_RSHIFT1 = 2, // overall right shift of the result from input, aligned by MSB (>=3 will never cause saturation)
parameter OUT_RSHIFT2 = 0, // overall right shift for the second (vertical) pass parameter OUT_RSHIFT2 = 0, // overall right shift for the second (vertical) pass
parameter DSP_B_WIDTH = 18, // signed, output from sin/cos ROM parameter DSP_B_WIDTH = 18, // signed, output from sin/cos ROM
parameter DSP_A_WIDTH = 25, parameter DSP_A_WIDTH = 25,
...@@ -58,6 +58,7 @@ module mclt16x16_bayer3#( ...@@ -58,6 +58,7 @@ module mclt16x16_bayer3#(
input clk, //!< system clock, posedge input clk, //!< system clock, posedge
input rst, //!< sync reset input rst, //!< sync reset
input start, //!< start convertion of the next 256 samples input start, //!< start convertion of the next 256 samples
input page, //!< parameter page number (valid @ start)
input [1:0] tile_size, //!< o: 16x16, 1 - 18x18, 2 - 20x20, 3 - 22x22 (max for 9-bit addr) input [1:0] tile_size, //!< o: 16x16, 1 - 18x18, 2 - 20x20, 3 - 22x22 (max for 9-bit addr)
input [1:0] color_wa, //!< color index to apply parameters to (0 - R, 1 - B, 2 - G) input [1:0] color_wa, //!< color index to apply parameters to (0 - R, 1 - B, 2 - G)
input inv_checker, //!< 0 - includes main diagonal (symmetrical DTT), 1 - antisymmetrical DTT input inv_checker, //!< 0 - includes main diagonal (symmetrical DTT), 1 - antisymmetrical DTT
...@@ -78,10 +79,18 @@ module mclt16x16_bayer3#( ...@@ -78,10 +79,18 @@ module mclt16x16_bayer3#(
input [PIXEL_WIDTH-1:0] pix_d, //!< pixel data, latency = 2 from pixel address input [PIXEL_WIDTH-1:0] pix_d, //!< pixel data, latency = 2 from pixel address
output pre_busy, //!< start should come each 256-th cycle (next after pre_last_in), and not after pre_busy) output pre_busy, //!< start should come each 256-th cycle (next after pre_last_in), and not after pre_busy)
output pre_last_in, //!< may increment page output pre_last_in, //!< may increment page
output pre_first_out,//!< next will output first of DCT/DCT coefficients output pre_first_out_r,//!< next will output first of DCT/DCT coefficients
output pre_last_out, //!< next will be last output of DST/DST coefficients output pre_first_out_b,//!< next will output first of DCT/DCT coefficients
output [7:0] out_addr, //!< address to save coefficients, 2 MSBs - mode (CC,SC,CS,SS), others - down first output pre_first_out_g,//!< next will output first of DCT/DCT coefficients
output dv, //!< output data valid output pre_last_out_r, //!< next will be last output of DST/DST coefficients
output pre_last_out_b, //!< next will be last output of DST/DST coefficients
output pre_last_out_g, //!< next will be last output of DST/DST coefficients
output [8:0] out_addr_r, //!< address to save coefficients: page, 2 bits - mode (CC,SC,CS,SS), others - down first
output [8:0] out_addr_b, //!< address to save coefficients: page, 2 bits - mode (CC,SC,CS,SS), others - down first
output [8:0] out_addr_g, //!< address to save coefficients: page, 2 bits - mode (CC,SC,CS,SS), others - down first
output dv_r, //!< output data valid
output dv_b, //!< output data valid
output dv_g, //!< output data valid
output signed [OUT_WIDTH - 1 : 0] dout_r, //!<frequency domain data output for red color components output signed [OUT_WIDTH - 1 : 0] dout_r, //!<frequency domain data output for red color components
output signed [OUT_WIDTH - 1 : 0] dout_b, //!<frequency domain data output for blue color components output signed [OUT_WIDTH - 1 : 0] dout_b, //!<frequency domain data output for blue color components
output signed [OUT_WIDTH - 1 : 0] dout_g //!<frequency domain data output for green color components output signed [OUT_WIDTH - 1 : 0] dout_g //!<frequency domain data output for green color components
...@@ -90,8 +99,13 @@ module mclt16x16_bayer3#( ...@@ -90,8 +99,13 @@ module mclt16x16_bayer3#(
// When defined, use 2 DSP multipleierts // When defined, use 2 DSP multipleierts
// `define DSP_ACCUM_FOLD 1 // `define DSP_ACCUM_FOLD 1
localparam DTT_OUT_DELAY = 128; // 191; // start output to sin/cos rotator, with checker - 2*64 +/=?
localparam DTT_IN_DELAY = 63; // 69; // wa -ra min = 1 localparam DTT_IN_DELAY = 63; // 69; // wa -ra min = 1
// localparam DTT_OUT_DELAY = 128; // 191; // start output to sin/cos rotator, with checker - 2*64 +/=?
// May be tweaked so outputs will appear simultaneously
localparam DTT_OUT_DELAY_R = 64; // 191; // start output to sin/cos rotator, with checker - 2*64 +/=?
localparam DTT_OUT_DELAY_B = 64; // 191; // start output to sin/cos rotator, with checker - 2*64 +/=?
localparam DTT_OUT_DELAY_G = 128; // 191; // start output to sin/cos rotator, with checker - 2*64 +/=?
reg [7:0] in_cntr; // reg [7:0] in_cntr; //
reg run_r; reg run_r;
...@@ -124,7 +138,7 @@ module mclt16x16_bayer3#( ...@@ -124,7 +138,7 @@ module mclt16x16_bayer3#(
reg valid_odd_ram[0:3]; // reg valid_odd_ram[0:3]; //
reg [SHIFT_WIDTH-1:0] x_shft_ram[0:3]; // reg [SHIFT_WIDTH-1:0] x_shft_ram[0:3]; //
reg [SHIFT_WIDTH-1:0] y_shft_ram[0:3]; // reg [SHIFT_WIDTH-1:0] y_shft_ram[0:3]; //
reg reg_rot_page; // odd/even register sets for long latency (rotator) // reg reg_rot_page; // odd/even register sets for long latency (rotator)
reg [1:0] regs_wa; reg [1:0] regs_wa;
reg inv_checker_rot_ram[0:7]; // reg inv_checker_rot_ram[0:7]; //
reg valid_odd_rot_ram[0:7]; // reg valid_odd_rot_ram[0:7]; //
...@@ -136,6 +150,12 @@ module mclt16x16_bayer3#( ...@@ -136,6 +150,12 @@ module mclt16x16_bayer3#(
reg valid_odd_ram_reg; // reg valid_odd_ram_reg; //
reg [SHIFT_WIDTH-1:0] x_shft_ram_reg; // reg [SHIFT_WIDTH-1:0] x_shft_ram_reg; //
reg [SHIFT_WIDTH-1:0] y_shft_ram_reg; // reg [SHIFT_WIDTH-1:0] y_shft_ram_reg; //
reg [1:0] rot_ram_copy;
reg [2:0] rot_ram_page;
reg inv_checker_rot_ram_reg; //
reg valid_odd_rot_ram_reg; //
reg [SHIFT_WIDTH-1:0] x_shft_rot_ram_reg; //
reg [SHIFT_WIDTH-1:0] y_shft_rot_ram_reg; //
// todo: add registers to read into rotators // todo: add registers to read into rotators
...@@ -155,8 +175,8 @@ module mclt16x16_bayer3#( ...@@ -155,8 +175,8 @@ module mclt16x16_bayer3#(
y_shft_rf_ram_reg <= y_shft_rf_ram[in_cntr[1:0]]; y_shft_rf_ram_reg <= y_shft_rf_ram[in_cntr[1:0]];
end end
if (rst) reg_rot_page <= 1; // if (rst) reg_rot_page <= 1;
else if (start) reg_rot_page <= ~reg_rot_page; // else if (start) reg_rot_page <= ~reg_rot_page;
if (copy_regs[1]) begin if (copy_regs[1]) begin
inv_checker_ram[regs_wa] <= inv_checker_rf_ram_reg; inv_checker_ram[regs_wa] <= inv_checker_rf_ram_reg;
...@@ -165,10 +185,10 @@ module mclt16x16_bayer3#( ...@@ -165,10 +185,10 @@ module mclt16x16_bayer3#(
x_shft_ram[regs_wa] <= x_shft_rf_ram_reg; x_shft_ram[regs_wa] <= x_shft_rf_ram_reg;
y_shft_ram[regs_wa] <= y_shft_rf_ram_reg; y_shft_ram[regs_wa] <= y_shft_rf_ram_reg;
inv_checker_rot_ram[{reg_rot_page,regs_wa}] <= inv_checker_rf_ram_reg; inv_checker_rot_ram[{page,regs_wa}] <= inv_checker_rf_ram_reg;
valid_odd_rot_ram[{reg_rot_page,regs_wa}] <= valid_odd_rf_ram_reg; valid_odd_rot_ram[{page,regs_wa}] <= valid_odd_rf_ram_reg;
x_shft_rot_ram[{reg_rot_page,regs_wa}] <= x_shft_rf_ram_reg; x_shft_rot_ram[{page,regs_wa}] <= x_shft_rf_ram_reg;
y_shft_rot_ram[{reg_rot_page,regs_wa}] <= y_shft_rf_ram_reg; y_shft_rot_ram[{page,regs_wa}] <= y_shft_rf_ram_reg;
end end
start_block_r <= {start_block_r[0], ((in_cntr[5:0] == 1) && (in_cntr[7:6] != 3))?1'b1:1'b0}; start_block_r <= {start_block_r[0], ((in_cntr[5:0] == 1) && (in_cntr[7:6] != 3))?1'b1:1'b0};
...@@ -180,6 +200,15 @@ module mclt16x16_bayer3#( ...@@ -180,6 +200,15 @@ module mclt16x16_bayer3#(
y_shft_ram_reg <= y_shft_ram[in_cntr[7:6]]; y_shft_ram_reg <= y_shft_ram[in_cntr[7:6]];
end end
if (rot_ram_copy[1]) begin
inv_checker_rot_ram_reg <= inv_checker_rot_ram[rot_ram_page];
valid_odd_rot_ram_reg <= valid_odd_rot_ram[rot_ram_page];
x_shft_rot_ram_reg <= x_shft_rot_ram[rot_ram_page];
y_shft_rot_ram_reg <= y_shft_rot_ram[rot_ram_page];
end
//rot_ram_page rot_ram_copy
end end
`ifdef DSP_ACCUM_FOLD `ifdef DSP_ACCUM_FOLD
...@@ -204,7 +233,7 @@ module mclt16x16_bayer3#( ...@@ -204,7 +233,7 @@ module mclt16x16_bayer3#(
// assign pre_last_out = pre_last_out_r; // assign pre_last_out = pre_last_out_r;
// assign pre_busy = pre_busy_r || start || (!pre_last_in_w && phases[0]); assign pre_busy = pre_busy_r || start || (!pre_last_in_w && phases[0]);
assign pre_last_in = pre_last_in_w; assign pre_last_in = pre_last_in_w;
mclt_bayer_fold_rgb #( mclt_bayer_fold_rgb #(
...@@ -307,14 +336,22 @@ module mclt16x16_bayer3#( ...@@ -307,14 +336,22 @@ module mclt16x16_bayer3#(
wire dtt_out_we; wire dtt_out_we;
wire dtt_sub16; wire dtt_sub16;
wire dtt_inc16; wire dtt_inc16;
wire dtt_start16;
wire dtt_start_red = (dtt_start16 & dtt_r_cntr[7:6] == 1); // after
wire dtt_start_blue = (dtt_start16 & dtt_r_cntr[7:6] == 2); // after
wire dtt_start_green = (dtt_start16 & dtt_r_cntr[7:6] == 3); // after
reg [4:0] dtt_out_ram_cntr; reg [4:0] dtt_out_ram_cntr;
reg [4:0] dtt_out_ram_wah; reg [4:0] dtt_out_ram_wah;
reg [1:0] dtt_out_ram_wpage; // one of 4 pages (128 samples long) being written to // reg [1:0] dtt_out_ram_wpage; // one of 4 pages (128 samples long) being written to
reg [1:0] dtt_out_ram_wpage2; // later by 1 DTT // reg dtt_out_ram_wpage; // one of 2 pages (256 samples long) being written to
// reg [1:0] dtt_out_ram_wpage2; // later by 1 DTT
// reg dtt_out_ram_wpage2; // later by 1 DTT
wire dtt_start_fill; // some data available in DTT output buffer, OK to start consecutive readout wire dtt_start_fill; // some data available in DTT output buffer, OK to start consecutive readout
reg dtt_start_first_fill; // reg dtt_start_first_fill;
reg dtt_start_second_fill; reg dtt_start_red_fill;
reg [1:0] dtt_start_out; // start read out to sin/cos rotator reg dtt_start_blue_fill;
reg dtt_start_green_fill;
// reg dtt_start_second_fill;
wire [8:0] dtt_out_ram_wa = {dtt_out_ram_wah,dtt_out_wa16}; wire [8:0] dtt_out_ram_wa = {dtt_out_ram_wah,dtt_out_wa16};
...@@ -325,13 +362,11 @@ module mclt16x16_bayer3#( ...@@ -325,13 +362,11 @@ module mclt16x16_bayer3#(
wire dtt_out_we_b = dtt_out_we & ~dtt_out_ram_wa[7] & dtt_out_ram_wa[6]; wire dtt_out_we_b = dtt_out_we & ~dtt_out_ram_wa[7] & dtt_out_ram_wa[6];
wire dtt_out_we_g = dtt_out_we & dtt_out_ram_wa[7]; wire dtt_out_we_g = dtt_out_we & dtt_out_ram_wa[7];
reg [7:0] dtt_dly_cntr;
reg [8:0] dtt_rd_cntr_pre; // 1 ahead of the former counter for dtt readout to rotator
reg [8:0] dtt_rd_ra0; wire [1:0] dtt_rd_regen_r; // dtt output buffer mem read, register enable, data valid
reg [8:0] dtt_rd_ra1; wire [1:0] dtt_rd_regen_g; // dtt output buffer mem read, register enable, data valid
wire [1:0] dtt_rd_regen_b; // dtt output buffer mem read, register enable, data valid
reg [3:0] dtt_rd_regen_dv; // dtt output buffer mem read, register enable, data valid
wire [35:0] dtt_rd_data_r_w; // high bits are not used wire [35:0] dtt_rd_data_r_w; // high bits are not used
wire [35:0] dtt_rd_data_b_w; // high bits are not used wire [35:0] dtt_rd_data_b_w; // high bits are not used
wire [35:0] dtt_rd_data_g_w; // high bits are not used wire [35:0] dtt_rd_data_g_w; // high bits are not used
...@@ -340,10 +375,27 @@ module mclt16x16_bayer3#( ...@@ -340,10 +375,27 @@ module mclt16x16_bayer3#(
wire signed [OUT_WIDTH-1:0] dtt_rd_data_b = dtt_rd_data_b_w[OUT_WIDTH-1:0]; // valid with dtt_rd_regen_dv[3] wire signed [OUT_WIDTH-1:0] dtt_rd_data_b = dtt_rd_data_b_w[OUT_WIDTH-1:0]; // valid with dtt_rd_regen_dv[3]
wire signed [OUT_WIDTH-1:0] dtt_rd_data_g = dtt_rd_data_g_w[OUT_WIDTH-1:0]; // valid with dtt_rd_regen_dv[3] wire signed [OUT_WIDTH-1:0] dtt_rd_data_g = dtt_rd_data_g_w[OUT_WIDTH-1:0]; // valid with dtt_rd_regen_dv[3]
wire dtt_first_quad_out = ~dtt_out_ram_cntr[2]; // wire dtt_first_quad_out = ~dtt_out_ram_cntr[2];
wire dtt_red_quad_out = dtt_out_ram_cntr[3:2] == 0;
wire dtt_blue_quad_out = dtt_out_ram_cntr[3:2] == 1;
wire dtt_green_quad_out = dtt_out_ram_cntr[3:2] == 2;
// wire dtt_last_quad_out = dtt_out_ram_cntr[3:2] == 3;
wire ram_wpage_r = dtt_out_ram_cntr[4]; // dtt_out_ram_wah[4];
reg ram_wpage_b;
reg ram_wpage_g;
wire [6:0] dtt_rd_ra_r;
wire [6:0] dtt_rd_ra_b;
wire [7:0] dtt_rd_ra_g;
always @ (posedge clk) begin always @ (posedge clk) begin
rot_ram_copy <= {rot_ram_copy[0], dtt_start16};
if (rot_ram_copy[0]) rot_ram_page <= dtt_out_ram_cntr[4:2];
//rot_ram_page
// reading memory and running DTT // reading memory and running DTT
start_dtt <= dtt_in_precntr == DTT_IN_DELAY; start_dtt <= dtt_in_precntr == DTT_IN_DELAY;
// if (start_dtt) dtt_r_page <= dtt_in_wa[7];// dtt_in_page; // if (start_dtt) dtt_r_page <= dtt_in_wa[7];// dtt_in_page;
...@@ -362,7 +414,7 @@ module mclt16x16_bayer3#( ...@@ -362,7 +414,7 @@ module mclt16x16_bayer3#(
dtt_iv_8x8_ad #( dtt_iv_8x8_ad #(
.INPUT_WIDTH (DTT_IN_WIDTH), .INPUT_WIDTH (DTT_IN_WIDTH),
.OUT_WIDTH (OUT_WIDTH), .OUT_WIDTH (OUT_WIDTH),
.OUT_RSHIFT1 (OUT_RSHIFT), .OUT_RSHIFT1 (OUT_RSHIFT1),
.OUT_RSHIFT2 (OUT_RSHIFT2), .OUT_RSHIFT2 (OUT_RSHIFT2),
.TRANSPOSE_WIDTH (TRANSPOSE_WIDTH), .TRANSPOSE_WIDTH (TRANSPOSE_WIDTH),
.DSP_B_WIDTH (DSP_B_WIDTH), .DSP_B_WIDTH (DSP_B_WIDTH),
...@@ -383,48 +435,32 @@ module mclt16x16_bayer3#( ...@@ -383,48 +435,32 @@ module mclt16x16_bayer3#(
.out_we (dtt_out_we), // output reg .out_we (dtt_out_we), // output reg
.sub16 (dtt_sub16), // output reg .sub16 (dtt_sub16), // output reg
.inc16 (dtt_inc16), // output reg .inc16 (dtt_inc16), // output reg
.start16 (dtt_start16), // output reg
.start_out (dtt_start_fill) // output[24:0] signed .start_out (dtt_start_fill) // output[24:0] signed
); );
always @(posedge clk) begin always @(posedge clk) begin
if (rst) dtt_out_ram_cntr <= 0; // if (rst) dtt_out_ram_cntr <= 0;
if (dtt_start_red) dtt_out_ram_cntr <= {page,4'b0};
else if (dtt_inc16) dtt_out_ram_cntr <= dtt_out_ram_cntr + 1; else if (dtt_inc16) dtt_out_ram_cntr <= dtt_out_ram_cntr + 1;
dtt_out_ram_wah <= dtt_out_ram_cntr - dtt_sub16;
dtt_start_first_fill <= dtt_start_fill & dtt_first_quad_out; dtt_out_ram_wah <= dtt_out_ram_cntr - dtt_sub16;
dtt_start_second_fill<= dtt_start_fill & ~dtt_first_quad_out; // dtt_start_first_fill <= dtt_start_fill & dtt_first_quad_out;
dtt_start_red_fill <= dtt_start_fill & dtt_red_quad_out;
dtt_start_blue_fill <= dtt_start_fill & dtt_blue_quad_out;
dtt_start_green_fill <= dtt_start_fill & dtt_green_quad_out;
if (dtt_start_first_fill) dtt_out_ram_wpage <= dtt_out_ram_wah[4:3]; // dtt_start_second_fill<= dtt_start_fill & ~dtt_first_quad_out;
if (dtt_start_second_fill) dtt_out_ram_wpage2 <= dtt_out_ram_wpage;
if (rst) dtt_dly_cntr <= 0;
else if (dtt_start_first_fill) dtt_dly_cntr <= DTT_OUT_DELAY;
else if (|dtt_dly_cntr) dtt_dly_cntr <= dtt_dly_cntr - 1;
dtt_start_out <= {dtt_start_out[0],(dtt_dly_cntr == 1) ? 1'b1 : 1'b0}; // if (dtt_start_first_fill) dtt_out_ram_wpage <= dtt_out_ram_wah[4:3];
/// if (dtt_start_red_fill) dtt_out_ram_wpage <= dtt_out_ram_wah[4:3];
if (rst) dtt_rd_regen_dv[0] <= 0; // if (dtt_start_red_fill) dtt_out_ram_wpage <= dtt_out_ram_wah[4];
else if (dtt_start_out[0]) dtt_rd_regen_dv[0] <= 1;
else if (&dtt_rd_cntr_pre[6:0]) dtt_rd_regen_dv[0] <= 0;
if (rst) dtt_rd_regen_dv[3:1] <= 0; if (dtt_start_blue) ram_wpage_b <= ram_wpage_r;
else dtt_rd_regen_dv[3:1] <= dtt_rd_regen_dv[2:0]; if (dtt_start_green) ram_wpage_g <= ram_wpage_b;
// if (dtt_start_out[0]) dtt_rd_cntr_pre <= {dtt_out_ram_wpage, 7'b0}; //copy page number
if (dtt_start_out[0]) dtt_rd_cntr_pre <= {dtt_out_ram_wpage2, 7'b0}; //copy page number
else if (dtt_rd_regen_dv[0]) dtt_rd_cntr_pre <= dtt_rd_cntr_pre + 1;
dtt_rd_ra0 <= {dtt_rd_cntr_pre[8:7],
dtt_rd_cntr_pre[0] ^ dtt_rd_cntr_pre[1],
dtt_rd_cntr_pre[0]? (~dtt_rd_cntr_pre[6:2]) : dtt_rd_cntr_pre[6:2],
dtt_rd_cntr_pre[0]};
dtt_rd_ra1 <= {dtt_rd_cntr_pre[8:7],
dtt_rd_cntr_pre[0] ^ dtt_rd_cntr_pre[1],
dtt_rd_cntr_pre[0]? (~dtt_rd_cntr_pre[6:2]) : dtt_rd_cntr_pre[6:2],
~dtt_rd_cntr_pre[0]};
end end
...@@ -438,9 +474,9 @@ module mclt16x16_bayer3#( ...@@ -438,9 +474,9 @@ module mclt16x16_bayer3#(
.LOG2WIDTH_RD(5) .LOG2WIDTH_RD(5)
) ram18p_var_w_var_r_dtt_out_r_i ( ) ram18p_var_w_var_r_dtt_out_r_i (
.rclk (clk), // input .rclk (clk), // input
.raddr (dtt_rd_ra0), // input[8:0] .raddr ({2'b0,dtt_rd_ra_r}), // input[8:0]
.ren (dtt_rd_regen_dv[1]), // input .ren (dtt_rd_regen_r[0]), // input
.regen (dtt_rd_regen_dv[2]), // input .regen (dtt_rd_regen_r[1]), // input
.data_out (dtt_rd_data_r_w), // output[35:0] .data_out (dtt_rd_data_r_w), // output[35:0]
.wclk (clk), // input .wclk (clk), // input
.waddr (dtt_out_ram_wa_rb), // input[8:0] .waddr (dtt_out_ram_wa_rb), // input[8:0]
...@@ -455,9 +491,9 @@ module mclt16x16_bayer3#( ...@@ -455,9 +491,9 @@ module mclt16x16_bayer3#(
.LOG2WIDTH_RD(5) .LOG2WIDTH_RD(5)
) ram18p_var_w_var_r_dtt_out_b_i ( ) ram18p_var_w_var_r_dtt_out_b_i (
.rclk (clk), // input .rclk (clk), // input
.raddr (dtt_rd_ra1), // input[8:0] .raddr ({2'b0,dtt_rd_ra_b}), // input[8:0]
.ren (dtt_rd_regen_dv[1]), // input .ren (dtt_rd_regen_b[0]), // input
.regen (dtt_rd_regen_dv[2]), // input .regen (dtt_rd_regen_b[1]), // input
.data_out (dtt_rd_data_b_w), // output[35:0] .data_out (dtt_rd_data_b_w), // output[35:0]
.wclk (clk), // input .wclk (clk), // input
.waddr (dtt_out_ram_wa_rb), // input[8:0] .waddr (dtt_out_ram_wa_rb), // input[8:0]
...@@ -472,9 +508,9 @@ module mclt16x16_bayer3#( ...@@ -472,9 +508,9 @@ module mclt16x16_bayer3#(
.LOG2WIDTH_RD(5) .LOG2WIDTH_RD(5)
) ram18p_var_w_var_r_dtt_out_g_i ( ) ram18p_var_w_var_r_dtt_out_g_i (
.rclk (clk), // input .rclk (clk), // input
.raddr (dtt_rd_ra1), // input[8:0] .raddr ({1'b0,dtt_rd_ra_g}), // input[8:0]
.ren (dtt_rd_regen_dv[1]), // input .ren (dtt_rd_regen_g[0]), // input
.regen (dtt_rd_regen_dv[2]), // input .regen (dtt_rd_regen_g[1]), // input
.data_out (dtt_rd_data_g_w), // output[35:0] .data_out (dtt_rd_data_g_w), // output[35:0]
.wclk (clk), // input .wclk (clk), // input
.waddr (dtt_out_ram_wa_g), // input[8:0] .waddr (dtt_out_ram_wa_g), // input[8:0]
...@@ -484,7 +520,105 @@ module mclt16x16_bayer3#( ...@@ -484,7 +520,105 @@ module mclt16x16_bayer3#(
); );
phase_rotator_rgb #(
.FD_WIDTH (OUT_WIDTH),
.SHIFT_WIDTH (SHIFT_WIDTH),
.DSP_B_WIDTH (DSP_B_WIDTH),
.DSP_A_WIDTH (DSP_A_WIDTH),
.DSP_P_WIDTH (DSP_P_WIDTH),
// .COEFF_WIDTH(COEFF_WIDTH),
.GREEN (0),
.START_DELAY (DTT_OUT_DELAY_R)
) phase_rotator_r_i (
.clk (clk), // input
.rst (rst), // input
.start (dtt_start_red_fill), // input
.wpage (ram_wpage_r), // input
.shift_h (x_shft_rot_ram_reg), // input[6:0] signed
.shift_v (y_shft_rot_ram_reg), // input[6:0] signed
.inv_checker (inv_checker_rot_ram_reg), // input
.inv_rows (valid_odd_rot_ram_reg), // input
.in_addr (dtt_rd_ra_r), // output[7:0]
.in_re (dtt_rd_regen_r), // output[1:0]
.fd_din (dtt_rd_data_r), // input[24:0] signed
.fd_out (dout_r), // output[24:0] signed
.pre_first_out (pre_first_out_r), // output
.pre_last_out (pre_last_out_r), // output reg
.fd_dv (dv_r), // output
.fd_wa (out_addr_r) // output[8:0]
);
phase_rotator_rgb #(
.FD_WIDTH (OUT_WIDTH),
.SHIFT_WIDTH (SHIFT_WIDTH),
.DSP_B_WIDTH (DSP_B_WIDTH),
.DSP_A_WIDTH (DSP_A_WIDTH),
.DSP_P_WIDTH (DSP_P_WIDTH),
// .COEFF_WIDTH(COEFF_WIDTH),
.GREEN (0),
.START_DELAY (DTT_OUT_DELAY_B)
) phase_rotator_b_i (
.clk (clk), // input
.rst (rst), // input
.start (dtt_start_blue_fill), // input
.wpage (ram_wpage_b), // input
.shift_h (x_shft_rot_ram_reg), // input[6:0] signed
.shift_v (y_shft_rot_ram_reg), // input[6:0] signed
.inv_checker (inv_checker_rot_ram_reg), // input
.inv_rows (valid_odd_rot_ram_reg), // input
.in_addr (dtt_rd_ra_b), // output[7:0]
.in_re (dtt_rd_regen_b), // output[1:0]
.fd_din (dtt_rd_data_b), // input[24:0] signed
.fd_out (dout_b), // output[24:0] signed
.pre_first_out (pre_first_out_b), // output
.pre_last_out (pre_last_out_b), // output reg
.fd_dv (dv_b), // output
.fd_wa (out_addr_b) // output[8:0]
);
phase_rotator_rgb #(
.FD_WIDTH (OUT_WIDTH),
.SHIFT_WIDTH (SHIFT_WIDTH),
.DSP_B_WIDTH (DSP_B_WIDTH),
.DSP_A_WIDTH (DSP_A_WIDTH),
.DSP_P_WIDTH (DSP_P_WIDTH),
// .COEFF_WIDTH(COEFF_WIDTH),
.GREEN (1),
.START_DELAY (DTT_OUT_DELAY_G)
) phase_rotator_g_i (
.clk (clk), // input
.rst (rst), // input
.start (dtt_start_green_fill), // input
.wpage (ram_wpage_g), // input
.shift_h (x_shft_rot_ram_reg), // input[6:0] signed
.shift_v (y_shft_rot_ram_reg), // input[6:0] signed
.inv_checker (inv_checker_rot_ram_reg), // input
.inv_rows (valid_odd_rot_ram_reg), // input
.in_addr (dtt_rd_ra_g), // output[7:0]
.in_re (dtt_rd_regen_g), // output[1:0]
.fd_din (dtt_rd_data_g), // input[24:0] signed
.fd_out (dout_g), // output[24:0] signed
.pre_first_out (pre_first_out_g), // output
.pre_last_out (pre_last_out_g), // output reg
.fd_dv (dv_g), // output
.fd_wa (out_addr_g) // output[8:0]
);
reg [3:0] dead_cntr;
reg pre_busy_r;
always @ (posedge clk) begin
if (rst) pre_busy_r <= 0;
else if (pre_last_in_w) pre_busy_r <= 1;
else if (dead_cntr == 0) pre_busy_r <= 0;
if (~pre_busy_r) dead_cntr <= DEAD_CYCLES;
else dead_cntr <= dead_cntr - 1;
end
endmodule endmodule
dsp/mclt_baeyer_fold_accum_rgb.v
View file @ 46f1a6c9
...@@ -108,7 +108,8 @@ module mclt_baeyer_fold_accum_rgb # ( ...@@ -108,7 +108,8 @@ module mclt_baeyer_fold_accum_rgb # (
reg [1:0] ced2; reg [1:0] ced2;
wire neg_m1, neg_m2, en_a2; wire neg_m1, neg_m2, en_a2;
wire accum1= !var_pre2_first; wire accum1= !var_pre2_first;
wire accum2= !var_pre_first && green_r[2]; // wire accum2= !var_pre_first && green_r[2];
wire accum2= !var_pre_first && green_r[3];
wire [DSP_P_WIDTH-1:0] pout1; wire [DSP_P_WIDTH-1:0] pout1;
wire [DSP_P_WIDTH-1:0] pout2; wire [DSP_P_WIDTH-1:0] pout2;
wire signed [DTT_IN_WIDTH-1:0] dtt_in_dsp_w = (var_last ? wire signed [DTT_IN_WIDTH-1:0] dtt_in_dsp_w = (var_last ?
...@@ -205,7 +206,8 @@ module mclt_baeyer_fold_accum_rgb # ( ...@@ -205,7 +206,8 @@ module mclt_baeyer_fold_accum_rgb # (
.rst (rst), // input .rst (rst), // input
.dly (4'h1), // input[3:0] .dly (4'h1), // input[3:0]
// .din (pix_sgn[1]), // input[0:0] // .din (pix_sgn[1]), // input[0:0]
.din (green_r[0]? pix_sgn[1]:pix_sgn[0]), // input[0:0] // .din (green_r[0]? pix_sgn[1]:pix_sgn[0]), // input[0:0]
.din (green_r[1]? pix_sgn[1]:pix_sgn[0]), // input[0:0]
.dout (neg_m2) // output[0:0] .dout (neg_m2) // output[0:0]
); );
......
dsp/mclt_test_05.tf
View file @ 46f1a6c9
...@@ -70,7 +70,7 @@ module mclt_test_05 (); ...@@ -70,7 +70,7 @@ module mclt_test_05 ();
parameter OUT_WIDTH = 25; // bits in dtt output parameter OUT_WIDTH = 25; // bits in dtt output
parameter DTT_IN_WIDTH = 25; // bits in DTT input parameter DTT_IN_WIDTH = 25; // bits in DTT input
parameter TRANSPOSE_WIDTH = 25; // width of the transpose memory (intermediate results) parameter TRANSPOSE_WIDTH = 25; // width of the transpose memory (intermediate results)
parameter OUT_RSHIFT = 2; // overall right shift of the result from input, aligned by MSB (>=3 will never cause saturation) parameter OUT_RSHIFT1 = 2; // overall right shift of the result from input, aligned by MSB (>=3 will never cause saturation)
parameter OUT_RSHIFT2 = 0; // overall right shift for the second (vertical) pass parameter OUT_RSHIFT2 = 0; // overall right shift for the second (vertical) pass
parameter DSP_B_WIDTH = 18; // signed, output from sin/cos ROM parameter DSP_B_WIDTH = 18; // signed, output from sin/cos ROM
parameter DSP_A_WIDTH = 25; parameter DSP_A_WIDTH = 25;
...@@ -92,6 +92,23 @@ module mclt_test_05 (); ...@@ -92,6 +92,23 @@ module mclt_test_05 ();
wire dv; // SuppressThisWarning VEditor - output only wire dv; // SuppressThisWarning VEditor - output only
wire [OUT_WIDTH-1:0] dout0; // SuppressThisWarning VEditor - output only wire [OUT_WIDTH-1:0] dout0; // SuppressThisWarning VEditor - output only
wire [OUT_WIDTH-1:0] dout1; // SuppressThisWarning VEditor - output only wire [OUT_WIDTH-1:0] dout1; // SuppressThisWarning VEditor - output only
wire pre_busy3; // output// SuppressThisWarning VEditor - output only
wire pre_last_in3; // output// SuppressThisWarning VEditor - output only
wire pre_first_out_r; // output// SuppressThisWarning VEditor - output only
wire pre_first_out_b; // output// SuppressThisWarning VEditor - output only
wire pre_first_out_g; // output// SuppressThisWarning VEditor - output only
wire pre_last_out_r; // output// SuppressThisWarning VEditor - output only
wire pre_last_out_b; // output// SuppressThisWarning VEditor - output only
wire pre_last_out_g; // output// SuppressThisWarning VEditor - output only
wire [8:0] out_addr_r; // output[7:0] // SuppressThisWarning VEditor - output only
wire [8:0] out_addr_b; // output[7:0] // SuppressThisWarning VEditor - output only
wire [8:0] out_addr_g; // output[7:0] // SuppressThisWarning VEditor - output only
wire dv_r; // output// SuppressThisWarning VEditor - output only
wire dv_b; // output// SuppressThisWarning VEditor - output only
wire dv_g; // output// SuppressThisWarning VEditor - output only
wire [OUT_WIDTH-1:0] dout_r; // output[24:0] signed // SuppressThisWarning VEditor - output only
wire [OUT_WIDTH-1:0] dout_b; // output[24:0] signed // SuppressThisWarning VEditor - output only
wire [OUT_WIDTH-1:0] dout_g; // output[24:0] signed // SuppressThisWarning VEditor - output only
// assign #(1) pre_busy = pre_busy_w; // assign #(1) pre_busy = pre_busy_w;
...@@ -306,14 +323,13 @@ module mclt_test_05 (); ...@@ -306,14 +323,13 @@ module mclt_test_05 ();
end end
integer n1, cntr1, diff1, p1;// SuppressThisWarning VEditor : assigned in $readmem() system task
wire [7:0] wnd_a_w = mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.wnd_a_w;
integer n1, cntr1, diff1;// SuppressThisWarning VEditor : assigned in $readmem() system task wire [2:0] pix_page= 3 * n1 + p1;
wire [7:0] wnd_a_w = mclt16x16_bayer_i.mclt_bayer_fold_i.wnd_a_w; wire [2:0] pix_page_d;
wire [10:0] jav_pix_in_now_a = {n1[2:0], wnd_a_w}; wire [10:0] jav_pix_in_now_a = {pix_page_d, wnd_a_w};
wire [PIXEL_WIDTH-1 : 0] jav_pix_in_now = cntr1[7]?{PIXEL_WIDTH{1'bz}}:jav_pix_in[jav_pix_in_now_a]; wire [PIXEL_WIDTH-1 : 0] jav_pix_in_now = cntr1[7]?{PIXEL_WIDTH{1'bz}}:jav_pix_in[jav_pix_in_now_a];
wire [PIXEL_WIDTH-1 : 0] jav_pix_in_now_d; wire [PIXEL_WIDTH-1 : 0] jav_pix_in_now_d;
dly_var #( dly_var #(
.WIDTH(PIXEL_WIDTH), .WIDTH(PIXEL_WIDTH),
.DLY_WIDTH(4) .DLY_WIDTH(4)
...@@ -325,48 +341,78 @@ module mclt_test_05 (); ...@@ -325,48 +341,78 @@ module mclt_test_05 ();
.dout (jav_pix_in_now_d) // output[0:0] .dout (jav_pix_in_now_d) // output[0:0]
); );
dly_var #(
.WIDTH(3),
.DLY_WIDTH(4)
) dly_jav_pix_page_d_i (
.clk (CLK), // input
.rst (RST), // input
.dly (4'h0), // 7), // input[3:0]
.din (pix_page), // input[0:0]
.dout (pix_page_d) // output[0:0]
);
initial begin initial begin
while (RST) @(negedge CLK); while (RST) @(negedge CLK);
for (n1 = 0; n1 < 6; n1 = n1+1) begin for (n1 = 0; n1 < 2; n1 = n1+1) begin
while (mclt16x16_bayer_i.mclt_bayer_fold_i.in_cntr != 2) begin while (!mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.run_r[0] ||
(mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.in_cntr != 2)) begin
@(negedge CLK); @(negedge CLK);
end end
for (cntr1 = 0; cntr1 < 128; cntr1 = cntr1 + 1) begin for (p1 = 0; p1 <3; p1=p1+1) begin
diff1 = PIX_D - jav_pix_in_now_d; // java_fold_index[cntr1]; for (cntr1 = 0; cntr1 < ((p1 > 1)?128:64); cntr1 = cntr1 + 1) begin
@(negedge CLK); diff1 = PIX_D3 - jav_pix_in_now_d; // java_fold_index[cntr1];
@(negedge CLK);
end
end end
end end
end end
//Compare DTT inputs //Compare DTT inputs
integer n4, cntr4, diff4, diff4a; // SuppressThisWarning VEditor : assigned in $readmem() system task
wire [DTT_IN_WIDTH-1:0] data_dtt_in = mclt16x16_bayer_i.data_dtt_in; integer n4, cntr4, diff4,p4; // SuppressThisWarning VEditor : assigned in $readmem() system task
// wire [DTT_IN_WIDTH-1:0] java_data_dtt_in = jav_dtt_in[{n4[2:0], cntr4[1:0],cntr4[7:2]}]; // java_dtt_in0[{cntr4[1:0],cntr4[7:2]}] wire [DTT_IN_WIDTH-1:0] data_dtt_in = mclt16x16_bayer3_i.data_dtt_in;
wire [DTT_IN_WIDTH-1:0] java_data_dtt_in = jav_dtt_in[{n4[2:0], 1'b0, cntr4[0],cntr4[6:1]}]; // java_dtt_in0[{cntr4[1:0],cntr4[7:2]}] wire [2:0] page4 = 3 * n4 + p4;
wire [10:0] java_dtt_in_addr = (p4>1)?
{page4, 1'b0, cntr4[0],cntr4[6:1]} :
{page4, 1'b0, 1'b0, cntr4[5:0]};
wire [DTT_IN_WIDTH-1:0] java_data_dtt_in = jav_dtt_in[java_dtt_in_addr]; // java_dtt_in0[{cntr4[1:0],cntr4[7:2]}]
initial begin initial begin
while (RST) @(negedge CLK); while (RST) @(negedge CLK);
for (n4 = 0; n4 < 6; n4 = n4+1) begin for (n4 = 0; n4 < 2; n4 = n4+1) begin
while ((mclt16x16_bayer_i.dtt_in_cntr != 0) ||!mclt16x16_bayer_i.dtt_we) begin `ifdef DSP_ACCUM_FOLD
while ((mclt16x16_bayer3_i.dtt_in_precntr != 1) ||!mclt16x16_bayer3_i.dtt_prewe) begin
@(negedge CLK); @(negedge CLK);
end end
for (cntr4 = 0; cntr4 < 128; cntr4 = cntr4 + 1) begin `else
#1; while ((mclt16x16_bayer3_i.dtt_in_precntr != 0) ||!mclt16x16_bayer3_i.dtt_prewe) begin
diff4 = data_dtt_in - java_data_dtt_in;
if (n4 < 1) diff4a = data_dtt_in - java_data_dtt_in; // TEMPORARY, while no other data
@(negedge CLK); @(negedge CLK);
end end
`endif
for (p4 = 0; p4 < 3; p4=p4+1) begin
for (cntr4 = 0; cntr4 < ((p4 > 1)?128:64); cntr4 = cntr4 + 1) begin
#1;
diff4 = data_dtt_in - java_data_dtt_in;
@(negedge CLK);
end
end
end end
end end
integer n5, cntr5, diff5, diff5a; // SuppressThisWarning VEditor : assigned in $readmem() system task integer n5, cntr5, diff5,p5; // SuppressThisWarning VEditor : assigned in $readmem() system task
wire [DTT_IN_WIDTH-1:0] dtt_r_data = mclt16x16_bayer_i.dtt_r_data; wire [2:0] page5 = 3 * n5 + p5;
wire [DTT_IN_WIDTH-1:0] java_dtt_r_data = jav_dtt_in[{n5[2:0], 1'b0, cntr5[6:0]}]; // java_dtt_in0[cntr5[7:0]]; // wire [10:0] java_dtt_r_addr = (p5>1)?
// {page5, 1'b0, cntr5[6:0]} :
// {page5, 2'b0, cntr5[5:0]};
wire [10:0] java_dtt_r_addr = {page5, 1'b0, cntr5[6:0]};
wire [DTT_IN_WIDTH-1:0] dtt_r_data = mclt16x16_bayer3_i.dtt_r_data;
wire [DTT_IN_WIDTH-1:0] java_dtt_r_data = jav_dtt_in[java_dtt_r_addr]; // java_dtt_in0[cntr5[7:0]];
wire dtt_r_regen = mclt16x16_bayer_i.dtt_r_regen; wire dtt_r_regen = mclt16x16_bayer3_i.dtt_r_regen;
reg dtt_r_dv; // SuppressThisWarning VEditor just for simulation reg dtt_r_dv; // SuppressThisWarning VEditor just for simulation
always @ (posedge CLK) begin always @ (posedge CLK) begin
if (RST) dtt_r_dv <= 0; if (RST) dtt_r_dv <= 0;
...@@ -377,49 +423,114 @@ module mclt_test_05 (); ...@@ -377,49 +423,114 @@ module mclt_test_05 ();
initial begin initial begin
while (RST) @(negedge CLK); while (RST) @(negedge CLK);
for (n5 = 0; n5 < 6; n5 = n5+1) begin for (n5 = 0; n5 < 6; n5 = n5+1) begin
while ((!dtt_r_dv) || (mclt16x16_bayer_i.dtt_r_cntr[6:0] != 2)) begin while ((!dtt_r_dv) || (mclt16x16_bayer3_i.dtt_r_cntr[6:0] != 2)) begin
@(negedge CLK); @(negedge CLK);
end end
for (cntr5 = 0; cntr5 < 128; cntr5 = cntr5 + 1) begin for (p5 = 0; p5 < 3; p5=p5+1) begin
#1; for (cntr5 = 0; cntr5 < ((p5 > 1)?128:64); cntr5 = cntr5 + 1) begin
diff5 = dtt_r_data - java_dtt_r_data; #1;
if (n5 < 1) diff5a = dtt_r_data - java_dtt_r_data; // TEMPORARY, while no other data diff5 = dtt_r_data - java_dtt_r_data;
@(negedge CLK); @(negedge CLK);
end
end end
end end
end end
integer n6, cntr6, diff60, diff61; // SuppressThisWarning VEditor : assigned in $readmem() system task integer n50, cntr50, diff50; // SuppressThisWarning VEditor : assigned in $readmem() system task
wire [DTT_IN_WIDTH-1:0] data_dtt_out0 = mclt16x16_bayer_i.dtt_rd_data0; wire [DTT_IN_WIDTH-1:0] dtt_r_data0 = mclt16x16_bayer_i.dtt_r_data;
wire [DTT_IN_WIDTH-1:0] data_dtt_out1 = mclt16x16_bayer_i.dtt_rd_data1; wire [DTT_IN_WIDTH-1:0] java_dtt_r_data0 = jav_dtt_in[{n50[2:0], 1'b0, cntr50[6:0]}]; // java_dtt_in0[cntr5[7:0]];
wire [DTT_IN_WIDTH-1:0] java_data_dtt_out0 = jav_dtt_out[{
n6[2:0], wire dtt_r_regen0 = mclt16x16_bayer_i.dtt_r_regen;
1'b0, reg dtt_r_dv0; // SuppressThisWarning VEditor just for simulation
cntr6[0] ^ cntr6[1], always @ (posedge CLK) begin
cntr6[0]? (~cntr6[6:2]) : cntr6[6:2], if (RST) dtt_r_dv0 <= 0;
cntr6[0]}]; else dtt_r_dv0 <= dtt_r_regen0;
wire [DTT_IN_WIDTH-1:0] java_data_dtt_out1 = jav_dtt_out[{ end
n6[2:0],
1'b0,
cntr6[0] ^ cntr6[1],
cntr6[0]? (~cntr6[6:2]) : cntr6[6:2],
~cntr6[0]}];
initial begin initial begin
while (RST) @(negedge CLK); while (RST) @(negedge CLK);
for (n6 = 0; n6 < 6; n6 = n6+1) begin for (n50 = 0; n50 < 6; n50 = n50+1) begin
while ((!mclt16x16_bayer_i.dtt_rd_regen_dv[2]) || (mclt16x16_bayer_i.dtt_rd_cntr_pre[6:0] != 3)) begin while ((!dtt_r_dv0) || (mclt16x16_bayer_i.dtt_r_cntr[6:0] != 2)) begin
@(negedge CLK); @(negedge CLK);
end end
for (cntr6 = 0; cntr6 < 128; cntr6 = cntr6 + 1) begin for (cntr50 = 0; cntr50 < 128; cntr50 = cntr50 + 1) begin
#1; #1;
diff60 = data_dtt_out0 - java_data_dtt_out0; diff50 = dtt_r_data0 - java_dtt_r_data0;
diff61 = data_dtt_out1 - java_data_dtt_out1;
@(negedge CLK); @(negedge CLK);
end end
end end
end end
integer n6, cntr6, diff6r, diff6b, diff6g; // SuppressThisWarning VEditor : assigned in $readmem() system task
wire [6:0] dtt_rd_ra_r = mclt16x16_bayer3_i.dtt_rd_ra_r;
wire [6:0] dtt_rd_ra_b = mclt16x16_bayer3_i.dtt_rd_ra_b;
wire [7:0] dtt_rd_ra_g = mclt16x16_bayer3_i.dtt_rd_ra_g;
wire [1:0] dtt_rd_regen_r = mclt16x16_bayer3_i.dtt_rd_regen_r;
wire [1:0] dtt_rd_regen_b = mclt16x16_bayer3_i.dtt_rd_regen_b;
wire [1:0] dtt_rd_regen_g = mclt16x16_bayer3_i.dtt_rd_regen_g;
wire [DTT_IN_WIDTH-1:0] dtt_rd_data_r = mclt16x16_bayer3_i.dtt_rd_data_r;
wire [DTT_IN_WIDTH-1:0] dtt_rd_data_b = mclt16x16_bayer3_i.dtt_rd_data_b;
wire [DTT_IN_WIDTH-1:0] dtt_rd_data_g = mclt16x16_bayer3_i.dtt_rd_data_g;
wire [DTT_IN_WIDTH-1:0] java_dtt_rd_data_r=jav_dtt_out['h300*dtt_rd_ra_r[6] + 'h000 + dtt_rd_ra_r[5:0]];
wire [DTT_IN_WIDTH-1:0] java_dtt_rd_data_b=jav_dtt_out['h300*dtt_rd_ra_b[6] + 'h100 + dtt_rd_ra_b[5:0]];
wire [DTT_IN_WIDTH-1:0] java_dtt_rd_data_g=jav_dtt_out['h300*dtt_rd_ra_g[7] + 'h200 + dtt_rd_ra_g[6:0]];
wire [DTT_IN_WIDTH-1:0] java_dtt_rd_data_rd;
wire [DTT_IN_WIDTH-1:0] java_dtt_rd_data_bd;
wire [DTT_IN_WIDTH-1:0] java_dtt_rd_data_gd;
reg dtt_rd_regen_rv;
reg dtt_rd_regen_bv;
reg dtt_rd_regen_gv;
always @ (posedge CLK) begin
dtt_rd_regen_rv <= dtt_rd_regen_r[1];
dtt_rd_regen_bv <= dtt_rd_regen_b[1];
dtt_rd_regen_gv <= dtt_rd_regen_g[1];
diff6r <= dtt_rd_regen_rv? (dtt_rd_data_r - java_dtt_rd_data_rd) : 'bz;
diff6b <= dtt_rd_regen_bv? (dtt_rd_data_b - java_dtt_rd_data_bd) : 'bz;
diff6g <= dtt_rd_regen_gv? (dtt_rd_data_g - java_dtt_rd_data_gd) : 'bz;
end
dly_var #(
.WIDTH(DTT_IN_WIDTH),
.DLY_WIDTH(4)
) dly_java_dtt_rd_data_rd_i (
.clk (CLK), // input
.rst (RST), // input
.dly (4'h1), // input[3:0]
.din (java_dtt_rd_data_r), // input[0:0]
.dout (java_dtt_rd_data_rd) // output[0:0]
);
dly_var #(
.WIDTH(DTT_IN_WIDTH),
.DLY_WIDTH(4)
) dly_java_dtt_rd_data_bd_i (
.clk (CLK), // input
.rst (RST), // input
.dly (4'h1), // input[3:0]
.din (java_dtt_rd_data_b), // input[0:0]
.dout (java_dtt_rd_data_bd) // output[0:0]
);
dly_var #(
.WIDTH(DTT_IN_WIDTH),
.DLY_WIDTH(4)
) dly_java_dtt_rd_data_gd_i (
.clk (CLK), // input
.rst (RST), // input
.dly (4'h1), // input[3:0]
.din (java_dtt_rd_data_g), // input[0:0]
.dout (java_dtt_rd_data_gd) // output[0:0]
);
reg FIRST_OUT; reg FIRST_OUT;
always @(posedge CLK) FIRST_OUT <= mclt16x16_bayer_i.pre_first_out; always @(posedge CLK) FIRST_OUT <= mclt16x16_bayer_i.pre_first_out;
...@@ -441,6 +552,26 @@ module mclt_test_05 (); ...@@ -441,6 +552,26 @@ module mclt_test_05 ();
end end
end end
reg FIRST_OUTa;
always @(posedge CLK) FIRST_OUTa <= mclt16x16_bayer_i.pre_first_out;
integer n7a, cntr7a, diff70a, diff71a; // SuppressThisWarning VEditor : assigned in $readmem() system task
wire [OUT_WIDTH-1:0] java_data_dtt_rot0a = jav_dtt_rot[{n7a[2:0], cntr7a[1],cntr7a[0],cntr7a[6:2],1'b0}]; //java_dtt_rot0[{cntr7[1],cntr7[0],cntr7[7:2]}];
wire [OUT_WIDTH-1:0] java_data_dtt_rot1a = jav_dtt_rot[{n7a[2:0], cntr7a[1],cntr7a[0],cntr7a[6:2],1'b1}]; //java_dtt_rot0[{cntr7[1],cntr7[0],cntr7[7:2]}];
initial begin
while (RST) @(negedge CLK);
for (n7a = 0; n7a < 6; n7a = n7a+1) begin
while (!FIRST_OUTa) begin
@(negedge CLK);
end
for (cntr7a = 0; cntr7a < 128; cntr7a = cntr7a + 1) begin
#1;
diff70a = dout0 - java_data_dtt_rot0a;
diff71a = dout1 - java_data_dtt_rot1a;
@(negedge CLK);
end
end
end
...@@ -455,7 +586,7 @@ module mclt_test_05 (); ...@@ -455,7 +586,7 @@ module mclt_test_05 ();
.OUT_WIDTH (OUT_WIDTH), .OUT_WIDTH (OUT_WIDTH),
.DTT_IN_WIDTH (DTT_IN_WIDTH), .DTT_IN_WIDTH (DTT_IN_WIDTH),
.TRANSPOSE_WIDTH (TRANSPOSE_WIDTH), .TRANSPOSE_WIDTH (TRANSPOSE_WIDTH),
.OUT_RSHIFT (OUT_RSHIFT), .OUT_RSHIFT (OUT_RSHIFT1),
.OUT_RSHIFT2 (OUT_RSHIFT2), .OUT_RSHIFT2 (OUT_RSHIFT2),
.DSP_B_WIDTH (DSP_B_WIDTH), .DSP_B_WIDTH (DSP_B_WIDTH),
.DSP_A_WIDTH (DSP_A_WIDTH), .DSP_A_WIDTH (DSP_A_WIDTH),
...@@ -537,7 +668,7 @@ module mclt_test_05 (); ...@@ -537,7 +668,7 @@ module mclt_test_05 ();
.OUT_WIDTH (OUT_WIDTH), .OUT_WIDTH (OUT_WIDTH),
.DTT_IN_WIDTH (DTT_IN_WIDTH), .DTT_IN_WIDTH (DTT_IN_WIDTH),
.TRANSPOSE_WIDTH (TRANSPOSE_WIDTH), .TRANSPOSE_WIDTH (TRANSPOSE_WIDTH),
.OUT_RSHIFT (OUT_RSHIFT), .OUT_RSHIFT1 (OUT_RSHIFT1),
.OUT_RSHIFT2 (OUT_RSHIFT2), .OUT_RSHIFT2 (OUT_RSHIFT2),
.DSP_B_WIDTH (DSP_B_WIDTH), .DSP_B_WIDTH (DSP_B_WIDTH),
.DSP_A_WIDTH (DSP_A_WIDTH), .DSP_A_WIDTH (DSP_A_WIDTH),
...@@ -547,6 +678,7 @@ module mclt_test_05 (); ...@@ -547,6 +678,7 @@ module mclt_test_05 ();
.clk (CLK), // input .clk (CLK), // input
.rst (RST), // input .rst (RST), // input
.start (start3), // input .start (start3), // input
.page (page3), // input
.tile_size (TILE_SIZE2), // input[1:0] .tile_size (TILE_SIZE2), // input[1:0]
.color_wa (pre_run_cntr), // input[1:0] .color_wa (pre_run_cntr), // input[1:0]
.inv_checker (jav_inv_check[color_page]), // input .inv_checker (jav_inv_check[color_page]), // input
...@@ -563,15 +695,23 @@ module mclt_test_05 (); ...@@ -563,15 +695,23 @@ module mclt_test_05 ();
.pix_re (PIX_RE3), // output .pix_re (PIX_RE3), // output
.pix_page (PIX_COPY_PAGE3), // output .pix_page (PIX_COPY_PAGE3), // output
.pix_d (PIX_D3), // input[15:0] .pix_d (PIX_D3), // input[15:0]
.pre_busy(), // output .pre_busy (pre_busy3), // output
.pre_last_in(), // output .pre_last_in (pre_last_in3), // output
.pre_first_out(), // output .pre_first_out_r(pre_first_out_r), // output
.pre_last_out(), // output .pre_first_out_b(pre_first_out_b), // output
.out_addr(), // output[7:0] .pre_first_out_g(pre_first_out_g), // output
.dv(), // output .pre_last_out_r (pre_last_out_r), // output
.dout_r(), // output[24:0] signed .pre_last_out_b (pre_last_out_b), // output
.dout_b(), // output[24:0] signed .pre_last_out_g (pre_last_out_g), // output
.dout_g() // output[24:0] signed .out_addr_r (out_addr_r), // output[7:0]
.out_addr_b (out_addr_b), // output[7:0]
.out_addr_g (out_addr_g), // output[7:0]
.dv_r (dv_r), // output
.dv_b (dv_b), // output
.dv_g (dv_g), // output
.dout_r (dout_r), // output[24:0] signed
.dout_b (dout_b), // output[24:0] signed
.dout_g (dout_g) // output[24:0] signed
); );
dly_var #( dly_var #(
......
dsp/phase_rotator_rgb.v 0 → 100644
View file @ 46f1a6c9
/*!
* <b>Module:</b> phase_rotator_rgb
* @file phase_rotator_rgb.v
* @date 2017-12-11
* @author eyesis
*
* @brief 2-d phase rotator in frequency domain (subpixel shift)
*
* @copyright Copyright (c) 2017 <set up in Preferences-Verilog/VHDL Editor-Templates> .
*
* <b>License </b>
*
* phase_rotator_rgb.v is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation, either version 3 of the License, or
* (at your option) any later version.
*
* phase_rotator_rgb.v is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with this program. If not, see <http://www.gnu.org/licenses/> .
*
* Additional permission under GNU GPL version 3 section 7:
* If you modify this Program, or any covered work, by linking or combining it
* with independent modules provided by the FPGA vendor only (this permission
* does not extend to any 3-rd party modules, "soft cores" or macros) under
* different license terms solely for the purpose of generating binary "bitstream"
* files and/or simulating the code, the copyright holders of this Program give
* you the right to distribute the covered work without those independent modules
* as long as the source code for them is available from the FPGA vendor free of
* charge, and there is no dependence on any encrypted modules for simulating of
* the combined code. This permission applies to you if the distributed code
* contains all the components and scripts required to completely simulate it
* with at least one of the Free Software programs.
*/
`timescale 1ns/1ps
module phase_rotator_rgb#(
parameter FD_WIDTH = 25, // input/output data width, signed
parameter SHIFT_WIDTH = 7, // x/y subpixel shift, signed -0.5<=shift<0.5
parameter DSP_B_WIDTH = 18, // signed, output from sin/cos ROM
parameter DSP_A_WIDTH = 25,
parameter DSP_P_WIDTH = 48,
parameter COEFF_WIDTH = 17, // = DSP_B_WIDTH - 1 or positive numbers,
parameter GREEN = 1, // 0: use 1 DTT block (R,B), 1: use two DTT blocks (G)
parameter START_DELAY = 128 // delay start of input memory readout
)(
input clk, //!< system clock, posedge
input rst, //!< sync reset
input start, //!< start of delay
input wpage, //!< page (64 for R,B, 128 for G) last being written (may need delay?)
input signed [SHIFT_WIDTH-1:0] shift_h, //!< subpixel shift horizontal
input signed [SHIFT_WIDTH-1:0] shift_v, //!< subpixel shift vertical
input inv_checker, //!< negate 2-nd and fourth samples (for handling inverted checkerboard)
input inv_rows, //!< 0 : use first row, 1 - second row (when GREEN=0)
// input data CC,CS,SC,SS in column scan order (matching DTT)
output [GREEN + 6:0] in_addr, //!< input buffer address
output [1:0] in_re, //!< input buffer re/regen
input signed [FD_WIDTH-1:0] fd_din, //!< frequency domain data in, LATENCY=3 from start
output signed [FD_WIDTH-1:0] fd_out, //!< frequency domain data in
output pre_first_out, //!< 1 cycle before output data valid
output reg pre_last_out, //!< 2 cycle before last data valid
output fd_dv, //!< output data valid
output [8:0] fd_wa // output address including page
);
reg signed [SHIFT_WIDTH-1:0] shift_h_r;
reg signed [SHIFT_WIDTH-1:0] shift_v_r;
reg inv_checker_r;
reg inv_rows_r;
reg wpage_r;
wire negate = inv_checker_r ^ inv_rows_r; // FIXME: put real
reg [1:0] dtt_start_out;
reg [7:0] dtt_dly_cntr;
reg [4:0] dtt_rd_regen_dv;
reg [8:0] dtt_rd_cntr_pre; // 1 ahead of the former counter for dtt readout to rotator
reg [7:0] in_addr_r; //!< input buffer address
reg [8:0] out_addr_r;
assign in_addr = in_addr_r[GREEN + 6:0];
assign in_re = dtt_rd_regen_dv[2:1];
assign fd_wa = {out_addr_r[8], out_addr_r[0],out_addr_r[1],out_addr_r[4:2],out_addr_r[7:5]};
always @ (posedge clk) begin
if (start) begin
shift_h_r <= shift_h;
shift_v_r <= shift_v;
inv_checker_r <= inv_checker;
inv_rows_r <= inv_rows;
wpage_r <= wpage;
end
if (rst) dtt_dly_cntr <= 0;
else if (start) dtt_dly_cntr <= START_DELAY;
else if (|dtt_dly_cntr) dtt_dly_cntr <= dtt_dly_cntr - 1;
dtt_start_out <= {dtt_start_out[0],(dtt_dly_cntr == 1) ? 1'b1 : 1'b0};
if (rst) dtt_rd_regen_dv[0] <= 0;
else if (dtt_start_out[0]) dtt_rd_regen_dv[0] <= 1;
else if (&dtt_rd_cntr_pre[7:0]) dtt_rd_regen_dv[0] <= 0;
if (rst) dtt_rd_regen_dv[3:1] <= 0;
else dtt_rd_regen_dv[3:1] <= dtt_rd_regen_dv[2:0];
if (dtt_start_out[0]) dtt_rd_cntr_pre <= {wpage_r, 8'b0}; //copy page number
else if (dtt_rd_regen_dv[0]) dtt_rd_cntr_pre <= dtt_rd_cntr_pre + 1;
if (GREEN) in_addr_r <= {dtt_rd_cntr_pre[8],
dtt_rd_cntr_pre[0] ^ dtt_rd_cntr_pre[0],
dtt_rd_cntr_pre[0] ? (~dtt_rd_cntr_pre[7:2]) : dtt_rd_cntr_pre[7:2]};
else in_addr_r <= {1'b0,
dtt_rd_cntr_pre[8],
// dtt_rd_cntr_pre[0] ^ dtt_rd_cntr_pre[0],
dtt_rd_cntr_pre[1] ?
(dtt_rd_cntr_pre[0] ? (~dtt_rd_cntr_pre[7:2]) : {~dtt_rd_cntr_pre[7:5],dtt_rd_cntr_pre[4:2]}):
(dtt_rd_cntr_pre[0] ? {dtt_rd_cntr_pre[7:5],~dtt_rd_cntr_pre[4:2]} : dtt_rd_cntr_pre[7:2])};
if (pre_first_out) out_addr_r <= {wpage_r,8'b0};
else if (fd_dv) out_addr_r <= out_addr_r + 1;
pre_last_out <= out_addr_r[7:0] == 8'hfe;
end
phase_rotator #(
.FD_WIDTH (FD_WIDTH),
.SHIFT_WIDTH(SHIFT_WIDTH), // should be exactly 7
.DSP_B_WIDTH(DSP_B_WIDTH),
.DSP_A_WIDTH(DSP_A_WIDTH),
.DSP_P_WIDTH(DSP_P_WIDTH),
.COEFF_WIDTH(COEFF_WIDTH),
.DECIMATE (1'b0),
.ODD (1'b0)
) phase_rotator0_i (
.clk (clk), // input
.rst (rst), // input
.start (dtt_start_out[1]), // input
// are these shift OK? Will need to be valis only @ dtt_start_out
.shift_h (shift_h_r), // input[6:0] signed
.shift_v (shift_v_r), // input[6:0] signed
.inv_checker (negate), // input only used for Bayer mosaic data
.fd_din (fd_din), // input[24:0] signed. Expected latency = 3 from start
.fd_out (fd_out), // output[24:0] reg signed
.pre_first_out (pre_first_out), // output reg
.fd_dv (fd_dv) // output reg
);
endmodule
mclt_test_04.sav
View file @ 46f1a6c9
[*] [*]
[*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI [*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI
[*] Thu Dec 28 00:31:10 2017 [*] Thu Dec 28 22:34:50 2017
[*] [*]
[dumpfile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/simulation/mclt_test_04-20171226220814551.fst" [dumpfile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/simulation/mclt_test_04-20171226220814551.fst"
[dumpfile_mtime] "Wed Dec 27 05:08:17 2017" [dumpfile_mtime] "Wed Dec 27 05:08:17 2017"
[dumpfile_size] 843036 [dumpfile_size] 843036
[savefile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/mclt_test_04.sav" [savefile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/mclt_test_04.sav"
[timestart] 0 [timestart] 0
[size] 1824 1171 [size] 1920 1171
[pos] 0 0 [pos] -1920 0
*-21.266958 10681000 3905000 5225000 7935000 9215000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 *-21.266958 1585000 3905000 5225000 7935000 9215000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] mclt_test_04. [treeopen] mclt_test_04.
[treeopen] mclt_test_04.mclt16x16_bayer_i. [treeopen] mclt_test_04.mclt16x16_bayer_i.
[treeopen] mclt_test_04.mclt16x16_bayer_i.dtt_iv_8x8_ad_i. [treeopen] mclt_test_04.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.
...@@ -299,7 +299,7 @@ mclt_test_04.mclt16x16_bayer_i.dtt_out_ram_wa[8:0] ...@@ -299,7 +299,7 @@ mclt_test_04.mclt16x16_bayer_i.dtt_out_ram_wa[8:0]
@20000 @20000
- -
- -
@8022 @8023
mclt_test_04.mclt16x16_bayer_i.dtt_rd_ra0[8:0] mclt_test_04.mclt16x16_bayer_i.dtt_rd_ra0[8:0]
@20000 @20000
- -
...@@ -367,6 +367,8 @@ mclt_test_04.mclt16x16_bayer_i.window_w[17:0] ...@@ -367,6 +367,8 @@ mclt_test_04.mclt16x16_bayer_i.window_w[17:0]
mclt_test_04.mclt16x16_bayer_i.start mclt_test_04.mclt16x16_bayer_i.start
@800200 @800200
-fold -fold
@28
mclt_test_04.mclt16x16_bayer_i.mclt_bayer_fold_i.start
@22 @22
mclt_test_04.mclt16x16_bayer_i.mclt_bayer_fold_i.valid_rows_r0[1:0] mclt_test_04.mclt16x16_bayer_i.mclt_bayer_fold_i.valid_rows_r0[1:0]
@c00022 @c00022
...@@ -576,7 +578,6 @@ mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.dsp_1_i.DSP48E1_i.qb_o_reg1[17:0 ...@@ -576,7 +578,6 @@ mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.dsp_1_i.DSP48E1_i.qb_o_reg1[17:0
mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.dsp_1_i.DSP48E1_i.qb_o_reg2[17:0] mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.dsp_1_i.DSP48E1_i.qb_o_reg2[17:0]
mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.dsp_1_i.DSP48E1_i.b_mult[17:0] mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.dsp_1_i.DSP48E1_i.b_mult[17:0]
mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.dsp_1_i.DSP48E1_i.qmult_o_reg[42:0] mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.dsp_1_i.DSP48E1_i.qmult_o_reg[42:0]
@23
mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.dsp_1_i.DSP48E1_i.qp_o_reg1[47:0] mclt_test_04.mclt16x16_bayer_i.phase_rotator0_i.dsp_1_i.DSP48E1_i.qp_o_reg1[47:0]
@200 @200
- -
......
mclt_test_05.sav
View file @ 46f1a6c9
[*] [*]
[*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI [*] GTKWave Analyzer v3.3.78 (w)1999-2016 BSI
[*] Thu Dec 28 08:27:56 2017 [*] Fri Dec 29 06:24:04 2017
[*] [*]
[dumpfile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/simulation/mclt_test_05-20171228004859468.fst" [dumpfile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/simulation/mclt_test_05-20171228231831461.fst"
[dumpfile_mtime] "Thu Dec 28 07:49:04 2017" [dumpfile_mtime] "Fri Dec 29 06:18:39 2017"
[dumpfile_size] 1234767 [dumpfile_size] 1622253
[savefile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/mclt_test_05.sav" [savefile] "/home/eyesis/nc393/elphel393/fpga-elphel/x393_branch_dct/mclt_test_05.sav"
[timestart] 0 [timestart] 0
[size] 1920 1171 [size] 1920 1171
[pos] -1920 0 [pos] 0 0
*-21.077135 3685000 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 *-21.263206 5611000 1045000 1785000 1790400 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1 -1
[treeopen] mclt_test_05. [treeopen] mclt_test_05.
[treeopen] mclt_test_05.mclt16x16_bayer3_i. [treeopen] mclt_test_05.mclt16x16_bayer3_i.
[treeopen] mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i. [treeopen] mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.
[treeopen] mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.dsp_fold_cs_i.
[treeopen] mclt_test_05.mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i. [treeopen] mclt_test_05.mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.
[treeopen] mclt_test_05.mclt16x16_bayer_i.
[treeopen] mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i. [treeopen] mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.
[treeopen] mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i. [treeopen] mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.
[treeopen] mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cc_i. [treeopen] mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cc_i.
...@@ -25,408 +25,144 @@ ...@@ -25,408 +25,144 @@
[treeopen] mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i. [treeopen] mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.
[treeopen] mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.dsp_1_i. [treeopen] mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.dsp_1_i.
[treeopen] mclt_test_05.mclt16x16_bayer_i.phase_rotator1_i. [treeopen] mclt_test_05.mclt16x16_bayer_i.phase_rotator1_i.
[sst_width] 204 [sst_width] 275
[signals_width] 348 [signals_width] 340
[sst_expanded] 1 [sst_expanded] 1
[sst_vpaned_height] 343 [sst_vpaned_height] 343
@800200 @800200
-top_3 -top_old
@28
mclt_test_05.CLK
mclt_test_05.START
mclt_test_05.start3
mclt_test_05.page3
@22
mclt_test_05.color_page[2:0]
@28
mclt_test_05.start
@22
mclt_test_05.PIX_ADDR10[9:0]
@28
mclt_test_05.PIX_RE
@22
mclt_test_05.PIX_D[15:0]
mclt_test_05.PIX_ADDR103[9:0]
@28
mclt_test_05.PIX_RE3
@22
mclt_test_05.PIX_D3[15:0]
@1000200
-top_3
@800200
-mclt_bayer3
@28
mclt_test_05.mclt16x16_bayer3_i.start
@c00022
mclt_test_05.mclt16x16_bayer3_i.in_cntr[7:0]
@28
(0)mclt_test_05.mclt16x16_bayer3_i.in_cntr[7:0]
(1)mclt_test_05.mclt16x16_bayer3_i.in_cntr[7:0]
(2)mclt_test_05.mclt16x16_bayer3_i.in_cntr[7:0]
(3)mclt_test_05.mclt16x16_bayer3_i.in_cntr[7:0]
(4)mclt_test_05.mclt16x16_bayer3_i.in_cntr[7:0]
(5)mclt_test_05.mclt16x16_bayer3_i.in_cntr[7:0]
(6)mclt_test_05.mclt16x16_bayer3_i.in_cntr[7:0]
(7)mclt_test_05.mclt16x16_bayer3_i.in_cntr[7:0]
@1401200
-group_end
@28
(1)mclt_test_05.mclt16x16_bayer3_i.start_block_r[1:0]
(0)mclt_test_05.mclt16x16_bayer3_i.start_block_r[1:0]
mclt_test_05.mclt16x16_bayer3_i.inv_checker_ram_reg
@22
mclt_test_05.mclt16x16_bayer3_i.top_left_ram_reg[7:0]
@28
mclt_test_05.mclt16x16_bayer3_i.valid_odd_ram_reg
@22
mclt_test_05.mclt16x16_bayer3_i.x_shft_ram_reg[6:0]
mclt_test_05.mclt16x16_bayer3_i.y_shft_ram_reg[6:0]
@28
mclt_test_05.mclt16x16_bayer3_i.green_late
mclt_test_05.mclt16x16_bayer3_i.dtt_we
@c00022
mclt_test_05.mclt16x16_bayer3_i.dtt_in_wa[8:0]
@28
(0)mclt_test_05.mclt16x16_bayer3_i.dtt_in_wa[8:0]
(1)mclt_test_05.mclt16x16_bayer3_i.dtt_in_wa[8:0]
(2)mclt_test_05.mclt16x16_bayer3_i.dtt_in_wa[8:0]
(3)mclt_test_05.mclt16x16_bayer3_i.dtt_in_wa[8:0]
(4)mclt_test_05.mclt16x16_bayer3_i.dtt_in_wa[8:0]
(5)mclt_test_05.mclt16x16_bayer3_i.dtt_in_wa[8:0]
(6)mclt_test_05.mclt16x16_bayer3_i.dtt_in_wa[8:0]
(7)mclt_test_05.mclt16x16_bayer3_i.dtt_in_wa[8:0]
(8)mclt_test_05.mclt16x16_bayer3_i.dtt_in_wa[8:0]
@1401200
-group_end
@22
mclt_test_05.mclt16x16_bayer3_i.data_dtt_in[24:0]
@28
mclt_test_05.mclt16x16_bayer3_i.dtt_r_re
@22
mclt_test_05.mclt16x16_bayer3_i.dtt_r_ra[8:0]
@1000200
-mclt_bayer3
@800200
-comp_addresses_1
@200
-
@28
mclt_test_05.mclt16x16_bayer3_i.dtt_we
@c08022
mclt_test_05.mclt16x16_bayer3_i.dtt_in_wa[8:0]
@28
(0)mclt_test_05.mclt16x16_bayer3_i.dtt_in_wa[8:0]
(1)mclt_test_05.mclt16x16_bayer3_i.dtt_in_wa[8:0]
(2)mclt_test_05.mclt16x16_bayer3_i.dtt_in_wa[8:0]
(3)mclt_test_05.mclt16x16_bayer3_i.dtt_in_wa[8:0]
(4)mclt_test_05.mclt16x16_bayer3_i.dtt_in_wa[8:0]
(5)mclt_test_05.mclt16x16_bayer3_i.dtt_in_wa[8:0]
(6)mclt_test_05.mclt16x16_bayer3_i.dtt_in_wa[8:0]
(7)mclt_test_05.mclt16x16_bayer3_i.dtt_in_wa[8:0]
(8)mclt_test_05.mclt16x16_bayer3_i.dtt_in_wa[8:0]
@1401200
-group_end
@20000
-
-
@28
mclt_test_05.mclt16x16_bayer3_i.dtt_r_re
@8022
mclt_test_05.mclt16x16_bayer3_i.dtt_r_ra[8:0]
@20000
-
-
@200
-
@8023
mclt_test_05.mclt16x16_bayer3_i.dbg_dtt_in_rawa[8:0]
@20000
-
-
@1000200 @1000200
-comp_addresses_1 -top_old
@800200
-fold
@28
mclt_test_05.mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.start
mclt_test_05.mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.pre_last_in_r
mclt_test_05.mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.last_in_r
mclt_test_05.mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.green
mclt_test_05.mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.green_r
mclt_test_05.mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.valid_odd
@c00022
mclt_test_05.mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.in_cntr[6:0]
@28
(0)mclt_test_05.mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.in_cntr[6:0]
(1)mclt_test_05.mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.in_cntr[6:0]
(2)mclt_test_05.mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.in_cntr[6:0]
(3)mclt_test_05.mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.in_cntr[6:0]
(4)mclt_test_05.mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.in_cntr[6:0]
(5)mclt_test_05.mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.in_cntr[6:0]
(6)mclt_test_05.mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.in_cntr[6:0]
@c00022
mclt_test_05.mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.run_r[6:0]
@28
(0)mclt_test_05.mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.run_r[6:0]
(1)mclt_test_05.mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.run_r[6:0]
(2)mclt_test_05.mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.run_r[6:0]
(3)mclt_test_05.mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.run_r[6:0]
(4)mclt_test_05.mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.run_r[6:0]
(5)mclt_test_05.mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.run_r[6:0]
(6)mclt_test_05.mclt16x16_bayer3_i.mclt_bayer_fold_rgb_i.run_r[6:0]
@1401200
-group_end
-group_end
@1000200
-fold
@c00200
-fold_accum
@28 @28
mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.green
@800022
mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.phases[6:0]
@28
(0)mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.phases[6:0]
(1)mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.phases[6:0]
(2)mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.phases[6:0]
(3)mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.phases[6:0]
(4)mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.phases[6:0]
(5)mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.phases[6:0]
(6)mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.phases[6:0]
@1001200
-group_end
@800028
mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.ced2[1:0]
@28
(0)mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.ced2[1:0]
(1)mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.ced2[1:0]
@1001200
-group_end
@28
mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.pre_phase
@22
mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.window[17:0]
mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.pix_d[15:0]
mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.pix_d_r[15:0]
@28
mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.pix_sgn[1:0]
mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.var_pre2_first
@22
[color] 2
mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.dtt_in[24:0]
@28
[color] 2
mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.dtt_in_dv
@c00028
mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.pix_sgn[1:0]
@28
(0)mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.pix_sgn[1:0]
(1)mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.pix_sgn[1:0]
@1401200
-group_end
@28
mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.en_a2
mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.accum1
mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.accum2
mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.neg_m2
@22
mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.pout1[47:0]
mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.pout2[47:0]
@28
mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.var_first
mclt_test_05.mclt16x16_bayer3_i.mclt_baeyer_fold_accum_rgb_i.var_last
@1401200
-fold_accum
@800200
-old_fold
@28
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.start
@22
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.in_cntr[6:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.run_r[6:0]
@28
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.var_pre2_first
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.var_first_d
@200
-
@1000200
-old_fold
@800200
- old_accum
@28
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.var_first
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.var_last
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.var_pre2_first
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.accum1
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.accum2
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.neg_m1
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.neg_m2
@22
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.pout1[47:0]
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.pout2[47:0]
[color] 3
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dtt_in[24:0]
@28
[color] 3
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dtt_in_dv
@200
-
@1000200
- old_accum
@c00200
-top
@28
mclt_test_05.RST
mclt_test_05.CLK mclt_test_05.CLK
mclt_test_05.START @420
mclt_test_05.SUB_PAGE[2:0] mclt_test_05.n1
mclt_test_05.pre_last_128 mclt_test_05.p1
mclt_test_05.last_128_r
mclt_test_05.pre_last_count
mclt_test_05.last_count_r
mclt_test_05.in_run
@c00022
mclt_test_05.in_cntr[8:0]
@28
(0)mclt_test_05.in_cntr[8:0]
(1)mclt_test_05.in_cntr[8:0]
(2)mclt_test_05.in_cntr[8:0]
(3)mclt_test_05.in_cntr[8:0]
(4)mclt_test_05.in_cntr[8:0]
(5)mclt_test_05.in_cntr[8:0]
(6)mclt_test_05.in_cntr[8:0]
(7)mclt_test_05.in_cntr[8:0]
(8)mclt_test_05.in_cntr[8:0]
@1401200
-group_end
@28
mclt_test_05.start
mclt_test_05.PAGE
@c00022
mclt_test_05.PIX_ADDR9[8:0]
@28
(0)mclt_test_05.PIX_ADDR9[8:0]
(1)mclt_test_05.PIX_ADDR9[8:0]
(2)mclt_test_05.PIX_ADDR9[8:0]
(3)mclt_test_05.PIX_ADDR9[8:0]
(4)mclt_test_05.PIX_ADDR9[8:0]
(5)mclt_test_05.PIX_ADDR9[8:0]
(6)mclt_test_05.PIX_ADDR9[8:0]
(7)mclt_test_05.PIX_ADDR9[8:0]
(8)mclt_test_05.PIX_ADDR9[8:0]
@1401200
-group_end
@c00022
mclt_test_05.PIX_ADDR10[9:0]
@28
(0)mclt_test_05.PIX_ADDR10[9:0]
(1)mclt_test_05.PIX_ADDR10[9:0]
(2)mclt_test_05.PIX_ADDR10[9:0]
(3)mclt_test_05.PIX_ADDR10[9:0]
(4)mclt_test_05.PIX_ADDR10[9:0]
(5)mclt_test_05.PIX_ADDR10[9:0]
(6)mclt_test_05.PIX_ADDR10[9:0]
(7)mclt_test_05.PIX_ADDR10[9:0]
(8)mclt_test_05.PIX_ADDR10[9:0]
(9)mclt_test_05.PIX_ADDR10[9:0]
@1401200
-group_end
@22
[color] 2
mclt_test_05.PIX_D[15:0]
@28
mclt_test_05.PIX_RE
mclt_test_05.pre_busy
@22
mclt_test_05.SUB_PAGE[2:0]
@28
mclt_test_05.mclt16x16_bayer_i.inv_checker
@22
mclt_test_05.mclt16x16_bayer_i.valid_rows[1:0]
mclt_test_05.mclt16x16_bayer_i.top_left[7:0]
mclt_test_05.mclt16x16_bayer_i.x_shft[6:0]
mclt_test_05.mclt16x16_bayer_i.y_shft[6:0]
@c00420
mclt_test_05.cntr1 mclt_test_05.cntr1
@c00022
mclt_test_05.wnd_a_w[7:0]
@28 @28
(0)mclt_test_05.cntr1 (0)mclt_test_05.wnd_a_w[7:0]
(1)mclt_test_05.cntr1 (1)mclt_test_05.wnd_a_w[7:0]
(2)mclt_test_05.cntr1 (2)mclt_test_05.wnd_a_w[7:0]
(3)mclt_test_05.cntr1 (3)mclt_test_05.wnd_a_w[7:0]
(4)mclt_test_05.cntr1 (4)mclt_test_05.wnd_a_w[7:0]
(5)mclt_test_05.cntr1 (5)mclt_test_05.wnd_a_w[7:0]
(6)mclt_test_05.cntr1 (6)mclt_test_05.wnd_a_w[7:0]
(7)mclt_test_05.cntr1 (7)mclt_test_05.wnd_a_w[7:0]
(8)mclt_test_05.cntr1
(9)mclt_test_05.cntr1
(10)mclt_test_05.cntr1
(11)mclt_test_05.cntr1
(12)mclt_test_05.cntr1
(13)mclt_test_05.cntr1
(14)mclt_test_05.cntr1
(15)mclt_test_05.cntr1
(16)mclt_test_05.cntr1
(17)mclt_test_05.cntr1
(18)mclt_test_05.cntr1
(19)mclt_test_05.cntr1
(20)mclt_test_05.cntr1
(21)mclt_test_05.cntr1
(22)mclt_test_05.cntr1
(23)mclt_test_05.cntr1
(24)mclt_test_05.cntr1
(25)mclt_test_05.cntr1
(26)mclt_test_05.cntr1
(27)mclt_test_05.cntr1
(28)mclt_test_05.cntr1
(29)mclt_test_05.cntr1
(30)mclt_test_05.cntr1
(31)mclt_test_05.cntr1
@1401200 @1401200
-group_end -group_end
@420
mclt_test_05.n1
@22 @22
mclt_test_05.wnd_a_w[7:0]
mclt_test_05.jav_pix_in_now_a[10:0] mclt_test_05.jav_pix_in_now_a[10:0]
mclt_test_05.jav_pix_in_now[15:0] mclt_test_05.jav_pix_in_now[15:0]
[color] 3 [color] 3
mclt_test_05.jav_pix_in_now_d[15:0] mclt_test_05.jav_pix_in_now_d[15:0]
@420 @420
mclt_test_05.diff1 mclt_test_05.diff1
mclt_test_05.n4 @28
mclt_test_05.START
@22 @22
mclt_test_05.pix_page_d[2:0]
@200
-
@420
mclt_test_05.n4
mclt_test_05.p4
@c08022
mclt_test_05.cntr4 mclt_test_05.cntr4
@28
(0)mclt_test_05.cntr4
(1)mclt_test_05.cntr4
(2)mclt_test_05.cntr4
(3)mclt_test_05.cntr4
(4)mclt_test_05.cntr4
(5)mclt_test_05.cntr4
(6)mclt_test_05.cntr4
(7)mclt_test_05.cntr4
(8)mclt_test_05.cntr4
(9)mclt_test_05.cntr4
(10)mclt_test_05.cntr4
(11)mclt_test_05.cntr4
(12)mclt_test_05.cntr4
(13)mclt_test_05.cntr4
(14)mclt_test_05.cntr4
(15)mclt_test_05.cntr4
(16)mclt_test_05.cntr4
(17)mclt_test_05.cntr4
(18)mclt_test_05.cntr4
(19)mclt_test_05.cntr4
(20)mclt_test_05.cntr4
(21)mclt_test_05.cntr4
(22)mclt_test_05.cntr4
(23)mclt_test_05.cntr4
(24)mclt_test_05.cntr4
(25)mclt_test_05.cntr4
(26)mclt_test_05.cntr4
(27)mclt_test_05.cntr4
(28)mclt_test_05.cntr4
(29)mclt_test_05.cntr4
(30)mclt_test_05.cntr4
(31)mclt_test_05.cntr4
@1401200
-group_end
@22
mclt_test_05.page4[2:0]
mclt_test_05.java_dtt_in_addr[10:0]
mclt_test_05.data_dtt_in[24:0] mclt_test_05.data_dtt_in[24:0]
mclt_test_05.java_data_dtt_in[24:0] mclt_test_05.java_data_dtt_in[24:0]
@420
mclt_test_05.diff4
@8420 @8420
mclt_test_05.diff4 mclt_test_05.diff4
@200
-
@420 @420
mclt_test_05.n5 mclt_test_05.n5
mclt_test_05.p5
@8420
mclt_test_05.cntr5 mclt_test_05.cntr5
@22 @22
[color] 3 [color] 3
mclt_test_05.dtt_r_data[24:0] mclt_test_05.dtt_r_data[24:0]
mclt_test_05.java_dtt_r_data[24:0] mclt_test_05.java_dtt_r_data[24:0]
@420
mclt_test_05.diff5
@8420 @8420
mclt_test_05.diff5 mclt_test_05.diff5
@420 @c00022
mclt_test_05.n6 mclt_test_05.mclt16x16_bayer3_i.dtt_r_cntr[7:0]
mclt_test_05.cntr6 @28
(0)mclt_test_05.mclt16x16_bayer3_i.dtt_r_cntr[7:0]
(1)mclt_test_05.mclt16x16_bayer3_i.dtt_r_cntr[7:0]
(2)mclt_test_05.mclt16x16_bayer3_i.dtt_r_cntr[7:0]
(3)mclt_test_05.mclt16x16_bayer3_i.dtt_r_cntr[7:0]
(4)mclt_test_05.mclt16x16_bayer3_i.dtt_r_cntr[7:0]
(5)mclt_test_05.mclt16x16_bayer3_i.dtt_r_cntr[7:0]
(6)mclt_test_05.mclt16x16_bayer3_i.dtt_r_cntr[7:0]
(7)mclt_test_05.mclt16x16_bayer3_i.dtt_r_cntr[7:0]
@1401200
-group_end
@22 @22
mclt_test_05.data_dtt_out0[24:0] mclt_test_05.mclt16x16_bayer3_i.dtt_r_data[24:0]
mclt_test_05.data_dtt_out1[24:0] @200
mclt_test_05.java_data_dtt_out0[24:0] -
mclt_test_05.java_data_dtt_out1[24:0] @8022
@420 mclt_test_05.dtt_rd_ra_r[6:0]
mclt_test_05.diff60 mclt_test_05.dtt_rd_ra_b[6:0]
mclt_test_05.diff61 mclt_test_05.dtt_rd_ra_g[7:0]
@22
mclt_test_05.dtt_rd_data_r[24:0]
mclt_test_05.dtt_rd_data_b[24:0]
mclt_test_05.dtt_rd_data_g[24:0]
mclt_test_05.java_dtt_rd_data_rd[24:0]
mclt_test_05.java_dtt_rd_data_bd[24:0]
mclt_test_05.java_dtt_rd_data_gd[24:0]
@28
mclt_test_05.dtt_rd_regen_rv
mclt_test_05.dtt_rd_regen_bv
mclt_test_05.dtt_rd_regen_gv
@8420 @8420
mclt_test_05.diff60 mclt_test_05.diff6r
mclt_test_05.diff61 mclt_test_05.diff6b
mclt_test_05.diff6g
@200
-
@420 @420
mclt_test_05.n7 mclt_test_05.n7
mclt_test_05.cntr7 mclt_test_05.cntr7
...@@ -437,753 +173,184 @@ mclt_test_05.java_data_dtt_rot0[24:0] ...@@ -437,753 +173,184 @@ mclt_test_05.java_data_dtt_rot0[24:0]
mclt_test_05.java_data_dtt_rot1[24:0] mclt_test_05.java_data_dtt_rot1[24:0]
@8420 @8420
mclt_test_05.diff70 mclt_test_05.diff70
@c08420
mclt_test_05.diff71 mclt_test_05.diff71
@200
-
@28
mclt_test_05.dv
@22
mclt_test_05.dout0[24:0]
mclt_test_05.dout1[24:0]
mclt_test_05.mclt16x16_bayer_i.dtt_rd_cntr_pre[8:0]
mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.out_wd[24:0]
@800200
-mclt16x16_bayer
@c00200
-dtt_iv_8x8_ad
@28
mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.start
@22
mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.xin[24:0]
@c00022
mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.x_wa[5:0]
@28 @28
(0)mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.x_wa[5:0] (0)mclt_test_05.diff71
(1)mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.x_wa[5:0] (1)mclt_test_05.diff71
(2)mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.x_wa[5:0] (2)mclt_test_05.diff71
(3)mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.x_wa[5:0] (3)mclt_test_05.diff71
(4)mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.x_wa[5:0] (4)mclt_test_05.diff71
(5)mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.x_wa[5:0] (5)mclt_test_05.diff71
(6)mclt_test_05.diff71
(7)mclt_test_05.diff71
(8)mclt_test_05.diff71
(9)mclt_test_05.diff71
(10)mclt_test_05.diff71
(11)mclt_test_05.diff71
(12)mclt_test_05.diff71
(13)mclt_test_05.diff71
(14)mclt_test_05.diff71
(15)mclt_test_05.diff71
(16)mclt_test_05.diff71
(17)mclt_test_05.diff71
(18)mclt_test_05.diff71
(19)mclt_test_05.diff71
(20)mclt_test_05.diff71
(21)mclt_test_05.diff71
(22)mclt_test_05.diff71
(23)mclt_test_05.diff71
(24)mclt_test_05.diff71
(25)mclt_test_05.diff71
(26)mclt_test_05.diff71
(27)mclt_test_05.diff71
(28)mclt_test_05.diff71
(29)mclt_test_05.diff71
(30)mclt_test_05.diff71
(31)mclt_test_05.diff71
@1401200 @1401200
-group_end -group_end
@28
mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.x_ra0h
@22
mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.x_ra0[2:0]
@28
mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.x_ra1h
@22
[color] 2
mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.x_ra1[2:0]
mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.dcth_xin0[24:0]
[color] 2
mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.dcth_xin1[24:0]
mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.dcth_dout0[24:0]
mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.dcth_dout1[24:0]
mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.transpose_di[24:0]
mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.transpose_wa[7:0]
mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.transpose_we[1:0]
@28
mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.transpose_out_start
@22
mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.transpose_out_run[2:0]
mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.transpose_ra[7:0]
mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.transpose_out[24:0]
mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.dctv_dout0[24:0]
mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.dctv_dout1[24:0]
@28
mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.start_out
mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.out_we
@22
mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.out_wa[3:0]
mclt_test_05.mclt16x16_bayer_i.dtt_iv_8x8_ad_i.out_wd[24:0]
@200
-
@1401200
-dtt_iv_8x8_ad
@22
mclt_test_05.mclt16x16_bayer_i.dtt_rd_cntr_pre[8:0]
mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra0[8:0]
mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra1[8:0]
mclt_test_05.mclt16x16_bayer_i.dtt_rd_data0[24:0]
mclt_test_05.mclt16x16_bayer_i.dtt_rd_data1[24:0]
[color] 2
mclt_test_05.mclt16x16_bayer_i.dbg_dtt_rd_data0[24:0]
[color] 2
mclt_test_05.mclt16x16_bayer_i.dbg_dtt_rd_data1[24:0]
@200 @200
- -
@420
mclt_test_05.n7a
mclt_test_05.cntr7a
@22 @22
mclt_test_05.mclt16x16_bayer_i.dtt_out_ram_wa[8:0] mclt_test_05.mclt16x16_bayer_i.dout0[24:0]
@28 mclt_test_05.mclt16x16_bayer_i.dout1[24:0]
mclt_test_05.mclt16x16_bayer_i.dtt_out_we mclt_test_05.java_data_dtt_rot0a[24:0]
@22 mclt_test_05.java_data_dtt_rot1a[24:0]
mclt_test_05.mclt16x16_bayer_i.dtt_out_wd[24:0] @8421
@28 mclt_test_05.diff70a
mclt_test_05.mclt16x16_bayer_i.dtt_start_fill mclt_test_05.diff71a
mclt_test_05.mclt16x16_bayer_i.dtt_first_quad_out @800200
mclt_test_05.mclt16x16_bayer_i.dtt_start_first_fill -pre_rot_buffers
@22
mclt_test_05.mclt16x16_bayer_i.dtt_out_ram_wpage[1:0]
mclt_test_05.mclt16x16_bayer_i.dtt_out_ram_wpage2[1:0]
@800028
mclt_test_05.mclt16x16_bayer_i.dtt_start_out[1:0]
@28
(0)mclt_test_05.mclt16x16_bayer_i.dtt_start_out[1:0]
(1)mclt_test_05.mclt16x16_bayer_i.dtt_start_out[1:0]
@1001200
-group_end
@22
mclt_test_05.mclt16x16_bayer_i.dtt_out_ram_cntr[4:0]
mclt_test_05.mclt16x16_bayer_i.dtt_out_ram_wa[8:0]
@8022
mclt_test_05.mclt16x16_bayer_i.dtt_rd_cntr_pre[8:0]
@20000
-
@22
mclt_test_05.mclt16x16_bayer_i.dtt_rd_regen_dv[3:0]
@8022
mclt_test_05.mclt16x16_bayer_i.dtt_out_ram_wa[8:0]
@20000
-
-
@8022
mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra0[8:0]
@20000
-
-
@8022
mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra1[8:0]
@20000
-
-
@22 @22
mclt_test_05.mclt16x16_bayer_i.dbg_diff_wara_dtt_in[8:0] mclt_test_05.mclt16x16_bayer3_i.dtt_out_wd[24:0]
mclt_test_05.mclt16x16_bayer_i.dbg_diff_wara_dtt_out0[8:0]
mclt_test_05.mclt16x16_bayer_i.dbg_diff_wara_dtt_out1[8:0]
@8022 @8022
mclt_test_05.mclt16x16_bayer_i.dbg_diff_wara_dtt_in[8:0] mclt_test_05.mclt16x16_bayer3_i.dtt_out_ram_wa_rb[8:0]
mclt_test_05.mclt16x16_bayer_i.dbg_diff_wara_dtt_out0[8:0]
@20000 @20000
- -
-
@8022 @8022
mclt_test_05.mclt16x16_bayer_i.dbg_diff_wara_dtt_out1[8:0] mclt_test_05.mclt16x16_bayer3_i.dtt_out_ram_wa_g[8:0]
@20000 @20000
- -
-
@200
-
@22
mclt_test_05.mclt16x16_bayer_i.valid_rows[1:0]
@28
mclt_test_05.mclt16x16_bayer_i.inv_checker
@22
mclt_test_05.mclt16x16_bayer_i.top_left[7:0]
mclt_test_05.mclt16x16_bayer_i.data_dtt_in[24:0]
@c00022
mclt_test_05.mclt16x16_bayer_i.dtt_in_wa[8:0]
@28 @28
(0)mclt_test_05.mclt16x16_bayer_i.dtt_in_wa[8:0] mclt_test_05.mclt16x16_bayer3_i.dtt_out_we_r
(1)mclt_test_05.mclt16x16_bayer_i.dtt_in_wa[8:0] mclt_test_05.mclt16x16_bayer3_i.dtt_out_we_b
(2)mclt_test_05.mclt16x16_bayer_i.dtt_in_wa[8:0] mclt_test_05.mclt16x16_bayer3_i.dtt_out_we_g
(3)mclt_test_05.mclt16x16_bayer_i.dtt_in_wa[8:0] @c08022
(4)mclt_test_05.mclt16x16_bayer_i.dtt_in_wa[8:0] mclt_test_05.mclt16x16_bayer3_i.dtt_rd_ra_r[6:0]
(5)mclt_test_05.mclt16x16_bayer_i.dtt_in_wa[8:0] @28
(6)mclt_test_05.mclt16x16_bayer_i.dtt_in_wa[8:0] (0)mclt_test_05.mclt16x16_bayer3_i.dtt_rd_ra_r[6:0]
(7)mclt_test_05.mclt16x16_bayer_i.dtt_in_wa[8:0] (1)mclt_test_05.mclt16x16_bayer3_i.dtt_rd_ra_r[6:0]
(8)mclt_test_05.mclt16x16_bayer_i.dtt_in_wa[8:0] (2)mclt_test_05.mclt16x16_bayer3_i.dtt_rd_ra_r[6:0]
@1401200 (3)mclt_test_05.mclt16x16_bayer3_i.dtt_rd_ra_r[6:0]
-group_end (4)mclt_test_05.mclt16x16_bayer3_i.dtt_rd_ra_r[6:0]
@c00022 (5)mclt_test_05.mclt16x16_bayer3_i.dtt_rd_ra_r[6:0]
mclt_test_05.mclt16x16_bayer_i.dtt_in_cntr[6:0] (6)mclt_test_05.mclt16x16_bayer3_i.dtt_rd_ra_r[6:0]
@28
(0)mclt_test_05.mclt16x16_bayer_i.dtt_in_cntr[6:0]
(1)mclt_test_05.mclt16x16_bayer_i.dtt_in_cntr[6:0]
(2)mclt_test_05.mclt16x16_bayer_i.dtt_in_cntr[6:0]
(3)mclt_test_05.mclt16x16_bayer_i.dtt_in_cntr[6:0]
(4)mclt_test_05.mclt16x16_bayer_i.dtt_in_cntr[6:0]
(5)mclt_test_05.mclt16x16_bayer_i.dtt_in_cntr[6:0]
(6)mclt_test_05.mclt16x16_bayer_i.dtt_in_cntr[6:0]
@1401200
-group_end
@28
mclt_test_05.mclt16x16_bayer_i.dtt_we
@22
mclt_test_05.mclt16x16_bayer_i.window_w[17:0]
@28
mclt_test_05.mclt16x16_bayer_i.start
@800200
-fold
@22
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.valid_rows_r0[1:0]
@c00022
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.in_cntr[6:0]
@28
(0)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.in_cntr[6:0]
(1)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.in_cntr[6:0]
(2)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.in_cntr[6:0]
(3)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.in_cntr[6:0]
(4)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.in_cntr[6:0]
(5)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.in_cntr[6:0]
(6)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.in_cntr[6:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.inv_checker_r
@1401200 @1401200
-group_end -group_end
@22 @c08022
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.fold_addr[9:0] mclt_test_05.mclt16x16_bayer3_i.dtt_rd_ra_b[6:0]
@c00022 @28
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.fold_rom_out[17:0] (0)mclt_test_05.mclt16x16_bayer3_i.dtt_rd_ra_b[6:0]
@28 (1)mclt_test_05.mclt16x16_bayer3_i.dtt_rd_ra_b[6:0]
(0)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.fold_rom_out[17:0] (2)mclt_test_05.mclt16x16_bayer3_i.dtt_rd_ra_b[6:0]
(1)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.fold_rom_out[17:0] (3)mclt_test_05.mclt16x16_bayer3_i.dtt_rd_ra_b[6:0]
(2)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.fold_rom_out[17:0] (4)mclt_test_05.mclt16x16_bayer3_i.dtt_rd_ra_b[6:0]
(3)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.fold_rom_out[17:0] (5)mclt_test_05.mclt16x16_bayer3_i.dtt_rd_ra_b[6:0]
(4)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.fold_rom_out[17:0] (6)mclt_test_05.mclt16x16_bayer3_i.dtt_rd_ra_b[6:0]
(5)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.fold_rom_out[17:0]
(6)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.fold_rom_out[17:0]
(7)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.fold_rom_out[17:0]
(8)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.fold_rom_out[17:0]
(9)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.fold_rom_out[17:0]
(10)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.fold_rom_out[17:0]
(11)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.fold_rom_out[17:0]
(12)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.fold_rom_out[17:0]
(13)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.fold_rom_out[17:0]
(14)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.fold_rom_out[17:0]
(15)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.fold_rom_out[17:0]
(16)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.fold_rom_out[17:0]
(17)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.fold_rom_out[17:0]
@1401200 @1401200
-group_end -group_end
@c00022 @8022
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.wnd_a_w[7:0] mclt_test_05.mclt16x16_bayer3_i.dtt_rd_ra_g[7:0]
@28 @28
(0)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.wnd_a_w[7:0] (1)mclt_test_05.mclt16x16_bayer3_i.dtt_rd_regen_r[1:0]
(1)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.wnd_a_w[7:0] (1)mclt_test_05.mclt16x16_bayer3_i.dtt_rd_regen_b[1:0]
(2)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.wnd_a_w[7:0] (1)mclt_test_05.mclt16x16_bayer3_i.dtt_rd_regen_g[1:0]
(3)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.wnd_a_w[7:0]
(4)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.wnd_a_w[7:0]
(5)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.wnd_a_w[7:0]
(6)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.wnd_a_w[7:0]
(7)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.wnd_a_w[7:0]
@1401200
-group_end
@22
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.pix_a_w[8:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.top_left_r[7:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.pix_a_r[8:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.pix_addr[8:0]
@1000200
-fold
@200 @200
- -
@1000200 @1000200
-mclt16x16_bayer -pre_rot_buffers
@1401200 @800200
-top -rotators
@c00200
-mclt_bayer
-top
@28
mclt_test_05.mclt16x16_bayer_i.clk
mclt_test_05.mclt16x16_bayer_i.start
mclt_test_05.mclt16x16_bayer_i.pre_last_in
mclt_test_05.mclt16x16_bayer_i.pre_last_in_w
mclt_test_05.mclt16x16_bayer_i.pre_busy
mclt_test_05.mclt16x16_bayer_i.pre_first_out
mclt_test_05.mclt16x16_bayer_i.dv
@22
mclt_test_05.mclt16x16_bayer_i.dout0[24:0]
mclt_test_05.mclt16x16_bayer_i.dout1[24:0]
[color] 7
mclt_test_05.mclt16x16_bayer_i.dbg_dout0[24:0]
[color] 7
mclt_test_05.mclt16x16_bayer_i.dbg_dout1[24:0]
@8420
[color] 7
mclt_test_05.mclt16x16_bayer_i.dbg_dout0[24:0]
[color] 7
mclt_test_05.mclt16x16_bayer_i.dbg_dout1[24:0]
@22
mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra0[8:0]
mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra1[8:0]
mclt_test_05.mclt16x16_bayer_i.dtt_r_data[24:0]
[color] 3
mclt_test_05.mclt16x16_bayer_i.dbg_dtt_r_data[24:0]
mclt_test_05.mclt16x16_bayer_i.dtt_out_wd[24:0]
[color] 3
mclt_test_05.mclt16x16_bayer_i.dbg_dtt_out_wd[24:0]
@c00200
-fold
@28
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.start
@22
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.valid_rows[1:0]
@28 @28
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.valid_rows_r0[1:0] mclt_test_05.mclt16x16_bayer3_i.dtt_rd_regen_r[1:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.pre_last_in @c08022
@22 mclt_test_05.mclt16x16_bayer3_i.dtt_rd_ra_r[6:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.in_cntr[6:0] @28
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.wnd_a_w[7:0] (0)mclt_test_05.mclt16x16_bayer3_i.dtt_rd_ra_r[6:0]
(1)mclt_test_05.mclt16x16_bayer3_i.dtt_rd_ra_r[6:0]
(2)mclt_test_05.mclt16x16_bayer3_i.dtt_rd_ra_r[6:0]
(3)mclt_test_05.mclt16x16_bayer3_i.dtt_rd_ra_r[6:0]
(4)mclt_test_05.mclt16x16_bayer3_i.dtt_rd_ra_r[6:0]
(5)mclt_test_05.mclt16x16_bayer3_i.dtt_rd_ra_r[6:0]
(6)mclt_test_05.mclt16x16_bayer3_i.dtt_rd_ra_r[6:0]
@1401200 @1401200
-fold -group_end
-top @22
mclt_test_05.mclt16x16_bayer3_i.dtt_rd_data_r[24:0]
@28
(0)mclt_test_05.mclt16x16_bayer3_i.dtt_r_cntr[7:0]
(1)mclt_test_05.mclt16x16_bayer3_i.dtt_r_cntr[7:0]
mclt_test_05.mclt16x16_bayer3_i.dtt_start16
mclt_test_05.mclt16x16_bayer3_i.dtt_start_red
mclt_test_05.mclt16x16_bayer3_i.dtt_start_red_fill
mclt_test_05.mclt16x16_bayer3_i.dtt_start_blue
mclt_test_05.mclt16x16_bayer3_i.dtt_start_blue_fill
mclt_test_05.mclt16x16_bayer3_i.dtt_start_green
mclt_test_05.mclt16x16_bayer3_i.dtt_start_green_fill
mclt_test_05.mclt16x16_bayer3_i.ram_wpage_r
mclt_test_05.mclt16x16_bayer3_i.ram_wpage_b
mclt_test_05.mclt16x16_bayer3_i.ram_wpage_g
@200 @200
- -
@22
mclt_test_05.mclt16x16_bayer_i.x_shft[6:0]
@28
mclt_test_05.mclt16x16_bayer_i.start
@22
mclt_test_05.mclt16x16_bayer_i.x_shft_r[6:0]
@28
(0)mclt_test_05.mclt16x16_bayer_i.start_r[1:0]
@22
mclt_test_05.mclt16x16_bayer_i.x_shft_r2[6:0]
@28
mclt_test_05.mclt16x16_bayer_i.start_dtt
@22
mclt_test_05.mclt16x16_bayer_i.x_shft_r3[6:0]
@28
mclt_test_05.mclt16x16_bayer_i.dtt_start_first_fill
mclt_test_05.mclt16x16_bayer_i.dtt_start_second_fill
@22
mclt_test_05.mclt16x16_bayer_i.x_shft_r4[6:0]
@c00200
-rotator0
@28
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.start
@22
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.start_d[5:0]
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.fd_din[24:0]
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.rom_a[9:0]
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.cos_sin_w[17:0]
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.fd_out[24:0]
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.shift_h[6:0]
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.shift_v[6:0]
@28
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.inv_checker
@22
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.shift_hr[6:0]
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.shift_v0[6:0]
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.shift_vr[6:0]
@28
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.inv_checker_r
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.inv_checker_r2
@22
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.shift_hv[6:0]
@28
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.hv_sin
@22
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.sign_cs[4:0]
@28
(12)mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.ph[16:0]
(1)mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.start_d[5:0]
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.negm_1
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.negm_2
@22
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.cntr_h_consec[6:0]
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.cntr_h[7:0]
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.cntr_v[7:0]
@28
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.pre_dv
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.pre_first_out
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.cea1_1
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.cea1_2
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.cea2_1
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.cea2_2
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.sela_1
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.negm_1
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.negm_2
(14)mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.ph[16:0]
(13)mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.ph[16:0]
(12)mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.ph[16:0]
(11)mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.ph[16:0]
(10)mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.ph[16:0]
(9)mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.ph[16:0]
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.inv_checker_r2
(2)mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.sign_cs[4:0]
(1)mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.sign_cs[4:0]
(0)mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.sign_cs[4:0]
@22
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.cos_sin_w[17:0]
@28
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.ceb1_1
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.ceb2_1
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.selb_1
@800200 @800200
-dsp1 -rotator_red
@28 @28
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.dsp_1_i.DSP48E1_i.CEA1 mclt_test_05.mclt16x16_bayer3_i.phase_rotator_r_i.start
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.dsp_1_i.DSP48E1_i.CEA2 mclt_test_05.mclt16x16_bayer3_i.phase_rotator_r_i.wpage
mclt_test_05.mclt16x16_bayer3_i.phase_rotator_r_i.wpage_r
(1)mclt_test_05.mclt16x16_bayer3_i.phase_rotator_r_i.dtt_start_out[1:0]
@22 @22
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.dsp_1_i.DSP48E1_i.qa_o_reg1[29:0] mclt_test_05.mclt16x16_bayer3_i.phase_rotator_r_i.dtt_rd_cntr_pre[8:0]
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.dsp_1_i.DSP48E1_i.qa_o_reg2[29:0] mclt_test_05.mclt16x16_bayer3_i.phase_rotator_r_i.in_addr[6:0]
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.dsp_1_i.DSP48E1_i.qad_o_reg1[24:0]
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.dsp_1_i.DSP48E1_i.qb_o_reg1[17:0]
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.dsp_1_i.DSP48E1_i.qb_o_reg2[17:0]
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.dsp_1_i.DSP48E1_i.b_mult[17:0]
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.dsp_1_i.DSP48E1_i.qmult_o_reg[42:0]
mclt_test_05.mclt16x16_bayer_i.phase_rotator0_i.dsp_1_i.DSP48E1_i.qp_o_reg1[47:0]
@200 @200
- -
@1000200 @1000200
-dsp1 -rotator_red
@1401200
-rotator0
@c00200 @c00200
-rotator1 -rotator_blue
@28
mclt_test_05.mclt16x16_bayer_i.phase_rotator1_i.start
@22
mclt_test_05.mclt16x16_bayer_i.phase_rotator1_i.start_d[5:0]
mclt_test_05.mclt16x16_bayer_i.phase_rotator1_i.fd_din[24:0]
mclt_test_05.mclt16x16_bayer_i.phase_rotator1_i.shift_h[6:0]
mclt_test_05.mclt16x16_bayer_i.phase_rotator1_i.shift_v[6:0]
@28
mclt_test_05.mclt16x16_bayer_i.phase_rotator1_i.inv_checker
@22
mclt_test_05.mclt16x16_bayer_i.phase_rotator1_i.shift_hr[6:0]
mclt_test_05.mclt16x16_bayer_i.phase_rotator1_i.shift_v0[6:0]
@28
mclt_test_05.mclt16x16_bayer_i.phase_rotator1_i.inv_checker_r
@22
mclt_test_05.mclt16x16_bayer_i.phase_rotator1_i.shift_vr[6:0]
@28
mclt_test_05.mclt16x16_bayer_i.phase_rotator1_i.inv_checker_r2
@22
mclt_test_05.mclt16x16_bayer_i.phase_rotator1_i.shift_hv[6:0]
@28
mclt_test_05.mclt16x16_bayer_i.phase_rotator1_i.hv_sin
@22
mclt_test_05.mclt16x16_bayer_i.phase_rotator1_i.sign_cs[4:0]
@28 @28
(12)mclt_test_05.mclt16x16_bayer_i.phase_rotator1_i.ph[16:0] mclt_test_05.mclt16x16_bayer3_i.phase_rotator_b_i.start
(1)mclt_test_05.mclt16x16_bayer_i.phase_rotator1_i.start_d[5:0] mclt_test_05.mclt16x16_bayer3_i.phase_rotator_b_i.wpage
mclt_test_05.mclt16x16_bayer_i.phase_rotator1_i.negm_1 mclt_test_05.mclt16x16_bayer3_i.phase_rotator_b_i.wpage_r
mclt_test_05.mclt16x16_bayer_i.phase_rotator1_i.negm_2 (1)mclt_test_05.mclt16x16_bayer3_i.phase_rotator_b_i.dtt_start_out[1:0]
@22 @22
mclt_test_05.mclt16x16_bayer_i.phase_rotator1_i.cntr_h_consec[6:0] mclt_test_05.mclt16x16_bayer3_i.phase_rotator_b_i.dtt_rd_cntr_pre[8:0]
mclt_test_05.mclt16x16_bayer_i.phase_rotator1_i.cntr_h[7:0] mclt_test_05.mclt16x16_bayer3_i.phase_rotator_b_i.in_addr_r[7:0]
mclt_test_05.mclt16x16_bayer_i.phase_rotator1_i.cntr_v[7:0]
@28
mclt_test_05.mclt16x16_bayer_i.phase_rotator1_i.pre_dv
mclt_test_05.mclt16x16_bayer_i.phase_rotator1_i.pre_first_out
@200 @200
- -
@1401200 @1401200
-rotator1 -rotator_blue
@c00200
-mclt_bayer_fold
@28
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.rst
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.tile_size_r[1:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.start
@22
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.in_cntr[6:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.top_left_r[7:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.x_shft_r[6:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.y_shft_r[6:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.i_mclt_fold_rom.addr_a[9:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.fold_rom_out[17:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.wnd_a_w[7:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.pix_a_w[8:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.pix_a_r[8:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.sgn_w[1:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.signs[1:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.pix_addr[8:0]
@28
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.pix_re
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.pix_page
@22
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.window[17:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.i_mclt_fold_rom.addr_a[9:0]
@28
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.i_mclt_fold_rom.en_a
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.i_mclt_fold_rom.regen_a
@c00200 @c00200
-mclt_wnd_mul -rotator_green
@22
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.x_in[3:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.y_in[3:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.x_shft[6:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.y_shft[6:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.wnd_out[17:0]
@28 @28
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.zero_in mclt_test_05.mclt16x16_bayer3_i.phase_rotator_g_i.start
(1)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.regen[2:0] mclt_test_05.mclt16x16_bayer3_i.phase_rotator_g_i.wpage
(0)mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.regen[2:0] mclt_test_05.mclt16x16_bayer3_i.phase_rotator_g_i.wpage_r
@22 (1)mclt_test_05.mclt16x16_bayer3_i.phase_rotator_g_i.dtt_start_out[1:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.x_full[9:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.y_full[9:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.wnd_out_x[17:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.wnd_out_y[17:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.wnd_out_x_r[17:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.wnd_out_y_r[17:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.wnd_out_full[35:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.wnd_out_w[17:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.data_out_a[17:0]
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.data_out_b[17:0]
@28
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.en_a
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.en_b
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.regen_a
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.regen_b
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.regrst_a
mclt_test_05.mclt16x16_bayer_i.mclt_bayer_fold_i.mclt_wnd_i.i_wnd_rom.regrst_b
@1401200
-mclt_wnd_mul
-mclt_bayer_fold
@22 @22
mclt_test_05.mclt16x16_bayer_i.pix_d[15:0] mclt_test_05.mclt16x16_bayer3_i.phase_rotator_g_i.dtt_rd_cntr_pre[8:0]
mclt_test_05.mclt16x16_bayer_i.window_w[17:0] mclt_test_05.mclt16x16_bayer3_i.phase_rotator_g_i.in_addr_r[7:0]
mclt_test_05.mclt16x16_bayer_i.data_dtt_in[24:0]
@28
mclt_test_05.mclt16x16_bayer_i.dtt_we
@22
mclt_test_05.mclt16x16_bayer_i.dtt_in_cntr[6:0]
@28
mclt_test_05.mclt16x16_bayer_i.dtt_in_page
mclt_test_05.mclt16x16_bayer_i.start_dtt
@c00200
-mclt_baeyer_fold_accum
@28
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.pre_phase
@c00022
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.phases[6:0]
@28
(0)mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.phases[6:0]
(1)mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.phases[6:0]
(2)mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.phases[6:0]
(3)mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.phases[6:0]
(4)mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.phases[6:0]
(5)mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.phases[6:0]
(6)mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.phases[6:0]
@1401200
-group_end
@22
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.pix_d[15:0]
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.window[17:0]
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.pix_sgn[1:0]
@28
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.var_pre_first
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.var_first
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.var_last
@22
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dtt_in[24:0]
@28
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dtt_in_dv
(0)mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.phases[6:0]
@200 @200
- -
@22
mclt_test_05.mclt16x16_bayer_i.signs[1:0]
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.pix_sgn[1:0]
@28
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.accum1
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.neg_m1
@22
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.pout1[47:0]
@28
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.accum2
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.neg_m2
@22
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.pout2[47:0]
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dtt_in_dsp[24:0]
@800200
-dsp1
@28
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cc_i.cead
@22
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cc_i.DSP48E1_i.qa_o_reg1[29:0]
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cc_i.DSP48E1_i.qa_o_reg2[29:0]
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cc_i.DSP48E1_i.qad_o_reg1[24:0]
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cc_i.DSP48E1_i.qb_o_reg1[17:0]
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cc_i.DSP48E1_i.qb_o_reg2[17:0]
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cc_i.DSP48E1_i.qmult_o_reg[42:0]
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cc_i.DSP48E1_i.qp_o_reg1[47:0]
@1000200
-dsp1
@800200
-dsp2
@28
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cs_i.cead
@22
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cs_i.DSP48E1_i.qa_o_reg1[29:0]
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cs_i.DSP48E1_i.qa_o_reg2[29:0]
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cs_i.DSP48E1_i.qad_o_reg1[24:0]
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cs_i.DSP48E1_i.qb_o_reg1[17:0]
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cs_i.DSP48E1_i.qb_o_reg2[17:0]
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cs_i.DSP48E1_i.qmult_o_reg[42:0]
mclt_test_05.mclt16x16_bayer_i.mclt_baeyer_fold_accum_i.dsp_fold_cs_i.DSP48E1_i.qp_o_reg1[47:0]
@200
-
@1000200
-dsp2
@1401200 @1401200
-mclt_baeyer_fold_accum -rotator_green
@c00200 @1000200
-membuf -rotators
@8022
mclt_test_05.mclt16x16_bayer_i.dbg_diff_wara_dtt_in[8:0]
@20000
-
-
-
@8022
mclt_test_05.mclt16x16_bayer_i.ram18p_var_w_var_r_dtt_in_i.raddr[8:0]
@20000
-
@8022
mclt_test_05.mclt16x16_bayer_i.ram18p_var_w_var_r_dtt_in_i.waddr[8:0]
@20000
-
-
@200 @200
- -
@28
mclt_test_05.mclt16x16_bayer_i.dtt_out_we
@8022
mclt_test_05.mclt16x16_bayer_i.dtt_out_ram_wa[8:0]
@20000
-
-
@8022
mclt_test_05.mclt16x16_bayer_i.dbg_last_dtt_out_ram_wa[8:0]
@20000
-
-
-
@8022
mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra0[8:0]
@20000
-
-
@8022
mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra1[8:0]
mclt_test_05.mclt16x16_bayer_i.dbg_diff_wara_dtt_out0[8:0]
@20000
-
-
@8022
mclt_test_05.mclt16x16_bayer_i.dbg_diff_wara_dtt_out1[8:0]
@20000
-
-
@1401200
-membuf
@22
mclt_test_05.mclt16x16_bayer_i.dtt_r_ra[8:0]
mclt_test_05.mclt16x16_bayer_i.dtt_r_data[24:0]
@8420
mclt_test_05.mclt16x16_bayer_i.dtt_r_data[24:0]
@28
mclt_test_05.mclt16x16_bayer_i.dtt_start
mclt_test_05.mclt16x16_bayer_i.dtt_start_fill
@22
mclt_test_05.mclt16x16_bayer_i.dtt_out_ram_cntr[4:0]
@28
mclt_test_05.mclt16x16_bayer_i.dtt_start_first_fill
@22
mclt_test_05.mclt16x16_bayer_i.dtt_out_wd[24:0]
@28
mclt_test_05.mclt16x16_bayer_i.dtt_out_we
@c00022
mclt_test_05.mclt16x16_bayer_i.dtt_out_ram_wa[8:0]
@28
(0)mclt_test_05.mclt16x16_bayer_i.dtt_out_ram_wa[8:0]
(1)mclt_test_05.mclt16x16_bayer_i.dtt_out_ram_wa[8:0]
(2)mclt_test_05.mclt16x16_bayer_i.dtt_out_ram_wa[8:0]
(3)mclt_test_05.mclt16x16_bayer_i.dtt_out_ram_wa[8:0]
(4)mclt_test_05.mclt16x16_bayer_i.dtt_out_ram_wa[8:0]
(5)mclt_test_05.mclt16x16_bayer_i.dtt_out_ram_wa[8:0]
(6)mclt_test_05.mclt16x16_bayer_i.dtt_out_ram_wa[8:0]
(7)mclt_test_05.mclt16x16_bayer_i.dtt_out_ram_wa[8:0]
(8)mclt_test_05.mclt16x16_bayer_i.dtt_out_ram_wa[8:0]
@1401200
-group_end
@22
mclt_test_05.mclt16x16_bayer_i.dtt_dly_cntr[7:0]
mclt_test_05.mclt16x16_bayer_i.dtt_out_ram_wa[8:0]
mclt_test_05.mclt16x16_bayer_i.dtt_out_ram_wah[4:0]
mclt_test_05.mclt16x16_bayer_i.dtt_out_wa16[3:0]
@c00022
mclt_test_05.mclt16x16_bayer_i.dtt_rd_cntr_pre[8:0]
@28
(0)mclt_test_05.mclt16x16_bayer_i.dtt_rd_cntr_pre[8:0]
(1)mclt_test_05.mclt16x16_bayer_i.dtt_rd_cntr_pre[8:0]
(2)mclt_test_05.mclt16x16_bayer_i.dtt_rd_cntr_pre[8:0]
(3)mclt_test_05.mclt16x16_bayer_i.dtt_rd_cntr_pre[8:0]
(4)mclt_test_05.mclt16x16_bayer_i.dtt_rd_cntr_pre[8:0]
(5)mclt_test_05.mclt16x16_bayer_i.dtt_rd_cntr_pre[8:0]
(6)mclt_test_05.mclt16x16_bayer_i.dtt_rd_cntr_pre[8:0]
(7)mclt_test_05.mclt16x16_bayer_i.dtt_rd_cntr_pre[8:0]
(8)mclt_test_05.mclt16x16_bayer_i.dtt_rd_cntr_pre[8:0]
@1401200
-group_end
@28
mclt_test_05.mclt16x16_bayer_i.ram18p_var_w_var_r_dtt_out0_i.we
@c00022
mclt_test_05.mclt16x16_bayer_i.ram18p_var_w_var_r_dtt_out0_i.waddr[8:0]
@28
(0)mclt_test_05.mclt16x16_bayer_i.ram18p_var_w_var_r_dtt_out0_i.waddr[8:0]
(1)mclt_test_05.mclt16x16_bayer_i.ram18p_var_w_var_r_dtt_out0_i.waddr[8:0]
(2)mclt_test_05.mclt16x16_bayer_i.ram18p_var_w_var_r_dtt_out0_i.waddr[8:0]
(3)mclt_test_05.mclt16x16_bayer_i.ram18p_var_w_var_r_dtt_out0_i.waddr[8:0]
(4)mclt_test_05.mclt16x16_bayer_i.ram18p_var_w_var_r_dtt_out0_i.waddr[8:0]
(5)mclt_test_05.mclt16x16_bayer_i.ram18p_var_w_var_r_dtt_out0_i.waddr[8:0]
(6)mclt_test_05.mclt16x16_bayer_i.ram18p_var_w_var_r_dtt_out0_i.waddr[8:0]
(7)mclt_test_05.mclt16x16_bayer_i.ram18p_var_w_var_r_dtt_out0_i.waddr[8:0]
(8)mclt_test_05.mclt16x16_bayer_i.ram18p_var_w_var_r_dtt_out0_i.waddr[8:0]
@1401200
-group_end
@28
mclt_test_05.mclt16x16_bayer_i.ram18p_var_w_var_r_dtt_out0_i.ren
mclt_test_05.mclt16x16_bayer_i.ram18p_var_w_var_r_dtt_out0_i.regen
@c00022
mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra1[8:0]
@28
(0)mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra1[8:0]
(1)mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra1[8:0]
(2)mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra1[8:0]
(3)mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra1[8:0]
(4)mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra1[8:0]
(5)mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra1[8:0]
(6)mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra1[8:0]
(7)mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra1[8:0]
(8)mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra1[8:0]
@1401200
-group_end
@22
mclt_test_05.mclt16x16_bayer_i.x_shft[6:0]
mclt_test_05.mclt16x16_bayer_i.x_shft_r[6:0]
mclt_test_05.mclt16x16_bayer_i.x_shft_r2[6:0]
mclt_test_05.mclt16x16_bayer_i.x_shft_r3[6:0]
mclt_test_05.mclt16x16_bayer_i.x_shft_r4[6:0]
mclt_test_05.mclt16x16_bayer_i.y_shft[6:0]
mclt_test_05.mclt16x16_bayer_i.y_shft_r2[6:0]
mclt_test_05.mclt16x16_bayer_i.y_shft_r3[6:0]
mclt_test_05.mclt16x16_bayer_i.y_shft_r4[6:0]
@28
mclt_test_05.mclt16x16_bayer_i.inv_checker
mclt_test_05.mclt16x16_bayer_i.inv_checker_r
mclt_test_05.mclt16x16_bayer_i.inv_checker_r2
mclt_test_05.mclt16x16_bayer_i.inv_checker_r3
mclt_test_05.mclt16x16_bayer_i.inv_checker_r4
@c00022
mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra0[8:0]
@28
(0)mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra0[8:0]
(1)mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra0[8:0]
(2)mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra0[8:0]
(3)mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra0[8:0]
(4)mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra0[8:0]
(5)mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra0[8:0]
(6)mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra0[8:0]
(7)mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra0[8:0]
(8)mclt_test_05.mclt16x16_bayer_i.dtt_rd_ra0[8:0]
@1401200
-group_end
-mclt_bayer
[pattern_trace] 1 [pattern_trace] 1
[pattern_trace] 0 [pattern_trace] 0
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