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Commit 46cf253d authored by Andrey Filippov's avatar Andrey Filippov
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added configuration for ISE, timing constraints for Vivado

parent 0bd9ef33
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.gitignore
View file @ 46cf253d
......@@ -3,3 +3,5 @@ glbl.v
vivado_*
syntax_*
simulation/*
ise_*
.project
View file @ 46cf253d
......@@ -43,80 +43,90 @@
<nature>com.elphel.vdt.veditor.HdlNature</nature>
</natures>
<linkedResources>
<link>
<name>ise_logs/ISExst.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/ise_logs/ISExst-20140531140025056.log</location>
</link>
<link>
<name>ise_state/eddr3-synth.tgz</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/ise_state/eddr3-synth-20140531140025056.tgz</location>
</link>
<link>
<name>vivado_logs/VivadoBitstream.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoBitstream-20140531004107237.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoBitstream-20140531175841733.log</location>
</link>
<link>
<name>vivado_logs/VivadoOpt.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOpt-20140531003924649.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOpt-20140531175841733.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPhys.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPhys-20140531004107237.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPhys-20140531175841733.log</location>
</link>
<link>
<name>vivado_logs/VivadoOptPower.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPower-20140531003924649.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoOptPower-20140531175841733.log</location>
</link>
<link>
<name>vivado_logs/VivadoPlace.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoPlace-20140531003924649.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoPlace-20140531175841733.log</location>
</link>
<link>
<name>vivado_logs/VivadoRoute.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoRoute-20140531004107237.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoRoute-20140531175841733.log</location>
</link>
<link>
<name>vivado_logs/VivadoSynthesis.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140531003924649.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoSynthesis-20140531175605664.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportImplemented.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportImplemented-20140531004107237.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportImplemented-20140531180006073.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimimgSummaryReportSynthesis.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140531003924649.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimimgSummaryReportSynthesis-20140531175605664.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimingReportImplemented.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportImplemented-20140531004107237.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportImplemented-20140531175841733.log</location>
</link>
<link>
<name>vivado_logs/VivadoTimingReportSynthesis.log</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140531003924649.log</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_logs/VivadoTimingReportSynthesis-20140531175605664.log</location>
</link>
<link>
<name>vivado_state/eddr3-opt-phys.dcp</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-opt-phys-20140531004107237.dcp</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-opt-phys-20140531175841733.dcp</location>
</link>
<link>
<name>vivado_state/eddr3-place.dcp</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-place-20140531003924649.dcp</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-place-20140531175841733.dcp</location>
</link>
<link>
<name>vivado_state/eddr3-route.dcp</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-route-20140531004107237.dcp</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-route-20140531175841733.dcp</location>
</link>
<link>
<name>vivado_state/eddr3-synth.dcp</name>
<type>1</type>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-synth-20140531003924649.dcp</location>
<location>/data/vdt/vdt-projects/eddr3/vivado_state/eddr3-synth-20140531175605664.dcp</location>
</link>
</linkedResources>
</projectDescription>
.settings/com.elphel.vdt.ISExst.prefs 0 → 100644
View file @ 46cf253d
ISExst_170_constraints=ddrc_test01.xcf
com.elphel.store.context.ISExst=ISExst_170_constraints<-@\#\#@->
eclipse.preferences.version=1
.settings/com.elphel.vdt.VivadoSynthesis.prefs
View file @ 46cf253d
VivadoSynthesis_102_ConstraintsFiles=ddrc_test01.xdc<-@\#\#@->
VivadoSynthesis_102_ConstraintsFiles=ddrc_test01.xdc<-@\#\#@->ddrc_test01_timing.xdc<-@\#\#@->
VivadoSynthesis_95_ShowInfo=false
com.elphel.store.context.VivadoSynthesis=VivadoSynthesis_102_ConstraintsFiles<-@\#\#@->VivadoSynthesis_95_ShowInfo<-@\#\#@->
eclipse.preferences.version=1
axi/axibram_read.v
View file @ 46cf253d
......@@ -77,7 +77,7 @@ module axibram_read #(
reg [ 1:0] rburst; // registered burst type
reg [ 3:0] rlen; // registered burst type
wire [ADDRESS_BITS-1:0] next_rd_address_w; // next transfer address;
assign next_rd_address_w=
assign next_rd_address_w= //SuppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 13-bit target.
rburst[1]?
(rburst[0]? {ADDRESS_BITS{1'b0}}:((read_address[ADDRESS_BITS-1:0]+1) & {{(ADDRESS_BITS-4){1'b1}}, ~rlen[3:0]})):
(rburst[0]? (read_address[ADDRESS_BITS-1:0]+1):(read_address[ADDRESS_BITS-1:0]));
......@@ -164,7 +164,7 @@ module axibram_read #(
if (rst) read_left <= 0;
else if (start_read_burst_w) read_left <= arlen_out[3:0]; // precedence over inc
else if (bram_reg_re_w) read_left <= read_left-1;
else if (bram_reg_re_w) read_left <= read_left-1; //SuppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 4-bit target.
if (rst) read_address <= {ADDRESS_BITS{1'b0}};
else if (start_read_burst_w) read_address <= araddr_out[ADDRESS_BITS-1:0]; // precedence over inc
......@@ -178,7 +178,7 @@ module axibram_read #(
else if (last_in_burst_d_w) rlast <= 1'b1;
else if (rready) rlast <= 1'b0;
end
always @ (posedge aclk) begin
always @ (posedge aclk) begin //SuppressThisWarning ISExst Assignment to bram_reg_re_0 ignored, since the identifier is never used
// bram_reg_re_0 <= read_in_progress_w && !pre_rvalid_w;
bram_reg_re_0 <= (ar_nempty && !read_in_progress) || (read_in_progress && !read_in_progress);
......@@ -230,7 +230,7 @@ fifo_same_clock #( .DATA_WIDTH(ADDRESS_BITS+20),.DATA_DEPTH(4))
.we(arvalid && arready),
.re(start_read_burst_w),
.data_in({arid[11:0], arburst[1:0],arsize[1:0],arlen[3:0],araddr[ADDRESS_BITS+1:2]}),
.data_out({arid_out[11:0], arburst_out[1:0],arsize_out[1:0],arlen_out[3:0],araddr_out[ADDRESS_BITS-1:0]}),
.data_out({arid_out[11:0], arburst_out[1:0],arsize_out[1:0],arlen_out[3:0],araddr_out[ADDRESS_BITS-1:0]}), //SuppressThisWarning ISExst Assignment to arsize ignored, since the identifier is never used
.nempty(ar_nempty),
.full(),
.half_full(ar_half_full)
......
axi/axibram_write.v
View file @ 46cf253d
......@@ -99,7 +99,7 @@ module axibram_write #(
assign w_nempty_ready=w_nempty && dev_ready_r; // should it be dev_ready?
reg dev_ready_r; // device, selected at start burst
assign next_wr_address_w=
assign next_wr_address_w= //SuppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 13-bit target.
wburst[1]?
(wburst[0]? {ADDRESS_BITS{1'b0}}:((write_address[ADDRESS_BITS-1:0]+1) & {{(ADDRESS_BITS-4){1'b1}}, ~wlen[3:0]})):
(wburst[0]? (write_address[ADDRESS_BITS-1:0]+1):(write_address[ADDRESS_BITS-1:0]));
......@@ -124,7 +124,7 @@ module axibram_write #(
if (rst) write_left <= 0;
else if (start_write_burst_w) write_left <= awlen_out[3:0]; // precedence over inc
else if (bram_we_w) write_left <= write_left-1;
else if (bram_we_w) write_left <= write_left-1; //SuppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 4-bit target.
if (rst) write_address <= {ADDRESS_BITS{1'b0}};
else if (start_write_burst_w) write_address <= awaddr_out[ADDRESS_BITS-1:0]; // precedence over inc
......@@ -168,7 +168,7 @@ fifo_same_clock #( .DATA_WIDTH(20+ADDRESS_BITS),.DATA_DEPTH(4))
.we(awvalid && awready),
.re(start_write_burst_w),
.data_in({awid[11:0], awburst[1:0],awsize[1:0],awlen[3:0],awaddr[ADDRESS_BITS+1:2]}),
.data_out({awid_out[11:0], awburst_out[1:0],awsize_out[1:0],awlen_out[3:0],awaddr_out[ADDRESS_BITS-1:0]}),
.data_out({awid_out[11:0], awburst_out[1:0],awsize_out[1:0],awlen_out[3:0],awaddr_out[ADDRESS_BITS-1:0]}), //SuppressThisWarning ISExst Assignment to awsize_out ignored, since the identifier is never used
.nempty(aw_nempty),
.full(),
.half_full(aw_half_full)
......@@ -180,7 +180,7 @@ fifo_same_clock #( .DATA_WIDTH(49),.DATA_DEPTH(4))
.we(wvalid && wready),
.re(bram_we_w), //start_write_burst_w), // wrong
.data_in({wid[11:0],wlast,wstb[3:0],wdata[31:0]}),
.data_out({wid_out[11:0],wlast_out,wstb_out[3:0],wdata_out[31:0]}),
.data_out({wid_out[11:0],wlast_out,wstb_out[3:0],wdata_out[31:0]}), //SuppressThisWarning ISExst Assignment to wlast ignored, since the identifier is never used
.nempty(w_nempty),
.full(),
.half_full(w_half_full)
......
ddrc_control.v
View file @ 46cf253d
......@@ -164,8 +164,8 @@ module ddrc_control #(
assign ld_delay = dly_ld_r;
assign dly_set = dly_set_r;
assign dly_data = wdata_fifo_out_r[ 7:0]; // WARNING: [Synth 8-3936] Found unconnected internal register 'wdata_fifo_out_r_reg' and it is trimmed from '32' to '11' bits. [ddrc_control.v:100]
assign dly_addr = waddr_fifo_out_r[ 6:0]; //WARNING: [Synth 8-3936] Found unconnected internal register 'waddr_fifo_out_r_reg' and it is trimmed from '12' to '7' bits. [ddrc_control.v:101]
assign dly_data = wdata_fifo_out_r[ 7:0]; // IgnoreThisWarning VivadoSynthesis WARNING: [Synth 8-3936] Found unconnected internal register 'wdata_fifo_out_r_reg' and it is trimmed from '32' to '11' bits. [ddrc_control.v:100]
assign dly_addr = waddr_fifo_out_r[ 6:0]; // IgnoreThisWarning VivadoSynthesis WARNING: [Synth 8-3936] Found unconnected internal register 'waddr_fifo_out_r_reg' and it is trimmed from '12' to '7' bits. [ddrc_control.v:101]
assign run_addr = wdata_fifo_out_r[10:0];
assign run_chn = waddr_fifo_out_r[3:0];
assign run_seq = run_seq_r && !ddr_rst;
......
ddrc_test01.v
View file @ 46cf253d
......@@ -276,7 +276,7 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
axibram_write #(
.ADDRESS_BITS(AXI_WR_ADDR_BITS)
) axibram_write_i (
) axibram_write_i ( //SuppressThisWarning ISExst Output port <bram_wstb> of the instance <axibram_write_i> is unconnected or connected to loadless signal.
.aclk (axi_aclk), // input
.rst (axi_rst), // input
.awaddr (axi_awaddr[31:0]), // input[31:0]
......@@ -302,14 +302,14 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.bram_wclk (axiwr_bram_wclk), // output
.bram_waddr (axiwr_bram_waddr[AXI_WR_ADDR_BITS-1:0]), // output[9:0]
.bram_wen (axiwr_bram_wen), // output
.bram_wstb (axiwr_bram_wstb[3:0]), // output[3:0]
.bram_wstb (axiwr_bram_wstb[3:0]), // output[3:0] //SuppressThisWarning ISExst Assignment to axiwr_bram_wstb ignored, since the identifier is never used
.bram_wdata (axiwr_bram_wdata[31:0]) // output[31:0]
);
/* Instance template for module axibram_read */
axibram_read #(
.ADDRESS_BITS(AXI_RD_ADDR_BITS)
) axibram_read_i (
) axibram_read_i ( //SuppressThisWarning ISExst Output port <bram_rclk> of the instance <axibram_read_i> is unconnected or connected to loadless signal.
.aclk (axi_aclk), // input
.rst (axi_rst), // input
.araddr (axi_araddr[31:0]), // input[31:0]
......@@ -328,7 +328,7 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.pre_araddr (axird_pre_araddr[AXI_RD_ADDR_BITS-1:0]), // output[9:0]
.start_burst (axird_start_burst), // output
.dev_ready (axird_dev_ready), // input
.bram_rclk (axird_bram_rclk), // output
.bram_rclk (axird_bram_rclk), // output //SuppressThisWarning ISExst Assignment to axird_bram_rclk ignored, since the identifier is never used
.bram_raddr (axird_bram_raddr[AXI_RD_ADDR_BITS-1:0]), // output[9:0]
.bram_ren (axird_bram_ren), // output
.bram_regen (axird_bram_regen), // output
......@@ -449,7 +449,7 @@ BUFG bufg_axi_aclk_i (.O(axi_aclk),.I(fclk[0]));
.SS_MOD_PERIOD (SS_MOD_PERIOD),
.CMD_PAUSE_BITS (CMD_PAUSE_BITS),
.CMD_DONE_BIT (CMD_DONE_BIT)
) ddrc_sequencer_i (
) ddrc_sequencer_i ( //SuppressThisWarning ISExst Output port <run_done> of the instance <ddrc_sequencer_i> is unconnected or connected to loadless signal.
.SDRST (SDRST), // output
.SDCLK (SDCLK), // output
.SDNCLK (SDNCLK), // output
......
ddrc_test01.xcf 0 → 100644
View file @ 46cf253d
#################################################################################
# Filename: ddrc_test01.xcf
# Date:2014-05-20
# Author: Andrey Filippov
# Description: DDR3 controller test with axi constraints
#
# Copyright (c) 2014 Elphel, Inc.
# ddrc_test01.xcf is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# ddrc_test01.xcf is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/> .
#################################################################################
# output SDRST, // output SDRST, active low
# set_property IOSTANDARD SSTL15 [get_ports {SDRST}]
# set_property PACKAGE_PIN J4 [get_ports {SDRST}]
NET "SDRST" LOC = "J4" | IOSTANDARD = "SSTL15" ;
# output SDCLK, // DDR3 clock differential output, positive
#set_property IOSTANDARD DIFF_SSTL15 [get_ports {SDCLK}]
#set_property PACKAGE_PIN K3 [get_ports {SDCLK}]
NET "SDCLK" LOC = "K3" | IOSTANDARD = "SSTL15" ;
# output SDNCLK,// DDR3 clock differential output, negative
#set_property IOSTANDARD DIFF_SSTL15 [get_ports {SDNCLK}]
#set_property PACKAGE_PIN K2 [get_ports {SDNCLK}]
NET "SDNCLK" LOC = "K2" | IOSTANDARD = "SSTL15" ;
# output [ADDRESS_NUMBER-1:0] SDA, // output address ports (14:0) for 4Gb device
#set_property IOSTANDARD SSTL15 [get_ports {SDA[0]}]
#set_property PACKAGE_PIN N3 [get_ports {SDA[0]}]
NET "SDA<0>" LOC = "N3" | IOSTANDARD = "SSTL15" ;
#set_property IOSTANDARD SSTL15 [get_ports {SDA[1]}]
#set_property PACKAGE_PIN H2 [get_ports {SDA[1]}]
NET "SDA<1>" LOC = "H2" | IOSTANDARD = "SSTL15" ;
#set_property IOSTANDARD SSTL15 [get_ports {SDA[2]}]
#set_property PACKAGE_PIN M2 [get_ports {SDA[2]}]
NET "SDA<2>" LOC = "M2" | IOSTANDARD = "SSTL15" ;
#set_property IOSTANDARD SSTL15 [get_ports {SDA[3]}]
#set_property PACKAGE_PIN P5 [get_ports {SDA[3]}]
NET "SDA<3>" LOC = "P5" | IOSTANDARD = "SSTL15" ;
#set_property IOSTANDARD SSTL15 [get_ports {SDA[4]}]
#set_property PACKAGE_PIN H1 [get_ports {SDA[4]}]
NET "SDA<4>" LOC = "H1" | IOSTANDARD = "SSTL15" ;
#set_property IOSTANDARD SSTL15 [get_ports {SDA[5]}]
#set_property PACKAGE_PIN M3 [get_ports {SDA[5]}]
NET "SDA<5>" LOC = "M3" | IOSTANDARD = "SSTL15" ;
#set_property IOSTANDARD SSTL15 [get_ports {SDA[6]}]
#set_property PACKAGE_PIN J1 [get_ports {SDA[6]}]
NET "SDA<6>" LOC = "J1" | IOSTANDARD = "SSTL15" ;
#set_property IOSTANDARD SSTL15 [get_ports {SDA[7]}]
#set_property PACKAGE_PIN P4 [get_ports {SDA[7]}]
NET "SDA<7>" LOC = "P4" | IOSTANDARD = "SSTL15" ;
#set_property IOSTANDARD SSTL15 [get_ports {SDA[8]}]
#set_property PACKAGE_PIN K1 [get_ports {SDA[8]}]
NET "SDA<8>" LOC = "K1" | IOSTANDARD = "SSTL15" ;
#set_property IOSTANDARD SSTL15 [get_ports {SDA[9]}]
#set_property PACKAGE_PIN P3 [get_ports {SDA[9]}]
NET "SDA<9>" LOC = "P3" | IOSTANDARD = "SSTL15" ;
#set_property IOSTANDARD SSTL15 [get_ports {SDA[10]}]
#set_property PACKAGE_PIN F2 [get_ports {SDA[10]}]
NET "SDA<10>" LOC = "F2" | IOSTANDARD = "SSTL15" ;
#set_property IOSTANDARD SSTL15 [get_ports {SDA[11]}]
#set_property PACKAGE_PIN H3 [get_ports {SDA[11]}]
NET "SDA<11>" LOC = "H3" | IOSTANDARD = "SSTL15" ;
#set_property IOSTANDARD SSTL15 [get_ports {SDA[12]}]
#set_property PACKAGE_PIN G3 [get_ports {SDA[12]}]
NET "SDA<12>" LOC = "G3" | IOSTANDARD = "SSTL15" ;
#set_property IOSTANDARD SSTL15 [get_ports {SDA[13]}]
#set_property PACKAGE_PIN N2 [get_ports {SDA[13]}]
NET "SDA<13>" LOC = "N2" | IOSTANDARD = "SSTL15" ;
#set_property IOSTANDARD SSTL15 [get_ports {SDA[14]}]
#set_property PACKAGE_PIN J3 [get_ports {SDA[14]}]
NET "SDA<14>" LOC = "J3" | IOSTANDARD = "SSTL15" ;
# output [2:0] SDBA, // output bank address ports
#set_property IOSTANDARD SSTL15 [get_ports {SDBA[0]}]
#set_property PACKAGE_PIN N1 [get_ports {SDBA[0]}]
NET "SDBA<0>" LOC = "N1" | IOSTANDARD = "SSTL15" ;
#set_property IOSTANDARD SSTL15 [get_ports {SDBA[1]}]
#set_property PACKAGE_PIN F1 [get_ports {SDBA[1]}]
NET "SDBA<1>" LOC = "F1" | IOSTANDARD = "SSTL15" ;
#set_property IOSTANDARD SSTL15 [get_ports {SDBA[2]}]
#set_property PACKAGE_PIN P1 [get_ports {SDBA[2]}]
NET "SDBA<2>" LOC = "P1" | IOSTANDARD = "SSTL15" ;
# output SDWE, // output WE port
#set_property IOSTANDARD SSTL15 [get_ports {SDWE}]
#set_property PACKAGE_PIN G4 [get_ports {SDWE}]
NET "SDWE" LOC = "G4" | IOSTANDARD = "SSTL15" ;
# output SDRAS, // output RAS port
#set_property IOSTANDARD SSTL15 [get_ports {SDRAS}]
#set_property PACKAGE_PIN L2 [get_ports {SDRAS}]
NET "SDRAS" LOC = "L2" | IOSTANDARD = "SSTL15" ;
# output SDCAS, // output CAS port
#set_property IOSTANDARD SSTL15 [get_ports {SDCAS}]
#set_property PACKAGE_PIN L1 [get_ports {SDCAS}]
NET "SDCAS" LOC = "L1" | IOSTANDARD = "SSTL15" ;
# output SDCKE, // output Clock Enable port
#set_property IOSTANDARD SSTL15 [get_ports {SDCKE}]
#set_property PACKAGE_PIN E1 [get_ports {SDCKE}]
NET "SDCKE" LOC = "E1" | IOSTANDARD = "SSTL15" ;
# output SDODT, // output ODT port
#set_property IOSTANDARD SSTL15 [get_ports {SDODT}]
#set_property PACKAGE_PIN M7 [get_ports {SDODT}]
NET "SDODT" LOC = "M7" | IOSTANDARD = "SSTL15" ;
# inout [15:0] SDD, // DQ I/O pads
#set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[0]}]
#set_property PACKAGE_PIN K6 [get_ports {SDD[0]}]
NET "SDD<0>" LOC = "K6" | IOSTANDARD = "SSTL15_T_DCI" ;
# inout [15:0] SDD, // DQ I/O pads
#set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[1]}]
#set_property PACKAGE_PIN L4 [get_ports {SDD[1]}]
NET "SDD<1>" LOC = "L4" | IOSTANDARD = "SSTL15_T_DCI" ;
# inout [15:0] SDD, // DQ I/O pads
#set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[2]}]
#set_property PACKAGE_PIN K7 [get_ports {SDD[2]}]
NET "SDD<2>" LOC = "K7" | IOSTANDARD = "SSTL15_T_DCI" ;
# inout [15:0] SDD, // DQ I/O pads
#set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[3]}]
#set_property PACKAGE_PIN K4 [get_ports {SDD[3]}]
NET "SDD<3>" LOC = "K4" | IOSTANDARD = "SSTL15_T_DCI" ;
# inout [15:0] SDD, // DQ I/O pads
#set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[4]}]
#set_property PACKAGE_PIN L6 [get_ports {SDD[4]}]
NET "SDD<4>" LOC = "L6" | IOSTANDARD = "SSTL15_T_DCI" ;
# inout [15:0] SDD, // DQ I/O pads
#set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[5]}]
#set_property PACKAGE_PIN M4 [get_ports {SDD[5]}]
NET "SDD<5>" LOC = "M4" | IOSTANDARD = "SSTL15_T_DCI" ;
# inout [15:0] SDD, // DQ I/O pads
#set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[6]}]
#set_property PACKAGE_PIN L7 [get_ports {SDD[6]}]
NET "SDD<6>" LOC = "L7" | IOSTANDARD = "SSTL15_T_DCI" ;
# inout [15:0] SDD, // DQ I/O pads
#set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[7]}]
#set_property PACKAGE_PIN N5 [get_ports {SDD[7]}]
NET "SDD<7>" LOC = "N5" | IOSTANDARD = "SSTL15_T_DCI" ;
# inout [15:0] SDD, // DQ I/O pads
#set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[8]}]
#set_property PACKAGE_PIN H5 [get_ports {SDD[8]}]
NET "SDD<8>" LOC = "H5" | IOSTANDARD = "SSTL15_T_DCI" ;
# inout [15:0] SDD, // DQ I/O pads
#set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[9]}]
#set_property PACKAGE_PIN J6 [get_ports {SDD[9]}]
NET "SDD<9>" LOC = "J6" | IOSTANDARD = "SSTL15_T_DCI" ;
# inout [15:0] SDD, // DQ I/O pads
#set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[10]}]
#set_property PACKAGE_PIN G5 [get_ports {SDD[10]}]
NET "SDD<10>" LOC = "G5" | IOSTANDARD = "SSTL15_T_DCI" ;
# inout [15:0] SDD, // DQ I/O pads
#set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[11]}]
#set_property PACKAGE_PIN H6 [get_ports {SDD[11]}]
NET "SDD<11>" LOC = "H6" | IOSTANDARD = "SSTL15_T_DCI" ;
# inout [15:0] SDD, // DQ I/O pads
#set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[12]}]
#set_property PACKAGE_PIN F5 [get_ports {SDD[12]}]
NET "SDD<12>" LOC = "F5" | IOSTANDARD = "SSTL15_T_DCI" ;
# inout [15:0] SDD, // DQ I/O pads
#set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[13]}]
#set_property PACKAGE_PIN F7 [get_ports {SDD[13]}]
NET "SDD<13>" LOC = "F7" | IOSTANDARD = "SSTL15_T_DCI" ;
# inout [15:0] SDD, // DQ I/O pads
#set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[14]}]
#set_property PACKAGE_PIN F4 [get_ports {SDD[14]}]
NET "SDD<14>" LOC = "F4" | IOSTANDARD = "SSTL15_T_DCI" ;
# inout [15:0] SDD, // DQ I/O pads
#set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDD[15]}]
#set_property PACKAGE_PIN F6 [get_ports {SDD[15]}]
NET "SDD<15>" LOC = "F6" | IOSTANDARD = "SSTL15_T_DCI" ;
# inout DQSL, // LDQS I/O pad
#set_property PACKAGE_PIN N7 [get_ports {DQSL}]
#set_property SLEW FAST [get_ports {DQSL}]
#set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {DQSL}]
NET "DQSL" LOC = "N7" | IOSTANDARD = "DIFF_SSTL15_T_DCI"; # | SLEW = "FAST";
# inout NDQSL, // ~LDQS I/O pad
#set_property PACKAGE_PIN N6 [get_ports {NDQSL}]
#set_property SLEW FAST [get_ports {NDQSL}]
#set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {NDQSL}]
NET "NDQSL" LOC = "N6" | IOSTANDARD = "DIFF_SSTL15_T_DCI";# | SLEW = "FAST";
# inout DQSU, // UDQS I/O pad
#set_property PACKAGE_PIN H7 [get_ports {DQSU}]
#set_property SLEW FAST [get_ports {DQSU}]
#set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {DQSU}]
NET "DQSU" LOC = "H7" | IOSTANDARD = "DIFF_SSTL15_T_DCI";# | SLEW = "FAST";
# inout NDQSU, // ~UDQS I/O pad
#set_property PACKAGE_PIN G7 [get_ports {NDQSU}]
#set_property SLEW FAST [get_ports {NDQSU}]
#set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {NDQSU}]
NET "NDQSU" LOC = "G7" | IOSTANDARD = "DIFF_SSTL15_T_DCI";# | SLEW = "FAST";
# inout SDDML, // LDM I/O pad (actually only output)
#set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDDML}]
#set_property IOSTANDARD SSTL15 [get_ports {SDDML}]
#set_property PACKAGE_PIN L5 [get_ports {SDDML}]
NET "SDDML" LOC = "L5" | IOSTANDARD = "SSTL15";
# inout SDDMU, // UDM I/O pad (actually only output)
#set_property IOSTANDARD SSTL15_T_DCI [get_ports {SDDMU}]
#set_property IOSTANDARD SSTL15 [get_ports {SDDMU}]
#set_property PACKAGE_PIN J5 [get_ports {SDDMU}]
NET "SDDMU" LOC = "J5" | IOSTANDARD = "SSTL15";
# Global constraints
#set_property INTERNAL_VREF 0.750 [get_iobanks 34]
CONFIG INTERNAL_VREF_BANK34=0.750;
#set_property DCI_CASCADE 34 [get_iobanks 35]
CONFIG DCI_CASCADE = "35 34";
#set_property INTERNAL_VREF 0.750 [get_iobanks 35]
CONFIG INTERNAL_VREF_BANK35=0.750;
#set_property CFGBVS GND [current_design]
# No UCF?
#set_property CONFIG_VOLTAGE 1.8 [current_design]
# No UCF?
ddrc_test01.xdc
View file @ 46cf253d
......@@ -175,12 +175,12 @@ set_property PACKAGE_PIN F6 [get_ports {SDD[15]}]
# inout DQSL, // LDQS I/O pad
set_property PACKAGE_PIN N7 [get_ports {DQSL}]
set_property SLEW FAST [get_ports {DQSL}]
#set_property SLEW FAST [get_ports {DQSL}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {DQSL}]
# inout NDQSL, // ~LDQS I/O pad
set_property PACKAGE_PIN N6 [get_ports {NDQSL}]
set_property SLEW FAST [get_ports {NDQSL}]
#set_property SLEW FAST [get_ports {NDQSL}]
set_property IOSTANDARD DIFF_SSTL15_T_DCI [get_ports {NDQSL}]
# inout DQSU, // UDQS I/O pad
......
ddrc_test01_timing.xdc 0 → 100644
View file @ 46cf253d
#################################################################################
# Filename: ddrc_test01_timing.xdc
# Date:2014-05-20
# Author: Andrey Filippov
# Description: DDR3 controller test with axi constraints
#
# Copyright (c) 2014 Elphel, Inc.
# ddrc_test01_timing.xdc is free software; you can redistribute it and/or modify
# it under the terms of the GNU General Public License as published by
# the Free Software Foundation, either version 3 of the License, or
# (at your option) any later version.
#
# ddrc_test01_timing.xdc is distributed in the hope that it will be useful,
# but WITHOUT ANY WARRANTY; without even the implied warranty of
# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
# GNU General Public License for more details.
#
# You should have received a copy of the GNU General Public License
# along with this program. If not, see <http://www.gnu.org/licenses/> .
#################################################################################
#create_clock -period 2.500 -name clk -waveform {0.000 1.250} [get_ports CLK]
#axi_aclk [get_pins -hierarchical *pll*CLKIN1]
create_clock -name axi_aclk -period 10 [get_nets -hierarchical *axi_aclk]
#Clock Period Waveform Attributes Sources
#axi_aclk 10.00000 {0.00000 5.00000} P {bufg_axi_aclk_i/O}
#clk_fb 10.00000 {0.00000 5.00000} P,G {ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKFBOUT}
#sdclk_pre 2.50000 {0.00000 1.25000} P,G {ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT0}
#clk_pre 2.50000 {0.00000 1.25000} P,G {ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT1}
#clk_div_pre 5.00000 {0.00000 2.50000} P,G {ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT2}
#mclk_pre 5.00000 {1.25000 3.75000} P,G {ddrc_sequencer_i/phy_cmd_i/phy_top_i/mmcm_phase_cntr_i/MMCME2_ADV_i/CLKOUT3}
#clkfb_ref 10.00000 {0.00000 5.00000} P,G {ddrc_sequencer_i/phy_cmd_i/phy_top_i/pll_base_i/PLLE2_BASE_i/CLKFBOUT}
#clk_ref_pre 3.33333 {0.00000 1.66667} P,G {ddrc_sequencer_i/phy_cmd_i/phy_top_i/pll_base_i/PLLE2_BASE_i/CLKOUT0}
create_generated_clock -name ddr3_sdclk [get_nets -hierarchical sdclk_pre]
create_generated_clock -name ddr3_clk [get_nets -hierarchical clk_pre]
create_generated_clock -name ddr3_clk_div [get_nets -hierarchical clk_div_pre]
create_generated_clock -name ddr3_mclk [get_nets -hierarchical mclk_pre]
create_generated_clock -name ddr3_clk_ref [get_nets -hierarchical clk_ref_pre]
# do not check timing between axi_aclk and other clocks. Code should provide correct asynchronous crossing of the clock boundary.
set_clock_groups -name ps_async_clock -asynchronous -group {axi_aclk}
phy/byte_lane.v
View file @ 46cf253d
......@@ -57,8 +57,8 @@ module byte_lane #(
wire dqs_read;
wire iclk; // source-synchronous clock (BUFR from DQS)
reg [31:0] din_r=0;
reg [3:0] din_dm_r=0, din_dqs_r=0, tin_dq_r=4'hf, tin_dqs_r=4'hf;
// Preventing register duplication
// Preventing register removal of equivalent registers
(* keep = "true" *) reg [3:0] din_dm_r=0, din_dqs_r=0, tin_dq_r=4'hf, tin_dqs_r=4'hf;
(* keep = "true" *) reg [7:0] dly_data_r=0;
(* keep = "true" *) reg set_r=0;
(* keep = "true" *) reg dci_disable_dqs_r, dci_disable_dq_r;
......
phy/ddrc_sequencer.v
View file @ 46cf253d
......@@ -178,7 +178,7 @@ module ddrc_sequencer #(
if (rst) pause_cntr <= 0;
else if (!cmd_busy[1]) pause_cntr <= 0; // not needed?
else if (cmd_fetch && phy_cmd_nop) pause_cntr <= pause_len;
else if (pause_cntr!=0) pause_cntr <= pause_cntr-1;
else if (pause_cntr!=0) pause_cntr <= pause_cntr-1; //SuppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 10-bit target.
// Fetch - command data valid
if (rst) cmd_fetch <= 0;
else cmd_fetch <= cmd_busy[0] && !pause;
......@@ -189,7 +189,7 @@ module ddrc_sequencer #(
// Command read address
if (rst) cmd_addr <= 0;
else if (run_seq) cmd_addr <= run_addr[9:0];
else if (cmd_busy[0] && !pause) cmd_addr <= cmd_addr + 1;
else if (cmd_busy[0] && !pause) cmd_addr <= cmd_addr + 1; //SuppressThisWarning ISExst Result of 11-bit expression is truncated to fit in 10-bit target.
// command bank select (0 - "manual" (software programmed sequences), 1 - "auto" (normal block r/w)
if (rst) cmd_sel <= 0;
else if (run_seq) cmd_sel <= run_addr[10];
......@@ -222,7 +222,7 @@ module ddrc_sequencer #(
(run_chn_d==4'h0)?1'b1:1'b0 };
if (rst) buf_raddr <= 9'h0;
else if (run_seq_d) buf_raddr <= {buf_page,7'h0};
else if (buf_wr || buf_rd) buf_raddr <= buf_raddr +1; // Separate read/write address? read address re-registered @ negedge
else if (buf_wr || buf_rd) buf_raddr <= buf_raddr +1; // Separate read/write address? read address re-registered @ negedge //SuppressThisWarning ISExst Result of 10-bit expression is truncated to fit in 9-bit target.
if (rst) run_chn_d <= 0;
else if (run_seq) run_chn_d <= run_chn;
......
phy/phy_top.v
View file @ 46cf253d
......@@ -108,7 +108,7 @@ module phy_top #(
output [PHASE_WIDTH-1:0] ps_out
);
reg rst=1'b0;
always @(posedge clk or posedge rst_in) begin
always @(posedge clk_div or posedge rst_in) begin
if (rst_in) rst <= 1'b1;
else rst <= 1'b0;
end
......
util_modules/fifo_cross_clocks.v
View file @ 46cf253d
......@@ -39,7 +39,7 @@ module fifo_cross_clocks
reg [DATA_WIDTH-1:0] ram [0:DATA_2DEPTH];
reg [DATA_DEPTH-1:0] raddr;
reg [DATA_DEPTH-1:0] waddr;
reg [DATA_DEPTH-1:0] waddr_gray; //VivadoSynthesis: [Synth 8-3332] Sequential element ddrc_test01.ddrc_control_i.fifo_cross_clocks_i.waddr_gray_reg[3] is unused and will be removed from module ddrc_test01.
reg [DATA_DEPTH-1:0] waddr_gray; //SuppressThisWarning ISExst VivadoSynthesis : MSB(waddr_gray) == MSB(waddr)
reg [DATA_DEPTH-1:0] waddr_gray_rclk;
wire [DATA_DEPTH-1:0] waddr_plus1 = waddr +1;
wire [DATA_DEPTH-1:0] waddr_plus1_gray = waddr_plus1 ^ {1'b0,waddr_plus1[DATA_DEPTH-1:1]};
......@@ -47,15 +47,13 @@ module fifo_cross_clocks
wire [DATA_DEPTH-1:0] raddr_gray = raddr ^ {1'b0,raddr[DATA_DEPTH-1:1]};
wire [DATA_DEPTH-1:0] raddr_plus1 = raddr +1;
wire [2:0] raddr_plus1_gray_top3 = raddr_plus1[DATA_DEPTH-1:DATA_DEPTH-3] ^ {1'b0,raddr_plus1[DATA_DEPTH-1:DATA_DEPTH-2]};
reg [2:0] raddr_gray_top3; //VivadoSynthesis: [Synth 8-3332] Sequential element ddrc_test01.ddrc_control_i.fifo_cross_clocks_i.raddr_gray_top3_reg[2] is unused and will be removed from module ddrc_test01.
reg [2:0] raddr_gray_top3; //SuppressThisWarning ISExst VivadoSynthesis : MSB(raddr_gray_top3) == MSB(raddr)
reg [2:0] raddr_gray_top3_wclk;
wire [2:0] raddr_top3_wclk = {
raddr_gray_top3_wclk[2],
raddr_gray_top3_wclk[2]^raddr_gray_top3_wclk[1],
raddr_gray_top3_wclk[2]^raddr_gray_top3_wclk[1]^raddr_gray_top3_wclk[0]};
//(* keep = "true" *) wire [2:0] addr_diff=waddr[DATA_DEPTH-1-:3]-raddr_top3_wclk; // just debugging 8-3332
wire [2:0] waddr_top3=waddr[DATA_DEPTH-1:DATA_DEPTH-3];
//(* keep = "true" *) wire [2:0] addr_diff=waddr[DATA_DEPTH-1:DATA_DEPTH-4]-raddr_top3_wclk; // just debugging 8-3332
wire [2:0] addr_diff=waddr_top3[2:0]-raddr_top3_wclk[2:0];
// half-empty does not need to be precise, it uses 3 MSBs of the write address
// converting to Gray code (easy) and then back (can not be done parallel easily).
......
util_modules/fifo_same_clock.v
View file @ 46cf253d
......@@ -56,19 +56,19 @@ module fifo_same_clock
assign outreg_use_inreg=(out_full && two_or_less) || just_one;
// assign next_fill = fill[4:0]+((we && ~rem)?1:((~we && rem)?5'b11111:5'b00000));
// TODO: verify rem is not needed instead of re
assign next_fill = fill[4:0]+((we && ~re)?1:((~we && re)?5'b11111:5'b00000));
assign next_fill = fill[4:0]+((we && ~re)?1:((~we && re)?5'b11111:5'b00000)); //SuppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 5-bit target.
always @ (posedge clk or posedge rst) begin
if (rst) fill <= 0;
else if (we && ~re) fill <= fill+1;
else if (~we && re) fill <= fill-1;
else if (we && ~re) fill <= fill+1; //SuppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 5-bit target.
else if (~we && re) fill <= fill-1; //SuppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 5-bit target.
if (rst) wa <= 0;
else if (wem) wa <= wa+1;
else if (wem) wa <= wa+1; //SuppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 4-bit target.
if (rst) ra <= 1; // 0;
else if (re) ra <= ra+1; //now ra is 1 ahead
else if (!nempty) ra <= wa+1; // Just recover from bit errors TODO: fix
else if (re) ra <= ra+1; //now ra is 1 ahead //SuppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 4-bit target.
else if (!nempty) ra <= wa+1; // Just recover from bit errors TODO: fix //SuppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 4-bit target.
if (rst) nempty <= 0;
else nempty <= (next_fill != 0);
......
wrap/idelay_fine_pipe.v
View file @ 46cf253d
......@@ -56,9 +56,9 @@ module idelay_fine_pipe
.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE),
.IDELAY_TYPE("VAR_LOAD_PIPE"),
.IDELAY_VALUE(DELAY_VALUE>>3),
.IS_C_INVERTED(1'b0),
.IS_DATAIN_INVERTED(1'b0),
.IS_IDATAIN_INVERTED(1'b0),
// .IS_C_INVERTED(1'b0), // ISE does not have this parameter
// .IS_DATAIN_INVERTED(1'b0), // ISE does not have this parameter
// .IS_IDATAIN_INVERTED(1'b0), // ISE does not have this parameter
.PIPE_SEL("TRUE"),
.REFCLK_FREQUENCY(REFCLK_FREQUENCY),
.SIGNAL_PATTERN("DATA")
......
wrap/mmcm_phase_cntr.v
View file @ 46cf253d
......@@ -117,8 +117,8 @@ module mmcm_phase_cntr#(
else ps_start0 <= ps_we && ps_ready;
if (rst) ps_dout_r <= 0;
else if (psen && psincdec) ps_dout_r <= ps_dout_r +1;
else if (psen && !psincdec) ps_dout_r <= ps_dout_r -1;
else if (psen && psincdec) ps_dout_r <= ps_dout_r +1; //SuppressThisWarning ISExst Result of 9-bit expression is truncated to fit in 8-bit target.
else if (psen && !psincdec) ps_dout_r <= ps_dout_r -1; //SuppressThisWarning ISExst Result of 32-bit expression is truncated to fit in 8-bit target.
if (rst) ps_target <= 0;
else if (ps_we && ps_ready) ps_target <= ps_din;
......@@ -171,11 +171,11 @@ module mmcm_phase_cntr#(
.CLKOUT6_USE_FINE_PS (CLKOUT6_USE_FINE_PS),
.COMPENSATION (COMPENSATION),
.DIVCLK_DIVIDE (DIVCLK_DIVIDE),
.IS_CLKINSEL_INVERTED (1'b0),
.IS_PSEN_INVERTED (1'b0),
.IS_PSINCDEC_INVERTED (1'b0),
.IS_PWRDWN_INVERTED (1'b0),
.IS_RST_INVERTED (1'b0),
// .IS_CLKINSEL_INVERTED (1'b0), // ISE does not have this parameter
// .IS_PSEN_INVERTED (1'b0), // ISE does not have this parameter
// .IS_PSINCDEC_INVERTED (1'b0), // ISE does not have this parameter
// .IS_PWRDWN_INVERTED (1'b0), // ISE does not have this parameter
// .IS_RST_INVERTED (1'b0), // ISE does not have this parameter
.REF_JITTER1 (REF_JITTER1),
.REF_JITTER2 (REF_JITTER2),
.SS_EN (SS_EN),
......
wrap/odelay_fine_pipe.v
View file @ 46cf253d
......@@ -56,8 +56,8 @@ module odelay_fine_pipe
.HIGH_PERFORMANCE_MODE(HIGH_PERFORMANCE_MODE),
.ODELAY_TYPE("VAR_LOAD_PIPE"),
.ODELAY_VALUE(DELAY_VALUE>>3),
.IS_C_INVERTED(1'b0),
.IS_ODATAIN_INVERTED(1'b0),
// .IS_C_INVERTED(1'b0), // ISE does not have this parameter
// .IS_ODATAIN_INVERTED(1'b0), // ISE does not have this parameter
.PIPE_SEL("TRUE"),
.REFCLK_FREQUENCY(REFCLK_FREQUENCY),
.SIGNAL_PATTERN("DATA")
......
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